PUCC28C57LDR

UCC28C53_V01 TI | Alldatasheet

Document overview

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Technical content

UCCx8C5x BiCMOS Low-Power Current-Mode PWM Controller

1 Features

• 28-V VDD recommended max operating ratings
• New undervoltage lockout options to support both Si and SiC MOSFET applications
• Operating frequency: 1 MHz
• 50-μA Standby Current, 75-μA Maximum
• Low operating current: 1.3 mA (@ fOSC = 52 kHz)
• Fast, cycle-by-cycle overcurrent limiting: 35-ns
• Peak driving current: ±1-A. Rail-to-rail output: – 25-ns rise time – 20-ns fall time
• Initial trimmed 2.5-V error amplifier reference: ±1%
• Pin-to-pin compatible to UCCx8C4x and drop-in substitution

2 Applications

• General purpose single-ended DC-DC or off-line isolated power converters
• Aux power supply in polyphase motor drives and energy storage systems
• Flyback power supplies in solar power inverters

3 Description

The UCCx8C5x family are high-performance, current- mode PWM controllers with low startup current. The UCCx8C5x is an enhanced BiCMOS version with pin-for-pin compatibility to the industry standard UCCx8C4x family. With the VDD absolute maximum rating extended from 20 V to 30 V for optimal gate voltage design on 20-Vgs, 18-Vgs or 15-Vgs SiC MOSFETs by the introduction of UCC28C56H/L, UCC28C57H/L and UCC28C58/9, three new sets of UVLO options allow SiC FET operating reliably while avoiding thermal runaway. Existing UVLO options of UCCx8C4x are maintained with improvements on startup current, operating current and VDD absolute maximum rating. The UCC28C5x series is specified for operation from –40°C to 125°C, and the UCC38C5x series is specified for operation from 0°C to 85°C. The table below compares the improvements from UCCx8C5x to UCCx8C4x. Device Comparison PARAMETER UCCx8C4x UCCx8C5x Supply current at 52 kHz 2.3 mA 1.3 mA Startup current (max) 100 µA 75 µA VDD abs max 20 V 30 V UVLO and DMAX for Si FET 6 options 6 options UVLO and DMAX for SiC FET none 6 options Smallest package option VSSOP (8) VSSOP (8) The UCCx8C5x family is offered in 8-pin VSSOP (DGK), and 8-pin SOIC (D) packages. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) UCC28C50(2), UCC28C51(2) UCC28C52(2), UCC28C53 UCC28C54, UCC28C55 UCC38C50(2), UCC38C51(2) UCC38C52(2), UCC38C53(2) UCC38C54(2), UCC38C55(2) SOIC (8) 3.91 mm × 4.90 mm VSSOP (8) 3.00 mm × 3.00 mm UCC28C56H, UCC28C56L(2) UCC28C57H, UCC28C57L UCC28C58(2), UCC28C59 SOIC (8) 3.91 mm × 4.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Marketing status for this device is PREVIEW. VDD VREF GND FB CS OUT RT/CT COMP VIN VOUT Simplified Application ADVANCE INFORMATION UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

12.3 Receiving Notification of Documentation Updates..41

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES June 2022 * Initial release. UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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5 Device Comparison Table

Temperature (TJ) (°C) Maximum duty cycle Turn on at 14.5 V Turn off at 9 V for off-line applications Turn on at 8.4 V Turn off at 7.6 V for dc/dc applications Turn on at 7 V Turn off at 6.6 V for battery applications UCC28C52 UCC28C53 UCC28C50 –40 to 125 100% UCC38C52 UCC38C53 UCC38C50 0 to 85 UCC28C54 UCC28C55 UCC28C51 –40 to 125 50% UCC38C54 UCC38C55 UCC38C51 0 to 85 UVLO Junction Temperature (TJ) (°C) Maximum duty cycle Turn on at 18.8 V Turn off at 15.5 V Suitable for HV applications using GEN-I SiC MOSFET Turn on at 18.8 V Turn off at 14.5 V Suitable for HV applications using GEN-II SiC MOSFET Turn on at 16 V Turn off at 12.5 V Suitable for HV applications using GEN-III SiC MOSFET UCC28C56H UCC28C56L UCC28C58 –40 to 125 100% UCC28C57H UCC38C57L UCC28C59 –40 to 125 50% www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

6 Pin Configuration and Functions

Figure 6-1. D Package 8-Pin SOIC (Top View) 1COMP 8 VREF 2FB 7 VDD 3CS 6 OUT 4RT/CT 5 GND Not to scale Figure 6-2. DGK Package, 8-Pin VSSOP 9 (Top View) Table 6-1. Pin Functions PIN TYPE (1) DESCRIPTION NAME NO. COMP 1 O This pin provides the output of the error amplifier for compensation. In addition, the COMP pin is frequently used as a control port, by utilizing a secondary-side error amplifier to send an error signal across the secondary-primary isolation boundary through an opto-isolator. The error amplifier is internally current limited so the user can command zero duty cycle by externally forcing COMP to GND. CS 3 I Primary-side current sense pin. The current sense pin is the noninverting input to the PWM comparator. Connect to current sensing resistor. This signal is compared to a signal proportional to the error amplifier output voltage. The PWM uses this to terminate the OUT switch conduction. A voltage ramp can be applied to this pin to run the device with a voltage mode control configuration. FB 2 I This pin is the inverting input to the error amplifier. FB is used to control the power converter voltage-feedback loop for stability. The noninverting input to the error amplifier is internally trimmed to 2.5 V ± 1%. GND 5 — Ground return pin for the output driver stage and the logic level controller section. OUT 6 O The output of the on-chip drive stage. OUT is intended to directly drive a MOSFET. The OUT pin in the UCCx8C50, UCCx8C52, UCCx8C53, UCC28C56H/L and UCC28C58 is the same frequency as the oscillator, and can operate near 100% duty cycle. In the UCCx8C51, UCCx8C54, and UCCx8C55, UCC28C57H/L and UCC28C59, the frequency of OUT is one-half that of the oscillator due to an internal T flipflop. This limits the maximum duty cycle to < 50%. Peak currents of up to 1 A are sourced and sunk by this pin. OUT is actively held low when VDD is below the turn-on threshold. RT/CT 4 I/O Fixed frequency oscillator set point. Connect timing resistor (RRT) to VREF and timing capacitor (CCT) to GND from this pin to set the switching frequency. For best performance, keep the timing capacitor lead to the device GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions. The switching frequency (fSW) of the UCCx8C50, UCCx8C52, UCCx8C53, UCC28C56H/L and UCC28C58 gate drive is equal to fOSC; the switching frequency of the UCCx8C51, UCCx8C54, and UCCx8C55, UCC28C57H/L and UCC28C59 is equal to half of the fOSC. VDD 7 I Analog controller bias input that provides power to the device. Total VDD current is the sum of the quiescent VDD current and the average OUT current. A bypass capacitor, typically 0.1 µF, connected directly to GND with minimal trace length, is required on this pin. Additional capacitance at least 10 times greater than the gate capacitance of the main switching FET used in the design and at least 10 times greater than the capacitance on the VREF pin used in the design are also required on VDD. VREF 8 O 5-V reference voltage. VREF is used to provide charging current to the oscillator timing capacitor through the timing resistor. It is important for reference stability that VREF is bypassed to GND with a ceramic capacitor connected as close to the pin as possible. A minimum value of 0.1 µF ceramic is required. Additional VREF bypassing is required for external loads on VREF. No external voltage higher than specified VREF is allowed to superimposed to VREF pin since VREF is an ouput. (1) I = input, O = output, G = ground UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT Input voltage VDD 30 V Input current IVDD 30 mA Output drive current (peak) ±1 A Output energy (capacitive load), EOUT 5 µJ Analog input voltage COMP, CS, FB, RT/CT –0.3 6.3 VOutput driver voltage OUT –0.3 30 Reference voltage VREF 7 Error amplifier output sink current COMP 10 mA Total power dissipation at TA = 25°C D package 50 °C/W DGK package 120 Lead temperature (soldering, 10 s), TLEAD 300 °C Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to GND pin. Currents are positive into and negative out of the specified terminals.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VVDD Input voltage 28 V VOUT Output driver voltage 28 V IOUT Average output driver current(1) 200 mA IOUT(VREF) Reference output current(1) –20 mA TJ Operating junction temperature(1) UCC28C5x –40 125 UCC38C5x 0 85 (1) TI recommends against operating the device under conditions beyond those specified in this table for extended periods of time. www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

7.4 Thermal Information

THERMAL METRIC(1) UCC28C5x, UCC38C5x UNITD (SOIC) DGK (VSSOP)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 107.7 159.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 52.7 53 °C/W RθJB Junction-to-board thermal resistance 48.3 80.5 °C/W ψJT Junction-to-top characterization parameter 11.3 6.2 °C/W ψJB Junction-to-board characterization parameter 47.8 79.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

VVDD = 20V for UCC28C56H/L, UCC28C57H/L, and UCC28C58/9, VVDD = 15 V for all other device options, RRT = 10 kΩ, CCT = 3.3 nF, CVDD = 0.1 µF and no load on the outputs, –40°C ≤ TJ ≤ 125°C for the UCC28C5x, 0°C ≤ TJ ≤ 85°C, for the UCC38C5x (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE VVREF VREF voltage, initial accuracy TA = 25°C, IOUT = 1 mA 4.95 5 5.05 V Line regulation 12 V ≤ VVDD ≤ 18 V 0.2 20 mV Load regulation 1 mA to 20 mA 3 25 mV Temperature stability(2) 0.2 0.4 mV/°C Total output variation(2) 4.85 5.15 V VREF noise voltage(2) 10 Hz to 10 kHz, TA = 25°C 50 µV Long term stability(2) 1000 hours, TA = 125°C 5 25 mV IVREF Output short circuit –55 –45 –30 mA OSCILLATOR fOSC Initial accuracy(3) TA = 25°C 50.5 53 55 kHz Voltage stability 12 V ≤ VVDD ≤ 18 V 0.2% 1% Temperature stability(2) TA(MIN) to TA(MAX) 1% 2.5% Amplitude RT/CT pin peak-to-peak voltage 1.9 V Discharge current(4) TA = 25°C, VRT/CT = 2 V 7.7 8.4 9 mA VRT/CT = 2 V 7.2 8.4 9.5 ERROR AMPLIFIER VFB Feedback input voltage, initial accuracy VCOMP = 2.5 V, TA = 25°C 2.475 2.5 2.525 V Feedback input voltage, total variation VCOMP = 2.5 V 2.45 2.5 2.55 V IFB Input bias current VFB = 5 V –0.1 –2 µA AVOL Open-loop voltage gain 2 V ≤ VOUT ≤ 4 V 65 90 dB Unity gain bandwidth(2) 1 1.5 MHz PSRR Power supply rejection ratio 12 V ≤ VVDD ≤ 18 V 60 dB Output sink current VFB = 2.7 V, VCOMP = 1.1 V 2 14 mA Output source current VFB = 2.3 V, VCOMP = 5 V –0.5 –1 mA VOH High-level COMP voltage VFB = 2.7 V, RCOMP = 15 kΩ COMP to GND VREF– 0.2 V VOL Low-level COMP voltage VFB = 2.7 V, RCOMP = 15 kΩ COMP to VREF 0.1 1.1 V CURRENT SENSE ACS Gain(5) (1) 2.85 3 3.15 V/V VCS Maximum input signal VFB < 2.4 V 0.9 1 1.1 V UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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VVDD = 20V for UCC28C56H/L, UCC28C57H/L, and UCC28C58/9, VVDD = 15 V for all other device options, RRT = 10 kΩ, CCT = 3.3 nF, CVDD = 0.1 µF and no load on the outputs, –40°C ≤ TJ ≤ 125°C for the UCC28C5x, 0°C ≤ TJ ≤ 85°C, for the UCC38C5x (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PSRR Power supply rejection ratio(2) (5) 12 V ≤ VVDD ≤ 18 V 60 dB ICS Input bias current –0.1 –2 µA tD CS to output delay 35 70 ns COMP to CS offset VCS = 0 V 1.15 V OUTPUT VOUT(low) RDS(on) pulldown ISINK = 200 mA 5.5 15 Ω VOUT(high) RDS(on) pullup ISOURCE = 200 mA 10 25 Ω tRISE Rise time TA = 25°C, COUT = 1 nF 25 50 ns tFALL Fall time TA = 25°C, COUT = 1 nF 20 40 ns UNDERVOLTAGE LOCKOUT VDDON Start threshold(6) UCCx8C52, UCCx8C54 13.5 14.5 15.5 V UCCx8C53, UCCx8C55 7.8 8.4 9 UCCx8C50, UCCx8C51 6.5 7 7.5 UCC28C56H, UCC28C57H 17.6 18.8 20 UCC28C56L, UCC28C57L 17.6 18.8 20 UCC28C58, UCC28C59 14.8 16 17.2 VDDOFF Minimum operating voltage(6) UCCx8C52, UCCx8C54 8 9 10 V UCCx8C53, UCCx8C55 7 7.6 8.2 UCCx8C50, UCCx8C51 6.1 6.6 7.1 UCC28C56H, UCC28C57H 15 15.5 16 UCC28C56L, UCC28C57L 14 14.5 15 UCC28C58, UCC28C59 12 12.5 13 VDDHyst VDDON - VDDOFFq UCCx8C52, UCCx8C54 5.4 5.5 V UCCx8C53, UCCx8C55 0.8 0.9 UCCx8C50, UCCx8C51 0.4 0.5 UCC28C56H, UCC28C57H 3.1 3.3 UCC28C56L, UCC28C57L 4.1 4.3 UCC28C58, UCC28C59 3.4 3.5 PWM DMAX Maximum duty cycle UCCx8C52, UCCx8C53, UCCx8C50,VFB < 2.4 V 94% 96% UCC28C56H, UCC28C56L, UCC28C58,VFB < 2.4 V 94% 96% UCCx8C54, UCCx8C55, UCCx8C51,VFB < 2.4 V 47% 48% UCC28C57H, UCC28C57L, UCC28C59,VFB < 2.4 V 47% 48% DMIN Minimum duty cycle VFB > 2.6 V 0% CURRENT SUPPLY ISTART-UP Start-up current VVDD = VDDON – 0.5 V 50 75 µA IVDD Operating supply current VFB = VCS = 0 V 1.3 2 mA (1) For UCC28C56H/L, UCC28C57H/L and UCC28C58/9 adjust VVDD to a value above the start threshold before setting it to 20 V. For all other device options, adjust VVDD to a value above the start threshold before setting it to 15.5 V (2) Specified by design. Not production tested. www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

(3) Output frequencies of the UCCx8C51, UCCx8C54, and the UCCx8C55, UCC28C57H/L and the UCC28C59 are half the oscillator frequency. (4) Oscillator discharge current is measured with RRT = 10 kΩ to VREF. (5) Parameter measured at trip point of latch with VFB = 0 V. Gain is defined as ACS = ΔVCOMP / ΔVCS , 0 V ≤ VCS ≤ 900 mV. (6) VDDON, VDDOFF and VREF are tracking each other in the same direction. (Minimum VDDOFF is due to minimum VDDON.) UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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7.6 Typical Characteristics

RRT Timing Resistance (k:) fOSC Oscillator Frequency (kHz) 1 10 100 100 1000 D001 220 pF 470 pF 1 nF 2.2 nF 4.7 nF Figure 7-1. Oscillator Frequency vs Timing Resistance and Capacitance IDISCH - - Oscillator Discharge Current - - mA Temperature ( C)° 9.0 9.5 8.0 7.5 7.0 8.5 - -50 - -25 0 25 50 75 100 125 Figure 7-2. Oscillator Discharge Current vs Temperature f - - Frequency - - Hz Gain - - (dB) 1 10 100 10 k 100 k 1 M 10 M1 k 200 180 140 120 100 160 100 Phase Margin - - ( °)GAIN PHASE MARGIN Figure 7-3. Error Amplifier Frequency Response Temperature (  C) COMP to CS Offset (V) -50 -25 0 25 50 75 100 125 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 Group 1, VDD = 12 V Group 2, VDD = 20 V VCS = 0 V Group 1: UCCx8C50 to UCCx8C55 Group 2: UCC28C56H/L, UCC28C57H/L, and UCC28C58/9 Figure 7-4. COMP to CS Offset Voltage vs Temperature www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

V REF - - Reference Voltage - - V - -50 - -25 0 25 50 75 100 125 Temperature ( C)° 4.96 4.97 4.98 4.99 5.01 5.02 5.03 5.04 5.05 5.00 4.95 Figure 7-5. Reference Voltage vs Temperature 2.46 2.55 2.54 2.52 2.51 2.49 2.47 2.45 2.48 2.50 2.53 - -50 - -25 0 25 50 75 100 125 V EAREF - - Error Amplifier Reference Voltage - - V Temperature ( C)° Figure 7-6. Error Amplifier Reference Voltage vs Temperature Temperature (  C) Reference Short Circuit (mA) -50 -25 0 25 50 75 100 125 -55 -53 -51 -49 -47 -45 -43 -41 -39 -37 -35 Group 1, VDD = 12 V Group 2, VDD = 20 V Group 1: UCCx8C50 to UCCx8C55 Group 2: UCC28C56H/L, UCC28C57H/L, and UCC28C58/9 Figure 7-7. Reference Short-Circuit Current vs Temperature - -200 200 150 - -50 - -150 100 - -100 IBIAS - - Error Amplifier Input Bias Current - - nA Temperature ( C)° - -50 - -25 0 25 50 75 100 125 Figure 7-8. Error Amplifier Input Bias Current vs Temperature - -50 - -25 0 25 50 75 100 125 UVLO ON UVLO OFF V UVLO - - UVLO Voltage - - V Temperature ( C)° UCCx8C52 and UCCx8C54 Figure 7-9. Undervoltage Lockout vs Temperature V UVLO - - UVLO Voltage - - V Temperature ( C)° 7.0 9.0 8.8 8.4 8.0 7.4 7.2 7.8 7.6 8.2 8.6 - -50 - -25 0 25 50 75 100 125 UVLO ON UVLO OFF UCCx8C53 and UCCx8C55 Figure 7-10. Undervoltage Lockout vs Temperature UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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Temperature (  C) Output - Rise and Fall Time (ns) -50 -25 0 25 50 75 100 125 tr (Group 1, 12 V, 1nF) tr (Group 2, 20 V, 1nF) tf (Group 1, 12 V, 1nF) tf (Group 2, 20 V, 1nF) Group 1: UCCx8C50 to UCCx8C55 Group 2: UCC28C56H/L, UCC28C57H/L, and UCC28C58/9 Figure 7-17. Output Rise Time and Fall Time vs Temperature Duty Cycle - - % f - - Frequency - - kHz 100 0 500 CT = 220 pF CT = 1 nF 1000 1500 2000 2500 Figure 7-18. Maximum Duty Cycle vs Oscillator Frequency Maximum Duty Cycle - - % 100 - -50 - -25 0 25 50 75 100 125 Temperature ( C)° Figure 7-19. Maximum Duty Cycle vs Temperature Output Rise and Fall TIme - - ns - -50 - -25 0 25 50 75 100 125 Temperature ( C)° Figure 7-20. Maximum Duty Cycle vs Temperature Temperature (  C) Current Sense Threshold (V) -50 -25 0 25 50 75 100 125 0.95 0.97 0.99 1.01 1.03 1.05 Group 1, VDD = 12 V Group 2, VDD = 20 V Group 1: UCCx8C50 to UCCx8C55 Group 2: UCC28C56H/L, UCC28C57H/L, and UCC28C58/9 Figure 7-21. Current Sense Threshold Voltage vs Temperature Temperature (  C) CS to OUT Delay Time (ns) -50 -25 0 25 50 75 100 125 Group 1, VDD = 12 V Group 1, VDD = 20 V Group 1: UCCx8C50 to UCCx8C55 Group 2: UCC28C56H/L, UCC28C57H/L, and UCC28C58/9 Figure 7-22. Current Sense to Output Delay Time vs Temperature UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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8 Detailed Description

8.1 Overview

The UCCx8C5x series of control integrated circuits provide the features necessary to implement AC-DC or DC‑to-DC fixed-frequency current-mode control schemes with a minimum number of external components. Protection circuitry includes undervoltage lockout (UVLO) and current limiting. Internally implemented circuits include a start-up current of less than 75 µA, a precision reference trimmed for accuracy at the error amplifier input, logic to ensure latched operation, a pulse-width modulation (PWM) comparator that also provides current- limit control, and an output stage designed to source or sink high-peak current. The output stage, suitable for driving N-channel MOSFETs, is low when it is in the OFF state. The oscillator contains a trimmed discharge current that enables accurate programming of the maximum duty cycle and dead time limit, making this device suitable for high-speed applications. Major differences between members of this series are the UVLO thresholds, acceptable ambient temperature range, maximum duty cycle and frequency. Typical UVLO thresholds of 14.5 V (ON) and 9 V (OFF) on the UCCx8C52 and UCCx8C54 devices make them ideally suited to off-line AC-DC applications. The corresponding typical thresholds for the UCCx8C53 and UCCx8C55 devices are 8.4 V (ON) and 7.6 V (OFF), making them ideal for use with regulated input voltages used in DC-DC applications. The UCCx8C50 and UCCx8C51 feature a start-up threshold of 7 V and a turnoff threshold of 6.6 V (OFF), which makes them suitable for battery-powered applications. The UCC28C56H/L, UCC28C57H/L, UCC28C58 and UCC28C59 operate with higher start-up thresholds for them suitably to work with SiC MOSFETs which often being used in high-voltage and high-power traction inverter applications. The UCC28C56H and UCC28C57H are with a start-up threshold 18.8 V (ON) and 15.5 V (OFF). The UCC28C56L and UCC28C57L are with a start-up threshold 18.8V (ON) and 14.5 V (OFF). The UCC28C58 and UCC28C59 are with a start-up threshold 16 V (ON) and 12.5 V (OFF). The UCCx8C50, UCCx8C52, UCCx8C53, UCC28C56H/L and UCC28C58 devices operate to duty cycles approaching 100%. The UCCx8C51, UCCx8C54, UCCx8C55, UCC28C57H/L and UCC28C59 obtain a duty cycle from 0% to 50% by the addition of an internal toggle flip-flop, which blanks the output off every other clock cycle. The UCC28C5x series is specified for operation from –40°C to 125°C, and the UCC38C5x series is specified for operation from 0°C to 85°C. The switching frequency (fSW) of the UCCx8C50, UCCx8C52, UCCx8C53, UCC28C56H/L and UCC28C58 gate drive is equal to f OSC; the switching frequency of the UCCx8C51, UCCx8C54, UCCx8C55, UCC28C57H/L and UCC28C59 is equal to half of the fOSC. The UCC28C5x and UCC38C5x series are an enhanced replacement with pin-to-pin compatibility to the BiCMOS UCCx8C4x, and to the bipolar UC284x, UC384x, UC284xA, and UC384xA families. The new series offers improved performance when compared to older bipolar devices and other competitive BiCMOS devices with similar functionality. These improvements generally consist of tighter specification limits that are a subset of the older product ratings, maintaining drop-in capability. In new designs, these improvements can reduce the component count or enhance circuit performance when compared to the previously available devices. www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

8.2 Functional Block Diagram

S R PWM LatchR 1 V E/A VDD RT/CT FB COMP CS PWM Comparator VREF OUT GND T 2. 5 V ( NOTE ) 5 V Copyright © 2016, Texas Instruments Incorporated Toggle flip-flop used only in UCCx8C51, UCCx8C54, UCCx8C55, UCC28C57H/L, and UCC28C59

8.3 Feature Description

The BiCMOS design allows operation at high frequencies that were not feasible in the predecessor bipolar devices. First, the output stage has been redesigned to drive the external power switch in approximately half the time of the earlier devices. Second, the internal oscillator is more robust, with less variation as frequency increases. This faster oscillator makes this device suitable for high speed applications and the trimmed discharge current enables precise programming of the maximum duty cycle and dead-time limit. In addition, the current sense to output delay is kept the same 45 ns (typical) as UCCx8C4x . Such a delay time in the current sense results in superior overload protection at the power switch. The reduced start-up current of this device minimizes steady state power dissipation in the startup resistor, and the low operating current maximizes efficiency while running, increasing the total circuit efficiency, whether operating off-line, DC input, or battery operated circuits. These features combine to provide a device capable of reliable, high-frequency operation. Table 8-1. Improved Key Parameters PARAMETER UCCx8C4x UCCx8C5x Supply current at 52 kHz 2.3 mA 1.3 mA Start-up current, maximum 100 µA 75 µA VVDD absolute maximum 20 V 30 V Reference voltage accuracy ± 1% ± 1% UVLO and Dmax for Si FETs 6 options 6 options UVLO and Dmax for SiC FETs No options 6 options Smallest package option VSSOP (8) VSSOP (8) UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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8.3.1 Detailed Pin Description

8.3.1.1 COMP

The error amplifier in the UCCx8C5x family has a unity-gain bandwidth of 1 MHz. The COMP terminal can both source and sink current. The error amplifier is internally current-limited, so that one can command zero duty cycle by externally forcing COMP to GND. 8.3.1.2 FB FB is the inverting input of the error amplifier. The noninverting input to the error amplifier is internally trimmed to 2.5 V ± 1%. FB is used to control the power converter voltage-feedback loop for stability. For best stability, keep FB lead length as short as possible and FB stray capacitance as small as possible. 8.3.1.3 CS The UCCx8C5x current sense input connects directly to the PWM comparator. Connect CS to the MOSFET source current sense resistor. The PWM uses this signal to terminate the OUT switch conduction. A voltage ramp can be applied to this pin to run the device with a voltage mode control configuration or to add slope compensation. To prevent false triggering due to leading edge noises, an RC current sense filter may be required. The gain of the current sense amplifier is typically 3 V/V.

8.3.1.4 RT/CT

The internal oscillator uses a timing capacitor (C CT) and a timing resistor (R RT) to program the oscillator frequency and maximum duty cycle. The operating frequency can be programmed based the curves in Figure 7-1, where the timing resistor can be found once the timing capacitor is selected. It is best for the timing capacitor to have a flat temperature coefficient, typical of most COG or NPO type capacitors. For this converter, 15.4 kΩ and 1000 pF were selected for RRT and CCT to operate at 110-kHz switching.

8.3.1.5 GND

GND is the signal and power returning ground. TI recommends separating the signal return path and the high current gate driver path so that the signal is not affected by the switching current.

8.3.1.6 OUT

The high-current output stage of the UCCx8C5x to drive the external power switch has been kept the same as the earlier devices UCC28C4x. To drive a power MOSFET directly, the totem-pole OUT driver sinks or source up to 1 A peak of current. The OUT of the UCCx8C50, UCCx8C52, UCCx8C53 UCC28C56H/L and UCC28C58 devices switch at the same frequency as the oscillator and can operate near 100% duty cycle. In the UCCx8C51, UCCx8C54, and UCCx8C55, UCC28C57H/L and UCC28C59, the switching frequency of OUT is one-half that of the oscillator due to an internal T flip-flop. This limits the maximum duty cycle in the UCCx8C51, UCCx8C54, and UCCx8C55, UCC28C57H/L and UCC28C59 to < 50%. The UCCx8C5x family houses unique totem pole drivers exhibiting a 10- Ω impedance to the upper rail and a 5.5‑Ω impedance to ground, typically. This reduced impedance on the low-side switch helps minimize turn-off losses at the power MOSFET, whereas the higher turnon impedance of the high-side is intended to better match the reverse recovery characteristics of many high-speed output rectifiers. Transition times, rising and falling edges, are typically 25 nanoseconds and 20 nanoseconds, respectively, for a 10% to 90% change in voltage. A low impedance MOS structure in parallel with a bipolar transistor, or BiCMOS construction, comprises the totem-pole output structure. This more efficient utilization of silicon delivers the high peak current required along with sharp transitions and full rail-to-rail voltage swings. Furthermore, the output stage is self-biasing, active low during under-voltage lockout type. With no VDD supply voltage present, the output actively pulls low if an attempt is made to pull the output high. This condition frequently occurs at initial power-up with a power MOSFET as the driver load.

8.3.1.7 VDD

VDD is the power input connection for this device. In normal operation, power VDD through a current limiting resistor. The absolute maximum supply voltage is 30 V (extended from 20 V of UCCx8C4x) to facilitate designs and applications. The voltage level of 30 V, including any transients that may be present, cannot be exceeded, www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

device damage is likely if otherwise. Because of this limitation, the UCCx8C5x devices match the predecessor bipolar devices, which could survive up to 30 V on the input bias pin. Because no internal clamp is included in the device, the VDD pin must be protected from external sources which could exceed the 30 V level. If containing the start-up and bootstrap supply voltage from the auxiliary winding N A below 30 V under all line and load conditions can not be achieved, use a zener protection diode from VDD to GND. Depending on the impedance and arrangement of the bootstrap supply, this may require adding a resistor, R VDD, in series with the auxiliary winding to limit the current into the zener as shown in Figure 8-1. Ensure that over all tolerances and temperatures, the minimum zener voltage is higher than the highest UVLO upper turn-on threshold. To prevent noise related problems, filter VDD with a ceramic bypass capacitor to GND. The VDD pin must be decoupled as close to the GND pin as possible. RSTART CVCC VDD OUT GNDCVDDbp 0.1 PF DBIAS RCS NP NA NS RVDDTo Input DZCLAMP Figure 8-1. VDD Protection Although quiescent VDD current is only 75 µA, the total supply current is higher, depending on the OUT current. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from Equation 1. IOUT = Qg × fSW (1)

8.3.1.8 VREF

VREF is the voltage reference for the error amplifier and also for many other internal circuits in the IC. The 5-V reference tolerance is ±1% for the UCCx8C5x family. The high-speed switching logic uses VREF as the logic power supply. The reference voltage is divided down internally to 2.5 V ±1% and connected to the error amplifier's noninverting input for accurate output voltage regulation. The reference voltage sets the internal bias currents and thresholds for functions such as the oscillator upper and lower thresholds along with the overcurrent limiting threshold. The output short-circuit current is 55 mA (maximum). To avoid device over-heating and damage, do not pull VREF to ground as a means to terminate switching. For reference stability and to prevent noise problems with high-speed switching transients, bypass VREF to GND with a ceramic capacitor close to the IC package. A ceramic capacitor with a minimum value of 0.1 µF is required. Additional VREF bypassing is required for external loads on the reference. An electrolytic capacitor may also be used in addition to the ceramic capacitor.

8.3.2 Undervoltage Lockout

Six sets of UVLO thresholds are available with turn-on and turnoff thresholds of: (14.5 V and 9 V), (8.4 V and set is primarily intended for off-line and 48-V distributed power applications, where the wider hysteresis allows for lower frequency operation and longer soft-starting time of the converter. The second group of UVLO options is ideal for high frequency DC-DC converters typically running from a 12-VDC input. The third, and newest, set has been added to address battery powered and portable applications. Table 8-2 shows the maximum duty cycle and UVLO thresholds by device. UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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Table 8-2. UVLO Options MAXIMUM DUTY CYCLE (%) UVLO ON (V) UVLO OFF (V) DEVICE NUMBER 100 14.5 9 UCCx8C52 100 8.4 7.6 UCCx8C53 100 7 6.6 UCCx8C50 100 18.8 15.5 UCC28C56H 100 18.8 14.5 UCC28C56L 100 16 12.5 UCC28C58 50 14.5 9 UCCx8C54 50 8.4 7.6 UCCx8C55 50 7 6.6 UCCx8C51 50 18.8 15.5 UCC28C57H 50 18.8 14.5 UCC28C57L 50 16 12.5 UCC28C59 During UVLO the IC draws less than 75 µA of supply current. Once crossing the turnon threshold the IC supply current increases to a maximum of 2mA, typically 1.3 mA. This low start-up current allows the power supply designer to optimize the selection of the startup resistor value to provide a more efficient design. In applications where low component cost overrides maximum efficiency, the low run current of 1.3 mA (typical) allows the control device to run directly through the single resistor to (+) rail, rather than requiring a bootstrap winding on the power transformer, along with a rectifier. The start and run resistor for this case must also pass enough current to allow driving the primary switching MOSFET, which may be a few milliamps in small devices. < 0.075 VOFF < 2 VON Operating Voltage (V) Supply Current (mA) Figure 8-2. UVLO ON and OFF Profile 8.3.3 ±1% Internal Reference Voltage The BiCMOS internal reference of 2.5 V has an enhanced design, and uses production trim to allow initial accuracy of ±1% at room temperature and ±2% over the full temperature range. This reference voltage can be used to eliminate an external reference in applications that do not require the extreme accuracy afforded by the additional device. This reference voltage is useful for non-isolated DC-DC applications, where the control device is referenced to the same common as the output. It is also applicable in off-line designs that regulate on the primary side of the isolation boundary by looking at a primary bias winding, or from a winding on the output inductor of a buck-derived circuit.

8.3.4 Current Sense and Overcurrent Limit

An external series resistor (R CS) senses the current and converts this current into a voltage that becomes the input to the CS pin. The CS pin is the noninverting input to the PWM comparator. The device compares the CS www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

input with a signal proportional to the error amplifier output voltage. The gain of the current sense amplifier is typically 3 V/V. The peak ISENSE current is determined using Equation 2 ISENSE = VCS RCS (2) The typical value for VCS is 1 V. A small RC filter (RCSF and CCSF) may be required to suppress switch transients caused by the reverse recovery of a secondary side diode or equivalent capacitive loading in addition to parasitic circuit impedances. The time constant of this filter should be considerably less than the switching period of the converter. CS GND COMP 2 R R CCSF RCSF RCS PWM Comparator 1 V Error Amplifier ISENSE Copyright © 2016, Texas Instruments Incorporated Figure 8-3. Current-Sense Circuit Schematic Cycle-by-cycle pulse width modulation performed at the PWM comparator essentially compares the error amplifier output to the current sense input. This is not a direct volt-to-volt comparison, as the error amplifier output network incorporates two diodes in series with a resistive divider network before connecting to the PWM comparator. The two-diode drop adds an offset voltage that enables zero duty cycle to be achieved with a low amplifier output. The 2R/R resistive divider facilitates the use of a wider error amplifier output swing that can be more symmetrically centered on the 2.5-V noninverting input voltage. The 1-V Zener diode associated with the PWM comparator input from the error amplifier is not an actual diode in the device design, but an indication that the maximum current sense input amplitude is 1 V (typical). When this threshold is reached, regardless of the error amplifier output voltage, cycle-by-cycle current limiting occurs, and the output pulse width is terminated within 35 ns (typical). The minimum value for this current limit threshold is 0.9 V with a 1.1-V maximum. In addition to the tolerance of this parameter, the accuracy of the current sense resistor, or current sense circuitry, must be taken into account. It is advised to factor in the worst case of primary and secondary currents when sizing the ratings and worst-case conditions in all power semiconductors and magnetic components.

8.3.5 Reduced-Discharge Current Variation

The oscillator design for the UCCx8C5x controllers incorporates a trimmed discharge current to accurately program maximum duty cycle and operating frequency. In its basic operation, a timing capacitor (CCT) is charged by a current source, formed by the timing resistor (R RT) connected to the device reference voltage (VREF). The oscillator design incorporates comparators to monitor the amplitude of the timing capacitor voltage. The exponentially shaped waveform charges up to a specific amplitude representing the oscillator upper threshold of 3 V. After the controller reaches this level, an internal current sink to ground turns on and the capacitor begins to discharge. This discharge continues until the oscillator lower threshold has reached 0.7 V at which point the current sink is turned off. Next, the timing capacitor starts charging again and a new switching cycle begins. UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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Copyright © 2016, Texas Instruments Incorporated 8.4 mA VDDON VDDOFF CCT tON tOFF tPERIOD Figure 8-4. Oscillator Circuit While the device discharges the timing capacitor, resistor RRT continues attempting to charge CCT. It is the exact ratio of these two currents, the discharging versus the charging current, which specifies the maximum duty cycle. During the discharge time of C CT, the device output is always off. This represents an ensured minimum off time of the switch, commonly referred to as dead-time. To program an accurate maximum duty cycle, use the information provided in Figure 7-18for maximum duty cycle versus oscillator frequency. Any number of maximum duty cycles can be programmed for a given frequency by adjusting the values of RRT and CCT. After selecting the value of R RT, find the oscillator timing capacitance using the curves in Figure 7-1. However, because resistors are available in more precise increments, typically 1%, and capacitors are only available in 5% accuracy, it might be more practical to select the closest capacitor value first and then calculate the timing resistor value.

8.3.6 Oscillator Synchronization

Synchronization is best achieved by forcing the timing capacitor voltage above the oscillator internal upper threshold. A small resistor is placed in series with C CT to GND. This resistor serves as the input for the sync pulse which raises the C CT voltage above the oscillator internal upper threshold. The PWM is allowed to run at the frequency set by R RT and C CT until the sync pulse appears. This scheme offers several advantages including having the local ramp available for slope compensation. The UCCx8C5x oscillator must be set to a lower frequency than the sync pulse stream, typically 20 percent with a 0.5-V pulse applied across the resistor. RRT CCT VREF RT/CT GND Copyright © 2016, Texas Instruments Incorporated CCT SYNC SYNC CCT + SYNC Figure 8-5. Oscillator Synchronization Circuit

8.3.7 Soft-start Timing

The soft-start timing is the technique to gradually power up the converter in a well-controlled fashion by slowly increasing the effective duty cycle starting at zero and gradually rising. Following start-up of the PWM, the error amplifier inverting input is low, commanding the error amplifier’s output to go high. The output stage of the amplifier can source 1 mA typically, which is enough to drive most high impedance compensation networks, but not enough for driving large loads quickly. Soft-start timing is achieved by charging a fairly large value, >1-µF, capacitor (CSS) connected to the error amplifier output through a PNP transistor as shown in Figure 8-6 www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

Figure 8-6. Soft-Start Implementation The limited charging current of the amplifier into the capacitor translates into a dv/dt limitation on the error amplifier output. This directly corresponds to some maximum rate of change of primary current in a current mode controlled system as one of the PWM comparator inputs gradually rises. The values of R SS and C SS must be selected to bring the COMP pin up at a controlled rate, limiting the peak current supplied by the power stage. After the soft-start interval is complete, the capacitor continues to charge to VREF, effectively removing the PNP transistor from the circuit consideration. Soft-start timing offers a different, frequently preferred function in current mode controlled systems than it does in voltage mode control. In current mode, soft start controls the rising of the peak switch current. In voltage mode control, soft start gradually widens the duty cycle, regardless of the primary current or rate of ramp-up. The purpose of resistor R SS and the diode is to remove the soft-start capacitor from the error amplifier path during normal operation, after the soft-start period completes and the capacitor charges fully. The optional diode in parallel with the resistor forces a soft-start period each time the PWM goes through UVLO condition that forces VREF to go low. Without the diode, the capacitor remains charged during a brief loss of supply or brown-out, and the device does not emable a soft-start function upon re-application of VDD.

8.3.8 Enable and Disable

There are several ways to enable or disable the UCCx8C5x devices, depending on which type of restart is required. The two basic techniques use external transistors to either pull the error amplifier output low (< 2 V BE) or pull the current sense input high (> 1.1 V). Application of the disable signal causes the output of the PWM comparator to be high. The PWM latch is reset dominant so that the output remains low until the next clock cycle after the shutdown condition at the COMP or CS pin is removed. Another choice for restart without a soft-start period is to pull the current sense input above the cycle-by-cycle current limiting threshold. A logic level P-channel FET from the reference voltage to the current sense input can be used. COMP DISABLE Figure 8-7. Disable Circuit

8.3.9 Slope Compensation

With current mode control, slope compensation is required to stabilize the overall loop with duty cycles exceeding 50%. Although not required, slope compensation also improves stability in applications using below a 50% maximum duty cycle. Slope compensation is introduced by injecting a portion of the oscillator waveform to the actual sensed primary current. The two signals are summed together at the current sense input (CS) connection at the filter capacitor. To minimize loading on the oscillator, it is best to buffer the timing capacitor waveform with a small transistor whose collector is connected to the reference voltage. UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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0.1 µF RRT RRAMP CCSF RCSF RCS ISENSE Copyright © 2016, Texas Instruments Incorporated Figure 8-8. Slope Compensation Circuit

8.3.10 Voltage Mode

In certain applications, voltage mode control may be a preferred control strategy for a variety of reasons. Voltage mode control is easily executable with any current mode controller, especially the UCCx8C5x family members. Implementation requires generating a 0-V to 0.9-V sawtooth shaped signal to input to the current sense pin (CS) which is also one input to the PWM comparator. This is compared to the divided down error amplifier output voltage at the other input of the PWM comparator. As the error amplifier output is varied, it intersects the sawtooth waveform at different points in time, thereby generating different pulse widths. This is a straightforward method of linearly generating a pulse whose width is proportional to the error voltage. Implementation of voltage mode control is possible by using a fraction of the oscillator timing capacitor (CCT) waveform. This value can be divided down and fed to the current sense pin as shown in Figure 8-9 . The oscillator timing components must be selected to approximate as close to a linear sawtooth waveform as possible. Although exponentially charged, large values of timing resistance and small values of timing capacitance help approximate a more linear shaped waveform. A small transistor is used to buffer the oscillator timing components from the loading of the resistive divider network. Due to the offset of the oscillator’s lower timing threshold, a DC blocking capacitor is added. VREF RT/CT RRT CCT CS 2N2222 Figure 8-9. Current Mode PWM Used as a Voltage Mode PWM www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

8.4 Device Functional Modes

8.4.1 Normal Operation

During normal operating mode, the controller can be used in peak current mode or voltage mode control. When the converter is operating in peak current mode, the controller regulates the converter's peak current and duty cycle. When used in voltage mode control, the controller regulates the power converter's duty cycle. The regulation of the system's peak current and duty cycle can be achieved with the use of the integrated error amplifier and external feedback circuitry.

8.4.2 UVLO Mode

During the system start-up, VDD voltage starts to rise from 0 V. Before the VDD voltage reaches its corresponding turn-on threshold, the IC is operating in UVLO mode. During UVLO mode operation, the VREF pin voltage is not generated. When VDD is above 1 V and below the turn-on threshold, the VREF pin is actively pulled low. This behavior allows VREF to be used as a logic signal to indicate UVLO mode. If the bias voltage to VDD drops below the UVLO-OFF threshold, the PWM switching stops and VREF returns to 0 V. The device can be restarted by applying a voltage greater than the UVLO-ON threshold to the VDD pin. UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The UCCx8C5x controllers are peak current mode pulse width modulators. These controllers have an onboard amplifier and can be used in isolated and nonisolated power supply designs. The onboard totem pole gate driver is capable of delivering 1 A of peak current. This high-speed PWM is capable of operating at switching frequencies up to 1 MHz. As UCCx8C5x can be used to directly substitute UCCx8C4x by drop-in, the design steps are the same as those for UCCx8C4x . The same design example, including the layout, of UCCx8c4x is re-used for UCCx8C5x in the below. Figure 9-1 shows a typical off-line application using UCC38C44. C53 8REF 7VCC UCC38C44 C13 R16 R12 C12 D50 C52 D51 R10 R11 C18C1A BR1+ RT1 L50 C54 R55 R53 R56 C55 R52 SEC COMMON 12 V OUT R50 C50 C51R50 IC3 R54 A R K 5 V OUT IC2 IC2

1 COMP

4 RT/CT

100 V – 240 V

Copyright © 2016, Texas Instruments Incorporated Figure 9-1. Typical Off-Line Application Figure 9-2 shows a forward converter with synchronous rectification. This application provides 48 V to 3.3 V at

10 A with over 85% efficiency, and uses the UCC38C42as the secondary-side controller and UCC3961 as the

primary-side startup control device. www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

20k 40% C16 5.6nF C15 1uF C14 1uF C13 0.22uF C12 3300pF C11 1500pF BZX84C15LT1 UCC38C4x COMP FB CS RT/CT GND OUT VCC REF C22 4.7nF C23 680pF C24 0.1uF C10 2.7nF 4.7uH C21 0.1uF C20 470uF C19 470uF 3r3V PWRGND 1nF C18 4700pF C25 0.047uF VinN VinP 0.1uF UCC3961 4 FB 5 RT

6 REF

7 AGND 8VS

1 OVS

3 SS 12VDD

0.22uF 0.1uF C6 470pFC7 100pF 1uF C17 4700pF TPS2832 8BOOT1 IN 6BTLO3 DT 7HIDR

4 VCC

2 PGND

7.5k R17 20k R16 21.5k R15 50k R23 402 R24 20k R25 20k R12

200 R13

4.7R26 4.7 10k R21 32.4k 1.2k 2.4k 1.5k R5 76.8k 4.7 5.1k 0.33 R10 R11 46.4k R20 Copyright © 2016, Texas Instruments Incorporated Figure 9-2. Forward Converter with Synchronous Rectification Using the UCC38C42 as the Secondary- Side Controller

9.2 Typical Application

A typical application for the UCC28C42 controller in an off-line flyback converter is shown in Figure 9-3. The controller uses an inner current control loop that contains a small current sense resistor which senses the primary inductor current ramp. This current sense resistor transforms the inductor current waveform to a voltage signal that is input directly into the primary side PWM comparator. This inner loop determines the response to input voltage changes. An outer voltage control loop involves comparing a portion of the output voltage to a reference voltage at the input of an error amplifier. When used in an off-line isolated application, the voltage feedback of the isolated output is accomplished using a secondary-side error amplifier and adjustable voltage reference, such as the TL431. The error signal crosses the primary to secondary isolation boundary using an opto-isolator whose collector is connected to the VREF pin and the emitter is connected to FB. The outer voltage control loop determines the response to load changes. UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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VIN = 85 VAC to 265 VAC DBRIDGE CIN 180 µF RSNUB 50 k CSNUB 10 nF NP NS NA DCLAMP LP =1. 5 mH NP:NS = 10 NP:NA = 10 COUT 2200 µF VOUT 12 V, 4 A DOUT RVDD DBIAS COMP FB CS RT/CT 5 GND OUT VDD VREF UCC28C42 RBLEEDER 10 k CVREF 1 µF CVDD 120 µF RSTART 420 k RG RCS 0. 75 CSS RSS CCSF 100 pF RCSF 3. 8 k RP Not Populated QSW TL431 RFBU 9. 53 k RFBB 2. 49 k CCOMPz 0. 01 µF RCOMPz 88. 7 k 10 V CCOMPp 10 nF RFBG 4. 99 k RLED 1.3 k ROPTO 1 k OPTO- COUPLER RTLbias CVDDbp CRAMP 10 nF RRAMP RRT 15. 4 k CCT 1000 pF RCOMPp 10 k DZ 18 V 1 k Copyright © 2016, Texas Instruments Incorporated 24.9 k 0. 1 µF Figure 9-3. Typical Application Design Schematic www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

9.2.1 Design Requirements

Table 9-1 shows a typical set of performance requirements for an off-line flyback converter capable of providing 48 W at 12-V output voltage from a universal AC input. The design uses peak primary current control in a continuous current mode PWM converter. Table 9-1. Design Parameters PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VIN Input Voltage 85 115/230 265 VRMS fLINE Line Frequency 47 50/60 63 Hz VOUT Output Voltage IVOUT(min) ≤ IVOUT ≤ IVOUT(max) 11.75 12 12.25 V VRIPPLE Output Ripple Voltage IVOUT(min) ≤ IVOUT ≤ IVOUT(max) 100 mVpp IVOUT Output Current 0 4 A fSW Switching Frequency 110 kHz η Efficiency 85%

9.2.2 Detailed Design Procedure

This procedure outlines the steps to design an off-line universal input continuous current mode (CCM) flyback converter. See Figure 9-3 for component names referred to in the design procedure.

9.2.2.1 Input Bulk Capacitor and Minimum Bulk Voltage

Bulk capacitance may consist of one or more capacitors connected in parallel, often with some inductance between them to suppress differential-mode conducted noise. The value of the input capacitor sets the minimum bulk voltage;. Setting the bulk voltage lower by using minimal input capacitance results in higher peak primary currents leading to more stress on the MOSFET switch, the transformer, and the output capacitors. Setting the bulk voltage higher by using a larger input capacitor results in higher peak current from the input source and the capacitor itself is physically larger. Compromising between size and component stresses determines the acceptable minimum input voltage. The total required value for the primary-side bulk capacitance (C IN) is selected based upon the power level of the converter (P OUT), the efficiency target (η), the minimum input voltage (VIN(min)), and is chosen to maintain an acceptable minimum bulk voltage level (VBULK(min)), using Equation 3. CIN = 2 × PIN × F0.25 +1 N × arcsinF VBULK (min ) ¾2 × VIN(min ) GG k2 × VIN(min )

2 F VBULK (min )

2 o × fLINE (min ) (3) where

• VIN(min) is the RMS value of the minimum AC input voltage (85 VRMS) whose minimum line frequency is denoted as fLINE(min), equal to 47 Hz Based on Equation 3, to achieve a minimum bulk voltage of 75 V, assuming 85% converter efficiency, the bulk capacitor must be larger than 126 µF. this design uses a value of 180 µF, with consideration for component tolerances and efficiency estimation.

9.2.2.2 Transformer Turns Ratio and Maximum Duty Cycle

The transformer design begins with selecting a suitable switching frequency for the given application. The UCC28C42 is capable of switching up to 1 MHz but considerations such as overall converter size, switching losses, core loss, system compatibility, and interference with communication frequency bands generally determine an optimum frequency that should be used. For this off-line converter, the switching frequency (f SW) is selected to be 110 kHz as a compromise to minimize the transformer size and the EMI filter size, and still have acceptable losses. UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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The transformer primary to secondary turns ratio (N PS) can be selected based on the desired MOSFET voltage rating and the secondary diode voltage rating. Because the maximum input voltage is 265 VRMS, the peak bulk input voltage can be calculated as shown in Equation 4. VBULK (max ) = ¾2 × VIN (max ) N 375 V (4) To minimize the cost of the system, a readily available 650-V MOSFET is selected. Derating the maximum voltage stress on the drain to 80% of its rated value and allowing for a leakage inductance voltage spike of up to 30% of the maximum bulk input voltage, the reflected output voltage must be less than 130 V as shown in Equation 5. R EFLECTED DS(rated) BULK(max)V 0.8 V 1.3 V 130.2 V u u (5) The maximum primary to secondary transformer turns ratio (NPS) for a 12 V output can be selected as NPS = VREFLECTED VOUT = 10.85 (6) A turns ratio of NPS = 10 is used in the design example. The auxiliary winding is used to supply bias voltage to the controller. Maintaining the bias voltage above the VDD minimum operating voltage after turnon is required for stable operation. The minimum VDD operating voltage for the controller selected for this design is 10 V. The auxiliary winding is selected to support a 12 V bias voltage so that it is above the minimum operating level but maintains a low level of losses in the IC. The primary to auxiliary turns ratio (NPA) can be calculated from Equation 7: NPA = NPS × VOUT VBIAS = 10 (7) The output diode experiences a voltage stress that is equal to the output voltage plus the reflected input voltage: VDIODE = VBULK :max ; NPS + VOUT = 49.5 V (8) TI recommends a Schottky diode with a rated blocking voltage greater than 60 V to allow for voltage spikes due to ringing. The forward voltage drop (VF) of this diode is estimated to be equal to 0.6 V To avoid high peak currents, the flyback converter in this design operates in continuous conduction mode. Once NPS is determined, the maximum duty cycle (D MAX) can be calculated using the transfer function for a CCM flyback converter: VOUT + VF VBULK :min ; = l 1 NPS p × l DMAX

1 F DMAX

p (9) PS OUT F MAX BULK(min) PS OUT F N V VD 0.627V N V V u u (10) Because the maximum duty cycle exceeds 50%, and the design is an off-line (AC-input) application, the UCC28C42 is best suited for this application.

9.2.2.3 Transformer Inductance and Peak Currents

For this design example, the transformer magnetizing inductance is selected based upon the CCM condition. An inductance value that allows the converter to stay in CCM over a wider operating range before transitioning into discontinuous current mode is used to minimize losses due to otherwise high currents and also to decrease the www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

output ripple. The design of the transformer in this example sizes the inductance so the converter enters CCM operation at approximately 10% load and minimum bulk voltage to minimize output ripple. The inductor (LP) for a CCM flyback can be calculated using Equation 11. LP = 1 kVBULK :min ;o × l NPS × VOUT VBULK :min ; + NPS × VOUT p 0.1 × PIN × fSW (11) where

• PIN is estimated by dividing the maximum output power (POUT) by the target efficiency (η)
• fSW is the switching frequency of the converter For the UCC28C42 the switching frequency is equal to the oscillator frequency and is set to 110 kHz. Selecting fSW to be 110 kHz provides a good compromise between size of magnetics, switching losses, and places the first harmonic below the 150-kHz lower limit of EN55022. Therefore, the transformer inductance must be approximately 1.8 mH. A 1.5 mH inductance is chosen as the magnetizing inductance, LP, value for this design. Based on calculated inductor value and the switching frequency, the current stress of the MOSFET and output diode can be calculated. The peak current in the primary-side MOSFET of a CCM flyback can be calculated as shown in Equation 12. IPK MOSFET = PIN VBULK :min ; × NPS × VOUT VBULK :min ; + :NPS × VOUT ; + n VBULK (min ) 2 × Lm NPS × VOUT VBULK :min ; + :NPS × VOUT ; fSW r (12) The MOSFET peak current is 1.36 A. The RMS current of the MOSFET is calculated to be 0.97 A as shown in Equation 13. Therefore, IRFB9N65A is selected to be used as the primary-side switch. IRM SMOSFET = ¨DMAX 3 × l VBULK (min ) LP × fSW p F F DMAX 2 × IPKMOSFET × VBULK (min ) LP × fSW G + kDMAX × IPKMOSFET (13) The output diode peak current is equal to the MOSFET peak current reflected to the secondary side. IPK DIODE = NPS × IPK MOSFET = 13.634 A (14) The diode average current is equal to the total output current (4 A) combined with a required 60-V rating and 13.6-A peak current requirement, a 48CTQ060-1 is selected for the output diode.

9.2.2.4 Output Capacitor

The total output capacitance is selected based upon the output voltage ripple requirement. In this design, 0.1% voltage ripple is assumed. Based on the 0.1% ripple requirement, the capacitor value can be selected using Equation 15. COUT R IOUT × NPS × VOUT VBULK :min ; + NPS × VOUT 0.001 × VOUT × fSW = 1865 JF (15) To design for device tolerances, a 2200-µF capacitor was selected. UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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9.2.2.5 Current Sensing Network

The current sensing network consists of the primary-side current sensing resistor (R CS), filtering components RCSF and C CSF, and optional R P. Typically, the direct current sense signal contains a large amplitude leading edge spike associated with the turnon of the main power MOSFET, reverse recovery of the output rectifier, and other factors including charging and discharging of parasitic capacitances. Therefore, C CSF and R CSF form a low-pass filter that provides immunity to suppress the leading edge spike. For this converter, C CSF is chosen to be 100 pF. Without RP, RCS sets the maximum peak current in the transformer primary based on the maximum amplitude of the CS pin, which is specified to be 1 V. To achieve 1.36-A primary side peak current, a 0.75-Ω resistor is chosen for RCS. The high current sense threshold of CS helps to provide better noise immunity to the system but also results in higher losses in the current sense resistor. These current sense losses can be minimized by injecting an offset voltage into the current sense signal using R P. R P and R CSF form a resistor divider network from the current sense signal to the reference voltage of the controller (V VREF) which adds an offset to the current sense voltage. This technique still achieves current mode control with cycle-by-cycle over-current protection. To calculate required offset value (VOFFSET), use Equation 16. VOFFSET = RCSF RCSF + RP × VREF (16) After adding the RP resistance, adjust the RCS value accordingly.

9.2.2.6 Gate Drive Resistor

RG is the gate driver resistor for the power switch (Q SW). The selection of this resistor value must be done in conjunction with EMI compliance testing and efficiency testing. Using a larger resistor value for R G slows down the turnon and turnoff of the MOSFET. A slower switching speed reduces EMI but also increases the switching loss. A tradeoff between switching loss and EMI performance must be carefully performed. For this design, a 10‑Ω resistor was chosen for the gate drive resistor.

9.2.2.7 VREF Capacitor

A precision 5-V reference voltage performs several important functions. The reference voltage is divided down internally to 2.5 V and connected to the error amplifier’s noninverting input for accurate output voltage regulation. Other duties of the reference voltage are to set internal bias currents and thresholds for functions such as the oscillator upper and lower thresholds. Therefore, the reference voltage must be bypassed with a ceramic capacitor. A 1-µF, 16-V ceramic capacitor was selected for this converter. Placement of this capacitor on the physical printed-circuit board layout must be as close as possible to the respective VREF and GND pins.

9.2.2.8 RT/CT

RT/CT is the oscillator timing pin. For fixed frequency operation, set the timing capacitor charging current by connecting a resistor from VREF to RT/CT. Set the frequency by connecting timing capacitor from RT/CT to GND. For the best performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions. The controller's oscillator allows for operation to 1 MHz. The device uses an external resistor to set the charging current for the external capacitor, which determines the oscillator frequency. TI recommends timing resistor values from 1 kΩ to 100 kΩ and timing capacitor values from 220 pF to 4.7 nF. The UCCx8C5x oscillator is true to the curves of the original BiCMOS devices at lower frequencies, yet extends the frequency programmability range to at least 1 MHz. This programmability allows the device to offer pin-to-pin capability where required, yet capable of extending the operational range to the higher frequencies. See Figure 7-1 for component values for setting the oscillator frequency. www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

9.2.2.9 Start-Up Circuit

At start-up, the IC gets its power directly from the high-voltage bulk, through a high-voltage resistor (R START). The selection of the start-up resistor is the tradeoff between power loss and start-up time. The current flowing through RSTART at the minimum input voltage must be higher than the VDD current under UVLO conditions (100 µA at its maximum value). A resistance of 420-k Ω was chosen for R START, providing 250 µA of start-up current at low-line conditions. The start-up resistor is physically comprised of two 210-k Ω resistors in series to meet the high voltage requirements and power rating at high-line. After VDD is charged up above the UVLO-ON threshold, the UCC28C42 starts to consume full operating current. The VDD capacitor is required to provide enough energy to prevent its voltage from dropping below the UVLO-OFF threshold during start-up, before the output is able to reach its regulated level. A large bulk capacitance would hold more energy but would result in slower start-up time. In this design, a 120-µF capacitor is chosen to provide enough energy and maintain a start-up time of approximately 7 seconds. For faster start-up, the bulk capacitor value may be decreased or the RSTART resistor modified to a lower value.

9.2.2.10 Voltage Feedback Compensation

Feedback compensation, also called closed-loop control, can reduce or eliminate steady state error, reduce the sensitivity of the system to parametric changes, change the gain or phase of a system over some desired frequency range, reduce the effects of small signal load disturbances and noise on system performance, and create a stable system from an unstable system. A system is stable if its response to a perturbation is that the perturbation eventually dies out. A peak current mode flyback uses an outer voltage feedback loop to stabilize the converter. To adequately compensate the voltage loop, the open-loop parameters of the power stage must be determined.

9.2.2.10.1 Power Stage Poles and Zeroes

The first step in compensating a fixed frequency flyback is to verify if the converter is continuous conduction mode (CCM) or discontinuous conduction mode (DCM). If the primary inductance (L P) is greater than the inductance for DCM or CCM boundary mode operation, called the critical inductance (L Pcrit), then the converter operates in CCM: LP > LPcrit , then CCM (17) LPcrit = ROUT × :NPS ;2 2 × fSW × l VIN VIN + VOUT × NPS p (18) For the entire input voltage range, the selected inductor has a value larger than the critical inductor. Therefore, the converter operates in CCM and the compensation loop requires design based on CCM flyback equations. The current-to-voltage conversion is done externally with the ground-referenced R CS and the internal 2R/R resistor divider which sets up the internal current sense gain, A CS = 3. The exact value of these internal resistors is not critical but the IC provides tight control of the resistor divider ratio, so regardless of the actual resistor value variations their relative value to each other is maintained. The DC open-loop gain (G O) of the fixed-frequency voltage control loop of a peak current mode control CCM flyback converter shown in Equation 19 is approximated by first using the output load (R OUT), the primary to secondary turns ratio (NPS), and the maximum duty cycle (D) as calculated in Equation 20. GO = ROUT × NPS RCS × ACS × 1 :1 F D;2 RL + :2 × M; + 1 (19) In Equation 19 , D is calculated with Equation 20 , τ L is calculated with Equation 21 , and M is calculated with Equation 22. UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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D = NPS × VOUT VBULKmin + :NPS × VOUT ; (20) RL = 2 × LP × fSW ROUT × :NPS ;2 (21) M =VOUT × NPS VBULKmin (22) For this design, a converter with an output voltage (V OUT) of 12 V, and 48 W relates to an output load (R OUT) equal to 3 Ω at full load. With a maximum duty cycle of 0.627, a current sense resistance of 0.75 Ω, and a primary to secondary turns-ratio of 10, the open-loop gain calculates to 3.082 or 9.776 dB. A CCM flyback has two zeroes that are of interest. The ESR and the output capacitance contribute a left-half plane zero ( ωESRz) to the power stage, and the frequency of this zero (f ESRz), are calculated with Equation 23 and Equation 24. XESRz = 1 RESR × COUT (23) fESRz = 1 2 ×N × RESR × COUT (24) The fESRz zero for an output capacitance of 2200 µF and a total ESR of 43 mΩ is located at 1.682 kHz. CCM flyback converters have a zero in the right-half plane (RHP) in their transfer function. A RHP zero has the same 20 dB per decade rising gain magnitude with increasing frequency just like a left-half plane zero, but it adds a 90° phase lag instead of lead. This phase lag tends to limit the overall loop bandwidth. The frequency location (fRHPz) of the RHP zero ( ωRHPz) is a function of the output load, the duty cycle, the primary inductance (LP), and the primary to secondary side turns ratio (NPS). XRHPz = ROUT × :1 F D;2 × :NPS ;2 LP × D (25) fRHPz = ROUT × :1 F D;2 × :NPS ;2 2 × N × LP × D (26) The right-half plane zero frequency increases with higher input voltage and lighter load. Generally, the design requires consideration of the worst case of the lowest right-half plane zero frequency and the converter must be compensated at the minimum input and maximum load condition. With a primary inductance of 1.5 mH, at 75-V DC input, the RHP zero frequency (fRHPz) is equal to 7.07 kHz at maximum duty cycle, full load. The power stage has one dominate pole ( ωP1) which is in the region of interest, located at a lower frequency (fP1); which is related to the duty cycle, the output load, and the output capacitance, and calculated with Equation 28. There is also a double pole placed at half the switching frequency of the converter (f P2) calculated with Equation 30. For this example, pole fP1 is located at 40.37 Hz and fP2 is at 55 kHz. XP1 = :1 F D;3 RL + 1 + D ROUT × COUT (27) www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

fP1 = :1 F D;3 RL + 1 + D 2 ×N × ROUT × COUT (28) XP2 = N × fSW (29) fP2 = fSW (30)

9.2.2.10.2 Slope Compensation

Slope compensation is the large signal subharmonic instability that can occur with duty cycles that may extend beyond 50% where the rising primary side inductor current slope may not match the falling secondary side current slope. The subharmonic oscillation would result in an increase in the output voltage ripple and may even limit the power handling capability of the converter. The target of slope compensation is to achieve an ideal quality coefficient (QP), equal to 1 at half of the switching frequency. The QP is calculated with Equation 31. QP = 1 N × >MC × :1 F D; F 0.5? (31) where

• D is the primary side switch duty cycle
• MC is the slope compensation factor, which is defined with Equation 32 MC = Se Sn + 1 (32) where
• Se is the compensation ramp slope
• Sn is the inductor rising slope The optimal goal of the slope compensation is to achieve Q P = 1; upon rearranging Equation 32 the ideal value of slope compensation factor is determined: Mideal = N + 0.5

1 F D

(33) For this design to have adequate slope compensation, M C must be 2.193 when D reaches it maximum value of 0.627. The inductor rising slope (Sn) at the CS pin is calculated with Equation 34. Sn = VINmin × RCS LP = 0.038 V Js (34) The compensation slope (Se) is calculated with Equation 35. Se = :MC F 1; × Sn = 44.74 mV Js (35) The compensation slope is added into the system through R RAMP and R CSF. The C RAMP is an AC-coupling capacitor that allows the voltage ramp of the oscillator to be used without adding an offset to the current sense; UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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select a value to approximate a high-frequency short circuit, such as 10 nF, as a starting point and make adjustments if required. The R RAMP and R CSF resistors form a voltage divider from the oscillator charge slope and this proportional ramp is injected into the CS pin to add slope compensation. Choose the value of R RAMP to be much larger than the RRT resistor so that it does not load down the internal oscillator and result in a frequency shift. The oscillator charge slope is calculated using the peak-to-peak voltage of the RT/CT sawtooth waveform (VOSCpp) equal to 1.9 V, and the minimum ON time, as shown in Equation 37. tONmin = D fSW (36) SOSC = VOSCpp tONmin = 1.9 V

5.7 Js = 333 mV

(37) To achieve a 44.74-mV/µs compensation slope, R CSF is calculated with Equation 38. In this design, R RAMP is selected as 24.9 kΩ, a 3.8-kΩ resistor was selected for RCSF. RCSF = RRAMP SOSC Se F 1 (38)

9.2.2.10.3 Open-Loop Gain

Once the power stage poles and zeros are calculated and the slope compensation is determined, the power stage open-loop gain and phase of the CCM flyback converter can be plotted as a function of frequency. The power stage transfer function can be characterized with Equation 39. HOPEN :s; = G0 × l1 + s:f; XESRz p × l1 F s:f; XRHPz p 1 +s:f; XP1 × 1 1 + s:f; XP2 × QP + s:f;2 :XP2;2 (39) The bode for the open-loop gain and phase can be plotted by using Equation 40. GainOPEN :s; = 20 × log:HOPEN :s;; (40) See Figure 9-4 and Figure 9-5. frequency (Hz) Gain (dB) 1 10 100 1000 10000 100000 -25 -20 -15 -10 D001 Figure 9-4. Converter Open-Loop Bode Plot - Gain frequency (Hz) Phase (q) 1 10 100 1000 10000 100000 -180 -135 -90 -45 D002 Figure 9-5. Converter Open-Loop Bode Plot - Phase www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

9.2.2.10.4 Compensation Loop

The design of the compensation loop involves selecting the appropriate components so that the required gain, poles, and zeros can be designed to result in a stable system over the entire operating range. There are three distinct portions of the loop: the TL431, the opto-coupler, and the error amplifier. Each of these stages combines with the power stage to result in a stable robust system. For good transient response, the bandwidth of the finalized design must be as large as possible. The bandwidth of a CCM flyback, fBW, is limited to ¼ of the RHP zero frequency, or approximately 1.77 kHz using Equation 41. fBW = fRHPz (41) The gain of the open-loop power stage at f BW can be calculated using Equation 40 or can be observed on the Bode plot (Figure 9-4) and is equal to –19.55 dB and the phase at fBW is equal to –58°. The secondary side portion of the compensation loop begins with establishing the regulated steady state output voltage. To set the regulated output voltage, a TL431 adjustable precision shunt regulator is ideally suited for use on the secondary side of isolated converters due to its accurate voltage reference and internal op-amp. The resistors used in the divider from the output terminals of the converter to the TL431 REF pin are selected based upon the desired power consumption. Because the REF input current for the TL431 is only 2 µA, selecting the resistors for a divider current (I FB_REF) of 1 mA results in minimal error. The top divider resistor (R FBU) is calculated: RFBU = VOUT F REFTL431 IFB_REF (42) The TL431 reference voltage (REFTL431) has a typical value of 2.495 V. A 9.53-kΩ resistor is chosen for RFBU. To set the output voltage to 12 V, 2.49 kΩ is used for RFBB. RFBB = REFTL431 VOUT F REFTL431 × RFBU (43) For good phase margin, a compensator zero (f COMPz) is required and should be placed at 1/10th the desired bandwidth: fCOMPz = fBW (44) XCOMPz = 2 ×N × fCOMPz (45) With this converter, f COMPz should be set at approximately 177 Hz. A series resistor (R COMPz) and capacitor (CCOMPz) placed across the TL431 cathode to REF sets the compensator zero location. Setting C COMPz to 0.01 µF, RCOMPz is calculated: RCOMPz = 1 XCOMPz × CCOMPz (46) Using a standard value of 88.7 kΩ for RZ and a 0.01 µF for CZ results in a zero placed at 179 Hz. In Figure 9-3, RTLbias provides cathode current to the TL431 from the regulated voltage provided from the Zener diode (DREG). For robust performance, 10 mA is provided to bias the TL431 by way of the 10-V Zener and a 1-kΩ resistor is used for RTLbias. The gain of the TL431 portion of the compensation loop is calculated with Equation 47. UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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GTL431 :s; = lRCOMPz + 1 s(f) × CZCOMPz p × 1 RFBU (47) A compensation pole is required at the frequency of right half plane zero or the ESR zero, whichever is lowest. Based previous the analysis, the right half plane zero (f RHPz) is located at 7.07 kHz and the ESR zero (f ESRz) is at 1.68 kHz; therefore, for this design, the compensation pole must be put at 1.68 kHz. The opto-coupler contains a parasitic pole that is difficult to characterize over frequency so the opto-coupler is set up with a pull-down resistor (ROPTO) equal to 1 kΩ, which moves the parasitic opto-coupler pole further out and beyond the range of interest for this design. The required compensation pole can be added to the primary side error amplifier using R COMPp and C COMPp. Choosing RCOMPp as 10 kΩ, the required value of CCOMPp is determined using Equation 48. CCOMPp = 1 2 × N × fESRz × RCOMPp = 9.46 nF (48) A 10-nF capacitor is used for CCOMPp setting the compensation pole at 1.59 kHz. Adding a DC gain to the primary-side error amplifier may be required to obtain the required bandwidth and helps to adjust the loop gain as needed. Using 4.99 k Ω for R FBG sets the DC gain on the error amplifier to 2. At this point the gain transfer function of the error amplifier stage (G EA(s)) of the compensation loop can be characterized using Equation 49. GEA :s; = lRCOMPp RFBG p × F 1 1 + s:f; × CCOMPp × RCOMPp G (49) Using an opto-coupler whose current transfer ratio (CTR) is typically at 100% in the frequency range of interest so that CTR = 1, the transfer function of the opto-coupler stage (GOPTO(s)) is found using Equation 50. GOPTO (s) =CTR × ROPTO RLED (50) The bias resistor (R LED) to the internal diode of the opto-coupler and the pull-down resistor on the opto emitter (ROPTO) sets the gain across the isolation boundary. R OPTO has already been set to 1 k Ω but the value of R LED has not yet been determined. The total closed loop gain (G TOTAL(s)) is the combination of the open-loop power stage (H o(s)), the opto gain (GOPTO(s)), the error amplifier gain (G EA(s)), and the gain of the TL431 stage (G TL431(s)), as shown in Equation 51. GTOTAL :s; = HOPEN :s; × GOPTO :s; × GEA :s; × GTL431 :s; (51) The required value for R LED can be selected to achieve the desired crossover frequency (f BW). By setting the total loop gain equal to 1 at the desired crossover frequency and rearranging Equation 51, the optimal value for RLED can be determined, as shown in Equation 52. RLED Q HOPEN :s; × CTR × COPTO × GEA :s; × GTL431 :s; (52) A 1.3-kΩ resistor suits the requirement for RLED. Based on the compensation loop structure, the entire compensation loop transfer function is written as Equation 53. www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

GCLOSED :s; = HOPEN :s; × lCTR × ROPTO RLED p × lRCOMPp RFBG p × F 1 1 +ks × CCOMPp × RCOMPp oG × n RCOMPz + @ 1 s × CCOMPz A RFBU r (53) The final closed-loop bode plots are show in Figure 9-6 and Figure 9-7. The converter achieves a crossover frequency of approximately 1.8 kHz and has a phase margin of approximately 67°. TI recommends checking the loop stability across all the corner cases including component tolerances to ensure system stability. frequency (Hz) Gain (dB) 1 10 100 1000 10000 100000 -40 -20 D003 Figure 9-6. Converter Closed-Loop Bode Plot – Gain frequency (Hz) Degrees (q) 1 10 100 1000 10000 100000 -180 -135 -90 -45 D001 D004 Figure 9-7. Converter Closed-Loop Bode Plot – Phase

9.2.3 Application Curves

Figure 9-8. Primary Side MOSFET Drain to Source Voltage at 240-V AC Input (100 V/div) Figure 9-9. Primary Side MOSFET Drain to Source Voltage at 120-V AC Input (100 V/div) UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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CH1: Output Voltage AC Coupled, 200 mV/div CH4: Output Current, 1 A/div Figure 9-10. Output Voltage During 0.9-A to 2.7-A Load Transient Figure 9-11. Output Voltage Ripple at Full Load (100 mV/div) Figure 9-12. Output Voltage Behavior at Full Load Start-up (5 V/div)

10 Power Supply Recommendations

The absolute maximum supply voltage is 30 V of UCC28C52 , including any transients that may be present. If this voltage is exceeded, device damage is likely. Because no clamp is included in the device, the supply pin must be protected from external sources which could exceed the 30-V level. To prevent false triggering due to leading edge noises, an RC current sense filter may be required on CS. Keep the time constant of the RC filter well below the minimum on-time pulse width. To prevent noise problems with high-speed switching transients, bypass VREF to ground with a ceramic capacitor close to the IC package. A minimum of 0.1-µF ceramic capacitor is required. Additional VREF bypassing is required for external loads on the reference. An electrolytic capacitor may also be used in addition to the ceramic capacitor. www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

11 Layout

11.1 Layout Guidelines

11.1.1 Precautions

Careful layout of the printed board is a necessity for high-frequency power supplies. As the device-switching speeds and operating frequencies increase, the layout of the converter becomes increasingly important. This 8-pin device has only a single ground for the logic and power connections. This forces the gate-drive current pulses to flow through the same ground that the control circuit uses for reference. Thus, the interconnect inductance must be minimized as much as possible. One implication is to place the device (gate driver) circuitry close to the MOSFET it is driving. This can conflict with the need for the error amplifier and the feedback path to be away from the noise generating components. The single most critical item in a PWM controlled printed-circuit board layout is the placement of the timing capacitor. While both the supply and reference bypass capacitor locations are important, the timing capacitor placement is far more critical. Any noise spikes on the C CT waveform due to lengthy printed circuit trace inductance or pick-up noise from being in proximity to high power switching noise causes a variety of operational problems. Dilemmas vary from incorrect operating frequency caused by pre-triggering the oscillator due to noise spikes to frequency jumping with varying duty cycles, also caused by noise spikes. The placement of the timing capacitor must be treated as the most important layout consideration. Keep PC traces as short as possible to minimize added series inductance.

11.1.2 Feedback Traces

Try to run the feedback trace as far from the inductor and noisy power traces as possible. You would also like the feedback trace to be as direct as possible and somewhat thick. These two sometimes involve a trade-off, but keeping it away from EMI and other noise sources is the more critical of the two. If possible, run the feedback trace on the side of the PCB opposite of the inductor with a ground plane separating the two.

11.1.3 Bypass Capacitors

When using a low value ceramic bypass capacitor, it must be placed as close to the VDD pin of the device as possible. This eliminates as much trace inductance effects as possible and give the internal device rail a cleaner voltage supply. Using surface mount capacitors also reduces lead length and lessens the chance of noise coupling into the effective antenna created by through-hole components.

11.1.4 Compensation Components

For best stability, external compensation components must be placed close to the IC. Keep FB lead length as short as possible and FB stray capacitance as small as possible. TI recommends surface mount components here as well for the same reasons discussed for the filter capacitors. These must not be placed very close to traces with high switching noise.

11.1.5 Traces and Ground Planes

Make all of the power (high current) traces as short, direct, and thick as possible. It is good practice on a standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per ampere. The inductor, output capacitors, and output diode must be as close to each other possible. This helps reduce the EMI radiated by the power traces due to the high switching currents through them. This also reduces lead inductance and resistance as well, which in turn reduces noise spikes, ringing, and resistive losses that produce voltage errors. The grounds of the IC, input capacitors, output capacitors, and output diode, if applicable, must be connected close together directly to a ground plane. It would also be a good idea to have a ground plane on both sides of the PCB. This reduces noise as well by reducing ground loop errors as well as by absorbing more of the EMI radiated by the inductor. For multi-layer boards with more than two layers, a ground plane can be used to separate the power plane, where the power traces and components are, and the signal plane, where the feedback and compensation and components are, for improved performance. On multi-layer boards the use of vias is required to connect traces and different planes. It is good practice to use one standard via per 200 mA of current if the trace conducts a significant amount of current from one plane to the other. UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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Arrange the components so that the switching current loops curl in the same direction. Due to the way switching regulators operate, there are two power states. One state when the switch is ON and one when the switch is OFF. During each state there is a current loop made by the power components that are currently conducting. Place the power components so that during each of the two states the current loop is conducting in the same direction. This prevents magnetic field reversal caused by the traces between the two half-cycles and reduces radiated EMI. www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

11.2 Layout Example

Transformer => FBead CCOMPp RCOMPp RFBG Track To <= %XON&DSÅ MOSFET Heatsink Aux Cap S D G CSNUB RSNUB Wave Solder Direction ==> CVDD1 CVDD Track To <= Bulk Cap + TRANSFORMER AUX Winding ½ PRI Winding½ PRI Winding 22AWG Jumper Wire 22AWG Jumper Wires PCB Bottom-side View K AC E OPTO-ISOLATOR Copyright © 2016, Texas Instruments Incorporated Figure 11-1. UCCx8C4x Layout Example UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following: UC384x Provides Low-Cost Current-Mode Control (SLUA143)

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. www.ti.com UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: UCC28C53 UCC28C54 UCC28C55 UCC28C56H UCC28C57H UCC28C57L UCC28C59

12.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. UCC28C53, UCC28C54, UCC28C55 UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59 SLUSER8 – JUNE 2022 www.ti.com ADVANCE INFORMATION

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www.ti.com 10-Sep-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PUCC28C53DR ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 Samples PUCC28C54DR ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 Samples PUCC28C56HDR ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 Samples PUCC28C57HDR ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 Samples PUCC28C57LDR ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 Samples PUCC28C59DR ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

www.ti.com 10-Sep-2022 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC28C53, UCC28C54, UCC28C56H, UCC28C59 :

• Automotive : UCC28C53-Q1 , UCC28C54-Q1 , UCC28C56H-Q1 , UCC28C59-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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