PUCC256403DDB

Texas Instruments

UCC25640x LLC Resonant Controller with Ultra-Low Audible Noise and Standby Power

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Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCC256402, UCC256403, UCC256404 SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 UCC25640xLLCResonantController withUltra-LowAudibleNoiseandStandbyPower

1 Features

1• Optimized low power mode and burst mode algorithm – Burst mode with Soft-ON and Soft-OFF periods – Minimized audible noise at no load and standby – User option to disable burst mode – Opto-coupler low power operation – Efficiency performance exceeds DoE level VI and EU CoC Tier-2 External Power Supply Standards

Hybrid hysteretic control (HHC) – Best-in-class transient response – Fast exit from burst mode
Robust adaptive dead-time control
Integrated high-voltage gate driver with 0.6 A source and 1.2 A sink capability
Robust capacitive region (ZCS) avoidance scheme
Over temperature, output over voltage, input under voltage protection, three levels of over current protection
Integrated high voltage startup function
Active x-capacitor discharge function

2 Applications

SMPS power supply for TV
Lighting
AC-DC adapter
Power tools
Medical power supply
Multi-functional printer
Enterprise and cinema projector
PC power supply
Gaming console power supply

3 Description

The UCC25640x is a fully featured LLC controller with integrated high-voltage gate driver. It has been designed to pair with a PFC controller to provide a complete power system using a minimum of external components. The resulting power system is designed to meet the most stringent requirements for standby power without the need for a separate standby power converter. UCC25640x provides a highly efficient burst mode with soft-on and soft-off periods to minimize audible noise at standby operation. The burst power level and hysteresis are programmable, simplifying the optimization of efficiency and burst mode operation. Burst mode can also be disabled through pin configuration. UCC25640x uses hybrid hysteretic control to provide best in class line and load transient response. UCC25640x includes a range of features designed to make LLC converter operation well controlled and protected. It can be used with UCC28056 or UCC28064A PFC controllers, along with UCC24624 synchronous rectifier controller to offer a complete power supply solution. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) UCC256402 SOIC (14) 9.9 mm x 3.9 mm UCC256403 SOIC (14) 9.9 mm x 3.9 mm UCC256404 SOIC (14) 9.9 mm x 3.9 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic

12.3 Receiving Notification of Documentation Updates 67

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (August 2019) to Revision B Page

5 Device Comparison Table

Burst Soft On and Soft Off UCC256402 Yes No No No UCC256403 No No Yes Yes UCC256404 Yes Yes No Yes

6 Pin Configuration and Functions

NAME NO. BLK 4 I This pin is used to sense the LLC stage input voltage level. A resistor divider should be used to attenuate the signal before it is applied to this pin. The voltage level on this pin will determine when the LLC converter starts/stops switching. BW 8 I This pin is used to sense the output voltage through the bias winding. The sensed voltage is used for output over voltage protection. During startup, the pin is also used to program the ratio between the two burst mode thresholds (BMTL and BMTH). FB 5 I LLC stage control feedback input. The amount of current sourced from this pin will determine the LLC input power level. GND 11 G Ground reference for all signals. HB 14 I High-side gate-drive floating supply voltage. The bootstrap capacitor is connected between this pin and HS pin. A high voltage, high speed diode should be connected from RVCC to this pin to supply power to the high-side gate-driver during the period when the low-side MOSFET is conducting. HO 15 O High-side floating gate-drive output. HS 16 I High-side gate-drive floating ground. Current return for the high-side gate-drive current. HV 1 I Connects to internal HV startup JFET. For UCC256402 and UCC256404, this pin provides start up power for both PFC and LLC stage. This pin also monitors the AC line voltage for x- capacitor discharge function. For UCC256403, this pin needs to be connected to ground. ISNS 6 I Resonant current sense. The resonant capacitor voltage is differentiated with a first order filter to measure the resonant current. LL/SS 9 I The capacitance value connected from this pin to ground will impact the duration of the soft- start period. The resistor divider connected to the pin will define the initial voltage applied on the pin for startup. After system startup, this pin is used to program the burst mode threshold. LO 10 O Low-side gate-drive output. Missing 2 N/A Functional creepage and clearance Missing 13 N/A Functional creepage and clearance RVCC 12 P Regulated 13-V supply. This pin is used to supply the gate driver and PFC controller. VCC 3 P Supply input. VCR 7 I Resonant capacitor voltage sense.

UCC256402, UCC256403, UCC256404 www.ti.com SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted), all voltages are with respect to GND, currents are positive into and negative out of the specified terminal.(1) MIN MAX UNIT Input voltage HV, HB -0.3 640 V BLK, LL/SS -0.55 7.2 V VCR -0.8 Internally Clamped V HB - HS -0.3 17 V VCC -0.55 30 V BW, ISNS -5 7.2 V RVCC output voltage DC -0.3 17 V HO output voltage DC HS – 0.3 HB + 0.3 V Transient, less than 100ns HS - 2 HB + 0.3 LO output voltage DC -0.3 RVCC + 0.3 V Transient, less than 100ns -2 RVCC + 0.3 Floating ground slew rate dVHS/dt -50 50 V/ns HO, LO pulsed current IOUT_PULSED -0.6 1.2 A Junction temperature range TJ -40 150 Storage temperature range, Tstg Tstg -65 150 Lead temperature Soldering, 10 second 300 Reflow 260 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, HV, HO, HS, HB pins(1) ±1000 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all other pins(1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500

7.3 Recommended Operating Conditions

All voltages are with respect to GND, -40°C< TJ =TA < 125°C, currents are positive into and negative out of the specified terminal, unless otherwise noted. MIN NOM MAX UNIT HV, HS Input voltage 600 V VCC Supply voltage 13 15 26 V

7.4 Thermal Information

THERMAL METRIC(1) UCC256403/UCC256404 UNITD (SOIC)

14 PINS

RθJA Junction-to-ambient thermal resistance 74.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 30.7 °C/W RθJB Junction-to-board thermal resistance 31.8 °C/W ΨJT Junction-to-top characterization parameter 4.4 °C/W ΨJB Junction-to-board characterization parameter 31.4 °C/W

7.5 Electrical Characteristics

All voltages are with respect to GND, -40°C< TJ =TA < 125°C, VCC =15V, currents are positive into and negative out of the specified terminal, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE VCCShort Below this threshold, use reduced start up current UCC256402, UCC256404 0.3 0.5 0.8 V VCCReStartJfet Below this threshold, re-enable JFET. UCC256402, UCC256404 9.35 9.65 9.95 V VCCStartSelf Startup when VCC is above this level UCC256402, UCC256404 25 26 28 V VCCStartSwitching Startup when VCC is above this level UCC256403 10.9 V VCCUVLOrising VCC under voltage lockout voltage (rising) 7.85 8.25 8.70 V VCCUVLOHYS VCC under voltage lockout voltage hysteresis 0.15 0.25 0.35 V SUPPLY CURRENT ICCSleep Current drawn from VCC rail during burst off period 650 780 950 µA ICCRun Current drawn from VCC Pin while gate is switching. Excluding Gate Current Dead time = 1us maximum dead time 1.8 2.2 2.7 mA REGULATED SUPPLY VRVCC Regulated supply voltage VCC = 15V, no load 12.7 13 13.45 V Regulated supply voltage VCC = 15V, 100mA load 12.4 13 13.45 V Regulated supply voltage VCC = 13V, no load 12.7 12.98 V Regulated supply voltage VCC = 13V, 30mA load 12.4 12.6 V

UCC256402, UCC256403, UCC256404 www.ti.com SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) All voltages are with respect to GND, -40°C< TJ =TA < 125°C, VCC =15V, currents are positive into and negative out of the specified terminal, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) Ensured by characterization, not production tested. (2) Ensured by design, not production tested. VRVCCUVLO RVCC under voltage lock out voltage 6.5 7 7.5 V HIGH VOLTAGE STARTUP IHVLow Reduced startup pin current VHV=20V, VCC = 0V 0.3 0.5 0.65 mA IHVHigh Full startup pin current VHV=20V, VCC = 4V 7.6 10.20 13.5 mA IHVLeak HV current source leakage current VHV=600V 1 4 µA IHVZCD Highest AC zero crossing detection test current 1.4 1.7 2.1 mA IHVZCDStep AC zero crossing detection test current steps 0.38 mA IXCAPDischarge X-cap discharge current 8.9 11.5 13.5 mA Vzero-crossing HV pin voltage threshold that zero- crossing is detected 8 9 11 V tXCAPZCD AC zero crossing detection window length for first three test current stage (1) 10 12 14 ms tXCAPZCDLast AC zero crossing detection window length for final test current stage (1) 43 46 52 ms tXCAPIdle AC zero crossing detection idle period length (1) 635 700 772 ms tXCAPDischarge Time for X-cap discharge current active (1) 327 360 390 ms tXCAPJFETON Time of first X-cap detection after JFETON (1) 12 ms BULK VOLTAGE SENSE VBLKStart BLK voltage that allows LLC to start switching For UCC256402, UCC256403 2.94 3 3.06 V For UCC256404 0.98 1 1.02 V VBLKStop BLK voltage that forces LLC operation to stop For UCC256402, UCC256403 2.15 2.2 2.25 V For UCC256404 0.88 0.9 0.925 V FEEDBACK PIN RFBInternal Internal pull down resistor value 90 100 110 kΩ IFB FB internal current source For UCC256402, UCC256404 73 82 91 µA For UCC256403 147 164 182 µA VFB FB pin voltage when FB pin sink current is at (IFB - 50uA) 5.6 V ΔVFB FB pin voltage variation when FB pin sink current ranges from (IFB - 50uA) to (IFB - 5uA) 0.28 V ΔVclamp FB pin voltage variation when FB pin sink current ranges from (IFB - 5uA) to (IFB + 5uA) 0.4 V IFBclamp Maximum FB internal current source when FB is clamped 82 μA ΔVFBclamp FB pin voltage variation when FB pin sink current ranges from (IFB + 5uA) to (IFB + IFBClamp - 5uA) 0.25 V f-3dB Feedback chain -3dB cut off frequency (2)

1 MHz

UCC256402, UCC256403, UCC256404 SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) All voltages are with respect to GND, -40°C< TJ =TA < 125°C, VCC =15V, currents are positive into and negative out of the specified terminal, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (3) IMismatch calculated as [IPU-(IPD+IPU)/2]/[(IPD+IPU)/2] VISNS_OCP1 OCP1 threshold 3.9 4 4.1 V VISNS_OCP1_SS OCP1 threshold during soft start 4.85 5 5.15 V VISNS_OCP2 OCP2 threshold 0.57 0.6 0.63 V VISNS_OCP3 OCP3 threshold 0.40 0.43 0.46 V tISNS_OCP2 The time the average input current needs to stay above OCP2 threshold before OCP2 is triggered (1) 2 ms tISNS_OCP3 The time the average input current needs to stay above OCP3 threshold before OCP3 is triggered (1) 50 ms VIpolarityHyst Resonant current polarity detection hysteresis 16 30 44 mV nOCP1 Number of OCP1 cycles before OCP1 fault is tripped (1) RESONANT CAPACITOR VOLTAGE SENSE VCM Internal common mode voltage 2.90 3 3.14 V IRAMP Frequency compensation ramp current source value 1.84 2 2.16 mA IMismatch Pull up and pull down ramp current source mismatch (3) -1.25 1.25 % GATE DRIVER VLOL LO output low voltage Isink = 20mA 0.02 0.05 0.12 V VRVCC - VLOH LO output high voltage Isource = 20mA 0.10 0.18 0.3 V VHOL - VHS HO output low voltage Isink = 20mA 0.02 0.05 0.12 V VHB - VHOH HO output high voltage Isource = 20mA 0.10 0.18 0.3 V VHB-HSUVLOFall High side gate driver UVLO falling threshold 6.6 7.25 7.75 V VHB-HSUVLOHys High side gate driver UVLO threshold hysteresis 0.78 0.9 1.05 V Isource_pk_HO HO peak source current (2) -0.6 A Isource_pk_LO LO peak source current (2) -0.6 A Isink_pk_HO HO peak sink current (2) 1.2 A Isink_pk_LO LO peak sink current (2) 1.2 A BOOTSTRAP IBOOT_QUIESCENT (HB - HS) quiescent current HB - HS = 12V 42 62 80 µA IBOOT_LEAK HB to GND leakage current VHB=600V 0.40 5.40 µA tChargeBoot Length of charge boot state 230 265 300 µs SOFT START AND BURST MODE ISSUp Current output from SS pin to charge up the soft start capacitor 26 36 45 µA RSSDown SS pin pull down resistance ZCS or OCP1 300 370 450 Ω tSSInitVolPrgm SS initial voltage programming time (1) 720 776 830 µs RLL LL/SS voltage scaling resistor value 92 98 106 kΩ Nburst Minimum number of pulses in each burst packet (including burst soft on/off pulses)

UCC256402, UCC256403, UCC256404 www.ti.com SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) All voltages are with respect to GND, -40°C< TJ =TA < 125°C, VCC =15V, currents are positive into and negative out of the specified terminal, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Nsoftmax Maximum number of pulses for burst soft on/off 7 Ksoft Minimal ratio of Vcomp/VFBreplica during burst soft on/off 0.33 VLLVolPrgm LL pin voltage during the burst mode exit threshold (BMTH) programming 3.5 V BMTHmin Minimal burst mode exit threshold 0.2 V BMTLmin Minimal burst mode entry threshold 0.2 V BIAS WINDING VBWOVPos Output voltage OVP - Positive Threshold 3.86 4 4.12 V VBWOVNeg Output voltage OVP - Negative Threshold -4.12 -4 -3.86 V nBWOV Number of BW OVP cycles before BW OVP fault is tripped (1) 5 IBWPrgm BW pin sourcing current for BMTL/BMTH programming 51 54 57 µA tBWPrgm BMTL/BMTH programming time 2 ms KBMTL/BMTH1 Ratio of BMTL/BMTH Option 1 0.95 KBMTL/BMTH2 Ratio of BMTL/BMTH Option 2 1 KBMTL/BMTH3 Ratio of BMTL/BMTH Option 3 0.9 KBMTL/BMTH4 Ratio of BMTL/BMTH Option 4 0.8 KBMTL/BMTH5 Ratio of BMTL/BMTH Option 5 0.6 KBMTL/BMTH6 Ratio of BMTL/BMTH Option 6 0.6 KBMTL/BMTH7 Ratio of BMTL/BMTH Option 7 (Burst mode disable) 0.4 RBWPrgm1 BW pin equivalent resistance to choose BMTL/BMTH ratio option 1 (2) 24730 Ω RBWPrgm2 BW pin equivalent resistance to choose BMTL/BMTH ratio option 2 (2) 17125 19976 Ω RBWPrgm3 BW pin equivalent resistance to choose BMTL/BMTH ratio option 3 (2) 12562 13624 Ω RBWPrgm4 BW pin equivalent resistance to choose BMTL/BMTH ratio option 4 (2) 9018 9813 Ω RBWPrgm5 BW pin equivalent resistance to choose BMTL/BMTH ratio option 5 (2) 6478 6849 Ω RBWPrgm6 BW pin equivalent resistance to choose BMTL/BMTH ratio option 6 (BMTL=BMTLmin) (2) 4450 4732 Ω RBWPrgm7 BW pin equivalent resistance to choose BMTL/BMTH ratio option 7 (Burst mode disable) (2) 2422 3038 Ω ADAPTIVE DEADTIME dVHS/dt Detectable slew rate (1) -0.1 -50 V/ns FAULT RECOVERY tPauseTimeOut Paused timer (1) 1 s

7.6 Switching Characteristics

All voltages are with respect to GND, -40°C< TJ =TA < 125°C, VCC =15V, currents are positive into and negative out of the specified terminal, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr(LO) Rise time 10% to 90%, 1nF load 30 50 ns tf(LO) Fall time 10% to 90%, 1nF load 20 50 ns tr(HO) Rise time 10% to 90%, 1nF load 30 50 ns tf(HO) Fall time 10% to 90%, 1nF load 20 50 ns tDT(min) Minimum dead time (1) 100 ns tDT(max) Maximum dead time (dead time fault) (1) ZCS event is not detected 1.1 µs tDT(max_ZCS) Maximum dead time (dead time fault) (1) ZCS event is detected 150 µs tON(min) Minimum gate on time (1) 250 ns tON(max) Maximum gate on time (1) 16 µs

7.7 Typical Characteristics

Figure 1. IHVHigh vs Temperature Figure 2. IHVLow vs Temperature Figure 3. IHVLeak vs Temperature Figure 4. IBOOT_QUIESCENT vs Temperature Figure 5. IBOOT_LEAK vs Temperature Figure 6. IRAMP vs Temperature

Figure 25. VCCReStartJfet vs Temperature

8 Detailed Description

8.1 Overview

The UCC25640x is a fully featured LLC resonant controller for AC/DC power supplies. The high level of integration of UCC25640x enables significant reduction of component count and solution size without compromising functionality. UCC25640x achieves very low standby power and low audible noise standby operation using an optimized burst mode. The device's novel control scheme offers excellent transient performance. Many consumer applications, including large screen televisions, AC-DC adapters, industrial power supplies, and LED drivers, employ PFC + LLC power supplies because they offer improved efficiency, and small size, compared with a PFC + flyback topology. A disadvantage of the PFC + LLC power supply system is that it has poor light load efficiency and high no-load power consumption because the LLC stage requires a minimum amount of circulating current to maintain regulation. To meet light load efficiency and standby power consumption requirements, traditionally an auxiliary flyback converter is used. It runs continuously to allow the main PFC + LLC power system to be shut down when the system enters low power or standby mode. UCC25640x contains a number of novel features that enable it to offer excellent light load efficiency and low no- load power. This will allow power supply designers to create systems that meet the stringent no-load power target without needing an auxiliary flyback converter. UCC25640x uses a novel control algorithm, Hybrid Hysteretic Control (HHC), to achieve regulation. In this control algorithm, the switching frequency is defined by the resonant capacitor voltage, which carries accurate input current information. This allows the controller to monitor and correct the input current directly. Compared with traditional Direct Frequency Control (DFC), HHC makes the system close to a first order system if the frequency control portion is small. This enables excellent load and line transient response. UCC25640x adopts an advanced burst mode to meet the stringent requirements on standby power consumption and audible noise level. At low output power levels UCC25640x automatically transitions into light-load burst mode. In burst mode, UCC25640x repetitively delivers a burst packet with a fixed number of switching pulses and a shut-off period. The shut-off time period between burst packets is terminated by the secondary regulator loop based on the FB pin current. The LLC equivalent load current level during the burst on period is a programmable value. For each burst packet, the switching frequency slowly ramps down at the first few switching periods and ramps up at the last few switching periods, to slowly ramp up and ramp down the resonant current during burst operation. This burst soft-on and soft-off can effectively help to minimize the audible noise during burst mode operation. In addition, UCC25640x operates in a low power mode during burst mode with a very low quiescent current and biased optocoupler operation with low current. UCC25640x monitors the half-bridge switch node to determine the required dead-time for the gate signals. In this way the dead-time is automatically adjusted to provide optimum efficiency and robust operation. UCC25640x includes a slew rate detector with improved sensitivity of the switch node voltage for adaptive dead-time that makes its operation inherently robust compared with alternative parts. UCC25640x includes high and low-side drivers that can directly drive N-channel MOSFETs in an LLC power stage. This allows complete and fully featured power systems to be realized with minimum component count. UCC256402 and UCC256404 includes a high-voltage startup JFET to initially charge the VCC capacitor to provide the energy needed to start the PFC and LLC power system. Once running, power for the PFC and LLC controllers is derived from a bias winding on the LLC transformer. UCC256404 also includes the active x- capacitor discharge feature to discharge the remaining voltage on the x-capacitor of the EMC filters after unplugging the AC input. UCC256403 does not include the high voltage startup and active x-capacitor discharge features. It requires an auxiliary supply to power the VCC. UCC25640x includes robust algorithms for avoiding the zero-current switching (ZCS) operation region. When ZCS operation is detected, UCC25640x overrides the feedback signal and ramps up the switching frequency until non-capacitive operation is restored. After which the switching frequency is ramped back down at a rate determined by the soft-start capacitor until control has been handed back to the voltage control loop.

UCC256402, UCC256403, UCC256404 www.ti.com SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Overview (continued) Additional protection features of UCC25640x include three-level over current protection (OCP), output over voltage protection (OVP), input voltage under-voltage protection (UVP), gate driver under-voltage lock-out (UVLO) protection, and over temperature protection (OTP). The key features of UCC25640x can be summarized as follows:

Hybrid Hysteretic Control helps achieve best-in-class load and line transient response
Optimized light load burst mode enables less than 150-mW standby power designs
Burst soft-on and soft-off enables ultra-quiet standby operation
Robust adaptive dead time control
Integrated high-voltage gate driver
Integrated high-voltage startup for UCC256402 and UCC256404
Active x-capacitor discharge for UCC256404
Improved capacitive region operation prevention scheme
Comprehensive protection feature set

HV Startup ctrl & AC disconnect detect VCCReStartJfet VCCShort VCCStartSwitching HVFetOnOff Line Neutral RHV Bias winding or external supply HV Start Up FET VCCShort HO LO HSON LSON WaveGenEn HB HS Level Shift Adaptive Dead Time High Voltage Isolation Wake Up Control Active/Low Power To RVCC SlewDone_H2L BLKStartTh BLK BLKStart BLKStopTh BLKStop BW ISNS IPolarity OCP1Th OCP2 OCP2Th OCP3Th OCP3 VCM OCP1 +AverageMUX HSON RISNS VCR HSRampOn LSRampOn AVDD FBReplicaFeedback Opto- coupler RFB GND FB VCC ZCS ChargeSS SS Pick lower value Rdischarge LL/SS AVDD Pick higher value Vcm VCR VCM Waveform generator IPolarity SlewDone_H2L WaveGenEn ZCS HSON LSON System states and faults OVP OCP1 OCP2 OCP3 BLKStart BLKStop LDO RVCC RVCC To RVCC CISNSTo resonant capacitor VCM AVDD MUX AVDD SSEnd MUX SSEnd SS CtrlSSEn FBLessThanSS ZCS ChargeSS SSEnd FBLessThanBMT RVCCEn RVCCUVLO RVCCUVLO VCCReStartJfet VCCStartSwitching XcapDischarge ACZeroCrossing ACZeroCrossing HSRampOn LSRampOn Temperature sensor OTP OTP VCCClampEn SSEn HVFetOn XcapDischarge RVCCEn VCCClampEn FBLessThanBMT BMTL:BMTH 85µA max VSS_INITIAL Gen OVPTh OVPTh - OVP IFB UCC256402, UCC256403, UCC256404 SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

8.2 Functional Block Diagram

V V V 2 comp TH CM V V V 2 UCC256402, UCC256403, UCC256404 www.ti.com SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Hybrid Hysteretic Control

UCC25640x uses a novel control scheme, Hybrid Hysteretic Control (HHC), to achieve best-in-class line and load transient performance. The control method makes the compensator easier to design. The control method also makes light load management easier and more efficient. Improved line transient enables lower bulk capacitor and output capacitor value, reducing system cost. HHC is a control method which combines traditional frequency control and charge control. It is a charge control with added frequency compensation ramp. Compared with traditional frequency control, it changes the power stage transfer function from a second order system to a first order system, so that it makes the compensation network design easier. The control effort is directly related to input current, so the line and load transients are best-in-class. Compared with charge control, Hybrid Hysteretic Control avoids instability by adding in a frequency compensation ramp. The frequency compensation ensures system stability, and makes the output impedance lower as well. Lower output impedance makes the transient performance better than charge control. The frequency compensation also makes the implementation of burst mode soft-on and soft-off much easier, as changing the control effort can directly impact the switching frequency. For burst mode soft-on and soft-off, the converter switching frequency needs to be adjusted to achieve a reduced resonant current. In summary, HHC solves the following problems:

Help LLC converters achieve best in class load transient and line transient
Changes the small-signal transfer function to a first order system to easily achieve very high bandwidth
Inherently stable via frequency compensation
Makes burst mode control easier to optimize light load efficiency
Makes the implementation of burst mode soft-on and soft-off much easier, to achieve lower audible noise Figure 26 shows the HHC implementation in UCC25640x: a capacitor divider (C1 and C2) and two well matched controlled current sources. The resonant capacitor voltage is divided down by the capacitor divider formed by C1 and C2. The current sources are controlled by the gate drive signals. When the high-side switch is on, the upper current source injects a constant current into the capacitor divider; when the low-side switch is on, the lower current source pulls the same amount of constant current out of the capacitor divider. The two current sources add a triangular compensation ramp to the VCR node. The current sources are supplied by a reference voltage AVDD. AVDD needs to be equal to or larger than twice the common mode voltage VCM. The divided resonant capacitor voltage and the compensation ramp voltage are then added together to get the VCR node voltage. If the frequency compensation ramp dominates, the VCR node voltage will look like a triangular waveform, and the control will be similar to direct frequency control. If the resonant capacitor voltage dominates, the shape of the VCR node voltage will look like the actual resonant capacitor voltage, and the control will be similar to charge control. This is why the control method is called “hybrid” and the compensation ramp is called frequency compensation. This set up has an inherent negative feedback to keep the high-side and low-side on-time balanced, and also to keep the common mode voltage at VCR node at VCM. There are two input signals needed for the new control scheme: VCR and VCOMP. VCR is the sum of the scaled down version of the resonant capacitor voltage and the frequency compensation ramp. VCOMP is the voltage loop compensator output. The waveform below shows how the high-side and low-side switches are controlled based on VCR and VCOMP. The common mode voltage of VCR is VCM. Based on VCOMP and VCM (3 V), two thresholds: VTH and VTL are created. (1) (2) The VCR voltage is compared with the two thresholds. When VCR > VTH, the high-side switch is turned off; when VCR < VTL, low-side switch is turned off. HO and LO turn on edges are controlled by the adaptive dead time circuit.

8.3.2 Regulated 13-V Supply

8.3.3 Feedback Chain

normal soft start followed by a ZCS event, and load step into burst mode, and then exiting burst mode.

Optocoupler feedback signal input and bias
FB voltage clamp
Soft start function selection by a "pick lower value" block
Burst mode selection by a "pick higher value" block
Convert single ended feedback demand into two thresholds VTH and VTL; and VCR comparison with the thresholds and the common mode voltage VCM

Figure 28. Feedback Chain Block Diagram

Figure 29. Feedback Chain Timing Diagram

8.3.3.1 Optocoupler Feedback Signal Input and Bias

by the system. To achieve very low standby power it is necessary to drive the optocoupler in a low current mode.

8.3.3.2 FB Pin Voltage Clamp

As shown in the Optocoupler Feedback Signal Input and Bias section, the FBreplica decreases while Iopto increases. When Iopto reaches the value of IFB, the FB pin voltage starts to drop because there is no current flow through the PMOS. FB pin pulled low will impact the system transient response, due to the extra delay introduced by charging the parasitic capacitor of the optocoupler to pull up the FB pin voltage. A FB pin voltage clamp circuit is used to prevent this scenario. When FB pin voltage drops below the FB pin clamp voltage threshold, an extra current source is turned on to clamp the FB voltage. The clamp strength is IFBclamp. The FB pin clamp circuit improves the system transient performance from light load to heavy load. 8.3.3.3 "Pick Lower Value" Block and Soft Start Multiplexer This part of the circuit consists of 3 elements:

A pick lower block
A MUX which selects AVDD or SS signal as the second input to the pick lower block
A SS control block which handles the charge and discharge of the SS capacitor in the case of a ZCS fault The pick lower block has two inputs. The first input is FBreplica. The second input is selected between AVDD and SS pin voltage. The output of the block is the lower of the two inputs. The MUX selects between SS and AVDD. The selection is based on SSEnd (soft start end) signal, which is an output of the SS Ctrl block. SSEnd is high when SS is higher than FBreplica, and the soft start process has been initiated by the state machine, and there is no ZCS condition. Switching to AVDD after soft start has ended helps make sure that during non-soft start or non-ZCS fault condition, FBreplica signal is always sent through the pick lower block. It also releases the SS pin to perform the light load threshold programming. The SS control block handles the charge and discharge of the SS capacitor in the case of a ZCS fault. It resets the SSEnd signal when ZCS happens, so the effect of pulling down on SS pin to increase the switching frequency can pass through the pick lower block.

8.3.3.4 Pick Higher Block and Burst Mode Multiplexer

The output of the pick lower block goes into a pick higher block, which selects the higher of the pick lower block output and the burst mode threshold setting. The burst mode multiplexer selects between burst mode threshold (BMT) and ground. During soft start, the multiplexer selects ground. The startup process is open loop and controlled by the soft start ramp. Burst mode is not enabled during soft start phase. After soft start, the higher of the two inputs are sent to the differential amplifier. The output of the block is FBLessThanBMT. It is sent to the waveform generator state machine to control burst mode and system external shut down.

8.3.3.5 VCR Comparators

The output of the pick higher block is sent to a differential amplifier to convert the signal into two thresholds symmetrical to VCM. The difference between the two thresholds VTH and VTL equals the input amplitude. The VCR pin voltage is then compared with VTH, VTL, and VCM. The results are sent to the waveform generator.

8.3.4 Resonant Capacitor Voltage Sensing

The resonant capacitor voltage sense pin senses the resonant capacitor voltage through a capacitor divider. reduce the startup peak current, and help the VCR voltage to settle down quickly during burst mode. Figure 30. VCR Block Diagram at the falling edge of the high-side on or low-side on signal. Figure 31. VCR Compensation Ramp Current On/Off can be achieved by adjusting the ratio between Vdiv and Vramp.

8.3.5 Resonant Current Sensing

when the OCP2/OCP3 comparators output high for continuous 2 ms or 50 ms, will the faults be activated. threshold OCP1Th directly. The peak resonant current is checked once per cycle on the positive half cycle. OCP1 comparator output of the first 15 cycles are ignored. Figure 32. ISNS Block Diagram

8.3.6 Bulk Voltage Sensing

Bulk voltage level when LLC starts switching – VBLKStart
Bulk voltage level when LLC stops switching – VBLKStop A resistor divider is connected to the pin, to achieve the desired system input range. A fault is triggered if BLK pin voltage drops lower than VBLKStop during operation. The detailed action of Input Under Voltage Protection is described in Input Under Voltage Protection (VINUVP) section. Figure 33 shows the block diagram of the BLK pin.

Figure 33. BLK Pin Block Diagram

8.3.7 Output Voltage Sensing

voltage sense block is shown below. Figure 34. Bias Winding Sensing Block Diagram during an OVP fault are described in the Bias Winding Over Voltage Protection (BWOVP) section.

8.3.8 High Voltage Gate Driver

LO is the low-side gate driver output. The gate driver is supplied by the 13-V RVCC rail. bias rail, respectively, of the high-side driver, and HO connects to the gate of the upper half-bridge MOSFET. DBOOT, and capacitor CBOOT is charged to RVCC minus the forward drop on the diode. During periods when the upper half-bridge MOSFET is conducting, HS is connected to the LLC input voltage rail. At this time the HV diode is reverse biased and the high-side driver is powered by the charge stored in CBOOT. driver UVLO is implemented on RVCC; the high-side gate driver UVLO is implemented on (HB - HS) voltage. low power mode to reduce power consumption. The block diagram of the gate driver is shown in Figure 35. Figure 35. Gate Driver Block Diagram

8.3.8.1 Adaptive Dead Time Control

channel. Optimized dead time can help to minimize the power loss.

UCC256402, UCC256403, UCC256404 SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Feature Description (continued) The resonant current flowing through the HS node during the dead time depends on the LLC resonant tank design and varies by operating frequency and output/input voltage ratio. Therefore, the optimized dead time varies widely with LLC operating conditions. UCC25640x includes an adaptive dead time control to automatically find the optimized dead time across the entire operating range. It detects the change of slew rate of the HS node voltage. During a switching transition, the slew rate rises up first and then drops back to zero. A slew rate detector is used to detect the moment when the slew rate drops below a pre-defined threshold. A slew done event is only detected when the slew rate during dead time crosses the threshold and then drops back below the threshold. If the slew rate is lower than the threshold (i.e. minimal detectable slew rate) during the whole dead time period, no slew done will be detected. This is to prevent the mis-detection due to noise on the HS node voltage. If slew done is not detected, maximum dead time is used. Because of the natural symmetric operation of LLC, only the dead time between high-side MOSFET turn off and low-side MOSFET turn on is determined by the slew rate detector. This dead time is copied and then applied to the dead time between low-side MOSFET turn off and high-side MOSFET turn on.

8.3.9 Protections

8.3.9.1 ZCS Region Prevention

The capacitive region is an LLC operating region in which the voltage gain increases when the switching frequency increases. It is also called the ZCS region. Capacitive mode operation should be avoided for two reasons:

The feedback loop becomes positive feedback in the capacitive region
The MOSFET may be damaged because of body diode reverse recovery The capacitive region detection is done by checking the resonant current polarity at HSON or LSON falling edge. If the resonant current is positive at LSON falling edge, or negative at HSON falling edge, the ZCS signal in the waveform generator is turned high. The ZCS signal stays high until ZCS is cleared at the next HSON or LSON falling edge. If ZCS is detected, the next gate will be turned on at the next IPolarity flip event when the resonant current becomes inductive again. The IPolarity flip indicates that the capacitive operation cycle has already passed. The resonant current reverses direction and begins to discharge the switch node. In this stage, the body diode is no longer conducting and it is allowed to turn on the next gate. If there is a slew done event detected, it suggests that the opposite body diode must not be conducting and the next gate will be turned on as well. If neither the IPolarity flip event or slew done event is detected, the next gate will be turned on by the maximum dead time timer expiration. During a ZCS event, the maximum dead time is changed to 150 us. ZCS typically happens when the LLC operates at heavy load condition and the switching frequency is too low. Therefore, when ZCS is detected, the SS pin is pulled low through a diode to ground and the system enters a "ZCS soft start" process. The switching frequency is forced to ramp up in order for the system to recover from ZCS. The details of the "ZCS soft start" are described in the Soft-Start and Burst-Mode Threshold section. As the ZCS detection relies on the resonant current polarity detection, if LLC operates at very light load condition, the magnitude of the resonant current can be very small and there may be chances that the resonant current polarity detection can be distorted by the switching noise. In order to prevent the nuisance ZCS detection at light load condition, ZCS is disabled at light load condition by utilizing the burst mode control. The details are described in the Burst Mode Control section. Below is the flow chart of the capacitive region prevention algorithm and the timing diagram of a ZCS event:

Figure 36. ZCS Prevention Algorithm Flow Chart

Figure 37. Timing Diagram of a ZCS Event

8.3.9.2 Over Current Protection (OCP)

OCP1: peak current protection (highest threshold)
Fault action: If ISNS is higher than OCP1 threshold for 4 consecutive switching cycles, the switching will

stop. The system enters FAULT state, and waits for 1 s and then re-enters the startup state.

OCP2: average input current protection (high threshold)
Fault action: If sensed ISNS average value is above the threshold for 2 ms, the switching will stop. The

system enters FAULT state, and waits for 1 s and then re-enters the startup state.

OCP3: average input current protection (low threshold)
Fault action: If sensed ISNS average value is above the threshold for 50 ms, the switching will stop. The

system enters FAULT state, and waits for 1 s and then re-enters the startup state. The circuit block diagram has been discussed in the Resonant Current Sensing section.

8.3.9.3 Bias Winding Over Voltage Protection (BWOVP)

and then re-enters the startup state.

8.3.9.4 Input Under Voltage Protection (VINUVP)

and waits for 1 s and then re-enters the startup state.

8.3.9.5 Boot UVLO

output will be shut down. The system does not enter FAULT state.

8.3.9.6 RVCC UVLO

This is the regulated 13-V UVLO. When RVCC voltage is less than the threshold, both the high-side gate output and the low-side gate output will be turned off immediately. The system enters FAULT state, and waits for 1 s and then re-enters the startup state.

8.3.9.7 Over Temperature Protection (OTP)

This is the device over temperature protection. When OTP threshold is exceeded, the switching will stop. The system enters FAULT state, and waits for 1 s and then re-enters the startup state if the temperature is back below the OTP threshold.

8.4 Device Functional Modes

8.4.1 High Voltage Start-Up

supply current for both the PFC and the LLC controller devices. the IC. The HV pin needs to be grounded when using the UCC256403.

8.4.2 X-Capacitor Discharge

remain present on the pins of the AC plug indefinitely after it is physically removed from the AC power. and can be significant in the context of achieving very low standby power. support the fast discharge of up to 5-μF x-capacitance. the last half AC cycle. In reality, it can be disconnected anywhere within a switching cycle. Figure 38. AC Disconnect Waveform

Figure 41. AC ZCD and X-Capacitor Discharge Flow Chart

8.4.3 Burst Mode Control

two thresholds, and determines the burst mode operation.

At t1, FBreplica is below BMTL. The system enters burst mode and stops switching immediately. During the burst off period, UCC25640x disables some internal blocks to save power consumption.
At t2, FBreplica is above BMTH. The system starts to switch again, and this period is referred to burst on period. During burst on period, the control effort Vcomp sent to the VCR comparator is the higher value of FBreplica and BMTL. For the first switching pattern after the system enters burst mode, there is no burst soft on.
At t3, FBreplica falls below BMTL again. Switching will not stop until it reaches the predefined number (Nburst) of a burst packet. The Vcomp still selects the higher value of FBreplica and BMTL. For the last 7 switching cycles, soft off will be applied (only 3 soft on/off steps are shown in Figure 42 for conceptual introduction). The Vcomp is a fraction of the higher value between FBreplica and BMTL. The number of fractions for different switching cycles are described in Table 1. For burst soft off, it starts from step 7 and ramps down. After it reaches step 1, soft off steps are completed and the system enters burst off period. This helps to achieve slow ramping down of the LLC transformer current. For burst soft on, it reverses the direction by starting from step 1 and ends at step 7. If FBreplica becomes greater than BMTL before the soft off steps are completed, the burst soft off will end immediately and the system transitions to burst soft on. In this condition, the soft on

At t1, FBreplica is below BMTL. The system enters burst mode and stops switching immediately.
At t2, FBreplica is above BMTH. The system starts to switch again, and enters burst on period. The control effort Vcomp sent to the VCR comparator is the higher value of FBreplica and BMTL.
At t3, FBreplica falls below BMTL again. Switching will not stop until it reaches the predefined number (Nburst) of a burst packet. If switching reaches the Nburst before FBreplica falls below BMTL again, system will continue to deliver burst packet until FBreplica is below BMTL.
At t4, FBreplica is greater than BMTL. The system enters burst on period without soft on. So the control effort Vcomp is the higher value of FBreplica and BMTL.
At t5, FBreplica is greater than BMTL again after another burst off period. The control effort Vcomp follows FBreplica. At t6, FBreplica becomes above BMTH, Vcomp still follows FBreplica. If FBreplica remains above BMTH more than Nburst switching cycles, system exits burst mode.

Figure 43. Burst Mode Switching Pattern when Soft On and Soft Off is Disabled control effort Vcomp. In this case, BMTL will limit the maximum switching frequency of LLC. transient period, it is ok for FBreplica to be lower than BMTL.

8.4.3.1 Soft-Start and Burst-Mode Threshold

frequency. The pin block diagram is shown in Figure 44.

SS pull low phase - SS pin is internally pulled low with a typical 1.2 kΩ resistor to ground.
SS initial voltage program phase - The internal pull low is released. As shown in Figure 44, SS pin is typically connected with a resistor divider from RVCC and a capacitor to ground. When the internal pull low circuit is released, SS pin voltage can be charged up depending on the external resistor and capacitor. This phase ends when charge boot stage is completed and it has a fixed time of tSSInitVolPrgm.
Soft start phase - An internal constant current source charges the soft start capacitor right after the charge boot stage, and ends when FBreplica becomes lower than the SS pin voltage. During this phase, SS pin voltage is used as the control effort Vcomp. The slow ramp up of SS pin helps the LLC operate at a higher switching frequency when the output voltage is not established yet during startup. This can avoid the large inrush current during startup.
BMTL settling phase - When soft start phase is completed, LL/SS pin is used for burst mode threshold programming. As described in Burst Mode Control, two burst mode thresholds are used. During this phase, BMTH is fixed at either 0.6V (1.2 V if BW option 7 is selected). BMTL is also fixed which is determined by the programmed ratio of BMTL/BMTH. The typical duration of this phase is 600us.
BMTL and BMTH programming/setting phase - LL/SS pin is buffered at 3.5V during this phase. Depending on the resistors connected to the pin, LL/SS pin could either sink or source current. If LL/SS pin sinks current, the current will be internal mirrored to flow through RFB, and the voltage on RFB is the programmed voltage of BMTH. If LL/SS pin sources current, the programmed voltage of BMTH is set to minimal. If the programmed voltage of BMTH is different from the initial voltage, BMTH ramps to the target value at a refresh frequency of every 200us. The slow refresh frequency makes sure that BMTH does not change due to the noise on LL/SS pin. BMTL follows the change of BMTH based on the programmed ratio of BMTL/BMTH. The programmability of the SS initial voltage provides a freedom to limit the maximum switching frequency during startup. This helps to prevent hard switching due to excessively high switching frequency. For applications that require very high switching frequency during startup, an option is also provided to disable the SS initial voltage programming through BW pin, as described in BMTL/BMTH Ratio Programming. If this option is selected, SS pin continues pull low with the internal 1.2 kΩ resistor during the SS initial voltage program phase.

Figure 44. LL/SS Block Diagram

Figure 45. Timing Diagram of LL/SS Pin Programming

8.4.3.2 BMTL/BMTH Ratio Programming

Table 2. BMTL/BMTH Ratio Programming

8.4.4 System State Machine

state will change to JFETOFF. When the PFC output voltage reaches a certain level, the LLC is turned on. bias winding. When the load drops below a certain level, the LLC operates in burst mode. Figure 46. Block Diagram of System State Machine

Table 3 summarizes the inputs and outputs of Figure 46. Table 3. System State Machine Block Inputs and Outputs

Figure 47. System State Machine Transition

Table 4. States in System State Machine This is the first state after AC input is plugged-in for the system to load trim. supplied to PFC voltage supply pin, PFC soft start begins. stays in WAKEUP state for a short time for the analog circuits to wake up. certain period of time. The programmed initial voltage is buffered to SS pin. down and prevents frequent repetitive start ups in case of a persistent fault.

Table 5. System State Machine Transition Conditions

1 System ready (trim load done)

2 VCCStartSwitching = 1

5 LLSS/BW programming done

6 Charge boot done

7 VCCReStartJfet = 1

8 VCCReStartJfet = 1

9 VCCReStartJfet = 1

10 VCCReStartJfet = 1

11 VCCReStartJfet = 1

12 OTP = 1

13 OTP = 1

14 OTP = 1

15 OTP = 1

16 OTP = 1

Figure 49. Timing Diagram of System State Machine for UCC256402 and UCC256404

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

UCC25640x can be used in a wide range of applications in which LLC topology is implemented. In order to make the part easier to use, TI has prepared a list of materials to demonstrate the features of the device:

Full featured EVM hardware
A excel design calculator
Simulation models
Application notes on Hybrid Hysteretic Control theory In the following sections, a typical design example is presented.

9.2 Typical Application

Shown below is a typical half bridge LLC application using UCC25640x as the controller.

9.2.1 Design Requirements

The design specifications are summarized in Table 6. Table 6. System Design Specifications

E E /L C Q R M N R LL L l s PS s G max o 12 0.5 0.5N 16.5 1.175 / 2 365 / 2 fOUT max IN min V V V M V PSG min 12 0.5N 16.5 1.006 / 2 410 / 2 fOUT min IN max V V M V PS / 2 390 / 2N 16.25 16.5 12 IN nom OUT nom V V UCC256402, UCC256403, UCC256404 www.ti.com SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

9.2.2 Detailed Design Procedure

9.2.2.1 LLC Power Stage Requirements

Start the design by deciding the LLC power stage component values. The LLC power stage design procedure outlined here follows the one given in the TI application note “Designing an LLC Resonant Half-Bridge Power Converters”. The application note contains a full explanation of the origin of each of the equations used. The equations given below are based on the First Harmonic Approximation (FHA) method commonly used to analyze the LLC topology. This method gives a good starting point for any design, but a final design requires an iterative approach combining the FHA results, circuit simulation, and hardware testing. An alternative design approach is given in TI application note SLUA733, LLC Design for UCC29950.

9.2.2.2 LLC Gain Range

First, determine the transformer turns ratio by the nominal input and output voltages. (4) Then determine the LLC gain range MG(min) and MG(max). Assume there is a 0.5-V drop in the rectifier diodes (Vf) and an additional 0.5-V due to other losses (Vloss). (5) (6)

9.2.2.3 Select Ln and Qe

LN is the ratio between the magnetizing inductance and the resonant inductance. (7) QE is the quality factor of the resonant tank. (8) In this equation, RE is the equivalent load resistance.

u u P PM N R 6 84.4 506.4L L L H H P u u u R 2 R 1 1 84.4 2 2 100 30.0 L H I & N+] Q) u u u u u u :E0 R E 1 1 30.02 2 0.3 100 176.5C nF 4 I 5 N+] 0 100 f kHz u u u u : 2 2 PS 2E 2 8 N 8 16.5 12 176.515 OUT nom OUT nom V R I E 0.3Q N 6L UCC256402, UCC256403, UCC256404 SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Selecting LN and QE values should result in an LLC gain curve, that intersects with MG(min) and MG(max) traces. The peak gain of the resulting curve should be larger than MG(max). Details of how to select LN and QE are not discussed here. They are available in the UCC25640x Design Calculator. In this case, the selected LN and QE values are: (9) (10)

9.2.2.4 Determine Equivalent Load Resistance

Determine the equivalent load resistance by Equation 11. (11)

9.2.2.5 Determine Component Parameters for LLC Resonant Circuit

Before determining the resonant tank component parameters, a nominal switching frequency (resonant frequency) should be selected. In this design, 100 kHz is selected as the resonant frequency. (12) The resonant tank parameters can be calculated as the following: (13) (14) (15) After the preliminary parameters are selected, find the closest actual component value that is available, re-check the gain curve with the selected parameters, and then run time domain simulation to verify the circuit operation. The following resonant tank parameters are:

99.7SW Mgminf kHz 69.8SW Mgmaxf kHz N 1.0Mgminf N 0.7Mgmaxf u P R R 1 1 99.7 2 2 30 85 f kHz / & Q) + P M 510L H P R 85L H R 30C nF UCC256402, UCC256403, UCC256404 www.ti.com SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (16) (17) (18) Based on the final resonant tank parameters, the resonant frequency can be calculated: (19) Based on the new LLC gain curve, the normalized switching frequency at maximum and minimum gain are given by: (20) (21) The maximum and minimum switching frequencies are: (22) (23)

9.2.2.6 LLC Primary-Side Currents

The primary-side currents are calculated for component selection purposes. The currents are calculated based on a 110% overload condition. The primary side RMS load current is given by:

2 2 18.327 8.250I AI A u u OES WS 2 2 18.327 12.9592 2 I AI A u u OES O PS EN 16.5 1.111 18.327I I A A 2 2 2 M OER 2 1.111 0.797 1.367I I I A A A u u u u u PM M PS2 2 2 2 16.5 12 0.7972 64.8 510 OUTN V I A & / N+] + u u u OE 1.1 15 1.11116.52 2 2 2 oI $I An UCC256402, UCC256403, UCC256404 SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (24) The RMS magnetizing current at minimum switching frequency is given by: (25) The total current in resonant tank is given by: (26)

9.2.2.7 LLC Secondary-Side Currents

The total secondary side RMS load current is the current referred from the primary side current (IOE) to the secondary side. (27) In this design, the transformer’s secondary side has a center-tapped configuration. The current of each secondary transformer winding is calculated by: (28) The corresponding half-wave average current is: (29)

2 2 410 104.0 229.92 2 IN max CRCR rms V V V V u u R R 1.367A 104.02 69.8kHz 30nFCR IV V&& u u P u 2 69.8kHz 85 H 1.367A 50.946 RL R RV &/ , 9 UCC256402, UCC256403, UCC256404 www.ti.com SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

9.2.2.8 LLC Transformer

A bias winding is needed in order to utilize the HV self start up function. It is recommended to design the bias winding so that the VCC voltage is greater than 13 V. The transformer can be built or purchased according to these specifications:

Turns ratio: Primary : Secondary : Bias = 33 : 2 : 3
Primary terminal voltage: 450 Vac
Primary magnetizing inductance: LM = 510 µH
Primary side winding rated current: IR = 1.367 A
Secondary terminal voltage: 36 VAC
Secondary winding rated current: IWS = 12.959 A
Minimum switching frequency: 69.8 kHz
Maximum switching frequency: 99.7 kHz
Insulation between primary and secondary sides: IEC60950 reinforced insulation The minimum operating frequency during normal operation is calculated above. Please note that for some applications that operate as a wide input LLC where the PFC may be shut off in standby mode, the operating frequency may be much lower during heavy load shutdown and the LLC can operate at just above the ZCS boundary. which is a lower frequency. The magnetic components in the resonant circuit, the transformer and resonant inductor, should be rated to operate at this lower frequency.

9.2.2.9 LLC Resonant Inductor

The AC voltage across the resonant inductor is given by its impedance times the current: (30) The inductor can be built or purchased according to the following specifications:

Inductance: LR = 85 µH
Rated current: IR = 1.367 A
Terminal AC voltage:50.946
Frequency range: 69.8 kHz to 99.7 kHz Please note some designs may utilize the leakage inductance of the transformer as the resonant inductance and do not require an external resonant inductor.

9.2.2.10 LLC Resonant Capacitor

This capacitor carries the full-primary current at the switching frequency. A low dissipation factor capacitor is needed to prevent overheating. The AC voltage across the resonant capacitor is given by its impedance times the current. (31) (32)

u u OES2 2 18.329 8.250SAV II A u u PS 4101.2 1.2 29.82 16.5 IN max DB V V VN u 1.1 1.504QLLC RI I A 1.5 615 u QLLC peak IN maxV V V 1.367RI A u 4102 2 104.0 58.02 2 IN max CRCR valley V V V V u 4102 2 104.0 352.02 2 IN max CRCR peak V V V V UCC256402, UCC256403, UCC256404 SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Peak voltage: (33) Valley voltage: (34) Rated current: (35)

9.2.2.11 LLC Primary-Side MOSFETs

Each MOSFET sees the input voltage as its maximum applied voltage. Choose the MOSFET voltage rating to be 1.5 times of the maximum bulk voltage: (36) Choose the MOSFET current rating to be 1.1 times of the maximum primary side RMS current: (37)

9.2.2.12 LLC Rectifier Diodes

The voltage rating of the output diodes is given by: (38) The current rating of the output diodes is given by: (39)

20 LLCcapV V

15 16.66 2 2 2 2 u RECT OUT I I A UCC256402, UCC256403, UCC256404 www.ti.com SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

9.2.2.13 LLC Output Capacitors

The LLC converter topology does not require an output filter although a small second stage filter inductor may be useful in reducing peak-to-peak output noise. Assuming that the output capacitors carry the rectifier’s full wave output current then the capacitor ripple current rating is: (40) Use 20 V rating for 12-V output voltage: (41) The capacitor’s RMS current rating is: (42) Solid Aluminum capacitors with conductive polymer technology have high ripple-current ratings and are a good choice, especially if the design is required to operate at colder temperatures. The ripple-current rating for a single capacitor may not be sufficient so multiple capacitors are often connected in parallel. The ripple voltage at the output of the LLC stage is a function of the amount of AC current that flows in the capacitors. To estimate this voltage, assume that all the current, including the DC current in the load, flows in the filter capacitors. (43) The capacitor specifications are:

Voltage Rating: 20 V
Ripple Current Rating: 7.251 A
ESR: < 5.1 mΩ

9.2.2.14 HV Pin Series Resistors

Multiple resistors are connected in series with HV pin to limit the power dissipation of the UCC25640x device. The recommended series resistor with HV pin is 5 kΩ.

u 0.9365 328.51BulkStopV V V 365BulkStartV V : 15.17BLKupper BLKsns BLKlowerR R R M : : 15.21 41.67365 BLKsns BLKlower BLK R MR kk 2 2390 15.210.01 : IN nom BLKsns BLKsns V R M P 365 3651BLK Vk V UCC256402, UCC256403, UCC256404 SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

9.2.2.15 BLK Pin Voltage Divider

BLK pin senses the LLC input voltage and determines when to turn on and off the LLC converter. Different versions of UCC25640x have different BLK thresholds. Choose bulk startup voltage at 365 V, then the BLK resistor divider ratio can be calculated as below: (44) The desired power consumption of the BLK pin resistor divider is PBLKsns = 10 mW. The BLK sense resistor total value is given by: (45) The lower BLK divider resistor value is given by: (46) A standard value of 41.2kΩ is selected for RBLKlower.The higher BLK divider resistor value is given by: (47) A standard value of 3x 4.99MΩ in series is selected for RBLKupper. The actual bulk voltage thresholds can be calculated: (48) (49)

9.2.2.16 ISNS Pin Differentiator

ISNS pin sets the over current protection level. OCP1 is peak current protection level; OCP2 and OCP3 are Set OCP3 level at 130% of full load. Thus, the sensed average input current level at full load is given by:

u u 1 1 PS 6.02 16.5 99.N 33secpeakOCP respeakOCPI I A A u u u :u R ISNS ISNS 4 4 30nF 6.02R C 133 150pFrespeakOCP V C VI A u u u : 2 2 1.367 0.66 1.29ISNSpeak r ISNSV I k A V :u : 0.66 30 132150 ISNS r ISNS ISNS k C nFR C pF

150 ISNSC pF

0.331 0.66 180 11 0.92 390 ISNSfullload ISNS OUT bulknom V Vk WP V 9 0.43 0.331130ISNSfullload VV V % UCC256402, UCC256403, UCC256404 www.ti.com SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (50) The current sense ratio can then be calculated: (51) Select a current sense capacitor first, since there are less high voltage capacitor choices than resistors: (52) Then calculate the required ISNS resistor value: (53) After the current sense ratio is determined, the peak ISNS pin voltage at full load can be calculated: (54) The peak resonant current at OCP1 level is given by: (55) The peak secondary-side current at OCP1 level is given by: (56)

Ramp CR(pk pk ) VCRpin(pk pk ) VCRlower SW (Mgmin) CapDiv I V 1 1 2mA 294VV 4.17VC 2 F k 8.2nF 2 69.8kHz 121.59 VCRlower CapDiv VCRupper C 8.2nFk 1 1 121.59C 68pF VCRlower VCRupper CapDiv C 8.2nFC 70.6pF k 1 117.6 1 u u u u Ramp VCRlower Ramp(pk pk ) SW _ min I1 1 2mAC 8.2nFV 2 F 1.75V 2 69.8kHz CR(pk pk ) CapDiv VCRpin(pk pk ) Ramp(pk pk ) V 294Vk 117.6V V 4.25V 1.75V CR(pk pk ) CR(peak ) CR(valley)V V V 352V 58V 294V UCC256402, UCC256403, UCC256404 SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

9.2.2.17 VCR Pin Capacitor Divider

The capacitor divider on the VCR pin sets two parameters: (1) the divider ratio of the resonant capacitor voltage; (2) the amount of frequency compensation to be added. The first criteria the capacitor divider needs to meet is that under over load condition, the peak-to-peak voltage on the VCR pin is with in 6V.It is recommended to size the VCR capacitance to give a total peak to peak voltage between 3V and 4.5V at full load with the frequency compensation ramp contributing between 1V and 2V to the total VCR peak to peak voltage. For this design, the VCR pin capacitance was selected to give a maximum peak to peak voltage of approximately 4.25V at full load with the internal ramp contributing 1.75V to the total VCR waveform. The required VCR capacitance can be calculated directly from the resonant capacitor peak to peak voltage and the minimum expected switching frequency. (57) Based on the expected peak to peak resonant capacitor voltage, the required capacitor divider ratio can be derived (58) From the expected minimum switching frequency, the lower VCR capacitance can be derived (59) A standard value of 8.2nF is chosen for the lower VCR capacitor. From the selected lower VCR capacitor and calculated capacitor divider ratio, the upper VCR capacitance is given by: (60) A standard value of 68pF is selected for the upper VCR capacitor. From the selected upper and lower VCR capacitors, the actual peak to peak voltage on the VCR pin can be calculated (61) (62)

: : BiasWindingNom BWNom BWUpper BMWLower BWNom © ¹ BWlower BMT _ Pr ogram BW 1 1 R R 1 4.59k 1 5.38k k 1 6.825 1 :BMT _ Pr ogramR 4.59k u u KOVPBiasWindingNom BW BWOVP V 19.5V 140%k 6.825V 4V 4 2.86140BWnom VV V % u 312 0.5V 0.5V 19.5 2BiasWindingNomV V V UCC256402, UCC256403, UCC256404 www.ti.com SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

9.2.2.18 BW Pin Voltage Divider

The BW pin programs the ratio between burst mode entry and exit thresholds as well as senses the output voltage through the bias winding and protects the power stage from over voltage. The nominal output voltage is 12 V. The bias winding has 3 turns, and the secondary side winding has 2 turns. Assuming there is a 0.5-V drop in the rectifier diodes (Vf) and a further 0.5-V drop due to other losses (Vloss), the nominal voltage of the bias winding is given by: (63) The desired OVP threshold in this design is 140% of the nominal value. The OVP threshold level in UCC25640x device is 4 V, so the nominal BW pin voltage is given by: (64) The required BW divider ratio is then given by: (65) In this design, the burst mode threshold ratio is chosen to be 0.6 (Option 6).The target programming resistance is then: (66) The lower BW resistor can be calculated by: (67) A standard value of 5.36 kΩ is chosen for the lower BW resistor. The upper resistor can be calculated by: (68) A standard value of 30.9kΩ is chosen for the upper BW resistor.

u:u u TH SSInitVolPr gmTH s sin it TH TH SS V t 1.2k VV R R C § · ¨ ¸ ¨ ¸ © ¹ § · ¨ ¸ :u ¨ ¸ ¨ ¸ © ¹ SSInit Pr gm SS t C s sin it TH LL /SS _ Upper 1.2k RVCCV V 1 e R u TH TH LL /SS _ Upper R RVCCV R TH LL /SS _ Upper LL /SS _ LowerR R || R u P u SS _ Max LL /SS SS VCR(pk pk ) LL /SS _ prech arg e UCC256402, UCC256403, UCC256404 SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

9.2.2.19 Soft Start and Burst Mode Programming

The LL/SS and BW pins allow the designer to select a burst mode threshold as well as program hysteresis for entering and exiting burst mode. The resistor divider of connected to the LL/SS pin sets the BMT_H threshold while the BW pin sets the ratio between BMT_L and BMT_H. In addition to programming the burst mode threshold, the LL/SS pin provides the capability to program an initial voltage onto the LL/SS pin in order to limit the maximum switching frequency during startup. For initial selection of LL/SS components, it is recommended to select an initial LL/SS pin voltage between 0V and 1V and to select burst mode threshold between 1V and 2V. The LL/SS pin parameters can be fine tuned later based on bench measurement. In this design, an initial LL/SS pin voltage of 0.3V and a BMT_H threshold of 0.6V are selected. The soft start capacitor sets how quickly the voltage on the soft start capacitor rises. The soft start time varies with load condition. At full load or over load condition, the soft start time is the longest. It is not easy to calculate the exact soft start time value. However, it can be estimated that under full load condition, the longest possible soft start time is determined by how quickly the soft start pin voltage rises to the maximum VCR peak to peak voltage. For a start up time of 7.5ms, the soft start capacitor is sized to be the following: (69) A standard value of 68nF is selected for the soft start capacitor. In order to properly select the resistors on LL/SS, first define RTH as the equivalent resistance on the LL/SS pin and VTH as the equivalent voltage source on the LL/SS pin. (70) (71) During the SS pull low phase, the voltage on the LL/SS pin is internally pulled down through a 1.2kΩ resistor. During the SS initial program phase, the internal pulldown is released and the soft start capacitor is allowed to naturally charge up from RVCC. The total voltage offset on the LL/SS soft start capacitor can be calculated using the equation below. (72) Substituting for RVCC/RLL/SS_Upper and using a linear approximation for the exponential term, the equation can be simplified to the following. (73)

u :u : : : : TH LL/SS _ Upper LL/SS _ Lower LL/SS _ Upper TH R R 197k 549kR 307kR R 549k 197k u :u :TH LL/SS _ Upper TH R RVCC 197k 13VR 544kV 4.71 V :TH BMT 4.71 V 3.5VR 197k I ¨ ¸ © ¹ © ¹ TH SSInitVolPr gmBMT s sin it SS TH BMT TH V 3.5VI R P : H BMT LL BMT 0.6VI 6.12 A R 98k UCC256402, UCC256403, UCC256404 www.ti.com SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated The current used by the LL/SS pin to program BMTH, IBMT, has the following relationships. IBMT can be directly solved for based on the desired BMTH threshold. (74) (75) Rearranging Equation 73, VTH and RTH can now be calculated. (76) (77) Values for RLL/SS_Upper and RLL/SS_Lower can be determined from VTH and RTH (78) A standard value of 549kΩ is selected for RLL/SS_Upper. (79) A standard value of 316kΩ is selected for RLL/SS_Lower.

9.2.3 Application Curves

Figure 50. Efficiency Figure 51. Light Load Power Consumption Figure 52. Burst Mode with Soft On/Off (Ch2 = VCR, Ch3 = LO, Ch4 = Resonant Current)

u P u PBOOT _ QUIESCENT max off boot bootforwarddrop I t 62 A 150msC 2.32 FV 4V 8 13 1 8 4bootmaxdrop RVCC bootforwarddropV V V V V V V V 97.86tot VCC ccdropmax QC 26 9.65 16.35ccdropmaxV V V V 1.6 totQ mC UCC256402, UCC256403, UCC256404 www.ti.com SLUSD90B –JUNE 2019–REVISED NOVEMBER 2019 Product Folder Links: UCC256402 UCC256403 UCC256404 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

10 Power Supply Recommendations

10.1 VCC Pin Capacitor

The VCC capacitor should be sized based on the total start-up charge required by the system. The start-up charge will mostly be consumed by the gate driver circuit. Thus the total start-up charge can be estimated by the start-up switching frequency, MOSFET gate charge, and the soft-start time. Assume the total start-up charge required by the system is shown in Equation 80 (80) During PFC and LLC startup phase, the maximum VCC voltage drop allowed is (81) The minimum VCC capacitor needed: (82) Choose at least 100 µF capacitor or combination of capacitors.

10.2 Boot Capacitor

During burst off period, power consumed by the high-side gate driver from the HB pin must be drawn from CBOOT and will cause its voltage to decay. At the start of the next burst period there must be sufficient voltage remaining on CBOOT to power the high-side gate driver until the conduction period of LO allows it to be replenished from CRVCC. The power consumed by the high-side driver during this burst off period will therefore have a direct impact on the size and cost of capacitors that must be connected to HB and RVCC. Assume the system has a maximum burst off period of 150 ms and the bootstrap diode has a forward voltage drop of 1V. Target a minimum bootstrap voltage of 8V to avoid UVLO fault. The maximum allowable voltage drop on the boot capacitor is: (83) Boot capacitor can then be sized: (84)

10.3 RVCC Pin Capacitor

The RVCC capacitor needs to be at least 5 times greater than boot capacitor. In addition, sizing of the RVCC capacitor depends on the stability of the RVCC LDO. If the load is light on RVCC, smaller capacitors can be used. The larger the load, the larger the capacitor is needed. In a typical system, the RVCC LDO powers the PFC and LLC gate drivers.

11 Layout

11.1 Layout Guidelines

Put a 2.2-µF ceramic capacitor on VCC pin in addition to the energy storage electrolytic capacitor. The 2.2-µF ceramic capacitor should be put as close as possible to the VCC pin.
RVCC pin should have a bypass capacitor of 4.7 µF or more. It is recommended to add a 0.1-µF ceramic capacitor in addition to the 4.7 µF. The capacitors should be put as close as possible to the RVCC pin. RVCC cap is recommended to be size at least 5 times of boot capacitor.
Minimum recommended boot capacitor, CBOOT, is 0.1 µF. The minimum value of the boot capacitor needs to be determined by the minimum burst frequency. The boot capacitor should be large enough to hold the bootstrap voltage during the lowest burst frequency. Please refer to the boot leakage current in the electrical table.
Signal ground and power ground should be single-point connected. Power ground is recommended to connect to the negative terminal of the LLC input bulk capacitor.
The filtering capacitors for ISNS and BLK should be put as close as possible to the pins.
The bottom capacitor on VCR should be put as close as possible to the VCR pin.
FB trace should be as short as possible
Soft-start capacitor should be put as close as possible to LL/SS pin
Use film capacitors or C0G, NP0 ceramic capacitors for the VCR divider and ISNS capacitor for low distortion
Add necessary filtering capacitors on the BW pin to filter out the high spikes on the bias winding waveform. It is critical to filter out the high spikes because internally the signal is peak detected and then sampled at the low-side turn off edge.
Keep necessary high voltage clearance and creepage.
If 2kV HBM ESD rating is needed on HV pin, it is acceptable to place a 100pF capacitor from the HV pin to ground in order to pass up to 2kV HBM ESD.

11.2 Layout Example

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

Design Spreadsheet, , UCC25640x Design Calculator
User Guide, , Using UCC25640EVM-020

12.2 Related Links

resources, tools and software, and quick access to order now. Table 7. Related Links

12.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

from the experts. Search existing answers or ask your own question to get the quick design help you need. not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

E2E is a trademark of Texas Instruments.

12.6 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 16-Nov-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PUCC256403DDB ACTIVE SOIC DDB 14 40 TBD Call TI Call TI -40 to 125 PUCC256404DDB ACTIVE SOIC DDB 14 40 TBD Call TI Call TI -40 to 125 UCC256402DDBR ACTIVE SOIC DDB 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC256402 UCC256402DDBT ACTIVE SOIC DDB 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC256402 UCC256403DDBR ACTIVE SOIC DDB 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC256403 UCC256403DDBT ACTIVE SOIC DDB 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC256403 UCC256404DDBR ACTIVE SOIC DDB 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC256404 UCC256404DDBT ACTIVE SOIC DDB 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC256404 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

www.ti.com 16-Nov-2019 Addendum-Page 2 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

10X 1.27 14X 0.51 0.31 8.89 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 10.0 9.8 B 4.0 3.8 4222925/A 04/2016 SOIC - 1.75 mm max heightDDB0014A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-012, variation AC. 1 16

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 10X (1.27) (R ) TYP 0.05 (4.445) TYP 4222925/A 04/2016 SOIC - 1.75 mm max heightDDB0014A SOIC SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 8 9 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 14X (1.27) 14X (0.6) 14X (1.55) (4.445) TYP 4222925/A 04/2016 SOIC - 1.75 mm max heightDDB0014A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 8 9 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2019, Texas Instruments Incorporated

Product Information

PUCC256403DDB specifications and overview.

Summary

UCC25640x LLC Resonant Controller with Ultra-Low Audible Noise and Standby Power

Description

UCC25640x LLC Resonant Controller with Ultra-Low Audible Noise and Standby Power

Source title PUCC256403DDB Datasheet(PDF) - Texas Instruments

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