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PUCC23514MDWV

Texas Instruments

UCC23514 4-A Source, 5-A Sink, 5.0-kVRMS Opto-Compatible Single Channel Isolated Gate Drivers

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ADVANCE□INFORMATION e ANODE NC CATHODE VCC CLAMP VEE UVLO ISOLATION BARRIER 3 6 VOUT NC Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. UCC23514 SLUSDV0 –JUNE 2020 UCC235144-ASource,5-ASink,5.0-kVRMSOpto-Compatible SingleChannelIsolatedGateDrivers

1 Features

1• 5.0-kVRMS single channel isolated gate driver with opto-compatible input

Pin-to-pin, drop in upgrade for opto-isolated gate drivers
4.5-A source, 5.3-A sink, peak output current
12-V to 33-V output driver supply voltage
Rail-to-rail output
105-ns (maximum) propagation delay
25-ns (maximum) part-to-part delay matching
35-ns (maximum) pulse width distortion
150-kV/μs (minimum) common-mode transient immunity (CMTI)
Isolation barrier life > 50 Years
13-V reverse polarity voltage handling capability on input stage
DWV package with 8.5 mm creepage
Operating junction temperature, TJ: –40°C to +150°C
Safety-related certifications (Planned): – 7000-VPK reinforced isolation per DIN V VDE V0884-11: 2017-01 – 5.0-kVRMS isolation for 1 minute per UL 1577 – CQC certification per GB4943.1-2011

2 Applications

Industrial motor-control drives
Industrial power supplies, UPS
Solar inverters
Induction heating

3 Description

The UCC23514 is an Opto-compatible, single- channel, isolated gate driver for IGBTs, MOSFETs and SiC MOSFETs, with 4.5-A source and 5.3-A sink peak output current and 5.0-kVRMS reinforced isolation rating. The high supply voltage range of 33- V allows the use of bipolar supplies to effectively drive IGBTs and SiC power FETs. UCC23514 can drive both low side and high side power FETs. Key features and characteristics bring significant performance and reliability upgrades over standard opto-coupler based gate drivers while maintaining pin-to-pin compatibility in both schematic and layout design. Performance highlights include high common mode transient immunity (CMTI), low propagation delay, and small pulse width distortion. Tight process control results in small part-to-part skew. The input stage is an emulated diode (e-diode) which means long term reliability and excellent aging characteristics compared to traditional LEDs. It is offered in an 8-Pin surface mount 7.5 mm x 5.85 mm (typical) SOIC package, with creepage and clearance ≥ 8.5 mm, and a mold compound from material group I which has a comparative tracking index (CTI) > 600 V. UCC23514's high performance and reliability makes it ideal for use in all types of motor drives, solar inverters, industrial power supplies, and appliances. The higher operating temperature opens up opportunities for applications not previously able to be supported by traditional opto-couplers. The UCC23514V option provides the gate drive output on a single terminal. For applications requiring split gate drive output, the UCC23514S version provides two separate output pins, OUTH and OUTL. The UCC23514E version suits applications requiring an UVLO referenced to a separate COM pin, which facilitates bipolar gate drive supply applications. The UCC23514M option connects the gate of the transistor to an internal clamp to prevent false turn-on caused by Miller current. Device Information(1) PART NUMBER FEATURE DESCRIPTION UCC23514E Emitter-referenced UVLO UCC23514M Miller clamp UCC23514S Split output UCC23514V Single VOUT pin (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram of UCC23514M

ADVANCE□INFORMATION e ANODE NC CATHODE VCC OUTL VEE UVLO ISOLATION BARRIER 3 6 OUTH NC e ANODE NC CATHODE VCC NC VEE UVLO ISOLATION BARRIER 3 6 VOUT NC e ANODE NC CATHODE VCC COM VEE UVLO ISOLATION BARRIER 3 6 VOUT NC UCC23514 SLUSDV0 –JUNE 2020 www.ti.com Product Folder Links: UCC23514 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Functional Block Diagram of UCC23514E Functional Block Diagram of UCC23514S Functional Block Diagram of UCC23514V

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES June 2020 * Advance Information release.

ADVANCE□INFORMATION 1ANODE 8 VCC 2NC 7 VOUT 3CATHODE 6 CLAMP 4NC 5 VEE Not to scale 1NC 8 VCC 2ANODE 7 VOUT 3CATHODE 6 COM 4NC 5 VEE Not to scale UCC23514 SLUSDV0 –JUNE 2020 www.ti.com Product Folder Links: UCC23514 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

5 Pin Configuration and Function

Pin Functions for UCC23514E PIN TYPE DESCRIPTION NAME NO. UCC23514E NC 1 — No Connection ANODE 2 I Anode CATHODE 3 I Cathode NC 4 — No Connection VEE 5 P Negative output supply rail COM 6 G IGBT Emitter connection VOUT 7 O Gate Drive Output VCC 8 P Positive output supply rail 8-pin SOIC-WB Top View Pin Functions for UCC23514M PIN TYPE DESCRIPTION NAME NO. UCC23514M ANODE 1 I Anode NC 2 — No Connection CATHODE 3 I Cathode NC 4 — No Connection VEE 5 P Negative output supply rail CLAMP 6 O Miller Clamp Output VOUT 7 O Gate Drive Output VCC 8 P Positive output supply rail

ADVANCE□INFORMATION 1NC 8 VCC 2ANODE 7 NC 3CATHODE 6 VOUT 4NC 5 VEE Not to scale 1NC 8 VCC 2ANODE 7 OUTH 3CATHODE 6 OUTL 4NC 5 VEE Not to scale UCC23514 www.ti.com SLUSDV0 –JUNE 2020 Product Folder Links: UCC23514 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated 8-pin SOIC-WB Top View Pin Functions for UCC23514S PIN TYPE DESCRIPTION NAME NO. UCC23514S NC 1 — No Connection ANODE 2 I Anode CATHODE 3 I Cathode NC 4 — No Connection VEE 5 P Negative output supply rail OUTL 6 O Gate-drive Pull down OUTH 7 O Gate Drive Pull up VCC 8 P Positive output supply rail 8-pin SOIC-WB Top View Pin Functions for UCC23514V PIN TYPE DESCRIPTION NAME NO. UCC23514V NC 1 — No Connection ANODE 2 I Anode CATHODE 3 I Cathode NC 4 — No Connection VEE 5 P Negative output supply rail VOUT 6 O Gate-drive output NC 7 — No Connection VCC 8 P Positive output supply rail

ADVANCE□INFORMATION UCC23514 SLUSDV0 –JUNE 2020 www.ti.com Product Folder Links: UCC23514 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) To maintain the recommended operating conditions for TJ, see the .

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free air temperature range (unless otherwise noted)(1) MIN MAX UNIT Average Input Current IF(AVG) - 25 mA Peak Transient Input Current IF(TRAN) <1us pulse, 300pps 1 A Reverse Input Voltage VR(MAX) 14 V Output supply voltage VCC – VEE -0.3 35 V Output signal voltage VOUT – VCC 0.3 V Output signal voltage VOUT – VEE -0.3 V Junction temperature TJ(2) -40 150 °C Storage temperature Tstg -65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS–001(1) ±4000 VCharged device model (CDM), per JEDEC specification JESD22- C101(2) ±1000

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Output Supply Voltage(VCC – VEE) 14 33 V IF (ON) Input Diode Forward Current (Diode "ON") 7 16 mA VF (OFF) Anode voltage - Cathode voltage (Diode "OFF") -13 0.9 V TJ Junction temperature -40 150 °C TA Ambient temperature -40 125 °C (1) For more information about traditional and new thermal metrics, see the http://www.ti.com/lit/SPRA953 application report.

6.4 Thermal Information

THERMAL METRIC(1) UCC23514E, UCC23514M, UCC23514S, UCC23514V UNITDWV (SOIC)

8 PINS

RθJA Junction-to-ambient thermal resistance 108.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 52.0 °C/W RθJB Junction-to-board thermal resistance 58.6 °C/W ψJT Junction-to-top characterization parameter 32.7 °C/W ψJB Junction-to-board characterization parameter 56.6 °C/W

6.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PD Maximum power dissipation on input and output(1) VCC = 20 V, IF= 10mA 10-kHz, 50% duty cycle, square wave,180-nF load, TA=25oC 750 mW PD1 Maximum input power dissipation(2) 10 mW PD2 Maximum output power dissipation 740 mW

ADVANCE□INFORMATION UCC23514 SLUSDV0 –JUNE 2020 www.ti.com Product Folder Links: UCC23514 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications. (2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. (3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. (4) Apparent charge is electrical discharge caused by a partial discharge (pd). (5) All pins on each side of the barrier tied together creating a two-pin device.

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT CLR External clearance(1) Shortest pin-to-pin distance through air > 8.5 mm CPG External creepage(1) Shortest pin-to-pin distance across the package surface > 8.5 mm DTI Distance through the insulation Minimum internal gap (internal clearance) > 17 µm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V Material group According to IEC 60664-1 I Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS I-IV Rated mains voltage ≤ 1000 VRMS I-III DIN V VDE V 0884-11:2017-01(2) VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1500 VPK VIOWM Maximum working isolation voltage AC voltage (sine wave); time dependent dielectric breakdown (TDDB) test; 1060 VRMS DC Voltage 1500 VDC VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) 7000 VPK VIOSM Maximum surge isolation voltage(3) Test method per IEC 62368-1, 1.2/50 μs waveform, VTEST = 1.6 × VIOSM (qualification) 8000 VPK qpd Apparent charge(4) Method a, After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s ≤ 5 pC Method a, After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 2400 VPK, tm = 10 s ≤ 5 Method b1; At routine test (100% production) and preconditioning (type test) Vini = 1.2 × VIOTM; tini = 1 s; Vpd(m) = 1.875 × VIORM = 2813 VPK, tm = 1 s ≤ 5 CIO Barrier capacitance, input to output(5) VIO = 0.4 sin (2πft), f =1 MHz 0.5 pF RIO Isolation resistance, input to output(5) VIO = 500 V at TA = 25°C > 1012 ΩVIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011 VIO = 500 V at TS =150°C > 109 Pollution degree 2 Climatic category 40/125/21 UL 1577 VISO Withstand isolation voltage VTEST = VISO = 5000 VRMS, t = 60 s. (qualification), VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production) 5000 VRMS

6.7 Safety-Related Certifications

Plan to certify according to DIN V VDE V 0884-11: 2017-01 Plan to certify according to UL 1577 Component Recognition Program Plan to certify according to GB4943.1-2011 Reinforced insulation Maximum transient isolation voltage, VPK; Maximum repetitive peak isolation voltage,

1500 VPK;7000

Maximum surge isolation voltage, 8000 VPK Single protection, 5000 VRMS Reinforced insulation, Altitude ≤ 5000 m, Tropical Climate Certificate planned Certificate planned Certificate planned

6.8 Electrical Characteristics

Unless otherwise noted, all typical values are at TA = 25°C, VCC–VEE= 15V, VEE= GND. All min and max specifications are at recommended operating conditions (TJ = -40C to 150°C, IF(on)= 7 mA to 16 mA, VEE= GND, VCC= 15 V to 30 V, VF(off)= –5V to 0.8V) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT IFLH Input Forward Threshold Current Low to High VOUT > 5 V, Cg = 1 nF 1.5 2.8 4 mA VF Input Forward Voltage IF =10 mA 1.8 2.1 2.4 V VF_HL Threshold Input Voltage High to Low V < 5 V, Cg = 1 nF 0.9 V ΔVF/ΔT Temp Coefficient of Input Forward Voltage IF =10 mA 1 1.35 mV/ºC VR Input Reverse Breakdown Voltage IR= 10 uA 15 V CIN Input Capacitance F = 0.5 MHz 15 pF OUTPUT IOH High Level Peak Output Current IF = 10 mA, VCC =15V, CLOAD=0.18uF, CVDD=10uF, pulse width <10us 3 4.5 A IOL Low Level Peak Output Current VF= 0 V, VCC =15V, CLOAD=0.18uF, CVDD=10uF, pulse width <10us 3.5 5.3 A VOH High Level Output Voltage IF = 10 mA, IO= -20mA (with respect to VCC) 0.07 0.18 0.36 V IF = 10 mA, IO= 0 mA VCC V VOL Low Level Output Voltage VF = 0 V, IO= 20 mA 25 mV ICC_H Output Supply Current (Diode On) IF = 10 mA, IO= 0 mA 2.2 mA ICC_L Output Supply Current (Diode Off) VF = 0 V, IO= 0 mA 2 mA INTERNAL MILLER CLAMP VCLMPTH Miller Clamp Threshold Voltage CLAMP-VEE 2.1 2.3 V ICLMP Miller Clamp current CLAMP = 50mV below VCLMPTH 2 A RCLMP Miller Clamp Pull down resistance ICLMP= 0.2A 0.85 Ω tDCLMP Miller Clamp turn on delay time Measured fromCLAMP crossing belowVCLMPTH to when theclamp is turned on 45 ns UNDER VOLTAGE LOCKOUT UVLOR Under Voltage Lockout VCC, rising UCC23514M, UCC23514S, and UCC23514V: VCC to VEE, IF=10 mA 11 12.5 13.5 V UCC23514E: VCC to COM, IF=10 mA UVLOF Under Voltage Lockout VCC, falling UCC23514M, UCC23514S, and UCC23514V: VCC to VEE, IF=10 mA 10 11.5 12.5 V UCC23514E: VCC to COM, IF=10 mA UVLOHYS UVLO Hysteresis 1.0 V

6.9 Switching Characteristics

Unless otherwise noted, all typical values are at TA = 25°C, VCC-VEE= 30 V, VEE= GND. All min and max specifications are at recommended operating conditions (TJ = -40 to 150°C, IF(ON)= 7 mA to 16 mA, VEE= GND, VCC= 15 V to 30 V, VF(OFF)= –5V to 0.8V)

ADVANCE□INFORMATION UCC23514 www.ti.com SLUSDV0 –JUNE 2020 Product Folder Links: UCC23514 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Switching Characteristics (continued) Unless otherwise noted, all typical values are at TA = 25°C, VCC-VEE= 30 V, VEE= GND. All min and max specifications are at recommended operating conditions (TJ = -40 to 150°C, IF(ON)= 7 mA to 16 mA, VEE= GND, VCC= 15 V to 30 V, VF(OFF)= –5V to 0.8V) (1) tsk(pp) is the magnitude of the difference in propagation delay times between the output of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads ensured by characterization. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr Output-signal Rise Time Cg = 1nF FSW = 20 kHz, (50% Duty Cycle) VCC=15V 28 ns tf Output-signal Fall Time 25 ns tPLH Propagation Delay, Low to High 70 105 ns tPHL Propagation Delay, High to Low 70 105 ns tPWD Pulse Width Distortion |tPHL – tPLH| 35 ns tsk(pp) Part-to-Part Skew in Propagation Delay Between any Two Parts(1) Cg = 1nF FSW = 20 kHz, (50% Duty Cycle) VCC=15V, IF=10mA 25 ns tUVLO_rec UVLO Recovery Delay VCC Rising from 0V to 15V 20 30 µs CMTIH Common-mode Transient Immunity (Output High) IF = 10 mA, VCM = 1500 V, VCC= 30 V, TA= 25ºC 150 kV/µs CMTIL Common-mode Transient Immunity (Output Low) VF = 0 V, VCM = 1500 V, VCC= 30 V, TA= 25ºC 150 kV/µs

220 Yrs

1275 VRMS

1060 VRMS

6.10 Insulation Characteristics

Figure 1. Reinforced Isolation Capacitor Life Time Projection

6.11 Typical Characteristics

Figure 2. Output Drive currents versus Temperature Figure 3. Supply currents versus Temperature Figure 4. Supply current versus Supply Voltage Figure 5. Forward threshold current versus Temperature Figure 6. Propagation delay versus Temperature Figure 7. Propagation delay versus Forward current

Figure 14. Forward voltage drop versus Temperature

7 Parameter Measurement Information

7.1 Propagation Delay, rise time and fall time

circuit used to measure the rise (tr) and fall (tf) times and the propagation delays tPDLH and tPDHL. Figure 15. IF to VOUT Propagation Delay, Rise Time and Fall Time

7.2 IOH and IOL testing

and sink currents of the gate driver. Figure 16. IOH and IOL

7.3 CMTI Testing

considered as a failure. With IF= 0mA, if VOUT rises above 1V, it is considered as a failure. Figure 17. CMTI Test Circuit

8 Detailed Description

8.1 Overview

MOSFETs and SiC FETs. It has 4A peak output current capability with max output driver supply voltage of 33V.

Since the e-diode does not use light emission for its operation, the reliability and aging characteristics of

UCC23514 are naturally superior to those of standard opto isolated gate drivers.

Higher ambient operating temperature range of 125°C, compared to only 105°C for most opto isolated gate
The e-diode forward voltage drop has less part-to-part variation and smaller variation across temperature.
Higher common mode transient immunity than opto isolated gate drivers
Smaller propagation delay than opto isolated gate drivers
Due to superior process controls achievable in capacitive isolation compared to opto isolation, there is less
Smaller pulse width distortion than opto isolated gate drivers

8.2 Functional Block Diagram

Figure 18. Functional Block Diagram for UCC23514E (COM pin connection to IGBT Emitter)

Figure 21. Functional Block Diagram for UCC23514V (single output pin) Figure 22. On-Off Keying (OOK) Based Modulation Scheme

8.3 Feature Description

8.3.1 Power Supply

Since the input stage is an emulated diode, no power supply is needed at the input. IGBTs, and 20V and -5V for SiC MOSFETs. for SiC MOSFETs. The VEE supply is connected to 0V.

8.3.2 Input Stage

The input stage of UCC23514 is simply the e-diode and therefore has an Anode (Pin 1) and a Cathode (Pin 3). Figure 23. Interlock

8.3.3 Output Stage

Table 1. UCC23514 On-Resistance state in DC condition and is turned on only for a brief instant when the output is changing states from low to high. the parallel combination ROH || RNMOS. Figure 24. Output Stage

8.3.4 Protection Features

8.3.4.1 Undervoltage Lockout (UVLO)

supply UVLO feature holds the effected output low, regardless of the input forward current as shown in Table 2. the device starts switching and operating current consumption increases suddenly.

UVLO is referenced to COM on the UCC23514E, and to VEE in all other versions. Figure 25. UVLO functionality

8.3.4.2 Active Pulldown

8.3.4.3 Short-Circuit Clamping

20 mA. Use external Schottky diodes to improve current conduction capability as needed.

8.3.4.4 Active Miller Clamp (UCC23514M)

The active Miller-clamp function is used to prevent false turn on of the power switches caused by Miller current in applications where a unipolar power supply is used. The active Miller-clamp function is implemented by adding a low impedance path between the power-switch gate terminal and ground (VEE) to sink the Miller current. The Miller clamping function is implemented by adding a low impedance path between the gate of the power device and the VEE supply. Miller current sinks through the clamp pin, which clamps the gate voltage to be lower than the gate turn-on threshold value for the power device. The clamp engages whenever the voltage at the CLAMP pin goes below VCLMPTH.

8.4 Device Functional Modes

Table 2. Function Table for UCC23514 with VCC Rising Table 3. Function Table for UCC23514 with VCC Falling

8.4.1 ESD Structure

provides pictorial representation of the absolute maximum rating for the device. Figure 26. ESD Structure

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

UCC23514 is a single channel, isolated gate driver with opto-compatible input for power semiconductor devices, such as MOSFETs, IGBTs, or SiC MOSFETs. It is intended for use in applications such as motor control, industrial inverters, and switched-mode power supplies. It differs from standard opto isolated gate drivers as it does not have an LED input stage. Instead of an LED, it has an emulated diode (e-diode). To turn the e-diode "ON", a forward current in the range of 7mA to 16mA should be driven into the Anode. This will drive the gate driver output High and turn on the power FET. Typically, MCU's are not capable of providing the required forward current. Hence a buffer has to be used between the MCU and the input stage of UCC23514. Typical buffer power supplies are either 5V or 3.3V. A resistor is needed between the buffer and the input stage of UCC23514 to limit the current. It is simple, but important to choose the right value of resistance. The resistor tolerance, buffer supply voltage tolerance and output impedance of the buffer, have to be considered in the resistor selection. This will ensure that the e-diode forward current stays within the recommended range of 7mA to 16mA. Detailed design recommendations are given in the Application Information. The current driven input stage offers excellent noise immunity that is need in high power motor drive systems, especially in cases where the MCU cannot be located close to the isolated gate driver. UCC23514 offers best in class CMTI performance of >150kV/us at 1500V common mode voltages. The e-diode is capable of 25mA continuous in the forward direction. The forward voltage drop of the e-diode has a very tight part to part variation (1.8V min to 2.4V max). The temperature coefficient of the forward drop is <1.35mV/°C. The dynamic impedance of the e-diode in the forward biased region is ~1Ω. All of these factors contribute in excellent stability of the e-diode forward current. To turn the e-diode "OFF", the Anode - Cathode voltage should be <0.8V, or IF should be <IFLH. The e-diode can also be reverse biased up to 13V (14V abs max) in order to turn it off and bring the gate driver output low. The large reverse breakdown voltage of the input stage provides system designers the flexibility to drive the input stage with 12V PWM signals without the need for an additional clamping circuit on the Anode and Cathode pin. The output power supply for UCC23514 can be as high as 33V (35V abs max). The output power supply can be configured externally as a single isolated supply up to 33V or isolated bipolar supply such that VCC-VEE does not exceed 33V, or it can be bootstrapped (with external diode & capacitor) if the system uses a single power supply with respect to the power ground. Typical quiescent power supply current from VCC is 1.2mA (max 2.2mA).

9.2 Typical Application

The circuit in Figure 28, shows a typical application for driving IGBTs. Figure 27. Typical Application Circuit for UCC23514E to Drive IGBT with Split Gate Drive Supply Figure 28. Typical Application Circuit for UCC23514M to Drive IGBT Figure 29. Typical Application Circuit for UCC23514S to Drive IGBT

Figure 30. Typical Application Circuit for UCC23514V to Drive IGBT

9.2.1 Design Requirements

Table 4 lists the recommended conditions to observe the input and output of the UCC23514 gate driver. Table 4. UCC23514 Design Requirements

9.2.2 Detailed Design Procedure

9.2.2.1 Selecting the Input Resistor

Supply Voltage VSUP variation
Manufacturer's tolerance for the resistor and variation due to temperature
e-diode forward voltage drop variation (at IF=10mA, VF= typ 2.1 V, min 1.8 V, max 2.4 V, with a temperature

UCC23514. The input resistor can be selected using the equation shown. Figure 31. Configuration 1: Driving the input stage of UCC23514 with a single NMOS and split resistors Figure 32. Configuration 2: Driving the input stage of UCC23514 with one Buffer and split resistors

Figure 33. Configuration 3: Driving the input stage of UCC23514 with 2 buffers and split resistors

Target forward current IF is 7mA min, 10mA typ and 16mA max
e-diode forward voltage drop is 1.8V to 2.4V
VSUP (Buffer supply voltage) is 5V with ±5% tolerance
Manufacturer's tolerance for REXT is 1%
NMOS resistance is 0.25Ω to 1.0Ω (for configuration 1)
ROH(buffer output impedance in output "High" state) is 13Ω min, 18Ω typ and 22Ω max
ROL(buffer output impedance in "Low" state) is 10Ω min, 14Ω typ and 17Ω max

Table 5. REXT Values to Drive The Input Stage

9.2.2.2 Gate-Driver Output Resistor

Limit ringing caused by parasitic inductances and capacitances
Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery
Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss
Reduce electromagnetic interference (EMI)

ADVANCE□INFORMATION IOL = minH5.3A, 15 F0.7 (0.vÀ + srÀ+ rÀ) I = 1.38A IOL = min H5.3A, VCC F VGDF (ROL+ RGOFF + R GFETINT) I IOH = minH4.5A, 15 F0.7 (5.sÀ||9.wÀ + wÀ+ rÀ) I = 1.72A UCC23514 SLUSDV0 –JUNE 2020 www.ti.com Product Folder Links: UCC23514 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

RGON is the external turnon resistance.
RGFET_Int is the power transistor internal gate resistance, found in the power transistor data sheet. We will assume 0Ω for our example
IOH is the peak source current which is the minimum value between 4.5A, the gate-driver peak source current, and the calculated value based on the gate-drive loop resistance.
VGDF is the forward voltage drop for each of the diodes in series with RGON and RGOFF. The diode drop for this example is 0.7 V. In this example, the peak source current is approximately 1.7A as calculated in Equation 2. (2) Similarly, use Equation 3 to calculate the peak sink current. (3) where
RGOFF is the external turnoff resistance.
IOL is the peak sink current which is the minimum value between 5.3A, the gate-driver peak sink current, and the calculated value based on the gate-drive loop resistance. In this example, the peak sink current is the minimum of Equation 4 and 5.3A. (4) The diodes shown in series with each, RGON and RGOFF, in Figure 27, Figure 28, and Figure 30 ensure the gate drive current flows through the intended path, respectively, during turn-on and turn-off. Note that the diode forward drop will reduce the voltage level at the gate of the power switch. To achieve rail-to-rail gate voltage levels, add a resistor from the VOUT pin to the power switch gate, with a resistance value approximately 20 times higher than RGON and RGOFF. For the examples described in this section, a good choice is 100 Ω to 200 Ω. The UCC23514S provides split output pins, OUTH and OUTL, which provide separate paths for turn-on and turn- off current. The series diodes are not necessary when this device option is used, as shown in Figure 29. For this case, substitute VGDF = 0 V in the equations above. The UCC23514S provides rail-to-rail gate voltage levels without need for additional parallel resistors. NOTE The estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot and undershoot. Therefore, TI strongly recommends that the gate- driver loop should be minimized. Conversely, the peak source and sink current is dominated by loop parasitics when the load capacitance (CISS) of the power transistor is very small (typically less than 1 nF) because the rising and falling time is too small and close to the parasitic ringing period.

9.2.2.3 Estimate Gate-Driver Power Loss

The total loss, PG, in the gate-driver subsystem includes the power losses (PGD) of the UCC23514 device and the power losses in the peripheral circuitry, such as the external gate-drive resistor. The PGD value is the key power loss which determines the thermal safety-related limits of the UCC23514 device, and it can be estimated by calculating losses from several components. The first component is the static power loss, PGDQ, which includes power dissipated in the input stage (PGDQ_IN) as well as the quiescent power dissipated in the output stage (PGDQ_OUT) when operating with a certain switching frequency under no load. PGDQ_IN is determined by IF and VF and is given by Equation 5. The PGDQ_OUT parameter is measured on the bench with no load connected to VOUT pin at a given VCC, switching frequency, and ambient temperature. In this example, VCC is 15 V. The current on the power supply, with PWM switching at 10 kHz, is measured to be ICC = 1.33 mA . Therefore, use Equation 6 to calculate PGDQ_OUT.

ADVANCE□INFORMATION PGDO = fsw x f4.5A x ± (VCC TR _Sys F VOUT (t))dt + 5.3A x ± VOUT (t) TF_Sys dtj PGDO = 18 mW 2 H 9.5À||5.1À 0.4À + 10À + 0ÀI = 3.9 mW PGDO = PGSW

2 H ROH||RNMOS

ROH||RNMOS + RGON + RGFET_int + ROL ROL + RGOFF + RGFET_int I GSWP 15 V 120 nC 10 kHz 18 mWu u CC2GSW G SWP V Q f u u PGDQ = PGDQ _IN + PGDQ _OUT = 10 mW + 20mW = 30mW PGDQ _OUT = VCC* ICC PGDQ _IN = 1 Û VF * IF UCC23514 www.ti.com SLUSDV0 –JUNE 2020 Product Folder Links: UCC23514 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated (5) (6) The total quiescent power (without any load capacitance) dissipated in the gate driver is given by the sum of Equation 5 and Equation 6 as shown in Equation 7 (7) The second component is the switching operation loss, PGDSW, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Use Equation 8 to calculate the total dynamic loss from load switching, PGSW. where

QG is the gate charge of the power transistor at VCC. (8) So, for this example application the total dynamic loss from load switching is approximately 18 mW as calculated in Equation 9. (9) QG represents the total gate charge of the power transistor switching 520 V at 50 A, and is subject to change with different testing conditions. The UCC23514 gate-driver loss on the output stage, PGDO, is part of PGSW. PGDO is equal to PGSW if the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and all the gate driver-loss will be dissipated inside the UCC23514. If an external turn-on and turn-off resistance exists, the total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and power- transistor internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4.5A/5.3A, however, it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two scenarios. Case 1 - Linear Pull-Up/Down Resistor: (10) In this design example, all the predicted source and sink currents are less than 4.5 A and 5.3 A, therefore, use Equation 10 to estimate the UCC23514 gate-driver loss. (11) Case 2 - Nonlinear Pull-Up/Down Resistor: where
VOUT(t) is the gate-driver OUT pin voltage during the turnon and turnoff period. In cases where the output is saturated for some time, this value can be simplified as a constant-current source (4.5 A at turnon and 5.3 A at turnoff) charging or discharging a load capacitor. Then, the VOUT(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted. (12)

ADVANCE□INFORMATION J C JT GDT T P < u PGD = PGDQ + PGDO = 30mW + 3.9mW = 33.9mW UCC23514 SLUSDV0 –JUNE 2020 www.ti.com Product Folder Links: UCC23514 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the PGDO is a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown based on this discussion. Use Equation 13 to calculate the total gate-driver loss dissipated in the UCC23514 gate driver, PGD. (13)

9.2.2.4 Estimating Junction Temperature

Use Equation 14 to estimate the junction temperature (TJ) of UCC23514. where

TC is the UCC23514 case-top temperature measured with a thermocouple or some other instrument.
ΨJT is the junction-to-top characterization parameter from the table. (14) Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance (RθJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the total energy is released through the top of the case (where thermocouple measurements are usually conducted). The RθJC resistance can only be used effectively when most of the thermal energy is released through the case, such as with metal packages or when a heat sink is applied to an IC package. In all other cases, use of RθJC will inaccurately estimate the true junction temperature. The ΨJT parameter is experimentally derived by assuming that the dominant energy leaving through the top of the IC will be similar in both the testing environment and the application environment. As long as the recommended layout guidelines are observed, junction temperature estimations can be made accurately to within a few degrees Celsius.

9.2.2.5 Selecting VCC Capacitor

Bypass capacitors for VCC is essential for achieving reliable performance. TI recommends choosing low-ESR and low-ESL, surface-mount, multi-layer ceramic capacitors (MLCC) with sufficient voltage ratings, temperature coefficients, and capacitance tolerances. A 50-V, 10-μF MLCC and a 50-V, 0.22-μF MLCC are selected for the CVCC capacitor. If the bias power supply output is located a relatively long distance from the VCC pin, a tantalum or electrolytic capacitor with a value greater than 10 μF should be used in parallel with CVCC. NOTE DC bias on some MLCCs will impact the actual capacitance value. For example, a 25-V, 1-μF X7R capacitor is measured to be only 500 nF when a DC bias of 15-VDC is applied.

10 Power Supply Recommendations

The recommended input supply voltage (VCC) for the UCC23514 device is from 14V to 33V. The lower limit of the range of output bias-supply voltage (VCC) is determined by the internal UVLO protection feature of the device. VCC voltage should not fall below the UVLO threshold for normal operation, or else the gate-driver outputs can become clamped low for more than 20 μs by the UVLO protection feature. UVLO is referenced to COM on the UCC23514E, and to VEE in all other versions. The higher limit of the VCC range depends on the maximum gate voltage of the power device that is driven by the UCC23514 device, and should not exceed the recommended maximum VCC of 33 V. A local 220-nF to 10-μF bypass capacitor should be placed between the VCC and COM pins for the UCC23514E, or between the VCC and VEE pins for all other versions. TI recommends placing an additional 100-nF capacitor in parallel with the device biasing capacitor for high frequency filtering. Both capacitors should be positioned as close to the device pins as possible. Low-ESR, ceramic surface-mount capacitors are recommended. If only a single, primary-side power supply is available in an application, isolated power can be generated for the secondary side with the help of a transformer driver such as Texas Instruments' SN6501 or SN6505A. For such applications, detailed power supply design and transformer selection recommendations are available in SN6501 Transformer Driver for Isolated Power Supplies data sheet and SN6505A Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet.

11 Layout

11.1 Layout Guidelines

Designers must pay close attention to PCB layout to achieve optimum performance for the UCC23514. Some key guidelines are:

Component placement: – Low-ESR and low-ESL capacitors must be connected close to the device between the VCC and VEE pins to bypass noise and to support high peak currents when turning on the external power transistor. – To avoid large negative transients on the VEE pins connected to the switch node, the parasitic inductances between the source of the top transistor and the source of the bottom transistor must be minimized.
Grounding considerations: – Limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area is essential. This limitation decreases the loop inductance and minimizes noise on the gate terminals of the transistors. The gate driver must be placed as close as possible to the transistors.
High-voltage considerations: – To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or copper below the driver device. A PCB cutout or groove is recommended in order to prevent contamination that may compromise the isolation performance.
Thermal considerations: – A large amount of power may be dissipated by the UCC23514 if the driving voltage is high, the load is heavy, or the switching frequency is high. Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction-to-board thermal impedance (θJB). – Increasing the PCB copper connecting to the VCC and VEE pins is recommended, with priority on maximizing the connection to VEE. However, the previously mentioned high-voltage PCB considerations must be maintained. – If the system has multiple layers, TI also recommends connecting the VCC and VEE pins to internal ground or power planes through multiple vias of adequate size. These vias should be located close to the IC pins to maximize thermal conductivity. However, keep in mind that no traces or coppers from different high voltage planes are overlapping.

11.2 PCB Material

Use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self- extinguishing flammability-characteristics.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 25-Jul-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PUCC23514EDWV ACTIVE SOIC DWV 8 64 TBD Call TI Call TI -40 to 125 PUCC23514MDWV ACTIVE SOIC DWV 8 100 TBD Call TI Call TI -40 to 125 PUCC23514SDWV ACTIVE SOIC DWV 8 64 TBD Call TI Call TI -40 to 125 PUCC23514VDWV ACTIVE SOIC DWV 8 64 TBD Call TI Call TI -40 to 125 UCC23514EDWV PREVIEW SOIC DWV 8 64 TBD Call TI Call TI -40 to 125 UCC23514EDWVR PREVIEW SOIC DWV 8 1000 TBD Call TI Call TI -40 to 125 UCC23514MDWV PREVIEW SOIC DWV 8 64 TBD Call TI Call TI -40 to 125 UCC23514MDWVR PREVIEW SOIC DWV 8 1000 TBD Call TI Call TI -40 to 125 UCC23514SDWV PREVIEW SOIC DWV 8 64 TBD Call TI Call TI -40 to 125 UCC23514SDWVR PREVIEW SOIC DWV 8 1000 TBD Call TI Call TI -40 to 125 UCC23514VDWV PREVIEW SOIC DWV 8 64 TBD Call TI Call TI -40 to 125 UCC23514VDWVR PREVIEW SOIC DWV 8 1000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

www.ti.com 25-Jul-2020 Addendum-Page 2 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com PACKAGE OUTLINE C TYP 11.5 0.25

2.8 MAX

TYP0.33 0.13 0 -8 6X 1.27 8X 0.51 0.31 3.81 0.46 0.36 1.0 0.5 0.25 GAGE PLANE A NOTE 3 5.95 5.75 B NOTE 4 7.6 7.4 (2.286) (2) 4218796/A 09/2013 SOIC - 2.8 mm max heightDWV0008A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 1 8

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT (10.9)

0.07 MAX

0.07 MIN

8X (1.8) 8X (0.6) 6X (1.27) 4218796/A 09/2013 SOIC - 2.8 mm max heightDWV0008A SOIC SYMM SYMM SEE DETAILS LAND PATTERN EXAMPLE 9.1 mm NOMINAL CLEARANCE/CREEPAGE SCALE:6X NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.8) 8X (0.6) 6X (1.27) (10.9) 4218796/A 09/2013 SOIC - 2.8 mm max heightDWV0008A SOIC NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X SYMM SYMM

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Product Information

PUCC23514MDWV specifications and overview.

Summary

UCC23514 4-A Source, 5-A Sink, 5.0-kVRMS Opto-Compatible Single Channel Isolated Gate Drivers

Description

UCC23514 4-A Source, 5-A Sink, 5.0-kVRMS Opto-Compatible Single Channel Isolated Gate Drivers

Source title PUCC23514MDWV Datasheet(PDF) - Texas Instruments

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