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PUCC21736QDWQ1

Texas Instruments

UCC21736-Q1 10-A Source and Sink Reinforced Isolated Single Channel Gate Driver for SiC/IGBT with Active Protection and High-CMTI

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ADVANCE□INFORMATION Copyright © 2017, Texas Instruments Incorporated ISOLATION BARRIER VCC GND IN+ INÅ RDY FLT RST/EN APWM VDD COM VEE OUTH OUTL OC CLMPE ASC VCC Supply PWM Inputs MOD DEMOD Primary Logic Second - ary Logic VDD Supply ASC Control Output Stage t ON/OFF Control OCP Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. UCC21736-Q1 SLUSDM7 –OCTOBER 2019 UCC21736-Q110-ASourceandSinkReinforcedIsolatedSingleChannelGateDriver forSiC/IGBTwithActiveProtectionandHigh-CMTI

1 Features

1• 5.7-kVRMS single channel isolated gate driver

AEC-Q100 qualified for automotive applications
SiC MOSFETs and IGBTs up to 2121 Vpk
33-V maximum output drive voltage (VDD-VEE)
±10-A drive strength and split output
150-V/ns minimum CMTI
200-ns response time fast overcurrent protection
External active miller clamp
900-mA soft turn-off when fault happens
ASC input on isolated side to turn on power switch during system fault
Alarm FLT on over current and reset from RST/EN
Fast enable/disable response on RST/EN
Reject <40-ns noise transient and pulse on input pins
12V VDD UVLO and -3V VEE UVLO with power good on RDY
Inputs/outputs with over/under-shoot transient voltage Immunity up to 5 V
130-ns (maximum) propagation delay and 30-ns (maximum) pulse/part skew
SOIC-16 DW package with creepage and clearance distance > 8 mm
Operating junction temperature –40°C to 150°C

2 Applications

Traction inverter for EVs
On-board charger and charging pile
DC-to-DC converter for HEV/EVs

3 Description

The UCC21736-Q1 is a galvanic isolated single channel gate driver designed for SiC MOSFETs and IGBTs up to 2121-V DC operating voltage with advanced protection features, best-in-class dynamic performance and robustness. UCC21736-Q1 has up to ±10-A peak source and sink current. The input side is isolated from the output side with SiO2 capacitive isolation technology, supporting up to 1.5-kVRMS working voltage, 12.8-kVPK surge immunity with longer than 40 years Isolation barrier life, as well as providing low part-to-part skew, >150V/ns common mode noise immunity (CMTI). The UCC21736-Q1 includes the state-of-art protection features, such as fast overcurrent and short circuit detection, shunt current sensing support, fault reporting, active miller clamp, input and output side power supply UVLO to optimize SiC and IGBT switching behavior and robustness. The ASC feature can be utilized to force ON power switch during system failure events, further increasing the drivers' versatility and simplifying the system design effort, size and cost. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) UCC21736-Q1 DW SOIC-16 10.3 mm × 7.5 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Device Pin Configuration

12.2 Receiving Notification of Documentation Updates 49

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES October 2019 * Advance Information release

ADVANCE□INFORMATION VDD INÅ OUTH 4 COM ASC OC GND 7 10 8 9 VCC Not to scale OUTL VEE RDY

14 RST/EN

5 Pin Configuration and Functions

DW SOIC (16) Top View

ADVANCE□INFORMATION UCC21736-Q1 SLUSDM7 –OCTOBER 2019 www.ti.com Product Folder Links: UCC21736-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) P = Power, G = Ground, I = Input, O = Output Pin Functions PIN I/O(1) DESCRIPTION NAME NO. ASC 1 I Active high to enable active short circuit function to force output high during system failure events OC 2 I Over current detection pin, support lower threshold for SenseFET, DESAT, and Shunt resistor sensing COM 3 P Common ground reference, connecting to emitter pin for IGBT and source pin for SiC-MOSFET OUTH 4 O Gate driver output pull up VDD 5 P Positive supply rail for gate drive voltage, Bypassing a >220nF capacitor to COM to support specified gate driver source peak current capability OUTL 6 O Gate driver output pull down CLMPE 7 O External Active miller clamp, connecting this pin to the gate of the external miller clamp MOSFET VEE 8 P Negative supply rail for gate drive voltage. Bypassing a >220nF capacitor to COM to support specified gate driver sink peak current capability GND 9 P Input power supply and logic ground reference IN+ 10 I Non-inverting gate driver control input IN– 11 I Inverting gate driver control input RDY 12 O Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other RDY signals FLT 13 O Active low fault alarm output upon over current or short circuit. FLT is in open drain configuration and can be paralleled with other faults RST/EN 14 I The RST/EN serves two purposes: 1) Enable / shutdown of the output side. The FET is turned off by a general turn-off, if terminal EN is set to low; 2) Resets the OC condition signaled on FLT pin. if terminal RST/EN is set to low for more than 1000ns. A reset of signal FLT is asserted at the rising edge of terminal RST/EN. For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The FET is turned off by a general turn-off, if terminal EN is set to low. VCC 15 P Input power supply from 3V to 5.5V, bypassing a >100nF capacitor to GND APWM 16 O Isolated PWM output monitoring ASC pin status

ADVANCE□INFORMATION UCC21736-Q1 www.ti.com SLUSDM7 –OCTOBER 2019 Product Folder Links: UCC21736-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Values are verified by characterization on bench.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) PARAMETER MIN MAX UNIT VCC VCC – GND –0.3 6 V VDD VDD – COM –0.3 36 V VEE VEE – COM –17.5 0.3 V VMAX VDD – VEE –0.3 36 V IN+, IN–, RST/EN DC GND–0.3 VCC V Transient, less than 100 ns(2) GND–5.0 VCC+5.0 V ASC Reference to COM –0.3 6 V OC Reference to COM -0.3 6 OUTH, OUTL DC VEE–0.3 VDD V Transient, less than 100 ns(2) VEE–5.0 VDD+5.0 V CLMPE Reference to VEE –0.3 5 V RDY, FLT GND–0.3 VCC V IFLT, IRDY FLT, and RDY pin input current 20 mA IAPWM APWM pin output current 20 mA TJ Junction temperature range –40 150 °C Tstg Storage temperature range –65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±4000 V Charged-device model (CDM), per AEC Q100-011 ±1500

6.3 Recommended Operating Conditions

VCC VCC–GND 3.0 5.5 V VDD VDD–COM 13 33 V VMAX VDD–VEE – 33 V IN+, IN–, RST/EN Reference to GND High level input voltage 0.7×VCC VCC V Low level input voltage 0 0.3×VCC ASC Reference to COM 0 5 V tRST/EN Minimum pulse width that reset the fault 1000 ns TA Ambient Temperature –40 125 °C TJ Junction temperature –40 150 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) UCC21736-Q1 UNITDW (SOIC) RθJA Junction-to-ambient thermal resistance 68.3 °C/W

ADVANCE□INFORMATION UCC21736-Q1 SLUSDM7 –OCTOBER 2019 www.ti.com Product Folder Links: UCC21736-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Thermal Information (continued) THERMAL METRIC(1) UCC21736-Q1 UNITDW (SOIC) RθJC(top) Junction-to-case (top) thermal resistance 27.5 °C/W RθJB Junction-to-board thermal resistance 32.9 °C/W ψJT Junction-to-top characterization parameter 14.1 °C/W ψJB Junction-to-board characterization parameter 32.3 °C/W

6.5 Power Ratings

PARAMETER TEST CONDITIONS Value UNIT PD Maximum power dissipation (both sides) VCC = 5V, VDD-COM = 20V, COM-VEE = 5V, IN+/- = 5V, 150kHz, 50% Duty Cycle for 10nF load, Ta=25oC 985 mW PD1 Maximum power dissipation by transmitter side 20 mW PD2 Maximum power dissipation by receiver side 965 mW

ADVANCE□INFORMATION UCC21736-Q1 www.ti.com SLUSDM7 –OCTOBER 2019 Product Folder Links: UCC21736-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Current are positive into and negative out of the specified terminal. (2) All voltages are referenced to COM unless otherwise notified.

6.6 Electrical Characteristics

VCC=3.3V or 5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE =0V, 5V, 8V or 15V, CL=100pF, –40°C<TJ<150°C (unless otherwise noted)(1)(2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC UVLO THRESHOLD AND DELAY VVCC_ON VCC–GND 2.55 2.7 2.85 VVVCC_OFF 2.35 2.5 2.65 VVCC_HYS 0.2 tVCCFIL VCC UVLO Deglitch time 10 µs tVCC+ to OUT VCC UVLO on delay to output high IN+ = VCC, IN– = GND 37.8 tVCC– to OUT VCC UVLO off delay to output low 10 tVCC+ to RDY VCC UVLO on delay to RDY high RST/EN = VCC 37.8 tVCC– to RDY VCC UVLO off delay to RDY low 10 VDD UVLO THRESHOLD AND DELAY VVDD_ON VDD–COM 11.2 12.0 12.8 VVVDD_OFF 9.9 10.7 11.5 VVDD_HYS 0.8 tVDDFIL VDD UVLO Deglitch time 5 µs tVDD+ to OUT VDD UVLO on delay to output high IN+ = VCC, IN– = GND tVDD– to OUT VDD UVLO off delay to output low 5 tVDD+ to RDY VDD UVLO on delay to RDY high RST/EN = FLT=High tVDD– to RDY VDD UVLO off delay to RDY low 10 VEE UVLO THRESHOLD AND DELAY VVEE_ON VEE–COM –3.3 –3.0 –2.7 VVVEE_OFF –2.9 –2.6 –2.3 VVEE_HYS 0.4 tVEEFIL VEE UVLO Deglitch time 5 µs tVEE+ to OUT VEE UVLO on delay to output high IN+ = VCC, IN– = GND tVEE– to OUT VEE UVLO off delay to output low 5 tVEE+ to RDY VEE UVLO on delay to RDY high RST/EN = FLT=High tVEE– to RDY VEE UVLO off delay to RDY low 10 VCC, VDD QUIESCENT CURRENT IVCCQ VCC quiescent current OUT(H) = High, fS = 0Hz, AIN=2V 3 mA OUT(L) = Low, fS = 0Hz, AIN=2V 2 IVDDQ VDD quiescent current OUT(H) = High, fS = 0Hz, AIN=2V 4 mA OUT(L) = Low, fS = 0Hz, AIN=2V 3.7 LOGIC INPUTS — IN+, IN–, and RST/EN VINH Input high threshold VCC=3.3V 1.85 2.31 V VINL Input low threshold VCC=3.3V 0.99 1.52 V VINHYS Input threshold hysteresis VCC=3.3V 0.33 V IIH Input high level input leakage current VIN = VCC 90 µA IIL Input low level input leakage VIN = GND –90 µA RIND Input pins pull down resistance see Detailed Description for more information 55 kΩ RINU Input pins pull up resistance see Detailed Description for more information 55 TINFIL IN+, IN– and RST/EN deglitch (ON and OFF) filter time fS = 50kHz 28 40 ns TRSTFIL Deglitch filter time to reset /FLT 500 650 800 ns GATE DRIVER STAGE IOUT, IOUTH Peak source current CL=0.18µF, fS=1kHz –10 A IOUT, IOUTL Peak sink current 10 A ROUTH Output pull-up resistance IOUT = –0.1A 2.5 Ω

ADVANCE□INFORMATION UCC21736-Q1 SLUSDM7 –OCTOBER 2019 www.ti.com Product Folder Links: UCC21736-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) VCC=3.3V or 5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE =0V, 5V, 8V or 15V, CL=100pF, –40°C<TJ<150°C (unless otherwise noted)(1)(2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ROUTL Output pull-down resistance IOUT = 0.1A 0.3 Ω VOUTH High level output voltage IOUT = –0.2A, VDD=15V 14.5 V VOUTL Low level output voltage IOUT = 0.2A 60 mV ACTIVE PULLDOWN VOUTPD Output active pull down on OUT, OUTL IOUTL or IOUT = 0.1×IOUT(L)(tpy), VDD=OPEN, VEE=COM 2.5 V EXTERNAL MILLER CLAMP VCLMPTH Miller clamp threshold voltage Reference to VEE 1.5 2.0 2.5 V VCLMPE Output high voltage Reference to VEE 4.4 4.8 V ICLMPEH Peak source current CCLMPE = 10nF 0.12 0.25 A ICLMPEL Peak sink current 0.12 0.25 A tCLMPER Rising time CCLMPE = 330pF 20 40 ns tDCLMPE Miller clamp ON delay time 40 ns SHORT CIRCUIT CLAMPING VCLP-OUT(H) VOUT–VDD, VOUTH–VDD OUT = Low, IOUT(H) = 500mA, tCLP=10us 0.9 V VCLP-OUT(L) VOUT–VDD, VOUTL–VDD OUT = High, IOUT(L) = 500mA, tCLP=10us 1.8 V VCLP-CLMPI VCLMPI–VDD OUT = High, ICLMPI = -20mA, tCLP=10us 1.0 V OC PROTECTION IDCHG OC pull down current when VOC = 1V 40 mA VOCTH Detection Threshold 0.63 0.7 0.77 V VOCL Voltage when OUT(L) = LOW, Reference to COM IOC = 5mA 0.13 V tOCFIL OC fault deglitch filter 150 ns tOCOFF OC propagation delay to OUT(L) 90% 200 ns tOCFLT OC to FLT low delay 600 ns INTERNAL SOFT TURN-OFF ISTO Soft turn-off current on fault conditions 900 mA ASC - Active Short Circuit VASCL ASC Input low threshold 1.7 V VASCH ASC Input high threshold 3.2 V tASC_r ASC to output rising edge delay 660 ns tASC_f ASC to output falling edge delay 227 ns ISOLATED ASC MONITOR (APWM) fAPWM APWM output frequency 360 400 440 kHz DAPWM APWM Dutycycle — VASC = 0.5V 7 10 13 %VASC = 2.5V 47 50 53 VASC = 4.5V 87 90 93 FLT AND RDY REPORTING tRDYHLD VDD UVLO RDY low minimum holding time 0.55 1 ms tFLTMUTE Output mute time on fault Reset fault through RST/EN 0.55 1 ms RODON Open drain output on resistance IODON = 5mA 30 Ω VODL Open drain low output voltage IODON = 5mA 0.3 V COMMON MODE TRANSIENT IMMUNITY CMTI Common-mode transient immunity 150 V/ns

6.7 Switching Characteristics

VCC=5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE = 3V, 5V or 8V, CL=100pF, –40°C<TJ<150°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPDHL Propagation delay time – High to Low 90 ns tPDLH Propagation delay time – Low to High 90 PWD Pulse width distortion |tPDHL – tPDLH| 25 tsk-pp Part to Part skew Rising or Falling Propagation Delay 30 tr Driver output rise time CL=10nF 28 tf Driver output fall time CL=10nF 24 fMAX Maximum switching frequency 1 MHz

ADVANCE□INFORMATION UCC21736-Q1 SLUSDM7 –OCTOBER 2019 www.ti.com Product Folder Links: UCC21736-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves and ribs on the PCB are used to help increase these specifications. (2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. (3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. (4) Apparent charge is electrical discharge caused by a partial discharge (pd). (5) All pins on each side of the barrier tied together creating a two-terminal device

6.8 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT GENERAL CLR External clearance(1) Shortest terminal-to-terminal distance through air > 8 mm CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface > 8 mm DTI Distance through the insulation Minimum internal gap (Internal clearance) of the double insulation (2 × 0.0085 mm) > 17 µm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V Material group According to IEC 60664–1 I Overvoltage Category per IEC 60664–1 Rated mains voltage ≤ 300 VRMS I-IV Rated mains voltage ≤ 600 VRMS I-IV Rated mains voltage ≤ 1000 VRMS I-III DIN V VDE V 0884-11 (VDE V 0884-11):2017-01(2) VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK VIOWM Maximum isolation working voltage AC voltage (sine wave) Time dependent dielectric breakdown (TDDB) test 1500 VRMS DC voltage 2121 VDC VIOTM Maximum transient isolation voltage VTEST=VIOTM, t = 60 s (qualification test) 8000 VPK VTEST=1.2 x VIOTM, t = 1 s (100% production test) 9600 VIOSM Maximum surge isolation voltage(3) Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 12800 VPK (qualification) 8000 VPK qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s ≤ 5 pC Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s ≤ 5 Method b1: At routine test (100% production) and preconditioning (type test) Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s ≤ 5 CIO Barrier capacitance, input to output(5) VIO = 0.5 sin (2πft), f = 1 MHz ~ 1 pF RIO Insulation resistance, input to output(5) VIO = 500 V, TA = 25°C ≥ 1012 ΩVIO = 500 V, 100°C ≤ TA ≤ 125°C ≥ 1011 VIO = 500 V at TS = 150°C ≥ 109 Pollution degree 2 Climatic category 40/125/21 UL 1577 VISO Withstand isolation voltage VTEST = VISO = 5700 VRMS, t = 60 s (qualification); VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production)

5700 VRMS

6.9 Safety-Related Certifications

Plan to certify according to DIN V VDE V 0884-11 (VDE V 0884- 11):2017-01; DIN EN 61010-1 (VDE 0411-1):2011-07 Plan to certify according to UL 1577 Component Recognition Program

ADVANCE□INFORMATION UCC21736-Q1 www.ti.com SLUSDM7 –OCTOBER 2019 Product Folder Links: UCC21736-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Safety-Related Certifications (continued) VDE UL Reinforced insulation Maximum transient isolation voltage, 8000 VPK; Maximum repetitive peak isolation voltage, 2121 VPK; Maximum surge isolation voltage, 8000 VPK Single protection, 5700 VRMS Certification Planned Certification Planned (1) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

6.10 Safety Limiting Values

Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IS Safety input, output, or supply current RθJA =68.3°C/W, VDD = 20V, VEE=-5V, TJ = 150°C, TA = 25°C TBD mA RθJA =68.3°C/W, VDD = 20V, VEE=-5V, TJ = 150°C, TA = 25°C TBD PS Safety input, output, or total power RθJA =68.3°C/W, VDD = 20V, VEE=-5V, TJ = 150°C, TA = 25°C TBD mW TS Safety temperature 150 °C

54 Yrs

6.11 Insulation Characteristics Curves

Figure 1. Reinforced Isolation Capacitor Life Time Projection Figure 2. Thermal Derating Curve for Limiting Current per Figure 3. Thermal Derating Curve for Limiting Power per

6.12 Typical Characteristics

Figure 4. Output High Drive Current vs. Temperature Figure 5. Output Low Driver Current vs. Temperature Figure 6. IVCCQ Supply Current vs. Temperature Figure 7. IVCCQ Supply Current vs. Temperature Figure 8. IVCCQ Supply Current vs. Input Frequency IN+ = High IN- = Low Figure 9. IVDDQ Supply Current vs. Temperature

Figure 22. ICLMPEL Miller Clamp Sink Current vs. Figure 23. tDCLMPE Miller Clamp ON Delay Time vs. Figure 24. VOCTH OC Detection Threshold vs. Temperature

7 Parameter Measurement Information

7.1 Propagation Delay

7.1.1 Regular Turn-OFF

propagation delay measurement with the inverting configurations.

7.2 Input Deglitch Filter

pulse deglitch filter effect. Figure 27. IN+ ON Deglitch Filter Figure 28. IN+ OFF Deglitch Filter Figure 29. IN– ON Deglitch Filter Figure 30. IN– OFF Deglitch Filter

7.3 Active Miller Clamp

7.3.1 External Active Miller Clamp

clamp threshold, VCLMPTH. Figure 31 shows the timing diagram for external active miller clamp function. Figure 31. Timing Diagram for External Active Miller Clamp Function

7.4 Under Voltage Lockout (UVLO)

VCC — primary side power supply, and VDD — secondary side power supply.

7.4.1 VCC UVLO

the definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM. Figure 32. VCC UVLO Protection Timing Diagram

7.4.2 VDD UVLO

the definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM. Figure 33. VDD UVLO Protection Timing Diagram

7.4.3 VEE UVLO

the definition of UVLO ON/OFF threshold, deglitch filter, response time, and RDY. Figure 34. VEE UVLO Protection Timing Diagram

7.5 OC (Over Current) Protection

7.5.1 OC Protection with Soft Turn-OFF

condition. Figure 35 shows the timing diagram of OC operation with soft turn-off. Figure 35. OC Protection with Soft Turn-OFF

7.6 ASC Protection

VEE UVLO, and the overcurrent fault event are higher than ASC function.

Figure 36. ASC Protection with VCC UVLO

Figure 37. ASC Protection with VDD UVLO

Figure 38. ASC Protection with OC Fault

8 Detailed Description

8.1 Overview

The UCC21736-Q1 device is an advanced isolated gate driver with state-of-art protection and sensing features for SiC MOSFETs and IGBTs. The device can support up to 2121V DC operating voltage based on SiC MOSFETs and IGBTs, and can be used to above 10kW applications such as HEV/EV traction inverter, motor drive, on-board and off-board battery charger, solar inverter, etc. The galvanic isolation is implemented by the capacitive isolation technology, which can realize a reliable reinforced isolation between the low voltage DSP/MCU and high voltage side. The ±10A peak sink and source current of UCC21736-Q1 can drive the SiC MOSFET modules and IGBT modules directly without an extra buffer. The driver can also be used to drive higher power modules or parallel modules with external buffer stage. The input side is isolated with the output side with a reinforced isolation barrier based on capacitive isolation technology. The device can support up to 1.5-kVRMS working voltage, 12.8- kVPK surge immunity with longer than 40 years isolation barrier life. The strong drive strength helps to switch the device fast and reduce the switching loss. While the 150V/ns minimum CMTI guarantees the reliability of the system with fast switching speed. The small propagation delay and part-to-part skew can minimize the deadtime setting, so the conduction loss can be reduced. The device includes extensive protection and monitor features to increase the reliability and robustness of the SiC MOSFET and IGBT based systems. The 12V output side power supply UVLO is suitable for switches with gate voltage ≥ 15V. The active miller clamp feature prevents the false turn on causing by miller capacitance during fast switching. External miller clamp FET can be used, providing more versatility to the system design. The device has the state-of-art overcurrent and short circuit detection time, and fault reporting function to the low voltage side DSP/MCU. The soft turn off is triggered when the overcurrent or short circuit fault is detected, minimizing the short circuit energy while reducing the overshoot voltage on the switches. The active short circuit feature can create a phase to phase short circuit for a three-phase inverter, which is useful for the motor drive applications to protect the battary if the microcontroller loses control.

ADVANCE□INFORMATION IN+ VCC RDY OUTH OUTL APWM VDD INt GND DEMOD ISOLATION BARRIER VCC Supply PWM Inputs MOD Fault Decode Fault Encode LDO[s for VEE, COM and channel ASC Circuit Output Stage t ON/OFF Control STO OCP UVLO UVLO MODDEMOD FLT RST/EN VCC COM CLAMPE VEE OC ASCPWM Driver UCC21736-Q1 SLUSDM7 –OCTOBER 2019 www.ti.com Product Folder Links: UCC21736-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Power Supply

The input side power supply VCC can support a wide voltage range from 3V to 5.5V. The device supports both unipolar and bipolar power supply on the output side, with a wide range from 13V to 33V from VDD to VEE. The negative power supply with respect to switch source or emitter is usually adopted to avoid false turn on when the other switch in the phase leg is turned on. The negative voltage is especially important for SiC MOSFET due to its fast switching speed.

8.3.2 Driver Stage

can drive a SiC MOSFET module, IGBT module or paralleled discrete devices directly without extra buffer stage. UCC21736-Q1 can also be used to drive higher power modules or parallel modules with extra buffer stage. below VDD voltage. The effective resistance of the hybrid pull-up structure during this period is about 2 x ROL . the power semiconductor and reduces the turn on switching loss. time, but also helps to increase the noise immunity considering the miller effect. Figure 39. Gate Driver Output Stage

8.3.3 VCC, VDD and VEE Undervoltage Lockout (UVLO)

pulled up externally to VCC to indicate the power good.

8.3.4 Active Pulldown

can prevent the output be false turned on before the device is back to control. Figure 40. Active Pulldown

8.3.5 Short Circuit Clamping

Figure 41. Short Circuit Clamping

8.3.6 External Active Miller Clamp

Figure 42. Active Miller Clamp

8.3.7 Overcurrent and Short Circuit Protection

when the power semiconductor is turned off. pin to DSP/MCU. The output is held to LOW after the fault is detected, and can only be reset by the RST/EN pin. resistors. The DESAT threshold can be programmable in this case, which increases the versatility of the device. Detailed application diagrams of desaturation circuit and shunt resistor will be given in .

High current and high dI/dt during the overcurrent and short circuit fault can cause a voltage bounce on shunt resistor’s parasitic inductance and board layout parasitic, which results in false trigger of OC pin. High precision, low ESL and small value resistor must be used in this approach.
Shunt resistor approach is not recommended for high power applications and short circuit protection of the low power applications. The detailed applications of the overcurrent and short circuit feature will be discussed in the Application and Implementation section.

Figure 43. Overcurrent and Short Circuit Protection

8.3.8 Fault (FLT, Reset and Enable (RST/EN)

The FLT pin of UCC21736-Q1 is open drain and can report a fault signal to the DSP/MCU when the overcurrent and short circuit fault is detected through OC pin. The FLT pin is pulled down to GND, and is held in low state unless a reset signal is received from RST/EN. The device has a fault mute time tFLTMUTE, within which the device ignores any reset signal. The RST/EN is pulled down internally. The device is disabled by default if the RST/EN pin is floating. The pin has two purposes:

Resets the overcurrent and short circuit fault signaled on FLT pin. The RST/EN pin is active low, if the pin is set and held in low state for more than tRSTFIL, the fault signal is reset andFLT is reset back to the high impedance status at the rising edge of RST/EN pin.
Enable and shutdown the device. If the RST/EN pin is pulled low, the driver is disabled and shut down by the regular turn off. The pin must be pulled up externally to enable the part, otherwise the device is disabled by default.

8.3.9 ASC Protection and APWM Monitor

When VCC loses power, or MCU is malfunctional, the motor can lose control and reversely charging the battery. Overvoltage of the battery can cause battery break down, or even the fire hazard. In this case, the active short circuit (ASC) function is used to protect the system by forcing the output signal high, turning on the switch and creating an active short circuit loop between the phases to bypass the battery. The timing diagram of ASC protection with VCC UVLO, VDD UVLO and OC fault are shown in Figure 36, Figure 37, and Figure 38. The UCC21736-Q1 encodes the voltage signal VASC to a PWM signal, passing through the reinforced isolation barrier, and output to APWM pin on the input side. Thus the ASC pin status can be monitored. The PWM signal can either be transferred directly to DSP/MCU to calculate the duty cycle, or filtered by a simple RC filter as an analog signal. The ASC input voltage varies from 0V to 5V, and the corresponding duty cycle of the APWM output ranges from 95% to 5% with 400kHz frequency.

8.4 Device Functional Modes

Table 1. Function Table

9 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The UCC21736-Q1 device is very versatile because of the strong drive strength, wide range of output power supply, high isolation ratings, high CMTI and superior protection and sensing features. The 1.5-kVRMS working voltage and 12.8-kVPK surge immunity can support up both SiC MOSFET and IGBT modules with DC bus voltage up to 2121V. The device can be used in both low power and high power applications such as the traction inverter in HEV/EV, on-board charger and charging pile, motor driver, solar inverter, industrial power supplies and etc. The device can drive the high power SiC MOSFET module, IGBT module or paralleled discrete device directly without external buffer drive circuit based on NPN/PNP bipolar transistor in totem-pole structure, which allows the driver to have more control to the power semiconductor and saves the cost and space of the board design. UCC21736-Q1 can also be used to drive very high power modules or paralleled modules with external buffer stage. The input side can support power supply and microcontroller signal from 3.3V to 5V, and the device level shifts the signal to output side through reinforced isolation barrier. The device has wide output power supply range from 13V to 33V and support wide range of negative power supply. This allows the driver to be used in SiC MOSFET applications, IGBT application and many others. The 12V UVLO benefits the power semiconductor with lower conduction loss and improves the system efficiency. As a reinforced isolated single channel driver, the device can be used to drive either a low-side or high-side driver. UCC21736-Q1 device features extensive protection and monitoring features, which can monitor, report and protect the system from various fault conditions.

Fast detection and protection for the overcurrent and short circuit fault. The feature is preferable in a split source SiC MOSFET module or a split emitter IGBT module. For the modules with no integrated current mirror or paralleled discrete semiconductors, the traditional desaturation circuit can be modified to implement short circuit protection. The semiconductor is shutdown when the fault is detected and FLTb pin is pulled down to indicate the fault detection. The device is latched unless reset signal is received from the RST/EN pin.
Soft turn-off feature to protect the power semiconductor from catastrophic breakdown during overcurrent and short circuit fault. The shutdown energy can be controlled while the overshoot of the power semiconductor is limited.
UVLO detection to protect the semiconductor from excessive conduction loss. Once the device is detected to be in UVLO mode, the output is pulled down and RDY pin indicates the power supply is lost. The device is back to normal operation mode once the power supply is out of the UVLO status. The power good status can be monitored from the RDY pin.
Active short circuit feature creates phase to phase short circuit in three-phase inverter to protect the battery from overvoltage breakdown.
The active miller clamp feature protects the power semiconductor from false turn on by driving an external MOSFET. This feature allows the flexibility of the board layout design and the pulldown strength of miller clamp FET.
Enable and disable function through the RSTb/EN pin.
Short circuit clamping.
Active pulldown.

9.2 Typical Application

shows the typical application of a half bridge using two UCC21736-Q1 isolated gate drivers. The half bridge is a basic element in various power electronics applications such as traction inverter in HEV/EV to convert the DC current of the electric vehicle’s battery to the AC current to drive the electric motor in the propulsion system. The topology can also be used in motor drive applications to control the operating speed and torque of the AC motors.

Figure 44. Typical Application Schematic

9.2.1 Design Requirements

and sink current, power dissipation, overcurrent and short circuit protection and etc. Table 2. Design Parameters

9.2.2 Detailed Design Procedure

9.2.2.1 Input filters for IN+, IN- and RST/EN

PCB layout and coupled capacitance.

9.2.2.2 PWM Interlock of IN+ and IN-

high, the outputs of both gate drivers are logic low to prevent the shoot through condition. Figure 45. PWM Interlock for a Half Bridge

9.2.2.3 FLT, RDY and RST/EN Pin Circuitry

the FLT, RDY and RST/EN pins.

Figure 46. FLT, RDY and RST/EN Pins Circuitry

9.2.2.4 RST/EN Pin Control

down, the device is in disabled status. With a 50kΩ pulldown resistor existing, the driver is disabled by default. extra control signal from microcontroller to RST/EN pin.

Figure 47. Automatic Reset Control

9.2.2.5 Turn on and turn off gate resistors

ROH_EFF is the effective internal pull up resistance of the hybrid pull-up structure, which is approximately 2 x ROL, about 0.7 Ω
ROL is the internal pulldown resistance, about 0.3 Ω
RON is the external turn on gate resistance
ROFF is the external turn off gate resistance
RG_Int is the internal resistance of the SiC MOSFET or IGBT module

Figure 48. Output Model for Calculating Peak Gate Current

Qg = 3300 nC
RG_Int = 1.7 Ω
RON=ROFF= 1 Ω The peak source and sink current in this case are: (2) Thus by using 1Ω external gate resistance, the peak source current is 5.9A, the peak sink current is 6.7A. The collector-to-emitter dV/dt during the turn on switching transient is dominated by the gate current at the miller plateau voltage. The hybrid pullup structure ensures the peak source current at the miller plateau voltage, unless the turn on gate resistor is too high. The faster the collector-to-emitter, Vce, voltage rises to VDC, the smaller the turn on switching loss is. The dV/dt can be estimated as Qgc/Isource_pk. For the turn off switching transient, the drain-to-source dV/dt is dominated by the load current, unless the turn off gate resistor is too high. After Vce reaches the dc bus voltage, the power semiconductor is in saturation mode and the channel current is controlled by Vge. The peak sink current determines the dI/dt, which dominates the Vce voltage overshoot accordingly. If using relatively large turn off gate resistance, the Vce overshoot can be limited. The overshoot can be estimated by: (3) Where
Lstray is the stray inductance in power switching loop, as shown in Figure 49
Iload is the load current, which is the turn off current of the power semiconductor
Cies is the input capacitance of the power semiconductor
Vplat is the plateau voltage of the power semiconductor
Vth is the threshold voltage of the power semiconductor

Figure 49. Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration

Qg is the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD
fsw is the switching frequency In this example, the PSW can be calculated as: (6)

ADVANCE□INFORMATION DS CLMPE _ PK D _ PK DS _ ON VI min(I , ) R o j b jb DRT T P 150 C \\ | DR Q SWP P P 0.10W 0.505W 0.605W UCC21736-Q1 SLUSDM7 –OCTOBER 2019 www.ti.com Product Folder Links: UCC21736-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Thus, the total power loss is: (7) When the board temperature is 125°C, the junction temperature can be estimated as: (8) Therefore, for the application in this example, with 125°C board temperature, the maximum switching frequency is ~50kHz to keep the gate driver in the thermal limit. By using a lower switching frequency, or increasing external gate resistance, the gate driver can be operated at a higher switching frequency.

9.2.2.6 External Active Miller Clamp

External active miller clamp feature allows the gate driver to stay at the low status when the gate voltage is detected below VCLMPTH. When the other switch of the phase leg turns on, the dV/dt can cause a current through the parasitic miller capacitance of the switch and sink in the gate driver. The sinking current causes a negative voltage drop on the turn off gate resistance, and bumps up the gate voltage to cause a false turn on. The external active miller clamp features allows flexibility of board layout and active miller clamp pulldown strength. Limited by the board layout, if the driver cannot be placed close enough to the switch, external active miller clamp MOSFET can be placed close to the switch and the MOSFET can be chosen according to the peak current needed. Caution must be exercised when the driver is place far from the power semiconductor. Since the device has high peak sink and source current, the high dI/dt in the gate loop can cause a ground bounce on the board parasitics. The ground bounce can cause a positive voltage bump on CLMPE pin during the turn off transient, and results in the external active miller clamp MOSFET to turn on shortly and add extra drive strength to the sink current. To reduce the ground bounce, a 2Ω resistance is recommended to the gate of the external active clamp MOSFET. When the VOUTH is detected to be lower than VCLMPTH above VEE, the CLMPE pin outputs a 5V voltage with respect to VEE, the external clamp FET is in linear region and the pulldown current is determined by the peak drain current, unless the on-resistance of the external clamp FET is large. (9) Where

ID_PK is the peak drain current of the external clamp FET
VDS is the drain-to-source voltage of the clamp FET when the CLMPE is activated
RDS_ON is the on-resistance of the external clamp FET The total delay time of the active miller clamp circuit from the gate voltage detection threshold VCLMPTH can be calculated as tDCLMPE+tCLMPER. tCLMPER depends on the parameter of the external active miller clamp MOSFET. As long as the total delay time is longer than the deadtime of high side and low side switches, the driver can effectively protect the switch from false turn on issue caused by miller effect.

Figure 50. External Active Miller Clamp Configuration

9.2.2.7 Overcurrent and Short Circuit Protection

9.2.2.7.1 Protection Based on Power Modules with Integrated SenseFET

should also be considered for the protection circuitry design.

Figure 51. Overcurrent and Short Circuit Protection Based on IGBT Module with SenseFET

9.2.2.7.2 Protection Based on Desaturation Circuit

VOCTH is the detection threshold voltage of the gate driver
R1, R2 and R3 are the resistance of the voltage divider
CBLK is the blanking capacitor
VF is the forward voltage of the high voltage diode DHV The modified desaturation circuit has all the benefits of the conventional desaturation circuit. The circuit has negligible power loss, and is easy to implement. The detection threshold voltage of IGBT and blanking time can be programmed by external components. Different with the conventional desaturation circuit, the overcurrent detection threshold voltage of the IGBT can be modified to any voltage level, either higher or lower than the detection threshold voltage of the driver. A parallel schottky diode can be connected between OC and COM pins to prevent the negative voltage on the OC pin in noisy system. Since the desaturation circuit measures the VCE of the IGBT or VDS of the SiC MOSFET, not directly the current, the accuracy of the protection is not as high as the SenseFET based protection method. The current threshold cannot be accurately controlled in the protection.

Figure 52. Overcurrent and Short Circuit Protection Based on Desaturation Circuit

9.2.2.7.3 Protection Based on Shunt Resistor in Power Loop

optimal voltage drop and minimum noise injection to the gate loop. Figure 53. Overcurrent and Short Circuit Protection Based on Shunt Resistor

9.2.2.8 Higher Output Current Using an External Current Buffer

D45VH10 pair is up to 20 A peak. capacitor CSTO. CSTO is calculated using .

ISTO is the the internal STO current source, 400mA
tSTO is the desired STO timing

Figure 54. Current Buffer for Increased Drive Strength

10 Power Supply Recommendations

11 Layout

11.1 Layout Guidelines

Due to the strong drive strength of UCC21736-Q1, careful considerations must be taken in PCB design. Below are some key points:

The driver should be placed as close as possible to the power semiconductor to reduce the parasitic inductance of the gate loop on the PCB traces
The decoupling capacitors of the input and output power supplies should be placed as close as possible to the power supply pins. The peak current generated at each switching transient can cause high dI/dt and voltage spike on the parasitic inductance of PCB traces
The driver COM pin should be connected to the Kelvin connection of SiC MOSFET source or IGBT emitter. If the power device does not have a split Kelvin source or emitter, the COM pin should be connected as close as possible to the source or emitter terminal of the power device package to separate the gate loop from the high power switching loop
Use a ground plane on the input side to shield the input signals. The input signals can be distorted by the high frequency noise generated by the output side switching transients. The ground plane provides a low- inductance filter for the return current flow
If the gate driver is used for the low side switch which the COM pin connected to the dc bus negative, use the ground plane on the output side to shield the output signals from the noise generated by the switch node; if the gate driver is used for the high side switch, which the COM pin is connected to the switch node, ground plane is not recommended
If ground plane is not used on the output side, separate the return path of the OC and AIN ground loop from the gate loop ground which has large peak source and sink current
No PCB trace or copper is allowed under the gate driver. A PCB cutout is recommended to avoid any noise coupling between the input and output side which can contaminate the isolation barrier

11.2 Layout Example

Figure 55. Layout Example

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

Isolation Glossary

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resource

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 12-Dec-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PUCC21736QDWQ1 ACTIVE SOIC DW 16 40 TBD Call TI Call TI -40 to 125 PUCC21736QDWRQ1 ACTIVE SOIC DW 16 2000 TBD Call TI Call TI -40 to 125 UCC21736QDWQ1 PREVIEW SOIC DW 16 40 TBD Call TI Call TI -40 to 125 UCC21736QDWRQ1 PREVIEW SOIC DW 16 2000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 12-Dec-2019 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. SOIC - 2.65 mm max heightDW 16 SMALL OUTLINE INTEGRATED CIRCUIT7.5 x 10.3, 1.27 mm pitch 4224780/A

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Product Information

PUCC21736QDWQ1 specifications and overview.

Summary

UCC21736-Q1 10-A Source and Sink Reinforced Isolated Single Channel Gate Driver for SiC/IGBT with Active Protection and High-CMTI

Description

UCC21736-Q1 10-A Source and Sink Reinforced Isolated Single Channel Gate Driver for SiC/IGBT with Active Protection and High-CMTI

Source title PUCC21736QDWQ1 Datasheet(PDF) - Texas Instruments

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