Logic IC

PUCC21550BQDWRQ1

Texas Instruments

UCC21550x-Q1 Automotive 4-A, 6-A, Reinforced Isolation Dual-Channel Gate Driver MAY 2023

Manufacturer: Texas Instruments

Document: 41 Pages / 2Mb

Request Quote Download Datasheet Read online HTML view

More from Texas Instruments Browse P parts

Online Datasheet

Read PUCC21550BQDWRQ1 online.

UCC21550-Q1 TI | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 41

Technical content

UCC21550x-Q1 Automotive 4-A, 6-A, Reinforced Isolation Dual-Channel Gate Driver

1 Features

Universal: dual low-side, dual high-side or halfbridge driver
AEC-Q100 qualified with the following results – Device temperature grade 1 – Device HBM ESD classification level H2 – Device CDM ESD classification level C4B
Functional safety quality-managed – Documentation available to aid functional safety system design
Junction temperature range –40 to +150°C
Up to 4-A peak source and 6-A peak sink output
Common-mode transient immunity (CMTI) greater than 125 V/ns
Up to 25-V VDD output drive supply – 5-V ,8-V VDD UVLO options
Switching parameters: – 33-ns typical propagation delay – 5-ns maximum delay matching – 6-ns maximum pulse-width distortion – 10-µs maximum VDD power-up delay
Isolation barrier life > 40 Years
UVLO protection for all power supplies
Fast disable for power sequencing
Safety-related certifications: – 7000-VPK reinforced isolation per DIN V VDE V 0884-11:2017-01 – 5000-VRMS isolation for 1 minute per UL 1577 – CQC certification per GB4943.1-2011

2 Applications

HEV and EV battery chargers
Isolated converters in AC-DC and DC-DC
Motor drive and inverters
Uninterruptible power supply (UPS)

3 Description

The UCC21550x -Q1 is an isolated dual channel gate driver family with programmable dead time and wide temperature range. This device exhibits consistent performance and robustness under extreme temperature conditions. It is designed with 4-A peak-source and 6-A peak-sink current to drive power MOSFET, SiC, GaN, and IGBT transistors. The UCC21550x -Q1 can be configured as two low- sidedrivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 5-kVRMS isolation barrier, with a minimum of 125-V/ns common-mode transient immunity (CMTI). Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, integrated de-glitch filter that rejects input transients shorter than 5ns, and negative voltage handling for up to –2V spikes for 200ns on input and output pins. All supplies have UVLO protection. Device Information(1) PART NUMBER PACKAGE REC. VDD SUPPLY MIN UCC21550AQDWRQ1 SOIC (16) 6.7 V UCC21550BQDWRQ1 (2) SOIC (16) 9.2 V (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Product Preview Copyright © 2022, Texas Instruments Incorporated Driver VDDB OUTB VSSB NC NC UVLODEMODMOD Driver VDDA OUTA VSSA UVLODEMODMOD Functional Isolation Isolation Barrier Input Logic Disable, UVLO, Dead Time 3,8 GND INB NC DT DIS INA VCCI Functional Block Diagram ADVANCE INFORMATION UCC21550-Q1 SLUSEU6 – MAY 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains ADVANCE INFORMATION for pre-production products; subject to change without notice.

13.4 Receiving Notification of Documentation Updates..36

14 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES May 2023 * A Version Advance Information Release UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: UCC21550-Q1

5 Description (continued)

The UCC21550x -Q1 device accepts VDD supply voltages up to 25 V. An input VCCI range from 3 V to 5.5 V makes the driver suitable for interfacing with digital controllers. All supply voltage pins have undervoltage lock-out (UVLO) protection. With all these advanced features, the UCC21550x -Q1 device enables high efficiency, high power density, and robustness in a wide variety of power applications. www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: UCC21550-Q1

6 Pin Configuration and Functions

Figure 6-1. DW Package 16-Pin SOIC Top View Table 6-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. DIS 5 I Disables both driver outputs when asserted high, enables when asserted low. This pin is internally pulled high if left floating. Tie to GND if not used. It is recommended to use an RC filter on DIS, with R = 0Ω to 100Ω and C = 100pF to 1000pF. DT 6 I

DT pin float or short to VCCI disables dead time interlock function
Place 1.7kΩ to 100kΩ ressitor (RDT) between DT and GND to set minimum dead time between driver outputs
Place 0Ω to 150Ω resistor, or short DT pin to GND to st overlap protection mode GND 4 P Primary-side ground reference. All signals in the primary side are referenced to this ground. INA 1 I Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open. It is recommended to use an RC filter on INA, with R = 10Ω to 100Ω and C = 10pF to 100pF. INB 2 I Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open. It is recommended to use an RC filter on INA, with R = 10Ω to 100Ω and C = 10pF to 100pF. NC 7 – No Internal connection. NC 12 – No internal connection. NC 13 – No internal connection. OUTA 15 O Output of driver A. Connect to the gate of the A channel transistor. OUTB 10 O Output of driver B. Connect to the gate of the B channel transsitor. VCCI 3 P Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close to the device as possible. VCCI 8 P Primary-side supply voltage. This pin is internally shorted to pin 3. VDDA 16 P Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located as close to the device as possible. VDDB 11 P Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL capacitor located as close to the device as possible. VSSA 14 P Ground for secondary-side driver A. Ground reference for secondary side A channel. VSSB 9 P Ground for secondary-side driver B. Ground reference for secondary side B channel. (1) P = Power, G = Ground, I = Input, O = Output UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: UCC21550-Q1

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCCI to GND Input bias supply voltage –0.3 6 V VDDA, VDDB to VSS Output bias supply voltage –0.3 30 V OUTA to VSSA, OUTB to VSSB Output signal DC voltage –0.3 VDDA/B + 0.3 V Outout signal transient voltage for 200-ns –2 VDDA/B + 0.3 V INA, INB to GND PWM to GND Input signal DC voltage –0.3 VCCI + 0.3(2) V DT, DIS to GND –0.3 VCCI + 0.3(2) V TJ Junction temperature –40 150 ℃ Tstg Storage temperature –65 150 ℃ (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Maximum voltage must not exceed 6 V.

7.2 ESD Ratings (Automotive)

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V Charged device model (CDM), per AEC Q100-011 ±500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCCI Input bias pin supply voltage 3.0 5.5 V VDDA, VDDB UCC21550A-Q1 - 5V UVLO Output bias supply voltage, VDDA-VSSA, VDDB-VDDB 6.5 25 V VDDA, VDDB UCC21550B-Q1 - 8V UVLO Output bias supply voltage, VDDA-VSSA, VDDB-VDDB 9.2 25 V TJ Junction temperature –40 150 ℃

7.4 Thermal Information

THERMAL METRIC(1) UCC21550 UNITDW

16 PINS

RθJA Junction-to-ambient thermal resistance 67.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 34.4 °C/W RθJB Junction-to-board thermal resistance 32.1 °C/W ΨJT Junction-to-top(center) characterization parameter 18.0 °C/W ΨJB Junction-to-board characterization parameter 31.6 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: UCC21550-Q1

7.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PD Maximum power dissipation (both sides) VCCI = 5V, VDDA/VDDB = 20V, INA/B = 3.3V, 460kHz 50% duty cycle square wave, CL=2.2nF, TJ=150℃, TA=25℃ 950 mW PDI Maximum power dissipation by transmitter side 50 mW PDA, PDB Maximum power dissipation by each driver side 450 mW UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: UCC21550-Q1

7.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFIC ATION UNIT CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 mm CPG External Creepage(1) Shortest terminal-to-terminal distance across the package surface >8 mm DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V Material Group According to IEC 60664-1 I Overvoltage category Rated mains voltage ≤ 600 VRMS I-IV Rated mains voltage ≤ 1000 VRMS I-III DIN V VDE 0884-11 (VDE V 0884-11): 2017-01(2) VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; see Figure 1 1500 VRMS DC voltage 2121 VDC VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification) VTEST = 1.2 × VIOTM, t = 1 s (100% production) 7070 VPK VIOSM Maximum surge isolation voltage(3) Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 12800 VPK (qualification)

8000 VPK

qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s pC Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s Method b1: At routine test (100% production) and preconditioning (type test), Vini = 1.2 × VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM , tm = 1 s CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1 MHz ~1.2 pF RIO Insulation resistance, input to output(5) VIO = 500 V, TA = 25°C >1012 ΩVIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 VIO = 500 V at TS = 150°C >109 Pollution degree 2 Climatic category 40/125/21 UL 1577 VISO Withstand isolation voltage for UCC2155x VTEST = VISO = 5000 VRMS, t = 60 s (qualification), VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production)

5000 VRMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these specifications. (2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. (3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. (4) Apparent charge is electrical discharge caused by a partial discharge (pd). (5) All pins on each side of the barrier tied together creating a two-pin device. www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: UCC21550-Q1

7.7 Safety-Related Certifications

Plan to certify according to DIN V VDE V 0884-10 (VDE V 0884-10):2006- 12 and DIN EN 61010-1 (VDE 0411-1):2011-07 Plan to certify according to UL 1577 Component Recognition Program Plan to certify according to GB4943.1-2011 Basic Insulation Maximum Transient Overvoltage, 7000 VPK; Maximum Repetitive Peak Voltage, 2121 VPK Maximum Surge Isolation Voltage, 6250 VPK Single protection, 5000 VRMS Reinforced Insulation, Altitude ≤ 5000m, Tropical Climate, 660 VRMS maximum working voltage Certificate planned Certificate planned Certificate planned UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: UCC21550-Q1

7.8 Electrical Characteristics

VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitance from VCCI to GND, VVDDx = 12V (for 5V and 8V UVLO) , 1.1-µF capacitance from VDDA and VDDB to VSSA and VSSB, DT pin floating, EN = VCC or DIS = GND, TJ = –40°C to +150°C, CL = 0 pF, unless otherwise noted (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTS IVCC VCC quiescent current VINx = 0 V, EN = VCC; VCC=3.3V 1.5 2.5 mA VINx = 0 V, EN = VCC; VCC=5V 1.5 2.5 VINx = VCC, EN = VCC; VCC=3.3V 4.7 6.7 VINx = VCC, EN = VCC; VCC=5V 4.7 6.7 VINx PWM at 0V to VCC at fSW = 500kHz, EN = VCC; VCC=3.3V 3.2 4.6 VINx PWM at 0V to VCC at fSW = 500kHz, EN = VCC; VCC=5V 3.2 4.6 IVDDx VDDx quiescent current VINx = 0 V, EN = VCC; 2.7 3.7 mA VINx = 0 V, EN = VCC;VDD=25V 2.7 3.7 VINx = VCC, EN = VCC; 2.7 3.7 VINx = VCC, EN = VCC; VDD=25V 2.7 3.7 VINx PWM at 0V to VCC at fSW = 500kHz, EN = VCC; 4 5 VINx PWM at 0V to VCC at fSW = 500kHz, EN = VCC; VDD=25V 4 5 VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS VVCC_ON VCC UVLO Rising Threshold 2.55 2.7 2.85 VVVCC_OFF VCC UVLO Falling Threshold 2.35 2.5 2.65 VVCC_HYS VCC UVLO Threshold Hysteresis 0.2 tVCC+ to OUT VCC UVLO ON Delay 18 42 80 µstVCC– to OUT VCC UVLO OFF Delay 0.5 1.2 7 tVCCFIL VCC UVLO Deglitch Filter 0.4 0.9 3.1 VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS AND DELAY VVDD_ON VDDx UVLO Rising Threshold 5-V UVLO Option 5.7 6.0 6.3 VVVDD_OFF VDDx UVLO Falling Threshold 5.4 5.7 6.0 VVDD_HYS VDDx UVLO Threshold Hysteresis 0.30 VVDD_ON VDDx UVLO Rising Threshold 8-V UVLO Option 7.7 8.5 8.9 VVVDD_OFF VDDx UVLO Falling Threshold 7.2 7.9 8.4 VVDD_HYS VDDx UVLO Threshold Hysteresis 0.6 tVDD+ to OUT VDDx UVLO ON Delay 10 µstVDD– to OUT VDDx UVLO OFF Delay 0.1 0.5 2 tVDDFIL VDDx UVLO Deglitch Filter 0.1 0.17 INA, INB, AND / DIS VINx_H, VDIS_H , Input High Threshold Voltage 2 2.3 VVINx_L, VDIS_L , Input Low Threshold Voltage 0.8 1 VINx_HYS, VDIS_HYS , Input Threshold Hysteresis 1 RINxD INx Pin Pull Down Resistance INx = 3.3V 50 90 185 kΩ RDISD DIS Pin Pull Up Resistance DIS= 3.3V 50 90 185 kΩ OUTPUT DRIVER STAGE IO+ Peak Output Source Current CVDDx = 10 µF, CL = 0.22 µF, f = 1 kHz –4 A IO– Peak Output Sink Current CVDDx = 10 µF, CL = 0.22 µF, f = 1 kHz 6 A ROH Pull up resistance IOUTx = –0.05A 5 Ω ROL Pull down resistance IOUTx = 0.05A 0.55 ACTIVE PULL-DOWN www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: UCC21550-Q1

7.8 Electrical Characteristics (continued)

7.9 Switching Characteristics

125 V/ns

|CML| Low-level Common Mode Transient Immunity (see xxx) 125 V/ns UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: UCC21550-Q1

7.10 Typical Characteristics

VDDA = VDDB= 12 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted. TIME Y Axis Title (Unit) 2.2nF Load 10nF Load VDDA = VDDB= 15 V Figure 7-1. Typical Output Waveforms www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: UCC21550-Q1

8 Parameter Measurement Information

8.1 Propagation Delay and Pulse Width Distortion

Figure 8-1 shows how one calculates pulse width distortion (t PWD) and delay matching (t DM) from the propagation delays of channels A and B. It can be measured by ensuring that both inputs are in phase and disabling the dead time function by shorting the DT Pin to VCC. INA/B tPDLHA OUTA OUTB tPDLHB tDM tPDHLB tPDHLA tPWDB = |tPDLHB t tPDHLB| Figure 8-1. Overlapping Inputs, Dead Time Disabled

8.2 Rising and Falling Time

Figure 8-2 shows the criteria for measuring rising (t RISE) and falling (t FALL) times. For more information on how short rising and falling times are achieved see Section 9.3.4. 20% tRISE 80% 90% 10% tFALL Figure 8-2. Rising and Falling Time Criteria

8.3 Input and Disable Response Time

Figure 8-3 shows the response time of the disable function. It is recommended to bypass using a ≈1nF low ESR/ESL capacitor close to DIS pin when connecting DIS pin to a micro controller with distance. For more information, see Section 9.4.1. INA DIS OUTA tPDHL 10% 10% DIS Low Response Time tPDLH DIS High Response Time 90% 90% 10% Figure 8-3. Disable Pin Timing UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: UCC21550-Q1

8.4 Programmable Dead Time

Leaving the DT pin open or tying it to GND through an appropriate resistor (R DT) sets a dead-time interval. For more details on dead time, refer to Section 9.4.2. OUTB INA INB 10% 90% Dead Time (Set by RDT) tPDHL Dead Time (Determined by Input signals if longer than DT set by RDT) 90% 10% tPDLH tPDHL OUTA Figure 8-4. Dead-Time Switching Parameters

8.5 Power-up UVLO Delay to OUTPUT

Before the driver is ready to deliver a proper output state, there is a power-up delay from the UVLO rising edge to output and it is defined as t VCCI+ to OUT for VCCI UVLO (typically 40us) and t VDD+ to OUT for VDD UVLO (typically 5us). It is recommended to consider proper margin before launching PWM signal after the driver's VCCI and VDD bias supply is ready. Figure 8-5 and Figure 8-6 show the power-up UVLO delay timing diagram for VCCI and VDD. If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output will not update until t VCCI+ to OUT or t VDDx+ to OUT after VCCI or VDD crossing its UVLO rising threshold. However, when either VCCI or VDD receive a voltage less than their respective off thresholds, there is <2µs delay, depending on the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to ensure safe operation during VCCI or VDD brownouts. VCCI, INx VDDx VVCCI_ON OUTx VVCCI_OFF tVCCI+ to OUT Figure 8-5. VCCI Power-up UVLO Delay VCCI, INx VDDx VVDD_ON OUTx tVDD+ to OUT VVDD_OFF Figure 8-6. VDDA/B Power-up UVLO Delay www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: UCC21550-Q1

8.6 CMTI Testing

Figure 8-7 is a simplified diagram of the CMTI testing configuration. Figure 8-7. Simplified CMTI Testing Setup UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: UCC21550-Q1

9 Detailed Description

9.1 Overview

In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are often placed between the output of control devices and the gates of power transistors. There are several instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors. This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V logic signal capable of only delivering a few mA. The UCC21550x -Q1 is a flexible dual gate driver which can be configured to fit a variety of power supply and motor drive topologies, as well as drive several types of transistors, including SiC MOSFETs. The device has many features that allow it to integrate well with control circuitry and protect the gates it drives such as: resistor-programmable dead time (DT) control, a DIS pin, and under voltage lock out (UVLO) for both input and output voltages. The UCC21550x -Q1 also hold its outputs low when the inputs are left open or when the input pulse is not wide enough. The driver inputs are CMOS and TTL compatible for interfacing to digital and analog power controllers alike. Each channel is controlled by its respective input pins (INA and INB), allowing full and independent control of each of the outputs.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)

The UCC21550x-Q1 has an internal undervoltage lock out (UVLO) protection feature on the supply circuit blocks between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than V VDD_ON at device start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the effected output low, regardless of the status of the input pins (INA and INB). When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in Figure 9-1 ). In this condition, the upper PMOS is resistively held off by R Hi-Z while the lower NMOS gate is tied to the driver output through R CLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device, typically around 1.5 V, when no bias power is available. RHI_Z VDD RCLAMP OUT VSS RCLAMP is activated during UVLO Output Control Figure 9-1. Simplified Representation of Active Pulldown Feature The VDD UVLO protection has a hysteresis feature (V VDD_HYS). This hysteresis prevents chatter when there is ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is bound to happen when the device starts switching and operating current consumption increases suddenly. The input side of the UCC21550x -Q1 also has an internal undervoltage lock out (UVLO) protection feature. The device isn't active unless the voltage, VCCI, is going to exceed V VCCI_ON on start up. And a signal will cease to be delivered when that pin receives a voltage less than V VCCI_OFF. And, just like the UVLO for VDD, there is hysteresis (VVCCI_HYS) to ensure stable operation. UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: UCC21550-Q1

All versions of the UCC21550x-Q1 can withstand an absolute maximum of 30 V for VDD, and 5.5 V for VCCI. Table 9-1. UCC21550x-Q1 VCCI UVLO Feature Logic CONDITION INPUTS OUTPUTS INA INB OUTA OUTB VCCI-GND < VVCCI_ON during device start up H L L L VCCI-GND < VVCCI_ON during device start up L H L L VCCI-GND < VVCCI_ON during device start up H H L L VCCI-GND < VVCCI_ON during device start up L L L L VCCI-GND < VVCCI_OFF after device start up H L L L VCCI-GND < VVCCI_OFF after device start up L H L L VCCI-GND < VVCCI_OFF after device start up H H L L VCCI-GND < VVCCI_OFF after device start up L L L L Table 9-2. UCC21550x-Q1 VDD UVLO Feature Logic CONDITION INPUTS OUTPUTS INA INB OUTA OUTB VDD-VSS < VVDD_ON during device start up H L L L VDD-VSS < VVDD_ON during device start up L H L L VDD-VSS < VVDD_ON during device start up H H L L VDD-VSS < VVDD_ON during device start up L L L L VDD-VSS < VVDD_OFF after device start up H L L L VDD-VSS < VVDD_OFF after device start up L H L L VDD-VSS < VVDD_OFF after device start up H H L L VDD-VSS < VVDD_OFF after device start up L L L L

9.3.2 Input and Output Logic Table

Table 9-3. INPUT/OUTPUT Logic Table(1) Assume VCCI, VDDA, VDDB are powered up. See Section 9.3.1 for more information on UVLO operation modes. INPUTS DIS OUTPUTS NOTE INA INB OUTA OUTB L L L L L If Dead Time function is used, output transitions occur after the dead time expires. See Section 9.4.2 L H L L H H L L H L H H L L L H H L H H DT pin left open or tied to VCCI Left Open Left Open L L L - X X H or Left Open L L - (1) "X" means L, H or left open.

9.3.3 Input Stage

The input pins (INA, INB, and DIS) of the UCC21550x -Q1 are based on a TTL and CMOS compatible input- threshold logic that is totally isolated from the VDD supply voltage. The input pins are easy to drive with logic-level control signals (Such as those from 3.3-V micro-controllers), since the UCC21550x -Q1 has typical high threshold (VINAH) of 2.0 V and a typical low threshold of 1 V. A wide hysterisis (V INA_HYS) of 1 V makes for good noise immunity and stable operation. If any of the inputs are ever left open, internal pull-down resistors force the pin low. These resistors are typically 90 kΩ (See Section 9.2). However, it is still recommended to ground an input if it is not being used. www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: UCC21550-Q1

Since the input side of the UCC21550x -Q1 is isolated from the output drivers, the input signal amplitude can be larger or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater flexibility when integrating with control signal sources, and allows the user to choose the most efficient VDD for their chosen gate. That said, the amplitude of any signal applied to INA or INB must never be at a voltage higher than VCCI.

9.3.4 Output Stage

The UCC21550x -Q1 output stages feature a pull-up structure which delivers the highest peak-source current when it is most needed, during the Miller plateau region of the power-switch turn on transition (when the power switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel MOSFET and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to provide a brief boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing states from low to high. The ROH parameter is a DC measurement and it is representative of the on-resistance of the P-channel device only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on only for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the UCC21550x-Q1 pull-up stage during this brief turn-on phase is much lower than what is represented by the R OH parameter. Therefore, the value of ROH belies the fast nature of the UCC21550x-Q1 turn-on time. The pull-down structure in the UCC21550x -Q1 is simply composed of an N-channel MOSFET. The R OL parameter, which is also a DC measurement, is representative of the impedance of the pull-down state in the device. Both outputs of the UCC21550x-Q1 are capable of delivering 4-A peak source and 6-A peak sink current pulses. The output voltage swings between VDD and VSS provides rail-to-rail operation, thanks to the MOS-out stage which delivers very low drop-out. VDD OUT VSS Pull Up Shoot- Through Prevention Circuitry Input Signal ROH ROL RNMOS Figure 9-2. Output Stage UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: UCC21550-Q1

9.3.5 Diode Structure in the UCC21550x-Q1

Figure 9-3 illustrates the multiple diodes involved in the ESD protection components of the UCC21550x -Q1. This provides a pictorial representation of the absolute maximum rating for the device. INA INB DIS DT

20 V 20 V

3,8 VCCI 30 V 30 V VDDB OUTB OUTA VSSA VSSB VDDA Figure 9-3. ESD Structure

9.4 Device Functional Modes

9.4.1 Disable Pin

Setting the DIS pin high (or left open) shuts down both outputs simultaneously. Grounding the DIS pin allows the UCC21550x-Q1 to operate normally. The DIS response time is in the range of 48 ns and quite responsive, which is as fast as propagation delay. The DIS pin is only functional (and necessary) when VCCI stays above the UVLO threshold. It is recommended to tie this pin to ground if the DIS pin is not used to achieve better noise immunity, and it is recommended to bypass using a ≈1-nF low ESR/ESL capacitor close to DIS pin when connecting DIS pin to a micro controller with distance.

9.4.2 Programmable Dead-Time (DT) Pin

The UCC21550x-Q1 allows the user to adjust dead time (DT) in the following ways:

9.4.2.1 Tying the DT Pin to VCC

Outputs completely match inputs, so no dead time is asserted. This allows outputs to overlap.

9.4.2.2 DT Pin Connected to a Programming Resistor Between DT and GND Pins

One can program t DT by placing a resistor, R DT, between the DT pin and GND. The appropriate R DT value can be determined, where RDT is in kΩ and tDT is in ns: t DT ≈ 8.6 × R DT + 13 (1) DT pin current will be less than 10uA when RDT=100kΩ. It is not recommended to leave the DT pin floating. An input signal’s falling edge activates the programmed dead time for the other signal. The output signals’ dead time is always set to the longer of either the driver’s programmed dead time or the input signal’s own dead time. If both inputs are high simultaneously, both outputs will immediately be set low. This feature is used to prevent shoot-through, and it doesn’t affect the programmed dead time setting for normal operation. Various driver dead time logic operating conditions are illustrated and explained in Figure 9-4: www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: UCC21550-Q1

Figure 9-4. Input and Output Logic Relationship With Input Signals Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead time to OUTA. OUTA is allowed to go high after the programmed dead time. Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed dead time to OUTB. OUTB is allowed to go high after the programmed dead time. Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead time for OUTA. In this case, the input signal’s own dead time is longer than the programmed dead time. Thus, when INA goes high, it immediately sets OUTA high. Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead time to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, it immediately sets OUTB high. Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high. Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high. Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The UCC21550x -Q1 effectively combines both isolation and buffer-drive functions. The flexible, universal capability of the UCC21550x -Q1 (with up to 5.5-V VCCI and 25-V VDDA/VDDB) allows the device to be used as a low-side, high-side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or SiC MOSFETs. With integrated components, advanced protection features (UVLO, dead time, and disable) and optimized switching performance; the UCC21550x -Q1 enables designers to build smaller, more robust designs for enterprise, telecom, automotive, and industrial applications with a faster time to market. UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: UCC21550-Q1

10.2 Typical Application

The circuit in Figure 10-1 shows a reference design with the UCC21550x -Q1 driving a typical half-bridge configuration which could be used in several popular power converter topologies such as synchronous buck, synchronous boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications. Figure 10-1. Typical Application Schematic www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: UCC21550-Q1

10.2.1 Design Requirements

Table 10-1 lists reference design parameters for the example application: UCC21550x -Q1 driving 1200-V SiC- MOSFETs in a high side-low side configuration. Table 10-1. UCC21550x-Q1 Design Requirements PARAMETER VALUE UNITS Power transistor C2M0080120D - VCC 5.0 V VDD 20 V Input signal amplitude 3.3 V Switching frequency (fs) 100 kHz DC link voltage 800 V

10.2.2 Detailed Design Procedure

10.2.2.1 Designing INA/INB Input Filter

It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay) the signal at the output. However, a small input R IN-CIN filter can be used to filter out the ringing introduced by non-ideal layout or long PCB traces. Such a filter should use an R IN in the range of 0 Ω to100 Ω and a C IN between 10 pF and 100 pF. In the example, an RIN = 51 Ω and a CIN = 33 pF are selected, with a corner frequency of approximately 100 MHz. When selecting these components, it is important to pay attention to the trade-off between good noise immunity and propagation delay.

10.2.2.2 Select External Bootstrap Diode and its Series Resistor

The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop. Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver circuit. When selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes or SiC Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the loss introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage is 800 V DC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good margin. Therefore, a 1200-V SiC diode, C4D02120E, is chosen in this example. When designing a bootstrap supply, it is recommended to use a bootstrap resistor, R BOOT. A bootstrap resistor, is also used to reduce the inrush current in D BOOT and limit the ramp up slew rate of voltage of VDDA-VSSA during each switching cycle. Failure to limit the voltage to VDDx-VSSx to less than the Absolute Maximum Ratings of the FET and UCC21550x-Q1 may result in permanent damage to the device in certain cases. The recommended value for R BOOT is between 1 Ω and 20 Ω depending on the diode used. In the example, a current limiting resistor of 2.2 Ω is selected to limit the inrush current of bootstrap diode. The estimated worst case peak current through DBoot is, | : DD BDF DBoot pk Boot V V 20V 2.5VI 8AR 2.2 (2) where

VBDF is the estimated bootstrap diode forward voltage drop at 8 A. UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

22 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: UCC21550-Q1

10.2.2.3 Gate Driver Output Resistor

The external gate driver resistors, RON/ROFF, are used to: 1. Limit ringing caused by parasitic inductances/capacitances. 2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery. 3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss. 4. Reduce electromagnetic interference (EMI). As mentioned in Section 9.3.4, the UCC21550x -Q1 has a pull-up structure with a P-channel MOSFET and an additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak source current can be predicted with: § · ¨ ¸ ¨ ¸ © ¹ DD BDF OA NMOS OH ON GFET _ Int V V I min 4A, R || R R R (3) § · ¨ ¸ ¨ ¸ © ¹ DD OB NMOS OH ON GFET _ Int VI min 4A, R || R R R (4) where

RON: External turn-on resistance.
RGFET_INT: Power transistor internal gate resistance, found in the power transistor datasheet.
IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and the calculated value based on the gate drive loop resistance. In this example: | : : : : DD BDF OA NMOS OH ON GFET _ Int (5) | : : : : DD OB NMOS OH ON GFET _ Int V 20VI 2.5AR || R R R 1.47 || 5 2.2 4.6 (6) Therefore, the high-side and low-side peak source current is 2.4 A and 2.5 A respectively. Similarly, the peak sink current can be calculated with: § · ¨ ¸ ¨ ¸ © ¹ DD BDF GDF OA OL OFF ON GFET _ Int V V VI min 6A, R R || R R (7) § · ¨ ¸ ¨ ¸ © ¹ DD GDF OB OL OFF ON GFET _ Int V V I min 6A, R R || R R (8) where
ROFF: External turn-off resistance;
VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example is an MSS1P4.
IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated value based on the gate drive loop resistance. www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: UCC21550-Q1

In this example, DD BDF GDF OA OL OFF ON GFET _ Int | : : : (9) DD GDF OB OL OFF ON GFET _ Int V V 20V-0.75VI 3.7AR R || R R 0.55 0 4.6 | : : : (10) Therefore, the high-side and low-side peak sink current is 3.6 A and 3.7 A respectively. Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (C ISS) of the power transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the parasitic ringing period. Failure to control OUTx voltage to less than the Absolute Maximum Ratings in the datasheet (including transients) may result in permanent damage to the device in certain cases. To reduce excessive gate ringing, it is recommended to use a ferrite bead near the gate of the FET. External clamping diodes can also be added in the case of extended overshoot/undershoot, in order to clamp the OUTx voltage to the VDDx and VSSx voltages.

10.2.2.4 Gate to Source Resistor Selection

A gate to source resistor, RGS, is recommended to pull down the gate to the source voltage when the gate driver output is unpowered and in an indeterminate state. This resistor also helps to mitigate the risk of dv/dt induced turn-on due to Miller current before the gate driver is able to turn on and actively pull low. This resistor is typically sized between 5.1kΩ and 20kΩ, depending on the Vth and ratio of CGD to CGS of the power device.

10.2.2.5 Estimate Gate Driver Power Loss

The total loss, P G, in the gate driver subsystem includes the power losses of the UCC21550x -Q1(PGD) and the power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not included in PG and not discussed in this section. PGD is the key power loss which determines the thermal safety-related limits of the UCC21550x -Q1, and it can be estimated by calculating losses from several components. The first component is the static power loss, P GDQ, which includes quiescent power loss on the driver as well as driver self-power consumption when operating with a certain switching frequency. P GDQ is measured on the bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and ambient temperature. shows the per output channel current consumption vs operating frequency with no load. In this example, VVCCI = 5 V and V VDD = 20 V. The current on each power supply, with INA/INB switching from 0 V to 3.3 V at 100 kHz is measured to be I VCCI = 2.5 mA, and I VDDA = IVDDB = 1.5 mA. Therefore, the P GDQ can be calculated with GDQ VCCI VCCI VDDA DDA VDDB DDBP V I V I V I mW 72 u u | u (11) The second component is switching operation loss, P GDO, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Total dynamic loss due to load switching, P GSW, can be estimated with u u uGSW DD G SWP 2 V Q f (12) where

QG is the gate charge of the power transistor. UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

24 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: UCC21550-Q1

If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail to the negative rail. So, for this example application: u u u GSWP 2 20V 60nC 100kHz 240mW (13) QG represents the total gate charge of the power transistor switching 800 V at 20 A, and is subject to change with different testing conditions. The UCC21550x -Q1 gate driver loss on the output stage, P GDO, is part of PGSW. PGDO will be equal to P GSW if the external gate driver resistances are zero, and all the gate driver loss is dissipated inside the UCC21550x -Q1. If there are external turn-on and turn-off resistances, the total loss will be distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A, however, it will be non-linear if the source/sink current is saturated. Therefore, P GDO is different in these two scenarios. Case 1 - Linear Pull-Up/Down Resistor: GSW OH NMOS OL GDO OH NMOS ON GFET _ Int OL OFF ON GFET _ Int P R R RP 2 R R R R R R || || R R § · (14) In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21550x - Q1 gate driver loss can be estimated with: TBD (15) Case 2 - Nonlinear Pull-Up/Down Resistor: ª º u u u u« » « »¬ ¼ ³ ³ R _ Sys F _ SysT T GDO SW DD OUTA /B OUTA /B 0 0 P 2 f 4A V V t dt 6A V t dt (16) where

VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted. For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the PGDO will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pull-down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC21550x-Q1, PGD, is: GD GDQ GDOP P P (17) which is equal to TBD in the design example.

10.2.2.6 Estimating Junction Temperature

The junction temperature (TJ) of the UCC21550A-Q1 can be estimated with: J C JT GDT T P/c61 /c43 /c89 /c180 (18) where www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: UCC21550-Q1

TC is the UCC21550x-Q1 case-top temperature measured with a thermocouple or some other instrument, and
ΨJT is the Junction-to-top characterization parameter Using the junction-to-top characterization parameter ( ΨJT) instead of the junction-to-case thermal resistance (RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the total energy is released through the top of the case (where thermocouple measurements are usually conducted). RΘJC can only be used effectively when most of the thermal energy is released through the case, such as with metal packages or when a heatsink is applied to an IC package. In all other cases, use of R ΘJC will inaccurately estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy leaving through the top of the IC will be similar in both the testing environment and the application environment. As long as the recommended layout guidelines are observed, junction temperature estimates can be made accurately to within a few degrees Celsius. For more information, see the Semiconductor and IC Package Thermal Metrics Application Report.

10.2.2.7 Selecting VCCI, VDDA/B Capacitor

Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC) with sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an MLCC will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500 nF when a DC bias of 15 VDC is applied.

10.2.2.7.1 Selecting a VCCI Capacitor

A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended for this application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.

10.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor

A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor. The total charge needed per switching cycle can be estimated with VDD Total G SW I @100kHz No Load 1.5mAQ Q 60nC 75nC f 100kHz (19) where

QTotal: Total charge needed
QG: Gate charge of the power transistor.
IVDD: The channel self-current consumption with no load at 100kHz.
fSW: The switching frequency of the gate driver Therefore, the absolute minimum CBoot requirement is: Total Boot VDDA Q 75nCC 150nFV 0.5V (20) where
ΔVVDDA is the voltage ripple at VDDA, which is 0.5 V in this example. In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients. UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

Product Folder Links: UCC21550-Q1

Therefore, it is recommended to include a safety-related margin in the C Boot value and place it as close to the VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example. BootC 1 (21) Care should be taken when selecting the bootstrap capacitor to ensure that the VDD to VSS voltage does not drop below the recommended minimum operating level listed in section 6.3. The value of the bootstrap capacitor should be sized such that it can supply the initial charge to switch the power device, and then continuously supply the gate driver quiescent current for the duration of the high-side on-time. If the high-side supply voltage drops below the UVLO falling threshold, the high-side gate driver output will turn off and switch the power device off. Uncontrolled hard-switching of power devices can cause high di/dt and high dv/dt transients on the output of the driver and may result in permanent damage to the device. To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor placed very close to VDDx - VSSx pins with a low ESL/ESR. In this example a 100 nF, X7R ceramic capacitor, is placed in parallel with CBoot to optimize the transient performance. Note Too large CBOOT is not good. C BOOT may not be charged within the first few cycles and V BOOT could stay below UVLO. As a result, the high-side FET does not follow input signal command. Also during initial CBOOT charging cycles, the bootstrap diode has highest reverse recovery current and losses.

10.2.2.7.3 Select a VDDB Capacitor

Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as C VDD in Figure 10-1) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current for VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for CVDD. If the bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor, with a value over 10 µF, should be used in parallel with CVDD.

10.2.2.8 Dead Time Setting Guidelines

For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor is important for preventing shoot-through during dynamic switching. The UCC21550x-Q1 dead time specification in the electrical table is defined as the time interval from 90% of one channel’s falling edge to 10% of the other channel’s rising edge (see Figure 8-4). This definition ensures that the dead time setting is independent of the load condition, and guarantees linearity through manufacture testing. However, this dead time setting may not reflect the dead time in the power converter system, since the dead time setting is dependent on the external gate drive turn-on/off resistor, DC-Link switching voltage/current, as well as the input capacitance of the load transistor. Here is a suggestion on how to select an appropriate dead time for UCC21550x-Q1: Setting Req F _ Sys R _ Sys D onDT DT T T T (22) where

DTsetting: UCC21550x-Q1 dead time setting in ns, DTSetting = 8.6 × RDT(in kΩ) + 13.
DTReq: System required dead time between the real VGS signal of the top and bottom switch with enough margin, or ZVS requirement.
TF_Sys: In-system gate turn-off falling time at worst case of load, voltage/current conditions.
TR_Sys: In-system gate turn-on rising time at worst case of load, voltage/current conditions.
TD(on): Turn-on delay time, from 10% of the transistor gate signal to power transistor gate threshold. It should be noted that the UCC21550x-Q1 dead time setting is decided by the DT pin configuration (See Section 9.4.2), and it cannot automatically fine-tune the dead time based on system conditions. www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: UCC21550-Q1

10.2.2.9 Application Circuits with Output Stage Negative Bias

When parasitic inductances are introduced by non-ideal PCB layout and long package leads (for example, TO-220 and TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below the threshold. Below are a few examples of implementing negative gate drive bias. Figure 10-2 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on the isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power supply, VA, is equal to 25 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 25 V – 5.1 V ≈ 20 V. The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for a half-bridge configuration, and there will be steady state power consumption from RZ. Figure 10-2. Negative Bias with Zener Diode on Iso-Bias Power Supply Output UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

Product Folder Links: UCC21550-Q1

The last example, shown in Figure 10-4 , is a single power supply configuration and generates negative bias through a Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and the bootstrap power supply can be used for the high side drive. This design requires the least cost and design effort among the three solutions. However, this solution has limitations: 1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which means the negative bias voltage will change when the duty cycle changes. Therefore, converters with a fixed duty cycle (~50%) such as variable frequency resonant convertors or phase shift convertors favor this solution. 2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range, which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel) diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100% duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in the other two example circuits. Figure 10-4. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

Product Folder Links: UCC21550-Q1

10.2.3 Application Curves

Figure 10-5 shows the bench test waveforms for the design example shown in Figure 10-1 under these conditions: VCC = 5 V, VDD = 20 V, fSW = 100 kHz, VDC-Link = 0 V. Channel 1 (Yellow): UCC21550x-Q1 INA pin signal. Channel 2 (Blue): UCC21550x-Q1 INB pin signal. Channel 3 (Pink): Gate-source signal on the high side power transistor. Channel 4 (Green): Gate-source signal on the low side power transistor. Figure 10-5. Bench Test Waveform for INA/B and OUTA/B www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: UCC21550-Q1

11 Power Supply Recommendations

The recommended input supply voltage (VCCI) for the UCC21550x -Q1 is between 2.7 V and 5.5 V. The output bias supply voltage (VDDA/VDDB) range depends on which version of UCC21550x -Q1 one is using. The lower end of this bias supply range is governed by the internal under voltage lockout (UVLO) protection feature of each device. One mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more information on UVLO see Section 9.3.1). The upper end of the VDDA/VDDB range depends on the maximum gate voltage of the power device being driven by the UCC21550x-Q1 have a recommended maximum VDDA/VDDB of 25 V. A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further suggested that one place two such capacitors: one with a value of ≈10-µF for device biasing, and an additional ≤100-nF capacitor in parallel for high frequency filtering. Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of current drawn by the logic circuitry within the input side of the UCC21550x -Q1, this bypass capacitor has a minimum recommended value of 100 nF. UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

Product Folder Links: UCC21550-Q1

12 Layout

12.1 Layout Guidelines

One must pay close attention to PCB layout in order to achieve optimum performance for the UCC21550x -Q1. Below are some key points. Component Placement:

Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins and between the VDD and VSS pins to support high peak currents when turning on the external power transistor.
To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the source of the top transistor and the source of the bottom transistor must be minimized.
It is recommended to place the dead-time setting resistor, RDT, and its bypassing capacitor close to DT pin of the UCC21550x-Q1.
It is recommended to bypass using a ≈1nF low ESR/ESL capacitor, CDIS, close to DIS pin when connecting to a µC with distance. Grounding Considerations:
It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the transistors. The gate driver must be placed as close as possible to the transistors.
Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB- referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and area on the circuit board is important for ensuring reliable operation. High-Voltage Considerations:
To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination that may compromise the UCC21550x-Q1's isolation performance.
For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could operate with a DC-link voltage up to 1500 VDC, one should try to increase the creepage distance of the PCB layout between the high and low-side PCB traces. Thermal Considerations:
A large amount of power may be dissipated by the UCC21550x-Q1 if the driving voltage is high, the load is heavy, or the switching frequency is high (refer to Section 10.2.2.5 for more details). Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal impedance (θJB).
Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority on maximizing the connection to VSSA and VSSB (see Figure 12-2 and Figure 12-3). However, high voltage PCB considerations mentioned above must be maintained.
If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and VSSB pins to internal ground or power planes through multiple vias of adequate size. However, keep in mind that there shouldn’t be any traces/coppers from different high voltage planes overlapping. www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: UCC21550-Q1

12.2 Layout Example

Figure 12-1 shows a 2-layer PCB layout example with the signals and key components labeled. Figure 12-1. Layout Example Figure 12-2 and Figure 12-3 shows top and bottom layer traces and copper. Note There are no PCB traces or copper between the primary and secondary side, which ensures isolation performance. PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling. Figure 12-2. Top Layer Traces and Copper Figure 12-3. Bottom Layer Traces and Copper Figure 12-4 and Figure 12-5 are 3D layout pictures with top view and bottom views. Note The location of the PCB cutout between the primary side and secondary sides, which ensures isolation performance. UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

Product Folder Links: UCC21550-Q1

13 Device and Documentation Support

13.1 Device Support

13.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation see the following:

Semiconductor and IC Package Thermal Metrics Application Report
Isolation Glossary

13.3 Certifications

UL Online Certifications Directory, "FPPT2.E181974 Nonoptical Isolating Devices - Component" Certificate Number: 20160516-E181974, VDE Pruf- und Zertifizierungsinstitut Certification, Certificate of Conformity with Factory Surveillance CQC Online Certifications Directory, "GB4943.1-2011, Digital Isolator Certificate" Certificate Number:CQC16001155011 CSA Online Certifications Directory, "CSA Certificate of Compliance" Certificate Number:70097761, Master Contract Number:220991

13.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

13.5 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

13.6 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

13.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.8 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. UCC21550-Q1 SLUSEU6 – MAY 2023 www.ti.com ADVANCE INFORMATION

Product Folder Links: UCC21550-Q1

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com UCC21550-Q1 SLUSEU6 – MAY 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: UCC21550-Q1

www.ti.com 9-Jul-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PUCC21550AQDWRQ1 ACTIVE SOIC DW 16 2000 TBD Call TI Call TI -40 to 150 Samples PUCC21550BQDWRQ1 ACTIVE SOIC DW 16 2000 TBD Call TI Call TI -40 to 150 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 9-Jul-2023 Addendum-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. SOIC - 2.65 mm max heightDW 16 SMALL OUTLINE INTEGRATED CIRCUIT7.5 x 10.3, 1.27 mm pitch 4224780/A

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated

Product Information