Logic IC

PUCC21530QDWKQ1

Texas Instruments

UCC21530-Q1 4A, 6A, 5.7kVRMS Isolated Dual-Channel Gate Driver with 3.3mm Channel-to-Channel Spacing SEPTEMBER 2024

Manufacturer: Texas Instruments

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UCC21530-Q1 4A, 6A, 5.7kVRMS Isolated Dual-Channel Gate Driver with 3.3mm Channel-to-Channel Spacing

1 Features

AEC-Q100 qualified with: – Device temperature grade 1
Functional Safety Quality-Managed – Documentation available to aid functional safety system design
Universal: dual low-side, dual high-side or half- bridge driver
Wide body SOIC-14 (DWK) package
3.3mm spacing between driver channels
Switching parameters: – 33ns typical propagation delay – 20ns minimum pulse width – 6ns maximum pulse-width distortion
Common-mode transient immunity (CMTI) greater than 125V/ns
4A peak source, 6A peak sink output
TTL and CMOS compatible inputs
3V to 18V input VCCI range
Up to 25V VDD output drive supply – 8V,12V and 17V VDD UVLO options
Programmable overlap and dead time
Junction temperature range –40 to +150°C

2 Applications

HEV and BEV battery chargers
Solar string and central inverters
AC-to-DC and DC-to-DC charging piles
AC inverter and servo drive
AC-to-DC and DC-to-DC power delivery
Energy storage systems

3 Description

The UCC21530-Q1 is an isolated dual-channel gate driver with 4A source and 6A sink peak current. It is designed to drive IGBTs, Si MOSFETs, and SiC MOSFETs up to 5MHz. The input side is isolated from the two output drivers by a 5.7kV RMS reinforced isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI). Internal functional isolation between the two secondary-side drivers allows a working voltage of up to 1850V. This device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver with programmable dead time (DT). The EN pin pulled low shuts down both outputs simultaneously and allows for normal operation when left open or pulled high. As a fail-safe measure, primary-side logic failures force both outputs low. The device accepts VDD supply voltages up to 25V. A wide input VCCI range from 3V to 18V makes the driver suitable for interfacing with both analog and digital controllers. All the supply voltage pins have under voltage lock-out (UVLO) protection. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) UCC21530-Q1 DWK (SOIC 14) 10.30mm × 7.50mm UCC21530B-Q1 DWK (SOIC 14) 10.30mm × 7.50mm UCC21530D-Q1 DWK (SOIC 14) 10.30mm × 7.50mm (1) For all available packages, see Section 13. Functional Block Diagram UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11.3 Receiving Notification of Documentation Updates.. 37

13 Mechanical, Packaging, and Orderable

SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

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4 Pin Configuration and Functions

Figure 4-1. DWK Package, 14-Pin SOIC (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. DT 6 I DT pin configuration:

Tying DT to VCCI disables the DT feature and allows the outputs to overlap.
Placing a resistor (RDT) between DT and GND adjusts dead time according to the equation: DT (in ns) = 10 × RDT (in kΩ). TI recommends bypassing this pin with a ≤1nF ceramic capacitor close to DT pin to achieve better noise immunity. It is not recommended to leave DT floating. EN 5 I Enable both driver outputs if asserted high, disable the output if set low. It is recommended to tie this pin to VCCI if not used to achieve better noise immunity. Bypass using a ≈ 1-nF low ESR/ESL capacitor close to EN pin when connecting to a micro controller with distance. GND 4 P Primary-side ground reference. All signals in the primary side are referenced to this ground. INA 1 I Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity. INB 2 I Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity. NC 7 – No internal connection. This pin can be left floating, tied to VCCI, or tied to GND. OUTA 15 O Output of driver A. Connect to the gate of the A channel FET or IGBT. OUTB 10 O Output of driver B. Connect to the gate of the B channel FET or IGBT. VCCI 3 P Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close to the device as possible. VCCI 8 P Primary-side supply voltage. This pin is internally shorted to pin 3. VDDA 16 P Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located as close to the device as possible. VDDB 11 P Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL capacitor located as close to the device as possible. VSSA 14 P Ground for secondary-side driver A. Ground reference for secondary side A channel. VSSB 9 P Ground for secondary-side driver B. Ground reference for secondary side B channel. (1) P =Power, I= Input, O= Output www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: UCC21530-Q1

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input bias pin supply voltage VCCI to GND –0.3 20 V Driver bias supply VDDA-VSSA, VDDB-VSSB –0.3 30 V Output signal voltage OUTA to VSSA, OUTB to VSSB –0.3 VDDA/B + 0.3 V OUTA to VSSA, OUTB to VSSB, Transient for 200 ns –2 VDDA/B + 0.3 V Input signal voltage INA, INB, EN, DT to GND –0.3 VCCI + 0.3 V INA, INB Transient for 50ns –5 VCCI + 0.3 V Channel to channel internal isolation voltage |VSSA-VSSB| in DWK package 1850 V Junction temperature, TJ (2) –40 150 ℃ Storage temperature, Tstg –65 150 ℃ (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) To maintain the recommended operating conditions for TJ, see the Section 6.4

5.2 ESD Ratings (Automotive)

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V Charged device model (CDM), per AEC Q100-011 ±1000 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCCI VCCI Input supply voltage 3 18 V VDDA, VDDB Driver output bias supply refer to VSS UCC21530B 8-V UVLO version 9.2 25 V UCC21530 12-V UVLO version 13.5 25 V UCC21530D 17-V UVLO version 19 25 V TJ Junction temperature –40 150 ℃

5.4 Thermal Information

THERMAL METRIC(1) UCC21530-Q1 UNITDWK-14 (SOIC)

14 PINS

RθJA Junction-to-ambient thermal resistance 74.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 34.1 °C/W RθJB Junction-to-board thermal resistance 32.8 °C/W ΨJT Junction-to-top(center) characterization parameter 23.7 °C/W UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

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5.4 Thermal Information (continued)

THERMAL METRIC(1) UCC21530-Q1 UNITDWK-14 (SOIC) ΨJB Junction-to-board characterization parameter 32.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PD Maximum power dissipation (both sides) VCCI = 5V, VDDA/VDDB = 20V, INA/B = 3.3V, 460kHz 50% duty cycle square wave, CL=2.2nF, TJ=150℃, TA=25℃ 950 mW PDI Maximum power dissipation by transmitter side 50 mW PDA, PDB Maximum power dissipation by each driver side 450 mW www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: UCC21530-Q1

5.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFIC ATION UNIT General CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 mm CPG External Creepage(1) Shortest terminal-to-terminal distance across the package surface >8 mm DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V Material Group According to IEC 60664-1 I Overvoltage category IEC 60664-1 Rated mains voltage ≤ 600 VRMS I-IV Rated mains voltage ≤ 1000 VRMS I-III DIN EN IEC 60747-17 (VDE 0884-17) (2) VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test 1500 VRMS DC voltage 2121 VDC VIMP Maximum inpulse voltage Tested in air, 1.2/50-µs waveform per IEC 62368-1 7692 VPK VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification) VTEST = 1.2 × VIOTM, t = 1 s (100% production) 8000 VPK VIOSM Maximum surge isolation voltage(3) VIOSM ≥ 1.3 x VIMP; Tested in oil (qualification test), 1.2/50-μs waveform per IEC 62368-1 10000 VPK qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s pC Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s Method b1: At routine test (100% production) and preconditioning (type test), Vini = 1.2 × VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM , tm = 1 s CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1 MHz ~1.2 pF RIO Insulation resistance, input to output(5) VIO = 500 V, TA = 25°C >1012 ΩVIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 VIO = 500 V at TS = 150°C >109 Pollution degree 2 Climatic category 40/125/21 UL 1577 VISO Withstand isolation voltage VTEST = VISO = 5700 VRMS, t = 60 s (qualification), VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production)

5700 VRMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these specifications. (2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. (3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. (4) Apparent charge is electrical discharge caused by a partial discharge (pd). (5) All pins on each side of the barrier tied together creating a two-pin device. UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

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5.7 Safety Limiting Values

PARAMETER TEST CONDITIONS SIDE MIN TYP MAX UNIT IS Safety output supply current Rθ JA = 74.1°C/W, VDDA/B = 15 V, TJ = 150°C, TA = 25°C DRIVER DRIVER B mA Rθ JA = 74.1°C/W, VDDA/B = 25 V, TJ = 150°C, TA = 25°C 32 PS Safety supply power Rθ JA = 74.1°C/W, TJ = 150°C, TA = 25°C INPUT 50 mW DRIVER A 800 DRIVER B 800 TOTAL 1650 TS Maximum safety temperature(1) 150 °C (1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ , specified for the device. The IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RqJA, in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value for each parameter: TJ = TA + RqJA * P, where P is the power dissipated in the device. TJ(max) = TS = TA + RqJA * PS, where TJ(max) is the maximum allowed junction temperature. PS = IS * VI , where VI is the maximum supply voltage.

5.8 Electrical Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15V (for 8V and 12V UVLO variants) or 20V (for 17V UVLO variant), 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TJ = –40°C to +150°C, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTS IVCCI VCCI quiescent current VINA = 0 V, VINB = 0 V 1.4 2.0 mA IVDDA, IVDDB VDDA and VDDB quiescent current VINA = 0 V, VINB = 0 V 1.0 2.5 mA IVCCI VCCI operating current (f = 500 kHz) current per channel 3 3.5 mA IVDDA, IVDDB VDDA and VDDB operating current (f = 500 kHz) current per channel, COUT = 100 pF 2.5 4.2 mA VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS VVCCI_ON UVLO Rising threshold 2.55 2.7 2.85 V VVCCI_OFF UVLO Falling threshold 2.35 2.5 2.65 V VVCCI_HYS UVLO Threshold hysteresis 0.2 V VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS VVDDA_ON, VVDDB_ON UVLO Rising threshold 8-V UVLO 7.7 8.5 8.9 V VVDDA_OFF, VVDDB_OFF UVLO Falling threshold 8-V UVLO 7.2 7.9 8.4 V VVDDA_HYS, VVDDB_HYS UVLO Threshold hysteresis 8-V UVLO 0.6 V VVDDA_ON, VVDDB_ON UVLO Rising threshold 12-V UVLO 11.7 12.5 13.3 V VVDDA_OFF, VVDDB_OFF UVLO Falling threshold 12-V UVLO 10.7 11.5 12.3 V VVDDA_HYS, VVDDB_HYS UVLO Threshold hysteresis 12-V UVLO 1 V VVDDA_ON, VVDDB_ON UVLO Rising threshold 17-V UVLO 16.4 17.6 18.8 V VVDDA_OFF, VVDDB_OFF UVLO Falling threshold 17-V UVLO 15.4 16.6 17.8 V VVDDA_HYS, VVDDB_HYS UVLO Threshold hysteresis 17-V UVLO 1 V INA, INB AND ENABLE VINAH, VINBH, VENH Input high threshold voltage 1.2 1.8 2 V www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: UCC21530-Q1

5.8 Electrical Characteristics (continued)

5.9 Timing Requirements

DEADTIME AND OVERLAP PROGRAMMING MIN NOM MAX UNIT DT DT pin tied to VCCI Ovelap determined by INA, INB Ovelap determined by INA, INB Ovelap determined by INA, INB ns DT Dead time, RDT = 10 kΩ 80 100 120 ns DT Dead time, RDT = 20 kΩ 160 200 240 ns DT Dead time, RDT = 50 kΩ 400 500 600 ns

5.10 Switching Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15 (for 8V and 12V UVLO variants) or 20V (for 17V UVLO variant), 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, load capacitance COUT = 0 pF, TJ = –40°C to +150°C. (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tRISE Output rise time, 20% to 80% measured points COUT = 1.8 nF 6 16 ns tFALL Output fall time, 90% to 10% measured points COUT = 1.8 nF 7 12 ns tPWmin Minimum pulse width Output off for less than minimum, COUT = 0pF 20 ns tPDHL Propagation delay from INx to OUTx falling edges 26 33 45 ns tPDLH Propagation delay from INx to OUTx rising edges 26 33 45 ns tPWD Pulse width distortion |tPDLH – tPDHL| 6 ns tDM Propagation Delay Matching for Dual Channel Driver Input Pulse Width = 100ns, 500kHz, TJ = -40°C to -10°C |tPDLHA – tPDLHB|, |tPDHLA – tPDHLB| 6.5 ns Input Pulse Width = 100ns, 500kHz, TJ = -10°C to +150°C |tPDLHA – tPDLHB|, |tPDHLA – tPDHLB| 5 ns tVCCI+ to OUT VCCI Power-up Delay Time: UVLO Rise to OUTA, OUTB INA or INB tied to VCCI 50 μs UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

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5.10 Switching Characteristics (continued)

5.11 Insulation Characteristics Curves

Figure 5-1. Reinforced Isolation Capacitor Life Time Projection www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: UCC21530-Q1

A m b i e n t T e m p e r a t u r e ( ° C ) Safety Limiting Current per Channel (mA) 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 0 2 0 3 0 4 0 5 0 6 0 I V D D A / B f o r V D D = 1 5 V I V D D A / B f o r V D D = 2 5 V Figure 5-2. Thermal Derating Curve for Safety- Related Limiting Current (Current in Each Channel with Both Channels Running Simultaneously), A m b i e n t T e m p e r a t u r e ( ° C ) Safety Limiting Power (mW) 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 1 2 0 0 1 4 0 0 1 6 0 0 1 8 0 0 Figure 5-3. Thermal Derating Curve for Safety- Related Limiting Power UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

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5.12 Typical Characteristics

VDDA = VDDB = 15V (8V and 12V UVLO variants) or 20V (17V UVLO variant) , VCCI = 3.3 V, TA = 25°C, No load. (unless otherwise noted) F r e q u e n c y ( k H z ) Current (mA) 5 0 0 1 0 0 0 1 5 0 0 2 0 0 0 2 5 0 0 3 0 0 0 3 5 0 0 4 0 0 0 4 5 0 0 5 0 0 0 2 . 5 7 . 5 1 0 1 2 . 5 1 5 1 7 . 5 V D D = 1 5 V V D D = 2 5 V No load Figure 5-4. Per Channel Current Consumption vs Frequency F r e q u e n c y ( k H z ) Current (mA) 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 V D D = 1 5 V V D D = 2 5 V Figure 5-5. Per Channel Current Consumption (IVDDA/B) vs Frequency (1-nF Load, VDD=15V or 25V) F r e q u e n c y ( k H z ) Current (mA) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 2 1 5 1 8 2 1 2 4 2 7 3 0 V D D = 1 5 V V D D = 2 5 V Figure 5-6. Per Channel Current Consumption (IVDDA/B) vs Frequency (10-nF Load, VDD=15 or 25V) T e m p e r a t u r e ( ° C ) Current (mA) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 0 1 2 1 4 5 0 0 k H z 1 0 0 0 k H z 2 0 0 0 k H z 3 0 0 0 k H z Figure 5-7. Per Channel (IVDDA/B) Supply Current vs Temperature (No Load, Different Switching Frequencies) T e m p e r a t u r e ( ° C ) Current (mA) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 0 . 4 0 . 8 1 . 2 1 . 6 V D D = 1 5 V V D D = 2 5 V Figure 5-8. Per Channel (IVDDA/B) Quiescent Supply Current vs Temperature (No Load, Input Low, No Switching) T e m p e r a t u r e ( ° C ) Current (mA) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 . 2 1 . 3 1 . 4 1 . 5 1 . 6 V C C = 3 . 3 V V C C = 5 V Figure 5-9. IVCCI Quiescent Supply Current vs Temperature (No Load, Input Low, No Switching) www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: UCC21530-Q1

5.12 Typical Characteristics (continued)

VDDA = VDDB = 15V (8V and 12V UVLO variants) or 20V (17V UVLO variant) , VCCI = 3.3 V, TA = 25°C, No load. (unless otherwise noted) L o a d ( n F ) Time (ns) 1 2 3 4 5 6 7 8 9 1 0 7 . 5 1 0 1 2 . 5 1 5 1 7 . 5 2 0 2 2 . 5 2 5 2 7 . 5 3 0 t R i s e t F a l l Figure 5-10. Rising and Falling Times vs Load T e m p e r a t u r e ( ° C ) Resistance (Ohm) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 0 . 5 1 . 5 2 . 5 3 . 5 4 . 5 5 . 5 O u t p u t P u l l - U p O u t p u t P u l l - D o w n Figure 5-11. Output Resistance vs Temperature T e m p e r a t u r e ( ° C ) Propagation Delay (ns) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 2 0 2 4 2 8 3 2 3 6 4 0 R i s i n g E d g e ( t P D L H ) F a l l i n g E d g e ( t P D H L ) Figure 5-12. Propagation Delay vs Temperature V C C I ( V ) Propagation Delay (ns) 2 8 3 0 3 2 3 4 3 6 R i s i n g E d g e ( t P D L H ) F a l l i n g E d g e ( t P D H L ) Figure 5-13. Propagation Delay vs VCCI T e m p e r a t u r e ( ° C ) Pulse Width Distortion (ns) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 - 3 - 2 - 1 Figure 5-14. Pulse Width Distortion vs Temperature V D D ( V ) Propagation Delay Matching (ns) 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 R i s i n g E d g e F a l l i n g E d g e Figure 5-15. Propagation Delay Matching (tDM) vs VDD UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

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VDDA = VDDB = 15V (8V and 12V UVLO variants) or 20V (17V UVLO variant) , VCCI = 3.3 V, TA = 25°C, No load. (unless otherwise noted) T e m p e r a t u r e ( ° C ) Propagation Delay Matching (ns) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 R i s i n g E d g e F a l l i n g E d g e Figure 5-16. Propagation Delay Matching (tDM) vs Temperature T e m p e r a t u r e ( ° C ) UVLO Hysteresis (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 Figure 5-17. 8-V UVLO Hysteresis vs Temperature T e m p e r a t u r e ( ° C ) UVLO Threshold (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 0 V V D D _ O N V V D D _ O F F Figure 5-18. 8-V UVLO Threshold vs Temperature T e m p e r a t u r e ( ° C ) UVLO Hysteresis (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 0 . 5 1 . 5 2 Figure 5-19. 12-V UVLO Hysteresis vs Temperature T e m p e r a t u r e ( ° C ) UVLO Threshold (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 0 1 1 1 2 1 3 1 4 1 5 V V D D _ O N V V D D _ O F F Figure 5-20. 12-V UVLO Threshold vs Temperature T e m p e r a t u r e ( o C ) UVLO Threshold (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 5 1 5 . 5 1 6 1 6 . 5 1 7 1 7 . 5 1 8 1 8 . 5 1 9 V V D D _ O N V V D D _ O F F Figure 5-21. VDD 17-V UVLO Threshold vs Temperature www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: UCC21530-Q1

VDDA = VDDB = 15V (8V and 12V UVLO variants) or 20V (17V UVLO variant) , VCCI = 3.3 V, TA = 25°C, No load. (unless otherwise noted) T e m p e r a t u r e ( ° C ) UVLO Hysteresis (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 0 . 5 1 . 5 Figure 5-22. VDD 17-V UVLO Hysteresis vs Temperature T e m p e r a t u r e ( ° C ) Hysteresis (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 0 . 8 5 0 . 8 6 0 . 8 7 0 . 8 8 0 . 8 9 0 . 9 V C C = 3 . 3 V V C C = 5 V Figure 5-23. INA/B/EN Hysteresis vs Temperature Temperature (qC) IN/DIS Low Threshold (V) -40 -20 0 20 40 60 80 100 120 140 0.9 0.96 1.02 1.08 1.14 1.2 D001 VCC=3.3V VCC= 5V VCC=12V Figure 5-24. INA/B/EN Low Threshold Temperature (qC) IN/DIS High Threshold (V) -40 -20 0 20 40 60 80 100 120 140 1.6 1.68 1.76 1.84 1.92 D001 VCC=3.3V VCC= 5V VCC=12V Figure 5-25. INA/B/EN High Threshold Temperature (qC) Dead Time (ns) -40 -20 0 20 40 60 80 100 120 140 300 600 900 1200 1500 D001 RDT= 20k: RDT= 100k: Figure 5-26. Dead Time vs Temperature Temperature (qC) 'DT (ns) -40 -20 0 20 40 60 80 100 120 140 -50 -39 -28 -17 D001 RDT= 20k: RDT = 100k: Figure 5-27. Dead Time Matching vs Temperature UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

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6 Parameter Measurement Information

6.1 Propagation Delay and Pulse Width Distortion

Figure 6-1 shows how one calculates pulse width distortion (t PWD) and delay matching (t DM) from the propagation delays of channels A and B. It can be measured by ensuring that both inputs are in phase and disabling the dead time function by shorting the DT Pin to VCC. INA/B tPDLHA OUTA OUTB tPDLHB tDM tPDHLB tPDHLA tPWDB = |tPDLHB t tPDHLB| Figure 6-1. Overlapping Inputs, Dead Time Disabled

6.2 Rising and Falling Time

Figure 6-2 shows the criteria for measuring rising (t RISE) and falling (t FALL) times. For more information on how short rising and falling times are achieved see Section 7.3.4. 20% tRISE 80% 90% 10% tFALL Figure 6-2. Rising and Falling Time Criteria

6.3 Input and Enable Response Time

Figure 6-3 shows the response time of the enable function. For more information, see Section 7.4.1. INx EN OUTx tPDHL 10% 10% EN High Response Time tPDLH EN Low Response Time 90% 90% 10% Figure 6-3. Enable Pin Timing www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: UCC21530-Q1

6.4 Programable Dead Time

Tying DT to VCCI disables DT feature and allows the outputs to overlap. Placing a resistor (RDT) between DT pin and GND can adjust the dead time. For more details on dead time, refer to Section 7.4.2. OUTB INA INB 10% 90% Dead Time (Set by RDT) tPDHL Dead Time (Determined by Input signals if longer than DT set by RDT) 90% 10% tPDLH tPDHL OUTA Figure 6-4. Dead-Time Switching Parameters

6.5 Power-Up UVLO Delay to OUTPUT

Whenever the supply voltage VCCI crosses from below the falling threshold V VCCI_OFF to above the rising threshold VVCCI_ON, and whenever the supply voltage VDDx crosses from below the falling threshold V VDDx_OFF to above the rising threshold V VDDx_ON, there is a delay before the outputs begin responding to the inputs. For VCCI UVLO this delay is defined as t VCCI+ to OUT , and has a maximum of 50 µs. For VDDx UVLO this delay is defined as tVDD+ to OUT, and has a maximum of 10 µs. TI recommends allowing some margin before driving input signals, to ensure the driver VCCI and VDD bias supplies are fully activated. Figure 6-5 and Figure 6-6 show the power-up UVLO delay timing diagram for VCCI and VDD. Whenever the supply voltage VCCI crosses below the falling threshold V VCCI_OFF, or VDDx crosses below the falling threshold V VDDx_OFF, the outputs stop responding to the inputs and are held low within <2 µs. This asymmetric delay is designed to ensure safe operation during VCCI or VDDx brownouts. VCCI, INx VDDx VVCCI_ON OUTx VVCCI_OFF tVCCI+ to OUT Figure 6-5. VCCI Power-Up UVLO Delay VCCI, INx VDDx VVDD_ON OUTx tVDD+ to OUT VVDD_OFF Figure 6-6. VDDA/B Power-Up UVLO Delay UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

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6.6 CMTI Testing

Figure 6-7 is a simplified diagram of the CMTI testing configuration. Figure 6-7. Simplified CMTI Testing Setup www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: UCC21530-Q1

7 Detailed Description

7.1 Overview

In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are often placed between the output of control devices and the gates of power transistors. There are several instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors. This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V logic signal capable of only delivering a few mA. The UCC21530-Q1 is a flexible dual gate driver which can be configured to fit a variety of power supply and motor drive topologies, as well as drive several types of transistors, including SiC MOSFETs. UCC21530-Q1 has many features that allow it to integrate well with control circuitry and protect the transistors it drives such as: resistor-programmable dead time (DT) control, an EN pin, and under voltage lock out (UVLO) for both input and output voltages. The UCC21530-Q1 also holds its outputs low when the inputs are left open or when the input pulse is not wide enough. The driver inputs are CMOS and TTL compatible for interfacing to digital and analog power controllers alike. Each channel is controlled by its respective input pins (INA and INB), allowing full and independent control of each of the outputs.

7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)

The UCC21530-Q1 has an internal under voltage lock out (UVLO) protection feature on the supply circuit blocks between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than V VDD_ON at device start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the effected output low, regardless of the status of the input pins (INA and INB). When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in Figure 7-1). In this condition, the upper PMOS is resistively held off by R Hi-Z while the lower NMOS gate is tied to the driver output through RCLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device, typically less than 1.5V, when no bias power is available. RHI_Z VDD RCLAMP OUT VSS RCLAMP is activated during UVLO Output Control Figure 7-1. Simplified Representation of Active Pull Down Feature The VDD UVLO protection has a hysteresis feature (V VDD_HYS). This hysteresis prevents chatter when there is ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is bound to happen when the device starts switching and operating current consumption increases suddenly. The input side of the UCC21530-Q1 also has an internal under voltage lock out (UVLO) protection feature. The device isn't active unless the voltage, VCCI, is going to exceed V VCCI_ON on start up. The signal will cease to be delivered once the pin receives a voltage less than V VCCI_OFF. In the same way as the VDD UVLO, there is hysteresis (VVCCI_HYS) to ensure stable operation. UCC21530-Q1 can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI. Table 7-1. UCC21530-Q1 VCCI UVLO Feature Logic CONDITION INPUTS OUTPUTS INA INB OUTA OUTB VCCI-GND < VVCCI_ON during device start up H L L L VCCI-GND < VVCCI_ON during device start up L H L L VCCI-GND < VVCCI_ON during device start up H H L L VCCI-GND < VVCCI_ON during device start up L L L L VCCI-GND < VVCCI_OFF after device start up H L L L VCCI-GND < VVCCI_OFF after device start up L H L L VCCI-GND < VVCCI_OFF after device start up H H L L VCCI-GND < VVCCI_OFF after device start up L L L L Table 7-2. UCC21530-Q1 VDD UVLO Feature Logic CONDITION INPUT: INx OUTPUT: OUTx VDDx-VSSx < VVDD_ON during device start up L L VDDx-VSSx < VVDD_ON during device start up H L www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: UCC21530-Q1

Table 7-2. UCC21530-Q1 VDD UVLO Feature Logic (continued) CONDITION INPUT: INx OUTPUT: OUTx VDDx-VSSx < VVDD_OFF after device start up L L VDDx-VSSx < VVDD_OFF after device start up H L

7.3.2 Input and Output Logic Table

Table 7-3. INPUT/OUTPUT Logic Table Assume VCCI, VDDA, VDDB are powered up. See Section 7.3.1 for more information on UVLO operation modes. (1) INPUTS EN OUTPUTS NOTE INA INB OUTA OUTB L L H or Left Open L L If Dead Time function is used, output transitions occur after the dead time expires. See Section 7.4.2 L H H or Left Open L H H L H or Left Open H L H H H or Left Open L L DT is left open or programmed with RDT H H H or Left Open H H DT pin pulled to VCCI Left Open Left Open H or Left Open L L - X X L L L Bypass using a ≥ 1-nF low ESR/ESL capacitor close to EN pin when connecting to a µC with distance (1) "X" means L, H or left open.

7.3.3 Input Stage

The input signal pins (INA and INB) of UCC21530-Q1 are based on a TTL and CMOS compatible input- threshold logic that is totally isolated from the VDD supply voltage. The input pins are easy to drive with logic-level control signals (Such as those from 3.3-V micro-controllers), since UCC21530-Q1 has a typical high threshold (VINA/BH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature (see Figure 5-24, Figure 5-25). A wide hysterisis (V INA/B_HYS) of 0.8 V makes for good noise immunity and stable operation. If any of the inputs are ever left open, internal pull-down resistors force the pin low. These resistors are typically 200 kΩ (See Section 7.2). However, it is still recommended to ground an input if it is not being used. Since the input side of UCC21530-Q1 is isolated from the output drivers, the input signal amplitude can be larger or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater flexibility when integrating with control signal sources, and allows the user to choose the most efficient VDD for their chosen gate. That said, the amplitude of any signal applied to INA or INB must never be at a voltage higher than VCCI. UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

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7.3.4 Output Stage

The UCC21530-Q1’s output stages features a pull-up structure which delivers the highest peak-source current when it is most needed, during the Miller plateau region of the power-switch turn on transition (when the power switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel MOSFET and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to provide a brief boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing states from low to high. The on-resistance of this N-channel MOSFET (RNMOS) is approximately 1.47 Ω when activated. The ROH parameter is a DC measurement and it is representative of the on-resistance of the P-channel device only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on only for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the UCC21530-Q1 pull-up stage during this brief turn-on phase is much lower than what is represented by the R OH parameter. The pull-down structure in UCC21530-Q1 is simply composed of an N-channel MOSFET. The R OL parameter, which is also a DC measurement, is representative of the impedance of the pull-down state in the device. Both outputs of the UCC21530-Q1 are capable of delivering 4-A peak source and 6-A peak sink current pulses. The output voltage swings between VDD and VSS provides rail-to-rail operation, thanks to the MOS-out stage which delivers very low drop-out. To ensure robust and reliable operation of gate drivers, pay special attention to the minimum pulse width. The minimum pulse width shown in the electrical characteristics table describes the minimum input pulse that would be passed to the output in an unloaded driver. This is dictated by the deglitch filter present in the driver IC. An input ON or OFF pulse width longer than the maximum specification is needed to guarantee an output state change and avoid potential shoot-through. With a loaded driver, extra precaution must be taken to ensure robust operation of the system. During gate switching, if the output state changes before the driver completes each transition, a non-zero current switching event occurs. Combined with layout parasitics, non-zero current switching can cause internal rail overshoot and EOS damage of the gate driver. Thus, a minimum output width is needed for reliable system operation. This minimum output pulse width is dependent on several factors: gate capacitance, VDD supply voltage, gate resistance, and PCB layout parasitics. The minimum pulse width for robust operation might be magnitudes larger than the minimum pulse width shown in the electrical characteristics table. System-level study should be carried out to determine the minimum output pulse width required for each system. VDD OUT VSS Pull Up Shoot- Through Prevention Circuitry Input Signal ROH ROL RNMOS Figure 7-2. Output Stage www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: UCC21530-Q1

7.3.5 Diode Structure in UCC21530-Q1

Figure 7-3 illustrates the multiple diodes involved in the ESD protection components of the UCC21530-Q1. This provides a pictorial representation of the absolute maximum rating for the device. Figure 7-3. ESD Structure

7.4 Device Functional Modes

7.4.1 Enable Pin

Setting the EN pin low, that is V EN ≤ 0.8V, shuts down both outputs simultaneously. Pull the EN pin high (or left open), that is V EN ≥ 2.0V, allows UCC21530-Q1 to operate normally. The EN pin is quite responsive, as far as propagation delay and other switching parameters are concerned, the delay between EN are OUTA and OUTB is about 40ns. The EN pin is only functional (and necessary) when VCCI stays above the UVLO threshold. It is highly recommended to tie EN to VCCI directly to achieve better noise immunity.

7.4.2 Programmable Dead Time (DT) Pin

UCC21530-Q1 allows the user to adjust dead time (DT) in the following ways:

7.4.2.1 DT Pin Tied to VCC

Outputs completely match inputs, so no minimum dead time is asserted. This allows outputs to overlap. It is recommended to connect this pin to VCCI directly if it is not used to achieve better noise immunity.

7.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins

Program tDT by placing a resistor, R DT, between the DT pin and GND. TI recommends bypassing this pin with a ceramic capacitor ≤1nF close to DT pin to achieve better noise immunity. The appropriate R DT value can be determined from: DT DTt 10 R| u (1) where

tDT is the programmed dead time, in nanoseconds.
RDT is the value of resistance between DT pin and GND, in kilo-ohms. The steady state voltage at the DT pin is about 0.8 V. R DT programs a small current at this pin, which sets the dead time. As the value of R DT increases, the current sourced by the DT pin decreases. The DT pin current will be less than 10 µA when R DT = 100 k Ω. For larger values of R DT, TI recommends placing R DT and a ceramic UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

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capacitor ≤1nF as close to the DT pin as possible to achieve greater noise immunity and better dead time matching between both channels. The falling edge of an input signal initiates the programmed dead time for the other signal. The programmed dead time is the minimum enforced duration in which both outputs are held low by the driver. The outputs may also be held low for a duration greater than the programmed dead time, if the INA and INB signals include a dead time duration greater than the programmed minimum. If both inputs are high simultaneously, both outputs will immediately be set low. This feature is used to prevent shoot-through in half-bridge applications, and it does not affect the programmed dead time setting for normal operation. Various driver dead time logic operating conditions are illustrated and explained in Figure 7-4. INA INB OUTA OUTB A B C D E F DT Figure 7-4. Input and Output Logic Relationship With Input Signals Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead time to OUTA. OUTA is allowed to go high after the programmed dead time. Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed dead time to OUTB. OUTB is allowed to go high after the programmed dead time. Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead time for OUTA. In this case, the input signal’s own dead time is longer than the programmed dead time. Thus, when INA goes high, it immediately sets OUTA high. Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead time to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, it immediately sets OUTB high. Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high. Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high. www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: UCC21530-Q1

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The UCC21530-Q1 effectively combines both isolation and buffer-drive functions. The flexible, universal capability of the UCC21530-Q1 (with up to 18-V VCCI and 25-V VDDA/VDDB) allows the device to be used as a low-side, high-side, high-side and low-side or half-bridge driver for MOSFETs, IGBTs or SiC MOSFETs. With integrated components, advanced protection features (UVLO, dead time, and enable) and optimized switching performance; the UCC21530-Q1 enables designers to build smaller, more robust designs for enterprise, telecom, automotive, and industrial applications with a faster time to market.

8.2 Typical Application

The circuit in Figure 8-1 shows a reference design with UCC21530-Q1 driving a typical half-bridge configuration which could be used in several popular power converter topologies such as synchronous buck, synchronous boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications. This circuit uses two supplies (or single-input-double-output power supply). Power supply V A+ determines the positive drive output voltage and V A– determines the negative turn-off voltage. The configuration for channel B is the same as channel A. When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below the threshold. This solution has two separate power supplies for each driver channel, so it provides flexibility when setting the positive and negative rail voltages. Figure 8-1. Typical Application Schematic with Dual Power Supplies UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

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8.2.1 Design Requirements

Table 8-1 lists reference design parameters for the example application: UCC21530-Q1 driving 1000-V SiC- MOSFETs in a high side-low side configuration. Table 8-1. UCC21530-Q1 Design Requirements PARAMETER VALUE UNITS Power transistor C3M0065100K – VCC 5.0 V VDD 15 V VSS –4 V RON 2.2 Ω ROFF 0 Ω Input signal amplitude 3.3 V Switching frequency (fs) 100 kHz DC link voltage 600 V

8.2.2 Detailed Design Procedure

8.2.2.1 Designing INA/INB Input Filter

It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay) the signal at the output. However, a small input R IN-CIN filter can be used to filter out the ringing introduced by non-ideal layout or long PCB traces. Such a filter should use an R IN in the range of 0 Ω to 100 Ω and a C IN between 10 pF and 100 pF. In the example, an RIN = 51 Ω and a CIN = 33 pF are selected, with a corner frequency of approximately 100 MHz. When selecting these components, it is important to pay attention to the trade-off between good noise immunity and propagation delay.

8.2.2.2 Select Dead Time Resistor and Capacitor

From Equation 1, a 10-k Ω resistor is selected to set the dead time to 100 ns. A ≤1-nF capacitor is placed in parallel close to the DT pin to improve noise immunity.

8.2.2.3 Gate Driver Output Resistor

The external gate driver resistors, RON/ROFF, are used to: 1. Limit ringing caused by parasitic inductances/capacitances. 2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery. 3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss. 4. Reduce electromagnetic interference (EMI). As mentioned in Section 7.3.4, the UCC21530-Q1 has a pull-up structure with a P-channel MOSFET and an additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak source current can be predicted with: (2) where

RON: External turn-on resistance,RON=2.2 Ω in this example;.
RGFET_INT: Power transistor internal gate resistance, found in the power transistor datasheet.
IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and the calculated value based on the gate drive loop resistance. www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: UCC21530-Q1

In this example: (3) Therefore, the driver peak source current is 2.4 A for each channel. Similarly, the peak sink current can be calculated with: (4) where

ROFF: External turn-off resistance, ROFF=0 in this example;
VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example is an MSS1P4.
IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated value based on the gate drive loop resistance. In this example, (5) Therefore, the driver peak sink current is 3.5 A for each channel. Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (C ISS) of the power transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the parasitic ringing period.

8.2.2.4 Estimate Gate Driver Power Loss

The total loss, P G, in the gate driver subsystem includes the power losses of the UCC21530-Q1 (PGD) and the power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not included in PG and not discussed in this section. PGD is the key power loss which determines the thermal safety-related limits of the UCC21530-Q1, and it can be estimated by calculating losses from several components. The first component is the static power loss, P GDQ, which includes quiescent power loss on the driver as well as driver self-power consumption when operating with a certain switching frequency. P GDQ is measured on the bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and ambient temperature. Figure 5-4 shows the per output channel current consumption vs. operating frequency with no load. In this example, V VCCI = 5 V and V VDD-VVSS = 19 V. The current on each power supply, with INA/INB switching from 0 V to 3.3 V at 100 kHz is measured to be I VCCI ≈ 2.5 mA, and IVDDA = IVDDB ≈ 1.5 mA. Therefore, the PGDQ can be calculated with (6) UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

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The second component is switching operation loss, P GDO, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Total dynamic loss due to load switching, P GSW, can be estimated with (7) where

QG is the gate charge of the power transistor. If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail to the negative rail. So, for this example application: (8) QG represents the total gate charge of the power transistor switching 600 V at 20 A, and is subject to change with different testing conditions. The UCC21530-Q1 gate driver loss on the output stage, P GDO, is part of P GSW. PGDO will be equal to P GSW if the external gate driver resistances are zero, and all the gate driver loss is dissipated inside the UCC21530-Q1. If there are external turn-on and turn-off resistances, the total loss will be distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A, however, it will be non-linear if the source/sink current is saturated. Therefore, P GDO is different in these two scenarios. Case 1 - Linear Pull-Up/Down Resistor: (9) In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21530-Q1 gate driver loss can be estimated with: (10) Case 2 - Nonlinear Pull-Up/Down Resistor: (11) where
VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted. For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the PGDO will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: UCC21530-Q1

and pull-down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC21530-Q1, PGD, is: (12) which is equal to 103 mW in the design example.

8.2.2.5 Estimating Junction Temperature

The junction temperature of the UCC21530-Q1 can be estimated with: J C JT GDT T P < u (13) where

TJ is the junction temperature.
TC is the UCC21530-Q1 case-top temperature measured with a thermocouple or some other instrument.
ψJT is the junction-to-top characterization parameter from the Thermal Information table. Using the junction-to-top characterization parameter ( ΨJT) instead of the junction-to-case thermal resistance (RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the total energy is released through the top of the case (where thermocouple measurements are usually conducted). RΘJC can only be used effectively when most of the thermal energy is released through the case, such as with metal packages or when a heatsink is applied to an IC package. In all other cases, use of R ΘJC will inaccurately estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy leaving through the top of the IC will be similar in both the testing environment and the application environment. As long as the recommended layout guidelines are observed, junction temperature estimates can be made accurately to within a few degrees Celsius. For more information, see the Section 10.1 and Semiconductor and

8.2.2.6 Selecting VCCI, VDDA/B Capacitor

Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC) with sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an MLCC will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500 nF when a DC bias of 15 VDC is applied.

8.2.2.6.1 Selecting a VCCI Capacitor

A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended for this application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC. UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

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8.2.2.7 Other Application Example Circuits

When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below the threshold. Below are a few examples of implementing negative gate drive bias. Instead of using two separate power for generating positive and negative drive voltage Figure 8-2 shows the example with negative bias turn-off on the channel-A driver using a Zener diode on the isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power supply, V A, is equal to 19 V, the turn-off voltage will be –3.9 V and turn-on voltage will be 19 V -– 3.9 V ≈ 15 V. The channel-B driver circuit is the same as channel-A, therefore, this configuration needs only one power supply for each driver channel, and there will be steady state power consumption from RZ. Figure 8-2. Negative Bias with Zener Diode on Iso-Bias Power Supply Output www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: UCC21530-Q1

Figure 8-3 shows another example which uses bootstrap to provide power for the channel A, this solution doesn't have negative rail voltage, it is only suitable for circuits with less ringing or the power device has high threshold voltage. Figure 8-3. Bootstrap Power Supply for the High Side Device UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

30 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: UCC21530-Q1

The last example, shown in Figure 8-4 , is a single power supply configuration and generates negative bias through a Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and the bootstrap power supply can be used for the high side drive. This design requires the least cost and design effort among the three solutions. However, this solution has limitations: 1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which means the negative bias voltage will change when the duty cycle changes. Therefore, converters with a fixed duty cycle (~50%) such as variable frequency resonant convertors or phase shift convertors which favor this solution. 2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range, which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel) diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100% duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in the other two example circuits. Figure 8-4. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: UCC21530-Q1

8.2.3 Application Curves

Figure 8-5 shows a multiple pulses bench test circuit which uses L1 as the inductor load, and a group of control pulses are generated to evaluate driver and SiC MOSFET switching transient under different load conditions. The test conditions are: V DC-Link = 600 V, VCC = 5 V, VDD = 15 V, VSS = –4 V, f SW = 500 kHz, R ON = 5.1 Ω , ROFF = 1.0 Ω. Figure 8-6 shows the turn on and turn off waveforms at around 20 A current Channel 1 (Yellow): Gate-source voltage signal on the low side MOSFET. Channel 2 (Blue): Gate-source voltage signal on the high side MOSFET. Channel 3 (Pink): Drain-source voltage signal for the low side MOSFET. Channel 4 (Green): Drain-source current signal for the low side MOSFET. In Figure 8-6, the gate drive signals on the high and low power transistor have a 100-ns dead time, and both signals are measured with >= 500 MHz bandwidth probes. Figure 8-5. Bench Test Circuit with SiC MOSFET Switching Figure 8-6. SiC MOSFET Switching Waveforms UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

Product Folder Links: UCC21530-Q1

9 Power Supply Recommendations

The recommended input supply voltage (VCCI) for UCC21530-Q1 is between 3 V and 18 V. The output bias supply voltage (VDDA/VDDB) range depends on which version of UCC21530-Q1 one is using. The lower end of this bias supply range is governed by the internal under voltage lockout (UVLO) protection feature of each device. One mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more information on UVLO see Section 7.3.1). The upper end of the VDDA/VDDB range depends on the maximum gate voltage of the power device being driven by UCC21530-Q1. All versions of UCC21530-Q1 have a recommended maximum VDDA/VDDB of 25 V. Place a local bypass capacitor between the VDD and VSS pins. Position this capacitor as close to the device as possible. Use a low ESR, ceramic surface mount capacitor. Place two such capacitors: one with a value of between 220 nF and 10 µF for device biasing, and an additional 100-nF capacitor in parallel for high frequency filtering. Similarly, place a bypass capacitor between the VCCI and GND pins. Given the small amount of current drawn by the logic circuitry within the input side of UCC21530-Q1, this bypass capacitor has a minimum recommended value of 100 nF. www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: UCC21530-Q1

10 Layout

10.1 Layout Guidelines

Consider these PCB layout guidelines for in order to achieve optimum performance for the UCC21530-Q1.

10.1.1 Component Placement Considerations

Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins and between the VDD and VSS pins to support high peak currents when turning on the external power transistor.
To avoid large negative transients on the switch node VSSA (HS) pin in bridge configurations, the parasitic inductances between the source of the top transistor and the source of the bottom transistor must be minimized.
To improve noise immunity when driving the EN pin from a distant micro-controller, TI recommends adding a small bypass capacitor, ≥ 1 nF, between the EN pin and GND.
If the dead time feature is used, TI recommends placing the programming resistor RDT and bypassing capacitor close to the DT pin of the UCC21530-Q1 to prevent noise from unintentionally coupling to the internal dead time circuit. The capacitor should be ≤1 nF.

10.1.2 Grounding Considerations

It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the transistors. The gate driver must be placed as close as possible to the transistors.
Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB- referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and area on the circuit board is important for ensuring reliable operation.

10.1.3 High-Voltage Considerations

To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination that may compromise the isolation performance.
For half-bridge or high-side/low-side configurations, maximize the clearance distance of the PCB layout between the high and low-side PCB traces.

10.1.4 Thermal Considerations

A large amount of power may be dissipated by the UCC21530-Q1 if the driving voltage is high, the load is heavy, or the switching frequency is high (refer to Section 8.2.2.4 for more details). Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal impedance (θJB).
Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority on maximizing the connection to VSSA and VSSB (see Figure 10-2 and Figure 10-3). However, high voltage PCB considerations mentioned above must be maintained.
If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and VSSB pins to internal ground or power planes through multiple vias of adequate size. Ensure that no traces or copper from different high-voltage planes overlap. UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

Product Folder Links: UCC21530-Q1

10.2 Layout Example

Figure 10-1 shows a 2-layer PCB layout example with the signals and key components labeled. Figure 10-1. Layout Example Figure 10-2 and Figure 10-3 shows top and bottom layer traces and copper. Note There are no PCB traces or copper between the primary and secondary side, which ensures isolation performance. PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling. Figure 10-2. Top Layer Traces and Copper Figure 10-3. Bottom Layer Traces and Copper www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: UCC21530-Q1

Figure 10-4 and Figure 10-5 are 3D layout pictures with top view and bottom views. Note The location of the PCB cutout between the primary side and secondary sides, which ensures isolation performance. Figure 10-4. 3-D PCB Top View Figure 10-5. 3-D PCB Bottom View UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

Product Folder Links: UCC21530-Q1

11 Device and Documentation Support

11.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

Isolation Glossary

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (August 2024) to Revision F (September 2024) Page Changes from Revision D (April 2021) to Revision E (August 2024) Page www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: UCC21530-Q1

Changing all absolute maximum value from supply+0.5V to supply+0.3V to keep consistent with newly
Updated ESD spec from HBM = ±4000 and CDM = ±1500 to HBM = ±2000 and CDM = ±1000 to match ESD
Updated values from RθJA = 68.3°C/W, RθJC(top) = 31.7°C/W, RθJB = 27.6°C/W, ψJT = 17.7°C/W, ψJB =
Updated values from PD = 1810mW, PDI = 0.05W, PDA/PDB = 880mW to PD = 950mW, PDI = 50mW,
Updated values from DTI = >21mm, VIOSM = 8000VPK to DTI = >17mm, VIOSM = 10000VPK and added
Updated values from IS = 58mA/35mA, PS = 50mW/880mW/880mW/1810mW to IS = 53mA/32mA, PS =
Updated values from Rising threshold Min = 8V, Typ = 8.5V, Max = 9V to Min = 7.7V, Typ = 8.5V, Max =
Updated values from Falling threshold Min = 7.5V, Typ = 8V, Max = 8.5V to Min = 7.2V, Typ = 7.9V, Max =
Changed propagation delay TPDHL and TPDLH from Min = 14ns, Typ = 19ns, Max = 30ns to Min = 26ns,
Changed propagation delay matching from Max = 5ns to Max = 6.5ns from TJ = -40C to -10C and Max = 5ns UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 www.ti.com

Product Folder Links: UCC21530-Q1

Changes from Revision C (March 2019) to Revision D (April 2021) Page Changes from Revision B (November 2018) to Revision C (March 2019) Page

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com UCC21530-Q1 SLUSDG3F – AUGUST 2018 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: UCC21530-Q1

www.ti.com 11-Oct-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PUCC21530QDWKQ1 OBSOLETE SOIC DWK 14 TBD Call TI Call TI UCC21530BQDWKQ1 LIFEBUY SOIC DWK 14 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 U21530BQ UCC21530BQDWKRQ1 ACTIVE SOIC DWK 14 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 U21530BQ Samples UCC21530DQDWKRQ1 ACTIVE SOIC DWK 14 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 UCC21530DQ Samples UCC21530QDWKQ1 LIFEBUY SOIC DWK 14 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 UCC21530Q UCC21530QDWKRQ1 ACTIVE SOIC DWK 14 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 UCC21530Q Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

www.ti.com 11-Oct-2024 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC21530-Q1 :

Catalog : UCC21530 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC21530BQDWKRQ1 SOIC DWK 14 2000 350.0 350.0 43.0 UCC21530DQDWKRQ1 SOIC DWK 14 2000 353.0 353.0 32.0 UCC21530QDWKRQ1 SOIC DWK 14 2000 350.0 350.0 43.0 UCC21530QDWKRQ1 SOIC DWK 14 2000 356.0 356.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2024 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) UCC21530BQDWKQ1 DWK SOIC 14 40 506.98 12.7 4826 6.6 UCC21530QDWKQ1 DWK SOIC 14 40 506.98 12.7 4826 6.6 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 10.63

9.97 TYP

2.65 MAX

11X 1.27 14X 0.51 0.31 8.89 0.33

0.10 TYP

0.3 0.1 (1.4) 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 10.5 10.1 B NOTE 4 7.6 7.4 SOIC - 2.65 mm max heightDWK0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. 1 16

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.500 4224374/A 06/2018

www.ti.com EXAMPLE BOARD LAYOUT (9.75) R0.05 TYP

0.07 MAX

0.07 MIN

(9.3) 11X (1.27) R0.05 TYP 14X (1.65) 14X (0.6) 11X (1.27) 14X (2) 14X (0.6) SOIC - 2.65 mm max heightDWK0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM SEE DETAILS 8 9 SYMM HV / ISOLATION OPTION 8.1 mm CLEARANCE/CREEPAGE NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL SOLDER MASK DEFINED LAND PATTERN EXAMPLE SCALE:4X SYMM 8 9 IPC-7351 NOMINAL 7.3 mm CLEARANCE/CREEPAGE SEE DETAILS 4224374/A 06/2018

www.ti.com EXAMPLE STENCIL DESIGN R0.05 TYPR0.05 TYP 14X (1.65) 14X (0.6) 11X (1.27) (9.75) 14X (2) 14X (0.6) 11X (1.27) (9.3) SOIC - 2.65 mm max heightDWK0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 8 9 HV / ISOLATION OPTION 8.1 mm CLEARANCE/CREEPAGE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:4X SYMM SYMM 8 9 IPC-7351 NOMINAL 7.3 mm CLEARANCE/CREEPAGE 4224374/A 06/2018

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