PUCC14241QDWNRQ1

UCC14241-Q1 TI | Alldatasheet

Document overview

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Technical content

UCC14241-Q1 Automotive 2-W, 24-V VIN, 25-V VOUT, High-Density, > 5 kVRMS, Isolated DC/DC Module

1 Features

• Fully integrated high-density isolated DC/DC module with isolation transformer
• Isolated DC/DC for driving: IGBTs, SiC FETs
• Input voltage range: 21 V to 27 V with 32-V absolute maximum
• 2.0-W output power at TA ≤ 85°C and > 1.5 W at TA = 105 °C
• Adjustable (VDD – VEE) output voltage (with external resistors): 15 V to 25 V, ±1.3 % regulation accuracy over full temperature range
• Adjustable (COM – VEE) output voltage (with external resistors): from 2.5 V to (VDD – VEE), ±1.3 % regulation accuracy over full temperature range
• Low electromagnetic emission with spread spectrum modulation and integrated transformer design
• Enable, Power Good, UVLO, OVLO, soft-start, short-circuit, power-limit, under-voltage, over- voltage, and over-temperature protection
• CMTI > 150 kV/µs
• AEC-Q100 qualified for automotive applications – Temperature grade 1: –40°C ≤ TJ ≤ 150°C – Temperature grade 1: –40 °C ≤ TA ≤ 125°C
• Functional Safety-Capable – Documentation available to aid functional safety system design
• Planned safety-related certifications: – 7071-VPK reinforce isolation per DIN EN IEC 60747-17 (VDE 0884-17) – 5000-VRMS isolation for 1 minute per UL1577 – Reinforced insulation per CQC GB4943.1
• 36-pin, wide SSOP package

2 Applications

• Hybrid, electric and power train system (EV/HEV) – Inverter and motor control – On-board (OBC) and wireless charger – DC/DC converter
• Grid infrastructure – EV charging station power module – DC charging (pile) station – String inverter
• Motor drives – AC Inverters and VF Drives, Robot servo drive
• Industrial transport – Off-highway vehicles electric drive

3 Description

UCC14241-Q1 is an automotive qualified high isolation voltage DC/DC power module designed to provide power to IGBT or SiC gate drivers. The UCC14241-Q1 integrates a transformer and DC/DC controller with a proprietary architecture to achieve high efficiency with very low emissions. The high- accuracy output voltages provide better channel enhancement for higher system efficiency without over-stressing the power device gate. The UCC14241-Q1 provides up to 2.0 W (typical) of isolated output power at high efficiency. Requiring a minimum of external components and including on-chip device protection, the module provides extra features such as input undervoltage lockout, overvoltage lockout, output voltage power-good comparators, overtemperature shutdown, soft-start time-out, adjustable isolated positive and negative output voltage, an enable pin, and an open-drain output power-good pin.

Package Information

NUMBER(1) PACKAGE BODY SIZE (NOM) PUCC14241QDWNRQ1 DWN (SSOP, 36) 12.83 mm × 7.5 mm UCC14241QDWNRQ1 DWN (SSOP, 36) 12.83 mm × 7.5 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. PG ENA VIN GNDP VDD RLIM FBVDD FBVEE VEE RLIM PG ENA CIN VIN COUT2 COUT3 COUT1 COM VDD Source/ emitter VEE Isolation barrier Simplified Application Typical Power-up Sequence ADVANCE INFORMATION UCC14241-Q1 SLUSF09 – APRIL 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

10.2 Receiving Notification of Documentation Updates..39

11 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES April 2023 * Advance Information release UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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5 Device Comparison

Table 5-1. Device Comparison Table DEVICE NAME VVIN Range Output (VDD-VEE) Adjustable Range Typical power Isolation rating UCC14240-Q1 21 V to 27 V 18 V to 25 V 2 W Basic UCC14241-Q1 21 V to 27 V 15 V to 25 V 2 W Reinforced UCC14141-Q1

8 V to 18 V 18 V to 25 V 1 W

10.8 V to 13.2 V 18 V to 25 V 1.5 W UCC14341-Q1 13.5 V to 16.5 V 18 V to 25 V 1.5 W Reinforced UCC14131-Q1 12 V to 15 V 12 V to 15 V 1.5 W Reinforced 15 V to 18 V 15 V to 18 V 1.5 W

10 V to 18 V 10 V to 12 V 1 W

14 V to 18 V 10 V to 18 V 1 W

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6 Pin Configuration and Functions

Figure 6-1. DWN Package, 36-Pin SSOP (Top View) Table 6-1. Pin Functions PIN TYPE (1) DESCRIPTION NAME NO. GNDP 1, 2, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 G Primary-side ground connection for VIN. PIN 1,2, and 5 are analog ground. PIN 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18 are power ground. Place several vias to copper pours for thermal relief. See Layout Guidelines. PG 3 O Active low power-good open-drain output pin. PG remains low when (VVIN_UVLOP ≤ VVIN ≤ VVIN_OVLO); (VVDD_UVP ≤ VFBVDD ≤ VVDD_OVP); (VVEE_UVP ≤ VFBVEE ≤ VVEE_OVP); TJ_Primary ≤ TSHUTPPRIMARY_RISE; and TJ_secondary ≤ TSHUTSECONDARY_RISE ENA 4 I Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device functionality. 5.5-V recommended maximum. VIN 6, 7 P Primary input voltage. PIN 6 is for analog input, and PIN 7 is for power input. For PIN 7, connect one 10-µF ceramic capacitor from power VIN PIN 7 to power GNDP PIN 8. Connect a 0.1-µF high-frequency bypass ceramic capacitor close to PIN 7 and PIN 8. VEE 19, 20, 21, 22, 23, 24, 25,26, 27, 30,31, 36 G Secondary-side reference connection for VDD and COM. The VEE pins are used for the high current return paths. UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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Table 6-1. Pin Functions (continued) PIN TYPE (1) DESCRIPTION NAME NO. VDD 28, 29 P Secondary-side isolated output voltage from transformer. Connect a 2.2-µF and a parallel 0.1-µF ceramic capacitor from VDD to VEE. The 0.1-µF ceramic capacitor is the high frequency bypass and must be next to the IC pins. A 4.7-µF or 10-µF ceramic capacitor can be used instead of 2.2 µF to further reduce the output ripple voltage RLIM 32 P Secondary-side second isolated output voltage resistor to limit the source current from VDD to COM node, and the sink current from COM to VEE. Connect a resistor from RLIM to COM to regulate the (COM – VEE) voltage. See RLIM Resistor Selection for more detail. FBVEE 33 I Feedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage. Connect a resistor divider from COM to VEE so that the midpoint is connected to FBVEE, and the equivalent FBVEE voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor for high frequency bypass must be next to the FBVEE and VEEA IC pins on top layer or back layer connected with vias. FBVDD 34 I Feedback (VDD – VEE) output voltage sense pin and to adjust the output (VDD – VEE) voltage. Connect a resistor divider from VDD to VEE so that the midpoint is connected to FBVDD, and the equivalent FBVDD voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor for high frequency bypass must be next to the FBVDD and VEEA IC pins on top layer or back layer connected with vias. VEEA 35 G Secondary-side analog sense reference connection for the noise sensitive analog feedback inputs, FBVDD and FBVEE. Connect the low-side feedback resistors and high frequency decoupling filter capacitor close to the VEEA pin and respective feedback pin FBVDD or FBVEE. Connect to secondary-side gate drive lowest voltage reference, VEE. Use a single point connection and place the high frequency decoupling ceramic capacitor close to the VEEA pin. See Layout Guidelines. (1) P = power, G = ground, I = input, O = output www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: UCC14241-Q1

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) Parameters PIN MIN TYP MAX UNIT VIN to GNDP –0.3 32 V ENA, PG to GNDP –0.3 7 V VDD, VEE, RLIM, FBVDD, FBVEE to VEE –0.3 32 V POUT_VDD_MAX Total (VDD-VEE) output power at TA=25°C 2.5 W IRLIM_MAX_RMS_SOURCE Max RLIM pin rms current sourcing from VDD to RLIM. (16% average run time over lifetime of 24,500 hr) 0.125 A IRLIM_MAX_RMS_SINK Max RLIM pin rms current sinking from RLIM to VEE. (16% average run time over lifetime of 24,500 hr) 0.125 A TJ Operating junction temperature range –40 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Charged-device model (CDM), per AEC Q100-011 Section 7.2 ±500 V (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) PIN MIN TYP MAX UNIT VVIN Primary-side input voltage to GNDP 21 24 27 V VENA Enable to GNDP 0 5.5 V VPG Powergood to GNDP 0 5.5 V VVDD VDD to VEE 15 25 V VVEE COM to VEE 2.5 VDD-VEE V VFBVDD, VFBVEE FBVDD, FBVEE to VEE 0 2.5 5.5 V TA Ambient temperature –40 125 °C TJ ((1)) Junction temperature –40 150 °C (1) See the (VDD-VEE) and (COM-VEE) Load Recommended Operating Area section for maximum rated values across temperature and VVIN conditions for different (VDD-VEE) and (COM-VEE) output voltage settings.

7.4 Thermal Information

THERMAL METRIC(1) UNITDWN (SOIC)

36 PINS

RθJA Junction-to-ambient thermal resistance 52.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.5 °C/W RθJB Junction-to-board thermal resistance 25.9 °C/W ΨJT Junction-to-top characterization parameter 16.6 °C/W ΨJB Junction-to-board characterization parameter 25.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance – °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Power Ratings

VVIN = 24 V, CIN = 10µF, COUT = 2.2 uF, TJ = 150 °C, VENA = 5 V PARAMETER TEST CONDITIONS TYP VALUE UNIT PD Power dissipation (VDD – VEE) = 25 V, PVDD-VEE = 2 W; (COM – VEE) = 5 V, No Load from (VDD - COM) or (COM - VEE) 1.65 W www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: UCC14241-Q1

7.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT General CLR External clearance (1) Shortest terminal-to-terminal distance through air > 8 mm CPG External creepage (1) Shortest terminal-to-terminal distance across the package surface > 8 mm DTI Distance through the insulation Minimum internal gap (internal clearance – transformer power isolation) > 120 µm Minimum internal gap (internal clearance – capacitive signal isolation) > 15.4 µm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V Material group According to IEC 60664-1 I Overvoltage category Rated mains voltage ≤ 300 VRMS I-IV Rated mains voltage ≤ 600 VRMS I-IV Rated mains voltage ≤ 1000 VRMS I-III DIN EN IEC 60747-17 (VDE 0884-17) (Planned Certification Targets) (2) VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1414 VPK VIOWM Maximum working isolation voltage AC voltage (sine wave) Time dependent dielectric breakdown (TDDB) test 1000 VRMS DC voltage 1414 VDC VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60s (qualification); VTEST = 1.2 × VIOTM, t = 1s (100% production) 7071 VPK VIMP Maximum impulse voltage ((3)) Tested in air, 1.2/50-μs waveform per IEC 62368-1 6250 VPK VIOSM Maximum surge isolation voltage (3) Tested in oil (qualification test), 1.2/50 µs waveform per IEC 62368-1 10000 VPK qpd Apparent charge (4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 1696 VPK, tm = 10 s ≤ 5 pC Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM =

2262 VPK, tm = 10 s

≤ 5 pC Method b1: At routine test (100% production) and preconditioning (type test) Vini = 1.2 × VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM = 2651 VPK, tm = 1 s ≤ 5 pC CIO Barrier capacitance, input to output (5) VIO = 0.4 sin (2πft), f = 1 MHz < 3.5 pF RIO Isolation resistance, input to output (5) VIO = 500 V, TA = 25°C > 1012 Ω VIO = 500 V, 100°C ≤ TA ≤ 125°C > 1011 Ω VIO = 500 V at TS = 150°C > 109 Ω Pollution degree 2 Climatic category 40/125/21 UL 1577 (Planned Certification Target) VISO Withstand isolation voltage VTEST = VISO = 5000 VRMS, t = 60 s (qualification); VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production)

5000 VRMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these specifications. (2) This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. (3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier (4) Apparent charge is electrical discharge caused by a partial discharge (pd). UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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(5) All pins on each side of the barrier tied together creating a two-terminal device

7.7 Safety-Related Certifications

Plan to certify according to DIN EN IEC 60747-17 (VDE 0884-17) Plan to certify under UL 1577 Component Recognition Program Plan to certify according to GB4943.1 Reinforced insulation Maximum transient isolation voltage, 7071 VPK; Maximum repetitive peak isolation voltage, 1414 VPK; Maximum surge isolation voltage, 10000 VPK Single protection, 5000 VRMS Reinforced insulation, Altitude ≤ 5000 m, Tropical Climate, 700 VRMS maximum working voltage Certificate number: (planned) File number: (planned) Certificate number: (planned)

7.8 Electrical Characteristics

Over operating temperature range (TJ = –40 °C to 150 °C), VVIN = 21 V to 27 V, CIN = 10 µF, COUT = 2.2 µF, RLIM = 1 kΩ, VENA = 5 V, unless otherwise noted. All typical values at TA = 25 °C and VVIN = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY (Primary-side. All voltages with respect to GNDP) VVIN Input voltage range Primary-side input voltage to GNDP 21 24 27 V IVINQ_OFF VIN quiescent current, disabled VENA=0 V; VVIN=21 V - 27 V 700 µA IVIN_ON_NO_LOAD VIN operating current, enabled, No Load VENA=5 V; VVIN=21 V - 27 V; (VDD- VEE) =25-V regulating; IVDD-VEE = 0 mA. Single Output. 35 mA IVIN_ON_FULL_LOAD VIN operating current, enabled, Full Load VENA=5 V; VVIN=21 V - 27 V; (VDD- VEE) = 25-V regulating; IVDD-VEE = 60 mA. Single Output. 250 mA UVLOP COMPARATOR (Primary-side. All voltages with respect to GNDP) VVIN_ANALOG_UVLO P_RISING VIN analog undervoltage lockout rising threshold Analog Comparator Always Active First 7.8 8.2 8.5 V VVIN_ ANALOG_UVLOP_FALL ING VIN analog undervoltage lockout falling threshold Analog Comparator Always Active First 7 7.4 7.7 V VVIN_UVLOP_RISING VIN undervoltage lockout rising threshold 19 20 21 V VVIN_UVLOP_FALLIN G VIN undervoltage lockout falling threshold 17.1 18 18.9 V OVLO COMPARATOR (Primary-side. All voltages with respect to GNDP) VVIN_OVLO_RISING VIN overvoltage lockout rising threshold 29.45 31 32.55 V VVIN_OVLO_FALLING VIN overvoltage lockout falling threshold 27.55 29 30.45 V TSHUTP THERMAL SHUTDOWN COMPARATOR (Primary-side. All voltages with respect to GNDP) TSHUTPPRIMARY_ RISE Primary-side over-temperature shutdown rising threshold First time at power-up TJ needs to be < 130 °C to turnon 140 150 160 °C TSHUTPPRIMARY_ HYST Primary-side over-temperature shutdown hysteresis 15 20 25 °C ENA INPUT PIN (Primary-side. All voltages with respect to GNDP) VEN_IR Input voltage rising threshold, logic HIGH Rising edge 1.25 1.95 V VEN_IF Input voltage falling threshold, logic LOW Falling edge 0.84 1.44 V IEN Enable Pin Input Current VENA = 5.0 V 5 10 µA PG OPEN-DRAIN OUTPUT PIN (Primary-side. All voltages with respect to GNDP) VPG_OUT_LO PG output-low saturation voltage Sink Current = 5 mA, power good 0.5 V www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: UCC14241-Q1

Over operating temperature range (TJ = –40 °C to 150 °C), VVIN = 21 V to 27 V, CIN = 10 µF, COUT = 2.2 µF, RLIM = 1 kΩ, VENA = 5 V, unless otherwise noted. All typical values at TA = 25 °C and VVIN = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPG_OUT_HI PG Leakage current VPG = 5.5 V, power not good 5 µA Primary-side Control (All voltages with respect to GNDP) FSW Switching frequency VVIN = 24 V; VENA = 5 V; (VDD-VEE) =

25 V 11 13 15 MHz

Frequency of Spread Spectrum Modulation (SSM) triangle waveform Only during primary-side startup starting after VIN > UVLOP, and ENA = HIGH; FSS_BURST_P = 125 kHz 90 kHz SSM Percentage change of FCARRIER SSM Percent change of carrier frequency during Spread Spectrum Modulation (SSM) by triangle waveform Only during primary-side startup starting after VIN > UVLOP, and ENA = HIGH; FSS_BURST_P = 125 kHz 5 % tSOFT_START_TIME_O UT Primary-side soft-start time-out Timer begins when VIN > UVLOP and ENA = High and reset when Powergood pin indicates Good 28.4 ms (VDD-VEE) OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE) VVDD_RANGE (VDD – VEE) Output voltage range POUT_MAX up to 1.5W @ TA = 105oC 18 25 V VVDD_RANGE (VDD – VEE) Output voltage range POUT_MAX up to 1.3W @ TA = 105oC 15 25 V VVDD_DC_ACCURAC Y (VDD – VEE) Output voltage DC regulation accuracy Secondary-side (VDD – VEE) output voltage, over load, line and temperature range, externally adjust with external resistor divider -1.3 1.3 % (VDD-VEE) REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE) VFBVDD_REF Feedback regulation reference voltage for (VDD – VEE) (VDD – VEE) output in regulation 2.4675 2.5 2.5325 V VFBVDD_HYST FBVDD Hysteresis comparator hysteresis settings. Hysteresis at the FBVDD pin. [The (VDD-VEE) hysteresis would amplify this FBVDD hysteresis by the feedback resistor divider gain.] 9 10 12.3 mV (COM-VEE) OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE) VVEE_RANGE (COM – VEE) Output voltage range Secondary-side (COM – VEE), adjust with external resistor divider 2.5 (VDD- VEE) V VVEE_DC_ACURACY (COM - VEE) Output voltage DC regulation accuracy Secondary-side (COM – VEE) output voltage, over load, line and temperature range, externally adjust with external resistor divider –1.3 1.3 % VISO2 REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE) VFBVEE_REF Feedback regulation reference voltage for (COM – VEE) (COM – VEE) output in regulation 2.4675 2.5 2.5325 V VRLIM_SHORT_CHRG _CMP_RISE Rlim Short Charge comparator rising threshold to exit PWM Rising threshold 0.73 V tRLIM_SHORT_CHRG_ ON_TIME On-Time during RLIM pin Short Charge PWM mode RLIM pin < 0.645 V, while FBVEE pin < 2.48 V 1.2 us tRLIM_SHORT_CHRG_ OFF_TIME Off-Time during RLIM pin Short Charge PWM mode RLIM pin < 0.645 V, while FBVEE pin < 2.48 V 5 us UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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Over operating temperature range (TJ = –40 °C to 150 °C), VVIN = 21 V to 27 V, CIN = 10 µF, COUT = 2.2 µF, RLIM = 1 kΩ, VENA = 5 V, unless otherwise noted. All typical values at TA = 25 °C and VVIN = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (VDD-VEE) UVLOs COMPARATOR (Secondary-side. All voltages with respect to VEE) VVDD_UVLO_RISING (VDD – VEE) undervoltage lockout rising threshold Voltage at FBVDD 0.9 V VVDD_UVLO_HYST (VDD – VEE) undervoltage lockout hysteresis Voltage at FBVDD 0.2 V (VDD-VEE) OVLOs COMPARATOR (Secondary-side. All voltages with respect to VEE) VVDD_OVLOS_RISING (VDD – VEE) over-voltage lockout rising threshold Voltage from VDD to VEE, rising 29.45 31 32.55 V VVDD_OVLOS_FALLIN G (VDD – VEE) over-voltage lockout falling threshold Voltage from VDD to VEE, falling 27.55 29 30.45 V SOFT-START (Secondary-side. All voltages with respect to VEE) tblankout Blank out time after soft start before PG for (VDD-VEE) UVP and (COM- VEE) UVP & OVP 3 ms (VDD-VEE) UVP, UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE) VVDD_UVP_RISING (VDD – VEE) under-voltage protection rising threshold, VUVP = VREF × 90% 2.175 2.25 2.35 V VVDD_UVP_HYST (VDD – VEE) under-voltage protection hysteresis 20 mV (VDD-VEE) OVP, OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE) VVDD_OVP_RISING (VDD – VEE) over-voltage lockout rising threshold, VOVP = VREF ×110% 2.7 2.75 2.825 V VVDD_OVP_HYST (VDD – VEE) over-voltage protection hysteresis 20 mV (COM-VEE) UVP, UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE) VVEE_UVP_RISING (COM – VEE) under-voltage protection rising threshold, VUVP = VREF × 90% 2.1 2.25 2.4 V VVEE_UVP_HYST (COM – VEE) under-voltage protection hysteresis 20 mV (COM-VEE) OVP, OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE) VVEE_OVP_RISING (COM – VEE) over-voltage protection rising threshold, VOVP = VREF × 110% 2.7 2.75 2.825 V VVEE_OVP_HYST (COM – VEE) over-voltage protection hysteresis 20 mV TSHUTS THERMAL SHUTDOWN COMPARATOR (Secondary-side. All voltages with respect to VEE) TSHUTSSECONDAR Y_RISE Secondary -side over-temperature shutdown rising threshold First time at power-up Tj needs to be < 130oC to turnon. 145 150 155 °C TSHUTSSECONDAR Y_HYST Secondary-side over-temperature shutdown hysteresis 15 20 25 °C CMTI (Common Mode Transient Immunity) CMTI Common Mode Transient Immunity Positive VEE with respect to GNDP 150 V/ns Negative VEE with respect to GNDP -150 V/ns INTEGRATED MAGLAM TRANSFORMER (Primary-side to Secondary-side. Note: these values unique for each version of XFMR) N Transformer effective turns ratio Secondary side to primary side 1.18 - www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: UCC14241-Q1

7.9 Safety Limiting Values

PARAMETER TEST CONDITIONS MAX UNIT IS Safety input rms current RθJA = 52.3 °C/W, VVIN = 27 V, TJ = 150 °C, TA = RθJA = 52.3 °C/W, VVIN = 21 V, TJ = 150 °C, TA = PS Safety power dissipation (input power - output power) RθJA = 52.3 °C/W, TJ = 150 °C, TA = 25 °C ((1)) ((2)) 2.39 W TS Safety temperature ((1)) ((2)) 150 °C (1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS and PS parameters represent the safety current and safety power dissipation respectively. The maximum limits of IS and PS should not be exceeded. These limits vary with the ambient temperature, TA. (2) The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K JEDEC test board for leaded surface-mount packages. Use these equations to calculate the value for each parameter: TJ = TA + RθJA × P, where P is the power dissipated in the device. TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.

7.10 Typical Characteristics

Figure 7-1. SOA Derating Curves: VVDD-VEE = 18 V, VCOM-VEE = 5 V, No Load. Figure 7-2. SOA Derating Curves: VVDD-VEE = 20 V, VCOM-VEE = 5 V, No Load Figure 7-3. SOA Derating Curves: VVDD-VEE = 25 V, VCOM-VEE = 5 V, No Load UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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7.10 Typical Characteristics (continued)

Figure 7-4. Start-up: VIN = 24 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V, No Load Figure 7-5. Shutdown: VIN = 24 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V, No Load Figure 7-6. Load Transient Response: No Load to 1 W, VIN = 24 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V Figure 7-7. Load Transient Response: 1 W to No Load, VIN = 24 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V Figure 7-8. VVDD-VEE Load Regulation: VIN = 21 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V Figure 7-9. VVDD-VEE Load Regulation: VIN = 24 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: UCC14241-Q1

Figure 7-10. VVDD-VEE Load Regulation: VIN = 27 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V Figure 7-11. VCOM-VEE Load Regulation: VIN = 21 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V Figure 7-12. VCOM-VEE Load Regulation: VIN = 24 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V Figure 7-13. VCOM-VEE Load Regulation: VIN = 27 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V Figure 7-14. Efficiency vs Load on VVDD-VEE: VIN = 21 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V, No Load on VCOM-VEE Figure 7-15. Efficiency vs Load on VVDD-VEE: VIN = 24 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V, No Load on VCOM-VEE UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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Figure 7-16. Efficiency vs Load on VVDD-VEE: VIN = 27 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V, No Load on VCOM-VEE Figure 7-17. Input Current vs Load on VVDD-VEE: VIN = 21 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V, No Load on VCOM-VEE Figure 7-18. Input Current vs Load on VVDD-VEE: VIN = 24 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V, No Load on VCOM-VEE Figure 7-19. Input Current vs Load on VVDD-VEE: VIN = 27 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V, No Load on VCOM-VEE www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: UCC14241-Q1

8 Detailed Description

8.1 Overview

UCC14241-Q1 device is suitable for applications that have limited board space and require more integration. These devices are also suitable for very-high voltage applications, where power transformers meeting the required isolation specifications are bulky and expensive. The low-profile, low-center of gravity, and low weight provides a higher vibration tolerance than systems using large bulky transformers. The device is easy-to-use and provides flexibility to adjust both positive and negative output voltages as needed when optimizing the gate voltage for maximum efficiency while protecting gate oxide from over-stress with its tight voltage regulation accuracy. The device integrates a high-efficiency, low-emissions isolated DC/DC converter for powering the gate drive of SiC or IGBT power devices in traction inverter motor drives, industrial motor drives, or other high voltage DC/DC converters. This DC/DC converter provides greater than 1.5 W of power. The integrated DC/DC converter uses switched mode operation and proprietary circuit techniques to reduce power losses and boost efficiency. Specialized control mechanisms, clocking schemes, and the use of an on- chip transformer provide high efficiency and low radiated emissions. The integrated transformer provides power delivery throughout a wide temperature range while maintaining a 5000-V RMS isolation, and an 1000-V RMS continuous working voltage. The low isolation capacitance of the transformer provides high CMTI allowing fast dv/dt switching and higher switching frequencies, while emitting less noise. The VVIN supply is provided to the primary-side power controller that switches the input stage connected to the integrated transformer. Power is transferred to the secondary-side output stage, and regulated to a level set by the resistor divider connected between the (VDD – VEE) pin and the FBVDD pin with respect to the VEE pin. The output voltage is adjustable with external resistor divider allowing a wide (VDD – VEE) range. For optimal performance ensure to maintain the V VIN input voltage within the recommended operating voltage range. Do not exceed the absolute maximum voltage rating to avoid over-stressing the input pins. A fast hysteretic feedback burst control loop monitors (VDD – VEE) and ensures the output voltage is kept within the hysteresis with low overshoots and undershoots during load and line transients. The burst control loop enables efficient operation across full load and allows a wide VOUT adjustability throughout the whole V VIN range. The undervoltage lockout (UVLO) protection monitors the input voltage pin, VIN, with hysteresis and input filter ensuring robust system performance under noisy conditions. The overvoltage lockout (OVLO) protection monitors the input voltage pin, VIN, protects against over-voltage stress by disabling switching and reducing the internal peak voltage. Controlled soft-start timing, provided throughout the full power-up time, limits the peak input inrush current while charging the output capacitor and load. The UCC14241-Q1 also provides a second output rail, (COM – VEE), that is used as a negative bias for the gate drivers, allowing quicker turn-off switching for the IGBTs, and also to protect from unwanted turn-on during fast switching of SiC devices. (COM – VEE) has a simple, yet fast and efficient bias controller to ensure the positive and negative rails are regulated during the PWM switching. The COM pin can be connected from the source of SiC device or emitter of an IGBT device. An external current limiting resistor allows the designer to program the sink and source current peak according to the needs of the gate drive system. A fault protection and powergood status pin provides a mechanism for the host controller to monitor the status of the DC/DC converter and provide proper sequencing of power and PWM control signals to the gate driver. Fault protection includes undervoltage, overvoltage, over-temperature shutdown, and a 100 μs isolated channel communication interface watchdog timer. A typical soft-start ramp-up time is approximately 3 ms, but varies based on input voltage, output voltage, output capacitance, and load. If either output is shorted or over-loaded, the device is not able to power-up within the 28.4-ms soft-start watch-dog-timer protection time, so the device latches off for protection. The latch can be reset by toggling the ENA pin or powering VIN down and up. UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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The output load must be kept low until start-up is complete and PG pin is low. When powering up, do not apply a heavy load to (VDD – VEE) or (COM – VEE) outputs until the /PG pin has indicated power is good (pulling logic low) to avoid problems providing the power to ramp-up the voltage. TI recommends to use the PG status indicator as a trigger point to start the PWM signal into the gate driver. PG output removes any ambiguity as to when the outputs are ready by providing a robust closed loop indication of when both (VDD –VEE) and (COM – VEE) outputs have reached their regulation threshold within ±10%. Do not allow the host to begin PWM to gate driver until after PG goes low. This action typically occurs less than 28.4 ms after VVIN > VVIN_UVLOP and ENA goes high. The /PG status output indicates the power is good after soft start of (VDD – VEE) and (COM – VEE) and are within ±10% of regulation. If the host is not monitoring PG, then ensure that the host does not begin PWM to gate driver until 30 ms after VVIN > V VIN_UVLOP and ENA goes high to allow enough time for power to be good after soft start of VDD and VEE.

8.2 Functional Block Diagram

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8.3 Feature Description

8.3.1 Power Stage Operation

The UCC14241-Q1 module uses an active full-bridge inverter on the primary-side and a passive full-bridge rectifier on the secondary-side. The small integrated transformer has a relatively high carrier frequency to reduce the size for integrating into the 36-pin SSOP package. The power stage carrier frequency operates within 10 MHz to 16 MHz. The power stage carrier frequency is determined by input voltage with a feed-forward control: when VVIN is 21 V, the frequency is 16 MHz; when VVIN is 27 V, the frequency is 10 MHz; when VVIN is between 21 V and 27 V, the frequency reduces gradually from 16 MHz to 10 MHz as VVIN voltage rises. Spread spectrum modulation, SSM, is used to reduce emissions. ZVS operation is maintained to reduce switching power losses. The UCC14241-Q1 module creates two regulated outputs. It can be configured as a single output converter, VDD to VEE only, or a dual-output converter, VDD to VEE and COM to VEE. Even though the module uses VEE as the reference point to create two positive output voltages, the outputs can use COM as the reference point and become a positive and a negative output. These two outputs are controlled independently through hysteresis control. Furthermore, the VDD-VEE is the main output, and COM to VEE uses the main output as its input to created a second regulated output voltage.

8.3.1.1 VDD-VEE Voltage Regulation

The VDD-VEE output is the main output of the module. The power stage operation is determined by the sensed VDD-VEE voltage on FBVDD pin. As shown in Figure 8-1, the VDD-VEE voltage is sensed through a voltage divider R FBVDD_TOP and R FBVDD_BOT. When FBVDD voltage stays below the turn-off threshold, roughly 10 mV above the V FBVDD_REF, the power stage operates, delivers power to the secondary side and makes the VDD-VEE output voltage rise. After the output reaches the turn-off threshold, the power stage turns off. Output voltage drops because of the load current. After the output voltage drops below the turn-on threshold, roughly 10 mV below the V FBVDD_REF, the power stage is turned on again. With the accurate voltage reference and hysteresis control, the VDD-VEE output voltage can be regulated with high accuracy. To improve the noise immunity, a small capacitor of 330 pF should be added between FBVDD and VEE pins. Excessive capacitor slows down the hysteresis loop and can cause excessive output voltage ripple or even stability issue. VDD VEE FBVDD VIN GNDP Power stage VFBVDD_REF RFBVDD_TOP RFBVDD_BOTCFBVDD COUT1 Figure 8-1. VDD-VEE Voltage Regulation UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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8.3.1.2 COM-VEE Voltage Regulation

COM-VEE output takes VDD-VEE output as its input and creates a regulated output voltage. It can be considered as an LDO output from VDD-VEE, though the operation principle is not quite the same. Given its input voltage is VDD-VEE, the maximum output voltage from COM to VEE is the voltage between VDD and VEE. The COM-VEE output regulator stage uses the internal high-side or low-side FETs in series with the external current-limit resistor (R LIM) to charge or discharge the COM-VEE output voltage. The hysteresis control is used to control the switching instance of the two FETs, to achieve an accurately regulated COM-VEE voltage. As shown in Figure 8-2 , the COM-VEE output voltage is sensed through the voltage divider R FBVEE_TOP and RFBVEE_BOT on FBVEE pin. TI recommends a 330-pF capacitor on FBVEE pin to filter out the switching frequency noise. When the voltage on FBVEE is below the charging threshold, 20 mV below the V FBVEE_REF, the charging resistor is kept on and discharging resistor is kept off. COM-VEE output voltage rises. After FBVEE voltage reaches the stop charging threshold, 20 mV above the V FBVEE_REF, the charging resistor is turned off. Output voltage rise stops. When the charging resistor is turned off, the discharge resistor is controlled by another hysteresis controller, based on FBVEE pin voltage, with the same reference voltage V FBVEE_REF, and 20-mV of hysteresis. The COM-VEE output regulator stage will protect from having the high-side FET stay ON for a long time during a COM to VEE short. This protection feature is implemented by monitoring the RLIM-pin voltage and controlling the high-side FET duty-ratio. When the COM pin voltage is lower than 0.645 V while the FBVEE voltage is below 2.48 V, the hysteretic control of the COM-VEE regulator is overridden by an approximately 20 % duty-ratio control on high-side FET, with a typical on-time of t RLIM_SHORT_CHRG_ ON_TIME and off-time of t RLIM_SHORT_CHRG_ OFF_TIME in each duty cycle. When the COM pin voltage is higher than VRLIM_SHORT_CHRG_CMP_RISE, the duty ratio control is disabled and the hysteretic control resumes to normal operation. RLIM COM VEE SW SW FBVEE VFBVEE_REF VFBVEE_REF VDD RLIM COUT2 COUT3 VEE VDD 20 mV 1.25 mV RFBVEE_TOP RFBVEE_BOT CFBVEE RCharge RDischarge Figure 8-2. COM-VEE Voltage Regulation www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: UCC14241-Q1

2.52V 2.48V TurnON Charge FET TurnON Charge FET TurnOFF CHARGE FET 2.50125V Discharge Comparitor Discharge Control TurnON Discharge FET VFBVEE_REF = 2.5V Figure 8-3. COM-VEE Voltage Regulation Diagram

8.3.1.3 Power Handling Capability

The maximum power handling capability is determined by both circuit operation and thermal condition. For a given output voltage, the maximum power increases with input voltage before triggering the thermal protection. An over-power-protection (OPP) is implemented to limit maximum output power and reduces power stage RMS current at high input voltage. The OPP is implemented by a feed-forward control from the input voltage to the OPP burst duty cycle (D OPP). The D OPP adds a "baby" burst within the on-time of "Mama" burst from the main feedback loop for the (VDD-VEE) regulation. When the input voltage increases, the D OPP reduces automatically to limit the averaged output power. At high ambient temperature, the thermal performance determines the maximum power and safe operating area (SOA). A protective thermal shut-down is triggered after overtemperature is detected. The high-efficiency and optimized thermal design for transformer and silicon provide a high power handling capability at high ambient temperature in a small package. (VDD-VEE) burst OPP burst (VDD-VEE) Figure 8-4. Diagram of Over-Power-Protection with baby burst UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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8.3.2 Output Voltage Soft Start

UCC14241-Q1 power-up diagram of two output rails with soft start is shown in Figure 8-5 . After V VIN > VVIN_UVLOP and ENA is pulled high, the soft-start sequence starts with burst duty cycle control with soft duty cycle increment. The burst duty cycle gradually increases from 12.5% to 50% over time by the primary-side control signal (DSS_PRI), so both V VDD-VEE and VCOM-VEE increase ratiometrically with a controlled shallow rising slope. When V VDD-VEE is increased above V VDD_UVLOS, there is a sufficient bias voltage for the feedback-loop communication channel, so the burst feedback control on the secondary side takes over. As a result, the DSS_PRI is pulled high and does not affect burst duty cycle anymore. The burst duty cycle is determined by comparing VFBVDD and V REF. V REF increases from 0.9V to 2.5 V with seven increment steps, where the first 0.4-V step lasts 128 µs. After VVDD-VEE > VVDD_UVP, the RLIM source-sink regulator for VCOM-VEE is enabled. The polarity of source or sink current of RLIM pin is determined by comparing V FBVEE and VREF so as to keep VCOM-VEE in tight regulation. Once V VDD-VEE or V COM-VEE rises across its UVP threshold, there is a 3-ms (typical) blanking time for VVDD-VEE UVP and VCOM-VEE UVP and OVP, and then the power good signal is issued by pulling PG voltage low. The 3-ms (typical) blanking time is only applied during start up before the power good signal is issued. It provides enough time for both V VDD-VEE and V COM-VEE to settle in their hysteresis band of regulation after start up, so that the converter does not shut down due to the overshoot or undershoot during start up. The soft-start feature greatly reduces the input inrush current during power-up. In addition, if V VDD-VEE cannot reach to VVDD_UVLOS within 28.4 ms, then the device shuts down in a safe-state. The 28.4-ms soft-start time-out protects the module under output short circuit condition before power up. UVLOP DSS(PRI) tdelay ENA VIN VDD_UVLOS Comparator_Enable VREF RLIM Comparator_Enable 2.5V VVDD_OVP VVDD_UVP VVEE_OVP VVEE_UVP 128µs VVDD-VEE VCOM-VEE VIN_UVLOP VVDD_UVLOS D = 100% PG Figure 8-5. Output voltage Soft-Start Diagram www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: UCC14241-Q1

8.3.3 ENA and PG

The ENA input pin and PG output pin on the primary-side use 5-V TTL and 3.3-V LVTTL level logic thresholds. The active-high enable input (ENA) pin is used to turn-on the isolated DC/DC converter of the module. Either 3.3-V or 5-V logic rails can be used. Maintain the ENA pin voltage below 5.5 V. After ENA pin voltage becomes above the enable threshold VEN_IR, UCC14241-Q1 enables, starts switching, goes through the soft-start process and delivers power to the secondary side. After ENA pin voltage falls below the disable threshold V EN_IF, UCC14241-Q1 disables, stops switching. The ENA pin can also be used to reset the UCC14241-Q1 device after it enters the protection safe-state mode. After a detected fault, the protection logic will latch off and place the device into a safe state. When all the faults are cleared, the ENA-pin can be used to clear the UCC14241-Q1 latch by toggling the ENA pin voltage below VEN_IF for longer than 150 μs, then toggling back up to 3.3 V or 5 V. The device will then exit the latch-off mode and we initiate a soft-start. Figure 8-6 illustrates the latch-off reset timing. ENA Latch-off state Latched-off Latch-off reset Power-stage state Stop Run 150 µs PG Delay time determined by output condition Figure 8-6. Latch-off Reset Using ENA Pin The active-low power-good (PG) pin is an open-drain output that indicates (short) when the module has no fault and the output voltages are within ±10% of the output voltage regulation setpoints. Connect a pull-up resistor (> 1 kΩ) from PG pin to either a 5-V or 3.3-V logic rail. Maintain the PG pin voltage below 5.5 V without exceeding its recommended operating voltage. The logic of PG pin can be illustrated using Figure 8-7. 1.1×VFBVDD_REF 0.9×VFBVDD_REF 1.1×VFBVEE_REF 0.9×VFBVEE_REF Isolation VEN_IR/VEN_IFGNDP FBVDD FBVEE Protections (Over-temperature, output over voltage, input UVLO, input OVLO) ENA PG Figure 8-7. PG Pin Logic UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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8.3.4 Protection Functions

UCC14241-Q1 is equipped with a full feature of protection functions, include input undervoltage lockout, overvoltage lockout protections, output undervoltage protection, overvoltage protection, overpower protection, and over-temperature protection. The input undervoltage and overvoltage lockout protections have the auto recovery response. All other protections have the latch-off response. After the latch-off-response protections are triggered, the converter enters a latch off state, stops switching until the latch is reset by either toggling the ENA pin Off then On, or by lowering the V VIN voltage below the VVIN_ANALOG_UVLOP_FALLING threshold, and then above the VVIN_UVLOP_RISING threshold.

8.3.4.1 Input Undervoltage Lockout

UCC14241-Q1 can take wide input voltage range, from 21 V to 27 V. When the input voltage becomes too low, the output either cannot be regulated due to the transformer turns ratio limitation, or the converter operates with too much current stress. Either way, the converter must shut down to protect the system. The UCC14241-Q1 enters input undervoltage lockout when V VIN voltage becomes lower than the UVLO threshold V VIN_UVLOP_FALLING. In UVLO mode, the converter stops switching. After VIN pin voltage becomes lower than the VIN analog undervoltage lockout falling threshold V VIN_VULOP_FALLING , UCC14241-Q1 resets all the protections. After that, after the V VIN voltage becomes above the UVLO threshold V VIN_UVLOP_RISING, the converter is enabled. Depending on the ENA pin voltage, the converter can start switching, go through the soft-start process, or in the disable mode, waiting for ENA pin voltage becomes high.

8.3.4.2 Input Overvoltage Lockout

The input overvoltage lockout protection is used to protect the UCC14241-Q1 devices from overvoltage damage. It has an auto-recovery response. When the V VIN pin voltage becomes higher than the input overvoltage lockout threshold V VIN_OVLO_RISE, switching stops, converter stops sending energy to the secondary side. After input overvoltage lockout protection, after V VIN pin voltage drop below the recovery threshold V VIN_OVLO_FALLING, depending on the ENA pin voltage status, the converter can either resuming operation, go through the full soft-start process, or in the disabled mode, wait for ENA pin becomes high. The input overvoltage lockout does not reset other latch-off protections. www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: UCC14241-Q1

8.3.4.3 Output Overvoltage Protection

The UCC14241-Q1 devices sense the output voltage through FBVDD and FBVEE pins to control the output voltage. To prevent the output voltage becomes too high, damages the load or UCC14241-Q1 device itself, the UCC14241-Q1 devices are equipped with the output overvoltage protection. There are two levels of overvoltage protection, based on the feedback pin voltage, and the output voltage. During the normal operation, because of load transient, or load unbalancing between two outputs, the output voltages can exceed its regulation level. Based on the pin voltages on FBVDD and FBVEE, after the voltage exceeds the threshold, VVDD_OVP_RISE, or VVEE_OVP_RISE (10% above the target regulation voltage), the converter stops switching immediately. In rare cases, the voltage divider becomes malfunction and gives the wrong output voltage information. In turn, the control loop can regulate the output voltages at a wrong voltage level. The UCC14241-Q1 device is also equipped with a fail-safe overvoltage protection. After the VDD-VEE voltage becomes higher than the overvoltage protection threshold V VDD_OVLOS_RISE, the converter shuts down immediately. This fail-safe protection level is set at 31 V. It is meant to protect UCC14241-Q1 devices, instead of the load. The design must ensure the voltage feedback divider normal operation at all conditions. The output overvoltage protections have the latch-off response. UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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8.3.4.4 Overpower Protection

The Over Power Protection, OPP, limits the maximum average output power. When the output is overloaded, it is important to shutdown the module to prevent it from further damage, or propagating the fault into other portion of the entire system. Given the extremely high switching frequency, it is not practical to implement the traditional cycle-by-cycle current limit. Instead, the UCC14241-Q1 device relies on the Over Power Protection (OPP) working together with the output undervoltage protection. As discussed in Power Handling Capability , with the input voltage feedforward, and the "baby" burst duty cycle adjustment, the maximum power delivery capability of the UCC14241-Q1 is well controlled. The impact of OPP on the relationship between Vin and maximum output power is shown in Figure 8-8. Vin Max Power Disable OPP Enable OPP Figure 8-8. Maximum Output Power Under Different Input Voltage Condition When the load exceeds the maximum power delivery capability, the output voltage starts to droop. When the output voltage falls below the Under Voltage Protection threshold, the output undervoltage protection is triggered and the parts latches off into a safe state. www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: UCC14241-Q1

8.3.4.4.1 Output Undervoltage Protection

The output voltage under voltage protection is based on the FBVDD and FBVEE pin voltages. When the FBVDD pin voltage becomes lower than its UVP threshold VVDD_UVP_FALL, or the FBVEE pin voltage becomes lower than its UVP threshold V VEE_UVP_FALL, the undervoltage protection is activated. The UCC14241-Q1 stops switching, and the PG pin becomes open. During soft start, the output voltages rise from zero. Both FBVDD and FBVEE pin voltage are below the UVP thresholds. The UVP is disabled during the soft start. If the pin voltage cannot reach the UVP recovery thresholds (V VDD_UVP_RISE, V VEE_UVP_RISE) after the soft start completes, undervoltage protection is activated. The UCC14241-Q1 stops switching, and the PG pin becomes open. The undervoltage protection has a latched-off response. After it is activated, the latch-off state can be cleared by recycling VVIN. Toggling ENA pin can also reset the latch-off state. Refer to ENA and PG section for details.

8.3.4.5 Overtemperature Protection

UCC14241-Q1 integrates the primary-side, secondary-side power stages, as well as the isolation transformer. The power loss caused by the power conversion causes the module temperature higher than the ambient temperature. To ensure the safe operation of the power module, the UCC14241-Q1 device is equipped with over-temperature protection. Both the primary-side power stage, and the secondary-side power stage temperatures are sensed and compared with the over-temperature protection threshold. If the primary-side power stage temperature becomes higher than TSHUTP PRIMARY_RISE, or the secondary-side power stage temperature becomes higher than TSHUTS SECONDARY_RISE , the module enters over-temperature protection mode. The module stops switching; PG pin becomes open. After protection, the module enters latch-off mode. When the power stage temperature drops below the over-temperature recovery threshold, recycling V VIN, or toggling ENA pin voltage brings the model out of latch-off mode. Depending on ENA pin voltage, the module either starts switching, delivering power to the secondary side, or in the standby mode waiting for ENA pin voltage becomes high. UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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8.4 Device Functional Modes

Depending on the input and output conditions, ENA pin voltage, as well as the device temperature, the UCC14241-Q1 operates in one of the below operation modes. 1. Disable mode. In this mode, the module is off, but waiting for ENA pin becoming high to start operate. 2. Soft-start mode. In this mode, the module starts to deliver power to the secondary side. The primary-side operation duty cycle and secondary-side references are raised gradually to reduce the stress to the module. 3. Normal operation mode. In this mode, the module operates normally, delivers power to the secondary side. 4. Protection mode, auto-recovery. In this mode, the module is off, due to the input UVLO or OVLO protection. After the input voltage fault is cleared, depending on the ENA pin voltage condition, it either becomes disabled mode if the ENA pin voltage is low, or it goes through soft-start mode to the normal operation mode. 5. Protection mode, latched-off. In this mode, the module is off, due to other protections. The module remains off even the fault causing the protection is cleared. Recycling VVIN operation must ensure the input voltage goes below the analog UVLO falling threshold (VVIN_ ANALOG_UVLOP_FALLING ) first to reset the latch-off state, or the ENA pin is toggled Low (OFF) then High (ON). Table 8-1 lists the supply functional modes for this device. The ENA pin has an internal weak pull-down resistance to ground, but TI does not recommend leaving this pin open. Table 8-1. Device Functional Modes INPUT OUTPUTS Operation Mode VVIN ENA FAULT V(VDD – VEE) Isolated Output1 V(COM – VEE) Isolated Output2 PG Open Drain VVIN < VVIN_UVLOP_RISING X X OFF OFF High Protection mode, auto-recovery VVIN_UVLOP_RISING < VVIN < VVIN_OVLO_RISING LOW X OFF OFF High Disable mode VVIN_UVLOP_RISING < VVIN < VVIN_OVLO_RISING HIGH NO FAULT Regulating at Setpoint Regulating at Setpoint Low Normal operation VVIN_UVLOP_RISING < VVIN < VVIN_OVLO_RISING HIGH YES FAULT OFF OFF High Protection mode, latched-off VVIN > VVIN_OVLO_RISING X X OFF OFF High Protection mode, auto-recovery www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: UCC14241-Q1

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The UCC14241-Q1 device is suitable for applications that have limited board space and desire more integration. This device is also suitable for very high voltage applications, where power transformers meeting the required isolation specifications are bulky and expensive.

9.2 Typical Application

The following figures show the typical application schematics for the UCC14241-Q1 device configurations supplying an isolated load. COUT2 COUT3 COUT1 RLIM COM VDD CFBVEE CFBVDD RFBVDD_TOP RFBVDD_BOT RFBVEE_TOP RFBVEE_BOT PG ENA VIN GNDP FBVDD FBVEE VEE Isolation Barrier GNDP GNDP GNDP VIN GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP VEE VEEA RLIM VDD VEE VDD VEE VEE VEE VEE VEE VEE VEE VEE VEE PG ENA CIN VIN Figure 9-1. Dual Adjustable Output Configuration UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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RFBVDD_TOP RFBVDD_BOT Figure 9-2. Single Adjustable Output Configuration

9.2.1 Design Requirements

Designing with the UCC14241-Q1 module is simple. First, choose single output or dual output. Determine the voltage for each output and then set the regulation through resistor dividers. The gate charge of the power device determines the amount of output decoupling capacitance needed at the gate driver input. Calculate the RLIM resistor value for regulating the (COM – VEE) voltage rail for a dual output. Finally, add the recommended input and output capacitors according to the procedure below.

9.2.2 Detailed Design Procedure

Place ceramic decoupling capacitors as close as possible to the device pins. For the input supply, place the capacitors between pins 6 to 7 (VIN) and pins 8 to 9 (GNDP). For the isolated output supply, (VDD – VEE), place the capacitors between pins 28 to 29 (VDD) and pins 30 to 31 (VEE). For the isolated output supply, (COM – VEE), place an RLIM resistor between the RLIM pin and the gate driver COM supply input. Also place decoupling capacitors at the gate driver supply pins (VDD and COM) and at gate driver supply pins (COM and VEE) with values according to the following component calculation sections. These locations are of particular importance to all the decoupling capacitors because the capacitors supply the transient current associated with the fast switching waveforms of the power drive circuits. Ensure the capacitor dielectric material is compatible with the target application temperature. www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: UCC14241-Q1

9.2.2.1 Capacitor Selection

The UCC14241-Q1 device creates an isolated output VDD-VEE as its main output. The device also creates a second output COM-VEE, using VDD-VEE as its power source. Because both outputs are isolated from the input, and sharing VEE as the common reference point, the UCC14241-Q1 outputs can be configured as dual-output two-positive, dual-output two-negative, or dual-output one-positive and one-negative. UCC14241-Q1 output can also be used as a single positive output or single negative output. When the module is configured as dual-output, one-positive output, one-negative output; it is very important to properly select the output capacitor ratios C OUT2 and C OUT3 to optimize the regulation and avoid causing an over-voltage or under-voltage fault. Table 9-1. Calculated Capacitor Values CAPACITOR VALUE (µF) NOTES CIN 20 + 0.1 Place two 10-μF and a 0.1-μF high-frequency decoupling capacitor in parallel close to VIN pins. A capacitance greater than 20 uF can be used to reduce the voltage ripple when the series impedance from the voltage source to the VIN pins is large. COUT1 10 + 0.1 Add a 10-μF and a 0.1-μF capacitor for high-frequency decoupling of (VDD – VEE). Place close to the VDD and VEE pins. A capacitance greater than 10 uF can be used to reduce the output voltage ripple. COUT2 See below Bulk charge, decoupling output capacitors are required at the gate driver pins. The COUT2 and COUT3 capacitance ratio is important to optimize the dual output voltage divider accuracy during charge or discharge switching cycles.COUT3 See below The selection of C OUT2 and COUT3 is based on the gate charge requirement for the gate driver load, the charge balancing during the start-up, and the expected maximum current loading. During the startup, the ratio between C OUT2 and C OUT3 must be equal to the ratio between (COM −VEE) and (VDD−COM) and offset by the loading current from VDD-COM and COM-VEE, to allow both COM to VEE and VDD to VEE voltages reaches steady state at the same time, as shown in Equation 1. First calculate the C OUT2 value based on the Gate charge of the power device Q G_Total, whether IGBT or SiC power MOSFET, and the percent of voltage droop wanted during the turn-on of the gate with respect to the positive gate voltage applied, VDD to COM. where C OU T 2 = Q G _ To tal Pe rc en t _ C dr o op 100 × V VDD − C OM (1)

• QG_Total is the total gate charge of the power switch UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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Then calculate the C OUT3 value based on the output voltage ratios, the load current expected, and the variation of the output capacitors. C OU T 3 = C OU T 2 × V VDD − C OM × I M A X _ POW ER − I CO M − V EE V C OM − VE E × I M A X _ POW ER − I V DD − C OM (2) where the load I VDD-COM and I COM-VEE are the load currents respectively, and the I MAX_POWER is the SOA Maximum Power (PMAX_SOA) at 25oC ambient temperature divided by the VVDD-VEE output voltage. I VD D − CO M = I Q _ Dr i v er _ VD D − C OM + I Ot ℎ er _ l o ad _ V DD − C OM (3) I C OM − V EE = I Q _ Dr i v er _ C OM − VE E + I O t ℎ er _ l o ad _ C OM − VE E (4) where

• I(VDD-COM) is the total current from VDD to COM, excluding average gate drive current.
• I(COM-VEE) is the total current from COM to VEE, excluding average gate drive current.
• IQ_DRIVER_VDD-COM is the maximum quiescent current of the gate driver from (VDD – COM), and any current pulled from VDD by external logic must be included.
• IQ_DRIVER_COM-VEE is the maximum quiescent current of the gate driver from (COM – VEE),
• IOther_load_VDD-COM is the maximum current pulled from VDD to COM by external logic.
• IOther_load_COM-VEE is the maximum current pulled from COM to VEE by external logic. and I POW ER = P M A X V V DD − VE E (5) The approximate PMAX value can be extracted from the provided SOA curves at the 25oC ambient temperature. Calculate C OUT3 using worst case capacitor values based on expected variation, C OUT2_maximum. This action makes sure the capacitor ratio tends to push the COM-VEE voltage to a slightly lower value than the target regulation value during start up. Note COUT2 and COUT3 are the total capacitance on the VDD and VEE outputs. They include the capacitors from both the isolated bias supply and the gate driver circuit. The sizes of C OUT2 and C OUT3 are determined by the gate driver load gate charge and ripple voltage requirement. COUT1 can then be used to reduce the total ripple voltage and to soften the start-up time. Please also be noted that the ceramic capacitors lose their capacitance when voltage is applied. The design needs to consider the reduced capacitance due to the DC bias effect. www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: UCC14241-Q1

9.2.2.2 RLIM Resistor Selection

The UCC14241-Q1 device creates an isolated output VDD-VEE as its main output. It also creates a second output COM-VEE, using VDD-VEE as its power source. Because both outputs are isolated from the input, and sharing VEE as the common reference point, the UCC14241-Q1 outputs can be configured as dual-output two-positive, dual-output two-negative, or dual-output one-positive and one-negative, as shown in Figure 9-3. VDD VEE RLIM COM VOUT1 VOUT2 VIN GNDP VDD VEE RLIM COM VOUT1 VOUT2 VIN GNDP (a) Dual-output, two-positive (b) Dual-output, two-negative VDD VEE RLIM COM VOUT1 VOUT2 VIN GNDP (c) Dual-output, one-positive, one-negative Figure 9-3. Dual output configurations When the module is configured as dual-positive or dual-negative outputs, the RLIM resistor is a true current limiting resistor. Set up the RLIM resistor value as the maximum load current needed for V COM-VEE, using Equation 6. IVOUT2_max is the maximum load current for VCOM-VEE output. R L I M = V C OM − V EE I VD D − COM _ m ax − R L I M _ INT (6) RLIM_INT is the internal switch resistance value of 30 Ω typical. For isolated gate driver applications, one positive and one negative outputs are needed. In this case, VDD-VEE is the total output voltage, and the middle point becomes the reference point. Because the total voltage between VDD and VEE is always regulated through the FBVDD feedback, the RLIM pin only must regulate the middle point voltage so that it can give the correct positive and negative voltages. The RLIM control is achieved through FBVEE pin as described in COM-VEE Voltage Regulation. Based on Capacitor Selection , when selecting the output capacitor ratio proportional to the voltage ratio, the capacitors form a voltage divider. The middle point voltage must naturally give the correct positive and negative voltages. At the same time, for the gate driver circuit, the gate charge pulled out from the positive rail capacitor during turn-on is fed back to the negative rail capacitor during turn-off, the two output rail load must always be balanced. However, due to the gate driver circuit quiescent current unbalancing, and the two-rail capacitance tolerances, the middle point voltage can move away with time. The RLIM pin provides an opposite current to keep the middle point voltage at the correct level. As illustrated in Figure 9-4 (a), without considering the gate charge, the gate driver circuit quiescent current loads the positive rail and negative rail differently. The net current shows up as a DC offset current to the middle point. As illustrated in Figure 9-4 (b), every time the gate driver circuit turns-on the main power switch, it pulls the charge out of the positive and negative rail output capacitors. When the module power stage provides energy to the secondary side, refreshing those capacitors, the same charge is fed into both capacitors. If the capacitor values are perfect, the voltage rise in the capacitors will be proportional. The positive and negative voltages UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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would not change. However, due to the capacitor tolerances, the capacitor values are not perfectly matched. The voltages will rise at different ratios with the smaller capacitor rising faster. Over time, the middle point voltage, COM, would pull to a different value. A load across one of the capacitors will pull towards a voltage imbalance. The RLIM function counteract the voltage imbalance and bring the COM voltage back into regulation. VDD VEE RLIM COM VIN GNDP ISO Driver VDD VEE COM Iq_VDD Iq_VEE Iq_off Iq_off=Iq_VDD−Iq_VEE VDD VEE RLIM COM VIN GNDP ISO Driver VDD VEE COM OUT COM Q Q COUT2 COUT3 VDD VEE VDD=Q/COUT2 VEE=Q/COUT3 VDD/ VEE=COUT3/COUT2 (a) Load current unbalancing (b) Capacitance unbalancing Figure 9-4. Source of voltage unbalancing www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: UCC14241-Q1

Considering these two effects, the RLIM must provide enough current to compensate this offset current. The RLIM must be low enough to provide enough current, but not too low otherwise the middle point voltage is corrected at each turn on and turn off edge of the gate driver and excessive power loss is generated. The RLIM resistor chosen can provide enough current for the load using the following equations, whichever has lower RLIM value. Equation 7 shows source current due to capacitor variation and gate driver quiescent current (IQ). Equation 8 shows sink current due to capacitor variation and IQ. R LIM _ M AX V V DD − C OM C OUT3 × 1 − ∆ C OUT3 C OUT2 × 1 − ∆ C OUT2 + C OUT3 × 1 − ∆ C OUT3 − C O UT3 C O UT 2 + C OUT3 × Q G_Total × f SW + I COM − VEE − I VDD − COM − R L I M _ INT (7) R LIM _ M AX V C OM − VE E C OUT2 × 1 − ∆ C OUT2 C OUT2 × 1 − ∆ C OUT2 + C OUT3 × 1 − ∆ C OUT3 − C O UT2 C O UT 2 + C OUT3 × Q G_Total × f SW + I COM − VEE − I VDD − COM − R LIM _ INT (8) Select RLIM value to be the lowest of either 1) the RLIM needed for capacitor imbalance and the load, or 2) the RLIM needed to respond to a 10% overshoot of VCOM-VEE within 1.5 ms with the given load current. where R LI M _ M A X _ f or _ ov er s ℎ o o t = V C OM − VE E C O U T 3_ m ax × 0 . 10 × V CO M − V EE 1 . 5 ms + I VD D − CO M − I CO M − V EE − R L I M _ INT (9)

• QG_Total is the total gate charge of power switch.
• fSW is the switching frequency of gate drive load. RLIM value determines response time of (COM – VEE) regulation. Too low an R LIM value can cause oscillation and can overload (VDD – VEE). Too high an R LIM value can give offset errors, due to slow response. If R LIM is greater than above calculations, then there is not enough current available to replenish the charge to the output capacitors, causing a charge imbalance where the voltage is not able to maintain regulation, and eventually exceeds the OVP2 or UVP2 FAULT thresholds and shutting down the device for protection. Choose R LIM value to be 10% less than the smaller value of the two calculated results. UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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9.3 System Examples

The UCC14241-Q1 module is designed to allow a microcontroller host to enable it with the ENA pin for proper system sequencing. The /PG output also allows the host to monitor the status of the module. The /PG pin goes low when there are no faults and the output voltage is within ±10% of the set target output voltage. The output voltage is meant to power a gate driver for either IGBT or SiC FET power device. The host can start sending PWM control to the gate driver after the /PG pin goes low to ensure proper sequencing. Shown below is the system diagram for the dual-output configuration and a system diagram for the single output configuration. ISOLATION BARRIOR VEE VDD VIN GNDP CIN VIN ENA /PG VDD 400- 800V From Battery 5V/3.3V PG EN VCC Open - Drain To Motor Buck RLIM EMITTER/ SOURCE VISO1 = 25V VEE EMITTER/ SOURCE RLIM COUT2 COUT3 COUT1 PWM Control Microcontroller ISOLATION BARRIOR VCC VDD GNDP VEE GATEPWM Similar Isolated DC - DC + Isolated Gate Driver Block as Above VCC /PG_BIAS ON_BIAS 5V/3.3V COM Figure 9-5. Dual Output System Configuration ISOLATION BARRIOR VEE VDD VIN GNDP CIN VIN ENA /PG VDD 400- 800V From Battery 5V/3.3V PG EN VCC Open - Drain To Motor Buck RLIM EMITTER / SOURCE VISO1 = 25V VEE RLIM COUT PWM Control Microcontroller ISOLATION BARRIOR VCC VDD GNDP VEE GATEPWM Similar Isolated DC - DC + Isolated Gate Driver Block as Above VCC /PG_BIAS ON_BIAS 5V/3.3V GATE EMITTER / SOURCE Figure 9-6. Single Output System Configuration www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: UCC14241-Q1

9.4 Power Supply Recommendations

The recommended input supply voltage (V VIN) for UCC14241-Q1 is between 21 V and 27 V. To help ensure reliable operation, adequate decoupling capacitors must be located as close to supply pins as possible. Local bypass capacitors must be placed between the VIN and GNDP pins at the input; between VDD and VEE at the isolated output supply; and COM and VEE at the lower voltage output supply. TI recommends low ESR, ceramic surface mount capacitors. TI further suggests placing two such capacitors: one with a value of 2.2 μF for supply bypassing and an additional 0.1- μF capacitor in parallel for high frequency filtering. The input supply must have an appropriate current rating to support output load required by the end application.

9.5 Layout

9.5.1 Layout Guidelines

The UCC14241-Q1 integrated isolated power solution simplifies system design and reduces board area usage. Follow these guidelines for proper PCB layout to achieve optimum performance.

• Place decoupling capacitors as close as possible to the device pins. For the input supply, place the capacitors between pin 7 (power VIN) and pins 8–18 (power GNDP). For the isolated output supply, place the capacitors between pin 28, 29 (VDD) and pins 19–25, 30–31, 35–36 (VEE). This location is of particular importance to the input decoupling capacitor because this capacitor supplies the transient current associated with the fast switching waveforms of the power drive circuits. The capacitors between pin 6 (analog VIN) and pins 1, 2, and 5 (analog GNDP) are optional and recommended.
• Because the device does not have a thermal pad for heat-sinking, the device dissipates heat through the respective GND pins. Ensure that enough copper (preferably a connection to the ground plane) is present on GNDP and VEE pins for best heat-sinking.
• If space and layer count allow, TI recommends to connect the VIN, GNDP, VDD, and VEE pins to internal ground or power planes through multiple vias. Alternatively, make the traces that are connected to these pins as wide as possible to minimize losses.
• Minimize capacitive coupling between the RLIM pin and the FBVEE pin by separating the traces while routing, and if possible use a via near the FBVEE pin to route the feedback connection through a different layer.
• A minimum of four layers is recommended to accomplish a good thermal PCB design. Inner layers can be used to create a high-frequency bypass capacitor between GNDP and VEE, which in turn mitigates radiated emissions.
• Pay close attention to the spacing between primary ground plane (GNDP) and secondary ground plane (VEE) on the outer layers of the PCB. The effective creepage and clearance of the system is reduced if the two ground planes have a lower spacing than that of the UCC14241-Q1 package.
• To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or copper below the UCC14241-Q1 module.

9.5.2 Layout Example

The layout example shown in the following figures is from the evaluation board UCC14241-Q1EVM, UCC14240EVM-052, and based on the Figure 9-1 design. UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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Figure 9-9. UCC14241-Q1EVM, Signal Layer 3 (Same as Layer 2) Figure 9-10. UCC14241-Q1EVM, PCB Bottom Layer, Assembly (Mirrored View) UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs Requiring Single, Positive or Dual, Positive/Negative Bias Power user's guide
• Texas Instruments, Isolation Glossary

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: UCC14241-Q1

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. UCC14241-Q1 SLUSF09 – APRIL 2023 www.ti.com ADVANCE INFORMATION

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12 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant www.ti.com UCC14241-Q1 SLUSF09 – APRIL 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: UCC14241-Q1

www.ti.com 13-Apr-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PUCC14241QDWNQ1 ACTIVE SO-MOD DWN 36 37 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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