PUC24612-1DBVR

UCC24612 TI1 | Alldatasheet

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ADVANCE□INFORMATION Copyright © 2017, Texas Instruments Incorporated VDD VGVS VD REG Vout Copyright © 2017, Texas Instruments Incorporated VDD VG VSVD REG Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. UCC24612 SLUSCM5 –AUGUST 2017 UCC24612High-FrequencyMulti-ModeSynchronousRectifierController

1 Features

1• Secondary-Side Controller Optimized for up to 24- V Systems

Supporting Active Clamp Fyback, QR, DCM, CCM Flyback and LLC Resonant converter
High Side or Low Side Synchronous Rectifier
Up to 1-MHz Operating Frequency
MOSFET VDS Sensing
4-A Sink, 1-A Source Gate-Drive Capability
Proportion drive for fast turn off at CCM operation
CCM cycle limit pre-turn off for better CCM support
Adaptive minimum off time for better noise immunity
Automatic Light-Load Management
Synchronous Wake-Up From Sleep and Light- Load Modes
16-ns Typical Turnoff Propagation Delay
9.5-V Gate Drive Clamp Levels for Minimum Driving Loss

2 Applications

AC-to-DC Adapters
Server, Telecom Auxiliary Power Supply
Telecom DC-to-DC bricks

3 Description

This UCC24612 multi-mode synchronous rectifier controller is a high-performance controller and driver for standard and logic-level N-channel MOSFET power devices used for secondary-side synchronous rectification in high current and high efficiency designs. The combination of controller and MOSFET emulates a near-ideal diode rectifier. This solution not only directly reduces power dissipation of the rectifier but also indirectly reduces primary-side losses as well, due to compounding of efficiency gains. Using drain-to-source voltage sensing, the UCC24612 is ideal for Active Clamp Flyback, QR/DCM/CCM Flyback and LLC-resonant power supplies but can also be used with other power architectures. The proportion drive together with the CCM cycle limit pre-turn off design make part operate more robust in CCM operations. The wide VDD voltage range allow UCC24612 to support up to 24-V applications. The 9.5-V gate driver clamping level allows the minimum driving loss. UCC24612 uses adaptive off time control to improve the noise immunity. This greatly simplifies the design effort and allows the controller be used in wide application and frequency ranges. This device is available with SOT23-5 package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) UCC24612 SOT23 (5) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Flyback with High-Side SR Flyback with Low-Side SR

12 Mechanical, Packaging, and Orderable

4 Revision History

August 2017 * Advance Information release.

5 Pin Configuration and Functions

avoid the VD pin trace sharing the power path to minimize the impacts of parasitic inductor. connected with a large N-channel power MOSFET. Table 1. Device Comparison

ADVANCE□INFORMATION UCC24612 SLUSCM5 –AUGUST 2017 www.ti.com Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input voltages more negative than indicated may exist on any listed pin without excess stress or damage to the device if the pin’s input current magnitude is limited to less than -10mA. (3) In normal use, VG is connected to the gate of a power MOSFET through a small resistor. When used this way, VG current is limited by the UCC24612 and no absolute maximum output current considerations are required. The series resistor shall be selected to minimize overshoot and ringing due to series inductance of the VG output and power-MOSFET gate-drive loop. Continuous VG current is subject to the maximum operating junction temperature limitation.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Input voltage (2) VDD –0.3 30 V VD –0.7 230 V VG –0.3 VREG V VD for IVD ≤ –10 mA –1.0 230 V REG 12 V Output current, peak VG(3) pulsed, tPULSE ≤ 4 ms, duty cycle ≤ 1% ±4 A TJ Operating junction temperature –40 125 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins, except pin 5 (1) ±2,000 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, pin 5 (1) ±1,500 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 V

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VVDD VDD input voltage 4 28 V CVDD VDD bypass capacitor 1 µF CREG REG bypass capacitor 1.5 2.2 µF TJ Junction temperature –40 125 °C fS Switching frequency 1000 kHz (1) For more information about traditional and new thermal metrics, see the the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1) UCC24612 UNITDBV (SOT23-5)

5 PINs

RθJA Junction-to-ambient thermal resistance 206.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 97.6 °C/W RθJB Junction-to-board thermal resistance 44.2 °C/W ψJT Junction-to-top characterization parameter 9.9 °C/W ψJB Junction-to-board characterization parameter 43.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

6.5 Electrical Characteristics

At VDD = 12 VDC, CVG = 0 pF, CREG = 2.2 µF, −40°C ≤ TJ = TA ≤ +125°C, all voltages are with respect to VS, and currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical values are at TJ = +25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BIAS SUPPLY IVDDSTART VDD current, REG undervoltage VDD = 4 V, VD = 0 V 120 μA IVDDRUN VDD current, run VDD = 12 V 0.95 mA VDD = 5 V 0.9 mA IVDDSTBY VDD current, standby mode VDD = 12 V 390 μA VDD = 5 V 320 μA UNDERVOLTAGE LOCKOUT (UVLO) VREGON REG turnon threshold Turnon detected by 4.5 V VREGOFF REG turnoff threshold Turnoff detected by 4 V VREGHYST UVLO hysteresis VREGHYST = VREGON – VREGOFF 0.5 V MOSFET VOLTAGE SENSING VTHVGON GATE turnon threshold VD falling -226 mV VTHVGOFF GATE turnoff threshold VD rising -10 mV VTHREGLO Low level regulation threshold -50 mV VTHREGCCM High level regulation threshold for CCM -150 mV VTHARM Gate re-arming threshold 0.5 V IVDBIAS VD pin bias current VD = –100 mV -0.9 µA GATE DRIVER RSOURCE VG pullup resistance IVG = –20 mA, VDD = 12 V 5.7 Ω RSINK VG pulldown resistance IVG = 100 mA, VDD = 12 V 0.62 Ω VGH VG clamp level 9.4 V VGL VG output low voltage IVG = 100 mA, VDD = 12 V 60 mV VOLGUV VG output low voltage in UVLO IVG = 25 mA, VDD = 4 V 0.7 V IVGPU Gate driver maximum source current 1 A IVGPD Gate driver maximum sink current 4 A REG SUPPLY VREG REG pin regulation level VDD = 12 V 9.42 V VREGLG Load regulation on REG VDD = 12 V, ILOAD_REG= 10 mA to 0 mA 0.015 V VREGDO REG drop out on passthrough mode VDD = 5 V, ILOAD_REG= 10 mA 0.28 V IREGSC REG short circuit current VDD = 12 V, VREG = 0 V 5.2 mA IREGLIM REG current limit VDD = 12 V, VREG = 8V 42 mA

6.6 Timing Requirements

At VDD = 12 VDC, CVG = 0 pF, CREG = 2.2 µF, −40°C ≤ TJ = TA ≤ +125°C, all voltages are with respect to VS, and currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical values are at TJ = +25°C. TEST CONDITIONS MIN NOM MAX UNIT MOSFET VOLTAGE SENSING tdVGON Gate turn on propagation delay -1 version VD moves from 4.7 V to –0.3 V in 5 ns 70 ns Gate turn on propagation delay -2 verison VD moves from 4.7 V to –0.3 V in 5 ns 160 tdVGOFF Gate turn off propagation delay VD moves from -0.3 V to 4.7 V in 5 ns 16 ns MINIMUM ON-TIME tON(min) Minimum SR conduction time UCC24612 -1 383 ns UCC24612 -2 550 ns Adaptive MINIMUM OFF-TIME tOFFABSMIN Absolute minimum SR off blanking time 350 ns GATE DRIVER tr_VG VG rise time 10% to 90%, VDD = 12 V, CVG = 6.8 nF 35 ns tf_VG VG fall time, 90% to 10%, VDD = 12 V, CVG = 6.8 nF 18 ns LIGHTLOAD / STANDBY tSTBY_DET Standby mode detection time 4.4 ms fSLEEP Average frequency entering standby mode 11 kHz fWAKE Average frequency coming out of standby mode 14 kHz PROTECTION TTSD Thermal shut down threshold 165 ºC THYS Thermal shut down recovery hysteresis 15 ºC

6.7 Typical Characteristics

Figure 1. UVLO Threshold Voltage vs. Temperature Figure 2. Bias Supply Current vs. Temperature Figure 3. SR Turn Off Threshold Voltages vs. Temperature Figure 4. SR Turn On Threshold Voltage vs. Temperature

ADVANCE□INFORMATION Copyright © 2017, Texas Instruments Incorporated REGVDD VD START TSD VG VS Adaptive TOFF & DCM ring rejection (-220mV) S Q QR (-10mV) Minimum TON (-50mV) Prop-DRV threshold 9.5-V Linear Regulator REG UVLO POWER & FAULT MANGEMENT PROPORTION GATE DRIVE CONTROL GATE DRIVER UCC24612 www.ti.com SLUSCM5 –AUGUST 2017 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The UCC24612 synchronous rectifier (SR) controller uses drain-to-source voltage sensing to determine the SR MOSFET conduction interval. The SR MOSFET is turned on when VDS exceeds –200 mV, and is turned off when VDS diminishes to –10 mV. The SR conduction voltage drop is continuously monitored and regulated to minimize the conduction loss while allowing SR to pre-turn off to operate in CCM mode. The extremely fast turn off comparator and driving circuit allows the fast turn off of SR MOSFET, even in CCM condition. Fixed 350-ns minimum on time allows the controller effectively driving the SR operating up to 1-MHz switching frequency. The adaptive minimum off time control simplifies the design, making the controller suitable to be used in wide applications and switching frequencies, while immune to the noises caused by the parasitic ringing. To minimize the standby power, automatic light-load mode disables the GATE pulses when the average switching frequency of the converter becomes lower than 12 kHz. When the load increases such that the average switching frequency becomes above 15 kHz, the controller resumes normal SR operation. The wide VDD range and gate driver clamp makes the controller ideal for wide output voltage range such as USB-PD applications.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Power Management

achieve fast driving speed, low driving loss and higher noise immunity. In low side configuration, as shown in Figure 5, the UCC24612 is powered from the output voltage directly. Figure 5. UCC24612 Used in Low Side SR Configuration regulator. A 2.2 µF bypass capacitor is recommended. mode until the REG pin voltage drops below UVLO turn off level.

7.3.2 Synchronous Rectifier Control

Figure 8. GATE Output With Respect to VDS depicted in Figure 8 can be observed during SR operation in a simple Flyback circuit. driver design should avoid long turn on delay.

ADVANCE□INFORMATION UCC24612 www.ti.com SLUSCM5 –AUGUST 2017 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Feature Description (continued) UCC24612, two different versions are created. UCC24612-1, the SR driver with inherent short turn on propagation delay (70 ns typical) can be used with the converter needs shorter delay, such as standard Flyback converter or Active Clamp Flyback covnerter using GaN MOSFET as main switches. UCC24612-2, the SR driver with added 150-ns turn on delay, to further ignore the leading edge spike, can be used with Active Clamp Flyback with Si based super junction MOSFET as the main switch or the LLC covnerters. When SR body diode is conducting, VD pin becomes negative to VS pin, by a body diode drop. The connection of VD and VS pin should be directly to the SR MOSFET pins, to avoid any overlapping of sensing paths to the power path, minimizing the negative voltage and ringing caused by the parasitic inductors. Low package inductance MOSFETs are preferred to minimize this effect. Besides the simple comparator, UCC24612 also includes a proportional driver for the SR. For normal SR controller, the SR MOSFET is turn on and off by the full driving voltage. This way, the conduction loss can be minimized. However, this method has couple major drawbacks. The turn off threshold is a fixed value, often, to prevent shoot through, the SR is turned off before current reaches zero. This causes the SR body diode conduction and actually increases the conduction loss. Another issue is associated with the converter operate in continuous conduction mode (CCM) condition. When Flyback converter operates in CCM, the SR current slope (di/dt) at turn off could be as high as 150A/µs. This high current slope could cause large negative current with long propagation delays. Furthermore, the delay caused by discharging SR MOSFET gate voltage to full voltage to its threshold level introduces another delay, this further increases the negative current. Instead of always turning off the SR MOSFET in full gate driver voltage, UCC24612 reduces its gate driver voltage when the voltage drop across SR drain to source becoming more than -50mV (current approaching zero). During this time, UCC24612 reduces its gate drive voltage and tries to regulate SR voltage drop to -50mV. This brings two major benefits to the application: a) Preventing the SR premature turning off, which causes extra loss associated with body diode conduction and reverse recovery b) Shorter turn off delay since the SR MOSFET gate is already reduced close to threshold level and SR can be turned off with virtually no delay from moving gate voltage. In certain applications, such as telecom DC/DC bricks, due to the lower input and output voltage, the converter operate in deep CCM mode (low inductor ripple) gives the benefit of less conduction loss. In these applications, the SR turn off current is high and the SR MOFET voltage drop can still be less than the -50-mV threshold. UCC24612 increases -50-mV threshold to -150 mV to force the proportion drive activated and reducing the gate driver voltage for fast turn off. The time to increase the threshold is based on previous cycle SR conduction time. Because the regular proportion drive and the turn off mechanism are kept functional all the time, the UCC24612 can still provide correct SR control even the large SR conduction time change with two switching cycles. The forced proportion drive mechanism can be shown in Figure 9. In Figure 9, the turn on delay was ignored to simplify the illustration.

Figure 9. Forced Proportion Drive for Deep CCM Operation drive is always enabled on the current down slope and minimizes the impact to the conduction loss.

7.3.3 Adaptive Blanking Time

Figure 10. Parasitic Ringing Associated with DCM Operation

7.3.3.1 On Blanking Timer

Right after SR turn on, the SR is driven fully on. For some topologies, such as Flyback, the SR starts to conduct its maximum current. Due to the parasitic ringing, SR voltage drop might still trip the turn off threshold and prematurely turn off the SR. This is largely caused by the ringing current caused the voltage drop on the package inductor of the SR FET. The ringing voltage can be managed through appropriate snubbering and using low package inductance MOSFET. To further improve the noise immunity, UCC24612 blanks the turn off comparator with a fixed 350-ns minimum on time timer. The SR needs to conduct a minimum of 350 ns regardless its turn off comparator state. The minimum on time allows the UCC24612 used in up to 1 MHz switching frequency, while still maintain the good noise immunity.

7.3.3.2 Off Blanking Timer

When converter operate in discontinuous conduction mode (DCM), after SR turns off, there is large parasitic ringing caused by the inductor and the switch node capacitor. At first couple of ringing cycles, there is a good chance that the drain voltage resonant below the SR turn on threshold. SR could be false turned on at these instances and introduces extra loss and EMI noise. Due to different switching frequency and power level designs, this parasitic ringing frequency can vary quite a bit. Traditionally, the DCM ringing is blanked by a programmable off blanking timer. It is often called minimum off time. This allows the maximum flexibility of the circuit design and avoid the false triggering. However, there are couple limitations associated with the method. Firstly, the program pin can force the device using higher pin count package, this increases the overall cost and difficulty of layout. Secondly, the fixed off blanking timer might not work well for the entire line and load conditions. For example, for a quasi-resonant (QR) Flyback, in the light load mode, it enters DCM operation. In this case, the off blanking timer like to be long to avoid the DCM ringing causing SR false turning on. However, at high input voltage, when the converter operates in the QR mode, the primary side MOSFET conduction time is quite short, the long minimum off time might cut into the conduction time of the SR, introduce extra conduction loss. In UCC24612, instead of a fixed off blanking timer, adaptive off blanking timer is used to blank the parasitic ringing and avoid false turn on of the SR. The off blanking timer TOFFblankis determined by three values, the absolute minimum off banking time of 350 ns (tOFFABSMIN), the recorded DCM ring cycle time tDCM and previous cycle's SR off time tOFF. UCC24612 sets up the off blanking timer based on previous cycle's SR off time. By choose 70% of previous switching cycle's SR off time, the off blanking timer is maximized to prevent any false triggering. However, the off blanking timer minimum value is clamped by the 350-ns absolute minimum value and recorded DCM ringing cycle. After SR turn off, if the off blanking time is not sufficient, the SR could be turned on again by a DCM ring. Because of the DCM ring, SR's conduction time is limited by the minimum on time. By looking at the SR conduction time, UCC24612 is able to determine the conduction is a real SR conduction or false turn on triggered by the DCM ring. Once the false turn on is captured, the time duration between SR turn off and the SR false turn on is recorded as the DCM ring cycle. For the next switching cycle, the off blanking timer is clamped to 2.2 times of the recorded DCM ring cycle. This adaptive off blanking timer allows UCC24612 achieving the noise immunity without a dedicated program pin.

adaptive minimum off time schemes are illustrated in Figure 11. a good chance to cause shoot through the endanger the converter. The off blanking time also has a maximum value of 4.3 µs. Figure 11. Adaptive Off-Time Blanking

7.3.3.3 SR Turn ON Re-arm

The VG output may only turn on when the controller has been armed for the switching cycle. The controller is armed for each successive SR cycle only after TOFFBLANK expires after VD pin voltage rises 500 mV above VS pin.

7.3.4 Gate Voltage Clamping

With the wide VDD voltage range capability, UCC24612 clamps the gate driver voltage on a maximum level of 9.5 V to allow fast driving speed, low driving loss and compatible with different MOSFETs. The 9.5-V level is chosen to minimize the conduction loss for the non-logic level MOSFET. The gate driver voltage clamp is achieved through the regulated REG pin voltage. When VDD voltage above 9.5 V, the linear regulator regulates the REG pin voltage to be 9.5 V, which is also the power supply of the gate driver stage. This way, the MOSFET gate is well clamped at 9.5 V, regardless how high the VDD voltage is. When the VDD voltage is getting close to or below the programmed REG pin regulation voltage, UCC24612 can no long regulate the REG pin voltage. Instead, it enters a passthrough mode that the REG pin voltage follows the VDD pin voltage. During this time, the gate driver voltage is lower than its programmed value but still provides the SR driving capability. The UCC24612 is disabled once the REG pin voltage drops below its UVLO level.

7.3.5 Standby Mode

With the more stringent industrial standard such as Department of Energy (DoE) level VI, the external power supplies are expected to maintain very low standby power at no load condition. It is essential for the SR controller entering the low power standby mode to help save the standby power. During standby mode, the power converter loss allocation is quite different comparing with heavy load. At heavier load, both conduction loss and switching loss are quite high. However, at light load, the conduction loss becomes insignificant and switching loss dominates the loss. To help improve the standby power, modern power supply controllers often enters burst mode to save the switching loss. Furthermore, in each burst switching cycle, the energy delivered is maximized to minimize the number of switching cycle needed and further reduces the switching loss. Traditionally, the SR controller monitors the SR conduction time to distinguish the normal operation mode or the standby mode. This criterion is no longer suitable for the modern power supply controller designed for delivering minimum standby power. Instead, in UCC24612, a frequency based standby mode detection is used. UCC24612 continuously monitors the average switching frequency of the SR. Once average switching frequency of SR drops below 12 kHz, the UCC24612 enters the standby mode and reduces its current consumption to ISTB. During standby mode, the SR switching cycle is continuously monitored. Once the average switching frequency is more than 16 kHz within 4 ms, the SR operation is enabled again. UCC24612 ignores the first SR switching cycle after coming out of standby mode to make sure the SR isn't turned on in the middle of the switching cycle.

7.4 Device Functional Modes

7.4.1 UVLO Mode

UCC24612 uses REG pin voltage to detect UVLO instead of VDD pin voltage. When the REG voltage to the device has not yet reached the VTH_ON threshold, or has fallen below the UVLO threshold VTH_OFF, the device operates in the low-power UVLO mode. In this mode, most internal functions are disabled and ICC current is typically much less than 100 µA. If the REG pin is above 2 V, there is active pull down from VG to VS to prevent SR turning on by noise. When the REG pin voltage is less than 2 V, there is a weak pull down from VG to VS and this also prevents the noise turning on SR MOSFET. The device exits UVLO mode when REG increases above the VTH_ON threshold.

7.4.2 Standby Mode

Standby mode is a low-power operating mode to help achieve low standby power for the entire power supply. UCC24612 detects the operation frequency of SR MOSFET and enters or exists the standby mode operation automatically. REG current reduces to ISTB level. During standby mode, majority of the SR control functions are disabled, except the switching frequency monitoring and the active pull down on the gate driver.

7.4.3 Run Mode

Run mode is the normal operating mode of the controller when not in UVLO mode, or standby mode. In this mode, REG current is higher because all internal control and timing functions are operating and the GATE output is driving the controlled MOSFET for synchronous rectification. REG current is the sum of IRUN plus the average current necessary to drive the load on the VG output. The VG voltage is automatically adjusted based on the SR MOSFET drain to source voltage.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

LLC resonant converter to improve the efficiency.

8.2 Typical Application

roughly 85 kHz. Please refer to the UCC28740 data sheet for further details. Figure 12. UCC24612 Typical Application Example

8.2.1 Design Requirements

Table 2. 60W DCM Flyback Design Requirements

8.2.2 Detailed Design Procedure

8.2.2.1 SR MOSFET Selection

UCC24612 can be paired with the appropriate MOSFET to replace the diode rectifier on the existing designs and demonstrate the conduction loss reduction. The SR MOSFET selection should consider the tradeoff between the cost and performance. Lower on state resistance gives lower conduction loss, while it hurts the efficiency at light load. Due to the implementation of proportional gate drive, the benefit of lower on state resistance gets diminishing return. It is recommended to keep the proportional gate drive to kick in less than 50% of the full load SR conduction time. The MOSFET breakdown voltage should be higher than the maximum voltage the SR MOSFET sees under maximum input voltage. In this EVM, a 150-V, 19-mΩ MOSFET was used to get a balance between the cost and performance

8.2.2.2 Bypass Capacitor Selection

UCC24612 needs sufficient external bypass capacitor to allow internal regulator operate correctly. Referring to the power supply recommendation section, a 2.2-µF 15-V ceramic capacitor was chosen as the bypass capacitor on REG pin. For the VDD pin, it is normally powered by output voltage and there are plenty of capacitor there. A 0.1-µF ceramic capacitor is still recommended to be placed close to the IC to provide high frequency current.

ADVANCE□INFORMATION %3 = 0.01 5 ×BOS × 43 = 0.01 5 × 85G*V × 47.3KDI N 497L( 43 = 1 3¨.OHG %O = 1 ¨3.8Q* 1.7J( N 47 KDI %O = 1 (2 ×è × BN)2 × .OHG = 1 UCC24612 SLUSCM5 –AUGUST 2017 www.ti.com Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

8.2.2.3 Snubber design

It is required for the user to setup snubber components C3 and R3 to get the best performance when using the UCC24612EVM. To setup these components will require knowing the flyback transformers secondary leakage inductance (Lslk) and measuring the secondary resonant ring frequency (fr) in circuit. It is recommended that the SR is not engaged while doing this. TP3 should be disconnected from the flyback converter to ensure FET Q1 is turned off while setting up the snubber. The secondary winding capacitance (Cs) then needs to be calculated based on the following equation. Please note for a transformer with a secondary winding leakage inductance of 3.8 uH and a ring frequency of 2 MHz, the parasitic capacitance would be 1.7 nF. (1) Based on the calculated Cs, Lslk and fr the snubber resistor R3 can be set to critically dampen the ringing on the secondary, which requires setting the Q of the circuit equal to 1. (2) Capacitor C3 is used to limit the time the snubber resistor is applied to the aux winding during the switching cycle. It is recommended to set the snubber capacitor C3 with the following equation based on the flyback converters switching frequency (fSW). For a flyback converter switching at 85 kHz in the example would require a C3 of roughly 497 pF. (3) Please note that the calculations for R3 and C3 are just starting points and should be adjusted based on individual preference, performance and efficiency requirements.

8.2.2.4 High-Side Operation

To use the UCC24612EVM to replace a high-side rectifier requires removing jumper JP1 and connecting the EVM as shown in Figure 13. Please note that the EVM comes with a default filtering resistor (R2) of 20 kΩ. However, resistor R2 needs to be adjusted based on your individual application.

Figure 13. UCC24612-1EVM Used in High-Side Rectifier Application EVM ( 20 kΩ) and set R2 to 0 to 10 ohms and remove 27-V Zener diode D1 from the board. maximum switching frequency. In this example the converter's maximum switching frequency (fSW) was 85 kHz. Please note the switching frequency will vary based on design and preference.

8.2.3 Application Curves

roughly 85 kHz. Please refer to the UCC28740 data sheet for further details.

8.2.3.1 Steady State Testing Low Side

Snubber Components, R2 = 1.02 kΩ, R3 = 51.1Ω , C3 = 470 pF
CH1 = VG, CH2 = Q1 drain (TP2), CH3 = VOUT Voltage Ripple (TP3)

Figure 14. 85-VAC, 0-A Load Figure 15. 85-VAC, 3-A Load Figure 16. 265-VAC, 0-A Load Figure 17. 265-VAC, 3-A Load

8.2.3.2 Steady State Testing High Side

Snubber Components, R2 = 1.02 kΩ, R3 = 51.1 Ω , C3 = 470 pF
CH1 = VG, CH2 = Q1 drain (TP2), CH3 = VOUT Voltage Ripple (TP3)

Figure 18. 85-VAC, 0-A Load Figure 19. 85-VAC, 3-A Load Figure 20. 265-VAC. 0-A Load Figure 21. 265-VAC, 3-A Load

9 Power Supply Recommendations

have better bypassing and better gate driver performance. It is important to keep the sufficient bypass cap on REG pin. A minimum of 1-µF bypass capacitor is required. voltage is between 5 V to 24 V. according to the trade off between cost, and performance. limited by the transformer construction and cost constrains. applications. However, this provides a simple and low cost solution. source, this provides a simple solution without changing the transformer design. Figure 22. Power UCC24612 Using Auxiliary Winding

10 Layout

10.1 Layout Guidelines

especially when using single-sided PCBs.

Place a ceramic MLCC bypass capacitor as close as possible to VCC and GND.
Avoid connecting VD and VS sense points at locations where stray inductance is added to the SR MOSFET package inductance, as this will tend to turn off the SR prematurely.
Run a track from the VD pin directly to the MOSFET drain pad to avoid sensing voltage across the stray inductance in the SR drain current path.
Run a track from the VS pin directly to the MOSFET source pad to avoid sensing voltage across the stray inductance in the SR source current path. Because this trace shares both the gate driver path and the MOSFET voltage sensing path, it is recommended to make this trace as short as possible.
Run parallel tracks from GATE and GND to the SR MOSFET. Include a series gate resistance to dampen ringing.

10.2 Layout Example

Figure 25. PCB Layout for Driving an SR with SO-8 Package

11 Device and Documentation Support

11.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.2 Trademarks

E2E is a trademark of Texas Instruments.

11.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

ADVANCE□INFORMATION UCC24612 SLUSCM5 –AUGUST 2017 www.ti.com

(1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. space (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) space (3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. space (4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. space (5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device space (6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

12.1 Package Option Addendum

12.1.1 Packaging Information

Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish(3) MSL Peak Temp (4) Op Temp (°C) Device Marking(5)(6) UCC24612DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 U650 UCC24612DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 U650

ADVANCE□INFORMATION Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed UCC24612 www.ti.com SLUSCM5 –AUGUST 2017 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

12.1.2 Tape and Reel Information

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant

ADVANCE□INFORMATION TAPE AND REEL BOX DIMENSIONS Width (mm) W L H UCC24612 SLUSCM5 –AUGUST 2017 www.ti.com Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC24612DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 UCC24612DBVT SOT-23 DBV 5 250 180.0 180.0 18.0

www.ti.com 9-Sep-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PUC24612-1DBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PUC24612-2DBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 UCC24612-1DBVR PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 UCC24612-1DBVT PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125 UCC24612-2DBVR PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 UCC24612-2DBVT PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 9-Sep-2017 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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Summary

High-Frequency Multi-Mode Synchronous Rectifier Controller

Description