Power Management

PUA78L033AIPK

Texas Instruments

UA78L Series Positive-Voltage Linear Regulators REVISED APRIL 2023

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UA78L Series Positive-Voltage Linear Regulators

1 Features

Input voltage range (VI): – 4.75 V to 35 V (for legacy chip) – 4.75 V to 45 V (for new chip)
Output voltage range (VO): – 2.6 V to 15 V (for legacy chip) – 3.3 V to 15 V (for new chip)
Output current: Up to 100 mA
Quiescent current IQ: 3.8 mA
Built-in short-circuit current limiting and thermal protection
Stable without any external component
Supported temperature range: – Legacy chip C and AC versions: 0°C to +125°C – Legacy chip AI version: –40°C to +125°C – New chip: –40°C to +125°C
Packages: – 8-pin, 4.9-mm × 3.91-mm SOIC – 3-pin, 4.3-mm × 4.3-mm TO-92 – 3-pin, 4.5-mm × 2.5-mm SOT-89
M3-suffix devices are Advance Information devices

2 Applications

Motor drives
Appliances
Building automation
Flow transmitters
Factory automation and control

3 Description

The UA78L series of fixed-voltage linear regulators is designed for a wide range of applications. The UA78L series can be used for on-card regulation to eliminate the noise and distribution problems associated with single-point regulation. The UA78L can also be used with power-pass elements to make high-current voltage regulators. The UA78L series regulators can deliver up to 100 mA of output current. Additionally, the UA78L does not need an external capacitor for stable operation across the load current range. The internal current-limiting and thermal-shutdown features of these regulators help protect the device from overload. For the legacy chip, the UA78L00C and UA78L00AC series are characterized for the junction temperature range of 0°C to +125°C and the UA78L05AI device is characterized for the operating junction temperature range of –40°C to +125°C. For the new chip, the UA78L series is characterized for the junction temperature range of –40°C to +125°C.

Package Information

PART NUMBER PACKAGE(1) BODY SIZE (NOM) UA78L D (SOIC, 8) 4.90 mm × 3.91 mm LP (TO-92, 3) 4.30 mm × 4.30 mm PK (SOT-89, 3) 4.50 mm × 2.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. UA78L00 INPUT OUTPUT COMMON0.33 μF 0.1 μF GND VI VO Simplified Schematic UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

6.5 Electrical Characteristics: UA78L02 (for legacy

6.6 Electrical Characteristics: UA78L033 (for new

6.7 Electrical Characteristics: UA78L05 (for both

6.8 Electrical Characteristics: UA78L12 (for both

6.9 Electrical Characteristics: UA78L06 (for legacy

6.10 Electrical Characteristics: UA78L08 (for legacy

6.11 Electrical Characteristics: UA78L09 (for legacy

6.12 Electrical Characteristics: UA78L10 (for legacy

6.13 Electrical Characteristics: UA78L15 (for both

10 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision V (November 2016) to Revision W (April 2023) Page

Added plots for new chip, reordered plots for legacy chip, and changed condition statement in Typical
Changed Device Functional Modes section: added Device Functional Mode Comparison table, deleted Fixed- Changes from Revision U (January 2014) to Revision V (November 2016) Page
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

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5 Pin Configuration and Functions

Figure 5-1. D Package, 8-Pin SOIC (Top View) INPUT COMMON OUTPUT Figure 5-2. LP Package, 3-Pin TO-92 (Top View) INPUT COMMON OUTPUT Figure 5-3. PK Package, 3-Pin SOT-89 (Top View) PIN TYPE DESCRIPTION NAME SOIC TO-92 SOT-89 COMMON 2, 3, 6, 7 2 2 — Ground INPUT 8 3 3 I Input pin. Use the recommended capacitor value as listed in the Recommended Operating Conditions table. Place the input capacitor as close to the IN and GND pins of the device as possible. OUTPUT 1 1 1 O Output pin. Use the recommended capacitor value as listed in the Recommended Operating Conditions table. Place the output capacitor as close to the OUT and GND pins of the device as possible. NC 4, 5 — — — No connect pin. This pin is not connected internally. Connect this pin to ground for best thermal performance or leave floating. www.ti.com UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: UA78L

6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)((1)) MIN MAX UNIT Input voltage, VI (for legacy chip) UA78L02AC, UA78L05C, UA78L09C, and UA78L10AC 30 VUA78L12C, UA78L12AC, UA78L15C, and UA78L15AC 35 Input voltage, VI (for new chip) UA78L00AC, UA78L00C and UA78L00AI 45 Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 1000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1) MIN TYP MAX UNIT VI Input voltage UA78L02AC (for legacy chip only) 4.75 20 V UA78L033AC (for new chip only) 4.75 20 UA78L05C and UA78L05AC (for both legacy and new chip) 7 20 UA78L06C and UA78L06AC (for legacy chip only) 8.5 20 UA78L08C and UA78L08AC (for legacy chip only) 10.5 23 UA78L09C and UA78L09AC (for legacy chip only) 11.5 24 UA78L10AC (for legacy chip only) 12.5 25 UA78L12C and UA78L12AC (for both legacy and new chip) 14.5 27 UA78L15C and UA78L15AC (for both legacy and new chip) 17.5 30 IO Output current 100 mA CIN(2) Input capacitor (3) 0.33 µF COUT(2) Output capacitor ((4)) 0.1 TJ Operating junction temperature UA78L00C and UA78L00AC series (for legacy chip) 0 125 °CUA78L05AI (for legacy chip) –40 125 UA78L00C , UA78L00AC and UA78L05AI series (for new chip) –40 125 (1) All voltages are with respect to GND. (2) UA78L00 regulator doesn't need any external capacitors for the the LDO stability. (3) An input capacitor with value of 0.33 μF is recommended to counteract the effect of source resistance and inductance, which may in some cases cause symptoms of system level instability such as ringing or oscillation, especially in the presence of load transients. (4) An output capacitor with value of 0.1 μF is rrecommended to improve the load and line transient performance of the UA78L00 regulator. UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

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6.4 Thermal Information

THERMAL METRIC(1) UA78L00 UNITD (SOIC) LP (TO-92) PK (SOT-89)

8 PINS 3 PINS 3 PINS

RθJA Junction-to-ambient thermal resistance 115 143.6 54.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 60.3 74.4 88.1 °C/W RθJB Junction-to-board thermal resistance 55.6 — 9.6 °C/W ψJT Junction-to-top characterization parameter 16.2 24.2 6.2 °C/W ψJB Junction-to-board characterization parameter 55 120.9 9.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — 7.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics: UA78L02 (for legacy chip only)

at specified junction temperature, VI = 9 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted)((1)) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT Output voltage VI = 4.75 V to 20 V, and IO = 1 mA to 40 mA TJ = 25°C 2.5 2.6 2.7 VTJ = 0°C to 125°C 2.45 2.75 IO = 1 mA to 70 mA, and TJ = 0°C to 125°C 2.45 2.75 Input voltage regulation VI = 4.75 V to 20 V, and TJ = 25°C 20 100 mV VI = 5 V to 20 V, and TJ = 25°C 16 75 Ripple rejection VI = 6 V to 20 V, f = 120 Hz, and TJ = 25°C 43 51 dB Output voltage regulation IO = 1 mA to 100 mA, and TJ = 25°C 12 50 mV IO = 1 mA to 40 mA, and TJ = 25°C 6 25 Output noise voltage f = 10 Hz to 100 kHz, and TJ = 25°C 30 µV Dropout voltage TJ = 25°C 1.7 V Bias current TJ = 25°C 3.6 6 mA TJ = 125°C 5.5 Bias current change VI = 5 V to 20 V, and TJ = 0°C to 125°C 2.5 mA IO = 1 mA to 40 mA, and TJ = 0°C to 125°C 0.1 (1) Applies to UA78L02AC. (2) Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. For legacy chip, temperature range for the UA78L02AC is TJ = 0°C to 125°C. www.ti.com UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: UA78L

6.6 Electrical Characteristics: UA78L033 (for new chip only)

at specified junction temperature, VI = 9 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted)(1) PARAMETER TEST CONDITIONS (2) MIN TYP MAX UNIT Output voltage VI = 5.5 V to 20 V, and IO = 1 mA to 40 mA, TJ = 25°C 3.26 3.3 3.44 VVI = 5.5 V to 20 V, and IO = 1 mA to 40 mA, TJ = -40°C to 125°C 3.21 3.47 IO = 1 mA to 70 mA, TJ = -40°C to 125°C 3.23 3.45 Input voltage regulation VI = 5.5 V to 20 V, and TJ = 25°C 20 25 mV VI = 6 V to 20 V, and TJ = 25°C 16 27 Ripple rejection VI = 6 V to 20 V, f = 120 Hz, and TJ = 25°C 49 51 dB Output voltage regulation IO = 1 mA to 100 mA, and TJ = 25°C 15 28 mV IO = 1 mA to 40 mA, and TJ = 25°C 7.5 13 Output noise voltage f = 10 Hz to 100 kHz, and TJ = 25°C 85 µV Dropout voltage TJ = 25°C 1.7 V Bias current TJ = 25°C 3.53 4.1 mA TJ = 125°C 4.1 Bias current change VI = 6 V to 20 V, and TJ = -40°C to 125°C 0.675 mA IO = 1 mA to 40 mA, and TJ = -40°C to 125°C 0.01 (1) Applies to UA78L033 (2) Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately.

6.7 Electrical Characteristics: UA78L05 (for both legacy and new chip)

at specified junction temperature, VI = 10 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted)((1)) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT Output voltage VI = 7 V to 20 V, and IO = 1 mA to 40 mA (for legacy chip) TJ = 25°C UA78L05C 4.6 5 5.4 V UA78L05AC and UA78L05AI 4.8 5 5.2 TJ = full range UA78L05C 4.5 5.5 UA78L05AC and UA78L05AI 4.75 5.25 IO = 1 mA to 70 mA, and TJ = full range (for legacy chip) UA78L05C 4.5 5.5 UA78L05AC and UA78L05AI 4.75 5.25 VI = 7 V to 20 V, and IO = 1 mA to 40 mA (for new chip) TJ = 25°C UA78L05C 4.95 5 5.15 UA78L05AC and UA78L05AI 4.95 5 5.15 TJ = full range UA78L05C 4.85 5.15 UA78L05AC and UA78L05AI 4.85 5.15 IO = 1 mA to 70 mA, and TJ = full range (for new chip) UA78L05C 4.80 5.14 UA78L05AC and UA78L05AI 4.80 5.14 Input voltage regulation VI = 7 V to 20 V, and TJ = 25°C (for legacy chip) UA78L05C 32 200 mV UA78L05AC and UA78L05AI 32 150 VI = 8 V to 20 V, and TJ = 25°C (for legacy chip) UA78L05C 26 150 UA78L05AC and UA78L05AI 26 100 VI = 7 V to 20 V, and TJ = 25°C (for new chip) UA78L05C 32 33 UA78L05AC and UA78L05AI 32 33 VI = 8 V to 20 V, and TJ = 25°C (for new chip) UA78L05C 26 28 UA78L05AC and UA78L05AI 26 28 UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

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6.7 Electrical Characteristics: UA78L05 (for both legacy and new chip) (continued)

at specified junction temperature, VI = 10 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted)((1)) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT Ripple rejection VI = 8 V to 18 V, f = 120 Hz, and TJ = 25°C (for legacy chip) UA78L05C 40 49 dB UA78L05AC and UA78L05AI 41 49 VI = 8 V to 18 V, f = 120 Hz, and TJ = 25°C (for new chip) UA78L05C 48 49 UA78L05AC and UA78L05AI 48 49 Output voltage regulation for legacy chip IO = 1 mA to 100 mA, and TJ = 25°C 15 60 mV IO = 1 mA to 40 mA, and TJ = 25°C 8 30 for new chip IO = 1 mA to 100 mA, and TJ = 25°C 15 35 IO = 1 mA to 40 mA, and TJ = 25°C 8 15 Output noise voltage for legacy chip f = 10 Hz to 100 kHz, and TJ = 25°C 42 μV for new chip f = 10 Hz to 100 kHz, and TJ = 25°C 42 Dropout voltage for legacy chip TJ = 25°C 1.7 V for new chip 1.7 V Bias current for legacy chip TJ = 25°C 3.8 6 mA TJ = 125°C 5.5 mA for new chip TJ = 25°C 3.53 3.95 mA TJ = 125°C 4.0 Bias current change VI = 8 V to 20 V, and TJ = full range (for new legacy chip) 1.5 mA IO = 1 mA to 40 mA, and TJ = full range (for legacy chip) UA78L05C 1.5 mA UA78L05AC and UA78L05AI 1.5 mA VI = 8 V to 20 V, and TJ = full range (for new chip) 0.485 mAIO = 1 mA to 40 mA, and TJ = full range (for new chip) UA78L05C 0.01 UA78L05AC and UA78L05AI 0.01 (1) Applies to UA78L05C, UA78L05AC and UA78L05AI. (2) Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. For legacy chip, temperature range for the UA78L05C, UA78L05AC is TJ = 0°C to 125°C, and for the UA78L05AI is TJ = –40°C to 125°C. For new chip, temperature range for the UA78L05C, UA78L05AC and UA78L05AI is TJ = –40°C to 125°C. www.ti.com UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: UA78L

6.8 Electrical Characteristics: UA78L12 (for both legacy and new chip)

at specified junction temperature, VI = 19 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted)((1)) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT Output voltage VI = 14 V to 27 V, and IO = 1 mA to 40 mA TJ = 25°C UA78L12C (legacy chip) 11.1 12 12.9 V UA78L12AC (legacy chip) 11.5 12 12.5 TJ = 0°C to 125°C UA78L12C (legacy chip) 10.8 13.2 UA78L12AC (legacy chip) 11.4 12.6 TJ = 0°C to 125°C, and IO = 1 mA to 70 mA UA78L12C (legacy chip) 10.8 13.2 UA78L12AC (legacy chip) 11.4 12.6 VI = 14 V to 27 V, and IO = 1 mA to 40 mA TJ = 25°C UA78L12C (new chip) 11.83 12 12.31 UA78L12AC (new chip) TJ = -40°C to 125°C UA78L12C (new chip) 11.65 12.35 UA78L12AC (new chip) TJ = -40°C to 125°C, and IO = 1 mA to 70 mA UA78L12C (new chip) 11.47 12.35 UA78L12AC (new chip) Input voltage regulation TJ = 25°C VI = 14.5 V to 27 V for legacy chip 55 250 mV VI = 16 V to 27 V 49 200 VI = 14.0 V to 27 V for new chip 55 80 VI = 16 V to 27 V 49 65 Ripple rejection TJ = 25°C VI = 15 V to 25 V, and f = 120 Hz UA78L12C (legacy chip) 36 42 dB UA78L12AC (legacy chip) 37 42 UA78L12C (new chip) 40 42 UA78L12AC (new chip) Output voltage regulation TJ = 25°C IO = 1 mA to 100 mA for legacy chip 22 100 mV IO = 1 mA to 40 mA 13 50 IO = 1 mA to 100 mA for new chip 22 70 IO = 1 mA to 40 mA 13 30 Output noise voltage TJ = 25°C, and f = 10 Hz to 100 kHz for legacy chip 70 µV for new chip 70 µV Dropout voltage TJ = 25°C for legacy chip 1.7 V for new chip 1.7 Bias current TJ = 25°C for legacy chip 4.3 6.5 mA TJ = 125°C 6 TJ = 25°C for new chip 3.84 4.350 mA TJ = 125°C 4.355 UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

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6.8 Electrical Characteristics: UA78L12 (for both legacy and new chip) (continued)

at specified junction temperature, VI = 19 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted)((1)) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT Bias current change TJ = 0°C to 125°C VI = 16 V to 27 V (legacy chip) 1.5 mA IO = 1 mA to 40 mA UA78L12C (legacy chip) 0.2 UA78L12AC (legacy chip) 0.1 TJ = 0°C to 125°C VI = 16 V to 27 V (new chip) 0.450 IO = 1 mA to 40 mA UA78L12C (new chip) 0.01 UA78L12AC (new chip) 0.01 (1) Applies to UA78L12C and UA78L12AC. (2) Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. For legacy chip, temperature range for the UA78L12C, UA78L12AC is TJ = 0°C to 125°C. For new chip, temperature range for the UA78L12C and UA78L12AC is TJ = –40°C to 125°C. www.ti.com UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: UA78L

6.9 Electrical Characteristics: UA78L06 (for legacy chip only)

at specified junction temperature, VI = 12 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted)((1)) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT Output voltage VI = 8.5 V to 20 V, IO = 1 mA to 40 mA TJ = 25°C UA78L06C 5.7 6.2 6.7 V UA78L06AC 5.95 6.2 6.45 TJ = 0°C to 125°C UA78L06C 5.6 6.8 UA78L06AC 5.9 6.5 TJ = 0°C to 125°C, and IO = 1 mA to 70 mA UA78L06C 5.6 6.8 UA78L06AC 5.9 6.5 Input voltage regulation TJ = 25°C VI = 8.5 V to 20 V UA78L06C 35 200 mV UA78L06AC 35 175 VI = 9 V to 20 V UA78L06C 29 150 UA78L06AC 29 125 Ripple rejection TJ = 25°C, VI = 10 V to 20 V, and f = 120 Hz UA78L06C 39 48 dB UA78L06AC 40 48 Output voltage regulation TJ = 25°C IO = 1 mA to 100 mA 16 80 mV IO = 1 mA to 40 mA 9 40 Output noise voltage TJ = 25°C, and f = 10 Hz to 100 kHz 46 µV Dropout voltage TJ = 25°C 1.7 V Bias current TJ = 25°C 3.9 6 mA TJ = 125°C 5.5 Bias current change TJ = 0°C to 125°C VI = 9 V to 20 V 1.5 mA IO = 1 mA to 40 mA UA78L06C 0.2 UA78L06AC 0.1 (1) Applies to UA78L06C and UA78L06AC. (2) Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. For legacy chip, temperature range for the UA78L06C and UA78L06AC is TJ = 0°C to 125°C.

6.10 Electrical Characteristics: UA78L08 (for legacy chip only)

at specified junction temperature, VI = 14 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted)((1)) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT Output voltage VI = 10.5 V to 23 V, IO = 1 mA to 40 mA TJ = 25°C UA78L08C 7.36 8 8.64 V UA78L08AC 7.7 8 8.3 TJ = 0°C to 125°C UA78L08C 7.2 8.8 UA78L08AC 7.6 8.4 IO = 1 mA to 70 mA TJ = 0°C to 125°C UA78L08C 7.2 8.8 UA78L08AC 7.6 8.4 Input voltage regulation TJ = 25°C VI = 10.5 V to 23 V UA78L08C 42 200 mV UA78L08AC 42 175 VI = 11 V to 23 V UA78L08C 36 150 UA78L08AC 36 125 Ripple rejection VI = 13 V to 23 V, f = 120 Hz, and TJ = 25°C UA78L08C 36 46 dB UA78L08AC 37 46 Output voltage regulation TJ = 25°C IO = 1 mA to 100 mA 18 80 mV IO = 1 mA to 40 mA 10 40 Output noise voltage f = 10 Hz to 100 kHz, and TJ = 25°C 54 µV Dropout voltage TJ = 25°C 1.7 V Bias current TJ = 25°C 4 6 mA TJ = 125°C 5.5 UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

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6.10 Electrical Characteristics: UA78L08 (for legacy chip only) (continued)

at specified junction temperature, VI = 14 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted)((1)) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT Bias current change TJ = 0°C to 125°C VI = 11 V to 23 V 1.5 mA IO = 1 mA to 40 mA UA78L08C 0.2 UA78L08AC 0.1 (1) Applies to UA78L08C and UA78L08AC. (2) Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. For legacy chip, temperature range for the UA78L08C and UA78L08AC is TJ = 0°C to 125°C.

6.11 Electrical Characteristics: UA78L09 (for legacy chip only)

at specified junction temperature, VI = 16 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted)((1)) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT Output voltage VI = 12 V to 24 V, IO = 1 mA to 40 mA TJ = 25°C UA78L09C 8.3 9 9.7 V UA78L09AC 8.6 9 9.4 TJ = 0°C to 125°C UA78L09C 8.1 9.9 UA78L09AC 8.55 9.45 IO = 1 mA to 70 mA, and TJ = 0°C to 125°C UA78L09C 8.1 9.9 UA78L09AC 8.55 9.45 Input voltage regulation TJ = 25°C VI = 12 V to 24 V UA78L09C 45 225 mV UA78L09AC 45 175 VI = 13 V to 24 V UA78L09C 40 175 UA78L09AC 40 125 Ripple rejection VI = 15 V to 25 V, f = 120 Hz, and TJ = 25°C UA78L09C 36 45 dB UA78L09AC 38 45 Output voltage regulation TJ = 25°C IO = 1 mA to 100 mA 19 90 mV IO = 1 mA to 40 mA 11 40 Output noise voltage f = 10 Hz to 100 kHz, and TJ = 25°C 58 µV Dropout voltage TJ = 25°C 1.7 V Bias current TJ = 25°C 4.1 6 mA TJ = 125°C 5.5 Bias current change TJ = 0°C to 125°C VI = 13 V to 24 V 1.5 mA IO = 1 mA to 40 mA UA78L09C 0.2 UA78L09AC 0.1 (1) Applies to UA78L09C ad UA78L09AC. (2) Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. For legacy chip, temperature range for the UA78L09C and UA78L09AC is TJ = 0°C to 125°C.

6.12 Electrical Characteristics: UA78L10 (for legacy chip only)

at specified junction temperature, VI = 14 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted)((1)) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT Output voltage VI = 13 V to 25 V, and IO = 1 mA to 40 mA TJ = 25°C 9.6 10 10.4 VTJ = 0°C to 125°C 9.5 10.5 TJ = 0°C to 125°C, and IO = 1 mA to 70 mA 9.5 10.5 Input voltage regulation TJ = 25°C VI = 13 V to 25 V 51 175 mV VI = 14 V to 25 V 42 125 Ripple rejection TJ = 25°C, VI = 15 V to 25 V, and f = 120 Hz 37 44 dB Output voltage regulation TJ = 25°C IO = 1 mA to 100 mA 20 90 mV IO = 1 mA to 40 mA 11 40 Output noise voltage TJ = 25°C, and f = 10 Hz to 100 kHz 62 µV Dropout voltage TJ = 25°C 1.7 V www.ti.com UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: UA78L

6.12 Electrical Characteristics: UA78L10 (for legacy chip only) (continued)

at specified junction temperature, VI = 14 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted)((1)) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT Bias current TJ = 25°C 4.2 6 mA TJ = 125°C 5.5 Bias current change TJ = 0°C to 125°C VI = 14 V to 25 V 1.5 mA IO = 1 mA to 40 mA 0.1 (1) Applies to UA78L10AC. (2) Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. For legacy chip, temperature range for the UA78L10AC is TJ = 0°C to 125°C.

6.13 Electrical Characteristics: UA78L15 (for both legacy and new chip)

at specified junction temperature, VI = 23 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted) (1) PARAMETER TEST CONDITIONS (2) MIN TYP MAX UNIT Output voltage VI = 17.5 V to 30 V, and IO = 1 mA to 40 mA TJ = 25°C UA78L15C (legacy chip) 13.8 15 16.2 V UA78L15AC (legacy chip) 14.4 15 15.6 V TJ = 0°C to 125°C UA78L15C (legacy chip) 13.5 16.5 V UA78L15AC (legacy chip) 14.25 15.75 V TJ = 0°C to 125°C, and IO = 1 mA to 70 mA UA78L15C (legacy chip) 13.5 16.5 V UA78L15AC (legacy chip) 14.25 15.75 V VI = 17.5 V to 30 V, and IO = 1 mA to 40 mA TJ = 25°C UA78L15C (new chip) 14.750 15 15.425 V UA78L15AC (new chip) 14.750 15 15.425 TJ = -40°C to 125°C UA78L15C (new chip) 14.575 15.450 UA78L15AC (new chip) 14.575 15.450 TJ = -40°C to 125°C, and IO = 1 mA to 70 mA UA78L15C (new chip) 14.35 15.45 UA78L15AC (new chip) 14.35 15.45 Input voltage regulation TJ = 25°C VI = 17.5 V to 30 V for legacy chip 65 300 mV VI = 20 V to 30 V 58 250 VI = 17.5 V to 30 V for new chip 65 82 VI = 20 V to 30 V 58 60 Ripple rejection TJ = 25°C VI = 18.5 V to 28.5 V, and f = 120 Hz UA78L15C (legacy chip) 33 39 dB UA78L15AC (legacy chip) 34 39 VI = 18.5 V to 28.5 V, and f = 120 Hz UA78L15C (new chip) 40 45 UA78L15AC (new chip) 40 45 Output voltage regulation TJ = 25°C IO = 1 mA to 100 mA for legacy chip 25 150 mV IO = 1 mA to 40 mA 15 75 IO = 1 mA to 100 mA for new chip 25 27 IO = 1 mA to 40 mA 15 60 Output noise voltage TJ = 25°C, and f = 10 Hz to 100 kHz for legacy chip 82 μV for new chip 388 UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

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6.13 Electrical Characteristics: UA78L15 (for both legacy and new chip) (continued)

at specified junction temperature, VI = 23 V, CIN = 0.33 µF, COUT = 0.1µF and IO = 40 mA (unless otherwise noted) (1) PARAMETER TEST CONDITIONS (2) MIN TYP MAX UNIT Dropout voltage TJ = 25°C for legacy chip 1.7 V for new chip 1.7 Bias current TJ = 25°C for legacy chip 4.6 6.5 mA TJ = 125°C 6 TJ = 25°C for new chip 4.1 4.670 TJ = 125°C 4.675 Bias current change TJ = 0°C to 125°C VI = 10 V to 30 V legacy chip 1.5 mA IO = 1 mA to 40 mA UA78L15C (legacy chip) 0.2 UA78L15AC (legacy chip) 0.1 TJ = -40°C to 125°C VI = 20 V to 30 V new chip 0.425 IO = 1 mA to 40 mA UA78L15C (new chip) 0.01 UA78L15AC (new chip) 0.02 (1) Applies to UA78L15C and UA78L15AC. (2) Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. For legacy chip, temperature range for the UA78L15C, UA78L15AC is TJ = 0°C to 125°C. For new chip, temperature range for the UA78L15C and UA78L15AC is TJ = –40°C to 125°C. www.ti.com UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: UA78L

6.14 Typical Characteristics

at specified junction temperature TJ = 25 °C, VI = 10 V, VO = 5 V, CIN = 0.33 µF, COUT = 0.1µF, and IO = 1 mA (unless otherwise noted) Temperature(  C) Output Voltage (V o ) [V] -55 -35 -15 5 25 45 65 85 105 125 145 4.9 4.92 4.94 4.96 4.98 5.02 5.04 5.06 5.08 5.1 Figure 6-1. VO vs Temperature for New Chip Temperature(  C) Output Voltage (V o ) [V] -55 -30 -5 20 45 70 95 120 145 4.9 4.92 4.94 4.96 4.98 5.02 5.04 5.06 5.08 5.1 IO = 40 mA Figure 6-2. VO vs Temperature for New Chip Output Current (IO) [mA] Output Voltage (VO) [V] 0 10 20 30 40 50 60 70 80 90 100 4.9 4.92 4.94 4.96 4.98 5.02 5.04 5.06 5.08 5.1 D004 TA = 25qC VI = 10 V Figure 6-3. Load Regulation for Legacy Chip Output Current (I o ) [mA] Output Voltage (V o ) [V] 0 10 20 30 40 50 60 70 80 90 100 4.9 4.92 4.94 4.96 4.98 5.02 5.04 5.06 5.08 5.1 Figure 6-4. Load Regulation for New Chip at TJ = 25°C Output Current (I O ) [mA] Output Voltage (V O ) [V] 0 10 20 30 40 50 60 70 80 90 100 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 -55 °C -40 °C 0 °C 25 °C 85 °C 125 °C 150 °C Figure 6-5. Load Regulation for New Chip Input Voltage (VI) [V] Output Voltage (VO) [V] 6 8 10 12 14 16 18 20 4.9 4.92 4.94 4.96 4.98 5.02 5.04 5.06 5.08 5.1 D003 TA = 25qC IO = 40 mA IO = 40 mA Figure 6-6. Line Regulation at IO = 40 mA for Legacy Chip UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

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6.14 Typical Characteristics (continued)

at specified junction temperature TJ = 25 °C, VI = 10 V, VO = 5 V, CIN = 0.33 µF, COUT = 0.1µF, and IO = 1 mA (unless otherwise noted) Input Voltage (V I ) [V] Output Voltage (V o ) [V] 6 8 10 12 14 16 18 20 4.9 4.92 4.94 4.96 4.98 5.02 5.04 5.06 5.08 5.1 IO = 40 mA Figure 6-7. Line Regulation at IO = 40 mA for New Chip at TJ = 25°C Input Voltage (V I ) [V] Output Voltage (V o ) [V] 6 8 10 12 14 16 18 20 4.9 4.92 4.94 4.96 4.98 5.02 5.04 5.06 5.08 5.1 Figure 6-8. Line Regulation at IO = 1 mA for New Chip at TJ = 25°C IO = 40 mA Figure 6-9. Line Regulation at IO = 40 mA for New Chip Input Voltage (V I ) [V] Output Voltage (V o ) [V] 6 8 10 12 14 16 18 20 4.84 4.86 4.88 4.9 4.92 4.94 4.96 4.98 5.02 5.04 5.06 5.08 5.1 -55 °C -40 °C 0 °C 25 °C 85 °C 125 °C 150 °C Figure 6-10. Line Regulation at IO = 1 mA for New Chip Load Current (IO) [mA] Bias Current [mA] 0 10 20 30 40 50 60 70 80 90 100 4.16 4.162 4.164 4.166 4.168 4.17 4.172 4.174 D001 TA = 25qC VI = 10 V Figure 6-11. Bias Current vs Load Current for Legacy Chip Output Current (I o ) [mA] Ibias [mA] 0 10 20 30 40 50 60 70 80 90 100 3.4 3.5 3.6 3.7 3.8 3.9 Figure 6-12. Bias Current vs Load Current for New Chip at TJ = 25°C www.ti.com UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: UA78L

at specified junction temperature TJ = 25 °C, VI = 10 V, VO = 5 V, CIN = 0.33 µF, COUT = 0.1µF, and IO = 1 mA (unless otherwise noted) Output Current I o [mA] I bias [mA] 0 10 20 30 40 50 60 70 80 90 100 -35 -30 -25 -20 -15 -10 -55 °C -40 °C 0 °C 25 °C 85 °C 125 °C 150 °C Figure 6-13. Bias Current vs Load Current for New Chip Input Voltage (VI) [V] Bias Current [mA] 8 10 12 14 16 18 20 3.75 4.25 4.5 4.75 5.25 D002 TA = 25qC IO = 40 mA IO = 40 mA Figure 6-14. Bias Current vs Input Voltage for Legacy Chip Input Voltage (V I ) [V] Ibias [mA] 6 8 10 12 14 16 18 20 3.25 3.5 3.75 4.25 4.5 4.75 5.25 IO = 40 mA Figure 6-15. Bias Current vs Input Voltage for New Chip at TJ = 25°C V in (V) I bias (mA) 7 9 11 13 15 17 19 20 0.5 1.5 2.5 3.5 4.5 I out = 40mA -55 °C -40 °C 0 °C 25 °C 85 °C 125 °C 150 °C IO = 40 mA Figure 6-16. Bias Current vs Input Voltage for New Chip V in (V) I bias (mA) 7 9 11 13 15 17 19 20 3.4 3.5 3.6 3.7 3.8 3.9 I out = 1mA -55 °C -40 °C 0 °C 25 °C 85 °C 125 °C 150 °C Figure 6-17. Bias Current vs Input Voltage at IO = 1 mA for New Chip V in (V) I sc (mA) 5 9 13 17 21 25 29 33 37 41 45 120 160 200 240 280 -55 °C -40 °C 0 °C 25 °C 85 °C 125 °C 150 °C VO = 0 V Figure 6-18. ISC vs VI for New Chip UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

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at specified junction temperature TJ = 25 °C, VI = 10 V, VO = 5 V, CIN = 0.33 µF, COUT = 0.1µF, and IO = 1 mA (unless otherwise noted) Temperature(  C) ICL(mA) -55 -35 -15 5 25 45 65 85 105 125 145 100 125 150 175 200 VO = 90% of VO (typ) Figure 6-19. ICL vs Temperature for New Chip Frequency (Hz) Noise Spectral Density (  V/  Hz) 1x10 1x10 1x10 1x10 1x10 1x10 1x10 0.005 0.01 0.02 0.05 0.1 0.2 0.5 Integrated Noise from 10Hz to 100KHz 1mA : 85  V 40mA : 85  V I OUT = 1mA I OUT = 40mA VI = 9 V, VO = 3.3 V Figure 6-20. Noise Spectral Density vs Frequency and IO for New Chip Frequency (Hz) Noise Spectral Density (  V/  Hz) 1x10 1x10 1x10 1x10 1x10 1x10 1x10 0.005 0.01 0.02 0.05 0.1 0.2 0.5 Integrated Noise from 10Hz to 100KHz 1mA : 388  V 40mA : 383  V 1mA 40mA VI = 23 V, VO = 15 V Figure 6-21. Noise Spectral Density vs Frequency and IO for New Chip Frequency (Hz) Power Supply Ripple Rejection (dB) 1x10 1x10 1x10 1x10 1x10 1x10 1x10 100 I OUT = 1mA I OUT = 40mA I OUT = 100mA VI = 9 V, VO = 3.3 V Figure 6-22. PSRR vs Frequency and IO for New Chip Frequency (Hz) Power Supply Ripple Rejection (dB) 1x10 1x10 1x10 1x10 1x10 1x10 1x10 100 I OUT = 1mA I OUT = 40mA I OUT = 100mA VI = 23 V, VO = 15 V Figure 6-23. PSRR vs Frequency and IO for New Chip www.ti.com UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: UA78L

7 Detailed Description

7.1 Overview

The UA78L series of fixed-voltage, integrated-circuit voltage regulators is designed for a wide range of applications. The UA78L series supports a wide range of input voltages and can deliver 100 mA of load current. This device features internal current-limiting and thermal shutdown mechanisms. To provide reliable operation across wide V I ranges, the current-limiting mechanism modulates the load current capacity both by monitoring the VO level and the difference between the V I and VO voltage levels. The operating ambient temperature range of the device is –40°C to +125°C for all variants of the new chip.

7.2 Functional Block Diagram

1 k to 14 kW W1.4 kW NOTE: Resistor values shown are nominal.

7.3 Feature Description

7.3.1 Current Limit

The device has an internal current-limit circuit that protects the regulator during transient high-load current faults or shorting events. In a high-load current fault, the current limit scheme limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table. The output voltage is not regulated when the device is in current limit. When a current-limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in current limit, the pass transistor dissipates power [(V I – V O) × I CL]. For more information on current limits, see the Know Your Limits application note. UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

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To achieve a safe operation across a wide range of Input voltage, the UA78L series also has a built-in protection mechanism with current limit. The protection mechanism decreases the current limit as input-to-output voltage increases and keeps the power transistor inside a safe operating region for all values of input-to-output voltage. This protection is designed to provide some output current at all values of input-to-output voltage limits defined in the Recommended Operating Conditions table. Figure 7-1 shows the behavior of the current limit variation. V in (V) I sc (mA) 5 9 13 17 21 25 29 33 37 41 45 120 160 200 240 280 -55 °C -40 °C 0 °C 25 °C 85 °C 125 °C 150 °C Figure 7-1. Current-Limit Behavior Variation

7.3.2 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to T SD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the device resets (turns on) when the temperature falls to TSD(reset) (typical). The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start-up can be high from large VI – VO voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes. For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating Conditions table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

7.3.3 Dropout Voltage (VDO)

Dropout voltage (V DO) is defined as the input voltage minus the output voltage (V I – V O) at the rated output current (I RATED), where the pass transistor is fully on. I RATED is the maximum I O listed in the Recommended Operating Conditions table. In dropout operation, the pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the value required to maintain output regulation, then the output voltage falls as well. www.ti.com UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: UA78L

7.4 Device Functional Modes

Table 7-1 provides a quick comparison between the normal and dropout modes of operation. Table 7-1. Device Functional Mode Comparison OPERATING MODE PARAMETER VI IO Normal VI > VOUT(nom) + VDO IO < ICL Dropout VI < VOUT(nom) + VDO IO < ICL

7.4.1 Normal Operation

The device regulates to the nominal output voltage under the following conditions:

The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IO < ICL)
The device junction temperature is greater than –40°C and less than +125°C

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, V I < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (V OUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

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8 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The UA78L series is designed for use as a linear regulator with only a few external components needed. The UA78L can also be used to clean power-supply noise by attenuating ripple on the input signal.

8.2 Typical Application

The UA78L series is typically used as a fixed-output linear regulator, sourcing current up to 100 mA into a load. UA78L00 INPUT OUTPUT COMMON0.33 μF 0.1 μF GND VI VO Figure 8-1. Fixed-Output Regulator

8.2.1 Design Requirements

The COMMON pin must be tied to ground to set the OUTPUT pin to the desired fixed output voltage. Although not required, a 0.33-µF bypass capacitor is recommended on the input, and a 0.1-µF bypass capacitor is recommend on the output.

8.2.2 Detailed Design Procedure

8.2.2.1 Input and Output Capacitor Requirements

Although both input and output capacitor are not required for stability, good analog design practice is to connect a capacitor from IN to COMMON and from OUT to COMMON. The input capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Dynamic performance of the device is improved with the use of a large output capacitor. Use an output capacitor within the range specified in the Recommended Operating Conditions table for stability.

8.2.2.2 Power Dissipation (PD)

Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VI – VO) × IO (1) www.ti.com UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: UA78L

Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation, use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (T A) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (R θJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) (2) Thermal resistance (R θJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, R θJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization.

8.2.2.3 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi ( Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (T J), as described in the following equations. Use the junction-to-top characterization parameter ( ψJT) with the temperature at the center-top of device package (T T) to calculate the junction temperature. Use the junction-to-board characterization parameter ( ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD (3) where:

PD is the dissipated power
TT is the temperature at the center-top of the device package UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

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TJ = TB + ψJB × PD (4) where:

TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note.

8.2.2.4 External Capacitor Requirements

The UA78L is designed to be stable without any external component. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors recommended in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value.

8.2.2.5 Overload Recovery

As the input voltage rises when power is first turned on, the output follows the input, allowing the regulator to start up into very heavy loads. The input-to-output voltage differential is small during start up when the input voltage is rising, allowing the regulator to supply large output currents. With a high input voltage, a problem can occur where removing an output short does not allow the output voltage to recover. Other regulators also exhibit this phenomenon, so the behavior is not unique to the UA78L. The problem occurs with a heavy output load when the input voltage is high and the output voltage is low. Common situations occur immediately after removing a short circuit or when the shutdown pin is pulled high after the input voltage is already turned on. The load line for such a load has the possibility to intersect the output current curve at two points. If this happens, there are two stable output operating points for the regulator. With this double intersection, the input power supply can possibly need to be cycled down to zero and brought up again to make the output recover to the desired voltage operating point.

8.2.2.6 Reverse Current

Excessive reverse current can damage this device. Reverse current flows through the emitter-base junction of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VO ≤ VI + 7 V. These conditions are:

If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. Limit reverse current to 5% or less of the rated output current of the device in the event this current cannot be avoided. www.ti.com UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: UA78L

Figure 8-2 shows one approach for protecting the device. IN OUT GND CIN GND GND COUT GND Internal Body Diode Schottky Diode Figure 8-2. Example Circuit for Reverse Current Protection Using a Schottky Diode

8.2.2.7 Polarity Reversal Protection

In many applications, a voltage regulator powers a load that is not connected to ground, but instead, is connected to a voltage source of the opposite polarity (for example, operational amplifiers, level-shifting circuits, and so on). During start-up and short-circuit events, this connection can lead to polarity reversal of the regulator output and can damage the internal components of the regulator. To avoid polarity reversal on the regulator output, use external protection to protect the device. Figure 8-3 shows one approach for protecting the device. INPUT OUTPUT COMMON CIN GND COUT +VO -VO Schottky Diode Figure 8-3. Example Circuit for Polarity Reversal Protection Using a Schottky Diode UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

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8.2.3 Application Curves

Input Voltage (VO) [V] Output Voltage (VO) [V] 0 2 4 6 8 10 12 14 16 18 20 D005 TA = 25qC VO = 40 mA (@ 5V) Figure 8-4. Output Voltage vs Input Voltage for Legacy Chip Input Voltage (VO) [V] Output Voltage (VO) [V] 0 2 4 6 8 10 12 14 16 18 20 D005 TA = 25qC VO = 40 mA (@ 5V) Figure 8-5. Output Voltage vs Input Voltage for New Chip VO = 3.3 V Figure 8-6. Start-Up With Fast VI Ramp for New Chip Time (s) V IN (V) V OUT (V) 0 4 8 12 16 20 -55°C -40°C 0°C 25°C 85°C 125°C 150°C VO = 3.3 V Figure 8-7. Start-Up With Slow VI Ramp Across Temperature for New Chip Time (  s) I OUT (mA)  V OUT (mV) 0 10 20 30 40 50 60 70 80 90 100 -20 -300 0 -250 20 -200 40 -150 60 -100 80 -50 100 0 120 50 140 100 160 150 180 200 I OUT  V OUT VO = 3.3 V, dIO/dt = 1 A/μs Figure 8-8. Load Transient Behavior for New Chip Time (ms) V IN (V)  V OUT (V) 0 0.5 1 1.5 2 2.5 3 3.5 4 0 -60 5 -50 10 -40 15 -30 20 -20 25 -10 30 0 35 10 40 20 45 30 50 40 55 50 V IN  V OUT VO = 3.3 V, dVIN/dt = 1 V/μs Figure 8-9. Line Transient Behavior for New Chip www.ti.com UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: UA78L

8.3 System Examples

8.3.1 Positive Regulator in Negative Configuration

Figure 8-10 shows the UA78L as a positive regulator used in a negative configuration. INPUT OUTPUT COMMON UA78L00 VI GND -VO Figure 8-10. Positive Regulator in Negative Configuration (VI Must Float)

8.3.2 Current Limiter Circuit

Figure 8-11 shows an example of using the UA78L as a current limiter. The output current limit is set by Equation O O O VI I Bias CurrentR1 /c230 /c246/c61 /c43 /c231 /c247 /c232 /c248 (5) INPUT OUTPUT COMMON UA78L00 VI Output IO VO(Reg)+ - Figure 8-11. Current Limiter Example

8.4 Power Supply Recommendations

See the Recommended Operating Conditions table for the recommended power-supply voltages for each variation of the UA78L. Each device variant can have a different recommended maximum operating voltage. UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

Product Folder Links: UA78L

8.5 Layout

8.5.1 Layout Guidelines

Keep trace widths large enough to eliminate problematic I×R voltage drops at the input and output pins. Place bypass capacitors as close to the UA78L as possible. Additional copper and vias connected to ground facilitate additional thermal dissipation, preventing the device from reaching thermal overload.

8.5.2 Layout Example

0.1 F 0.33 F VIVO Ground Figure 8-12. Example Layout for the PK Package www.ti.com UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: UA78L

9 Device and Documentation Support

9.1 Device Support

9.1.1 Development Support

9.1.1.1 Evaluation Module

An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the UA78L. The UA78LEVM-075 (and related user guide ) can be requested at the Texas Instruments website through the product folders or purchased directly from the TI eStore.

9.1.2 Device Nomenclature

Table 9-1. Device Nomenclature(1) PRODUCT VOUT UA78Lxxyyyz Legacy chip xx is the nominal output voltage (for example, 05 = 5.0 V, 15 = 15.0 V). yyy is the package designator. z is the package quantity. UA78Lxxyyyz M3 New chip xx is the nominal output voltage (for example, 05 = 5.0 V, 15 = 15.0 V). yyy is the package designator. z is the package quantity. M3 is a suffix designator for new chip redesigns on the latest TI process technology. (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. UA78L SLVS010W – JANUARY 1976 – REVISED APRIL 2023 www.ti.com

Product Folder Links: UA78L

www.ti.com 22-Apr-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PUA78L033AIPK ACTIVE SOT-89 PK 3 1000 TBD Call TI Call TI -40 to 125 Samples PUA78L05ACPKM3 ACTIVE SOT-89 PK 3 1000 TBD Call TI Call TI -40 to 125 Samples UA78L02ACD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L02A Samples UA78L02ACDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L02A Samples UA78L02ACLP LIFEBUY TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L02AC UA78L02ACLPE3 LIFEBUY TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L02AC UA78L05ACD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L05A Samples UA78L05ACDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L05A Samples UA78L05ACDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L05A Samples UA78L05ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 125 78L05A Samples UA78L05ACDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L05A Samples UA78L05ACDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L05A Samples UA78L05ACLP ACTIVE TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L05AC Samples UA78L05ACLPE3 ACTIVE TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L05AC Samples UA78L05ACLPM ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L05AC Samples UA78L05ACLPME3 ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L05AC Samples UA78L05ACLPR ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L05AC Samples UA78L05ACLPRE3 ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L05AC Samples UA78L05ACPK ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR 0 to 125 F5 Samples UA78L05ACPKE6 ACTIVE SOT-89 PK 3 1000 RoHS & Non-Green SNBI Level-1-260C-UNLIM 0 to 125 F5 Samples Addendum-Page 1

www.ti.com 22-Apr-2023 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples UA78L05ACPKG3 ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR 0 to 125 F5 Samples UA78L05AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 78L05AI Samples UA78L05AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 78L05AI Samples UA78L05AIDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 78L05AI Samples UA78L05AILP ACTIVE TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type -40 to 125 78L05AI Samples UA78L05AILPE3 ACTIVE TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type -40 to 125 78L05AI Samples UA78L05AILPR ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type -40 to 125 78L05AI Samples UA78L05AILPRE3 ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type -40 to 125 78L05AI Samples UA78L05AIPK ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 J5 Samples UA78L05AIPKG3 ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 J5 Samples UA78L05CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L05C Samples UA78L05CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L05C Samples UA78L05CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L05C Samples UA78L05CDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L05C Samples UA78L05CLP LIFEBUY TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L05C UA78L05CLPE3 LIFEBUY TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L05C UA78L05CLPR ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L05C Samples UA78L05CPK ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR 0 to 125 B5 Samples UA78L05CPKG3 ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR 0 to 125 B5 Samples UA78L06ACLP ACTIVE TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L06AC Samples UA78L06ACLPR LIFEBUY TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L06AC UA78L06ACLPRE3 LIFEBUY TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L06AC Addendum-Page 2

www.ti.com 22-Apr-2023 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples UA78L10ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L10A Samples UA78L10ACDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L10A Samples UA78L10ACLP ACTIVE TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L10AC Samples UA78L10ACLPE3 ACTIVE TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L10AC Samples UA78L10ACLPR ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L10AC Samples UA78L10ACLPRE3 ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L10AC Samples UA78L10ACPK ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR 0 to 125 FA Samples UA78L10ACPKG3 ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR 0 to 125 FA Samples UA78L12ACD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L12A Samples UA78L12ACDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L12A Samples UA78L12ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 125 78L12A Samples UA78L12ACDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L12A Samples UA78L12ACDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L12A Samples UA78L12ACLP LIFEBUY TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L12AC UA78L12ACLPE3 LIFEBUY TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L12AC UA78L12ACLPM LIFEBUY TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L12AC UA78L12ACLPR ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L12AC Samples UA78L12ACPK ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR 0 to 125 FC Samples UA78L12ACPKG3 ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR 0 to 125 FC Samples UA78L15ACD LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L15A UA78L15ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L15A Samples UA78L15ACDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 78L15A Samples UA78L15ACLP LIFEBUY TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L15AC Addendum-Page 4

www.ti.com 22-Apr-2023 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples UA78L15ACLPE3 LIFEBUY TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L15AC UA78L15ACLPR ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L15AC Samples UA78L15ACLPRE3 ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 78L15AC Samples UA78L15ACPK ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR 0 to 125 FF Samples UA78L15ACPKG3 ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR 0 to 125 FF Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 5

www.ti.com 22-Apr-2023 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 6

PACKAGE MATERIALS INFORMATION www.ti.com 27-Feb-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 27-Feb-2023 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 27-Feb-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UA78L05ACDR SOIC D 8 2500 364.0 364.0 27.0 UA78L05ACDRG4 SOIC D 8 2500 340.5 336.1 25.0 UA78L05ACPK SOT-89 PK 3 1000 340.0 340.0 38.0 UA78L05ACPKE6 SOT-89 PK 3 1000 182.0 182.0 20.0 UA78L05AIPK SOT-89 PK 3 1000 340.0 340.0 38.0 UA78L05CDR SOIC D 8 2500 340.5 336.1 25.0 UA78L05CPK SOT-89 PK 3 1000 340.0 340.0 38.0 UA78L06ACPK SOT-89 PK 3 1000 340.0 340.0 38.0 UA78L08ACDR SOIC D 8 2500 364.0 364.0 27.0 UA78L08ACDR SOIC D 8 2500 340.5 336.1 25.0 UA78L08ACDRG4 SOIC D 8 2500 340.5 336.1 25.0 UA78L08ACPK SOT-89 PK 3 1000 340.0 340.0 38.0 UA78L09ACDR SOIC D 8 2500 340.5 336.1 25.0 UA78L09ACPK SOT-89 PK 3 1000 340.0 340.0 38.0 UA78L09ACPKE6 SOT-89 PK 3 1000 182.0 182.0 20.0 UA78L10ACDR SOIC D 8 2500 340.5 336.1 25.0 UA78L10ACPK SOT-89 PK 3 1000 340.0 340.0 38.0 UA78L12ACDR SOIC D 8 2500 364.0 364.0 27.0 Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 27-Feb-2023 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UA78L12ACDR SOIC D 8 2500 340.5 336.1 25.0 UA78L12ACDRG4 SOIC D 8 2500 340.5 336.1 25.0 UA78L12ACPK SOT-89 PK 3 1000 340.0 340.0 38.0 UA78L15ACDR SOIC D 8 2500 340.5 336.1 25.0 UA78L15ACPK SOT-89 PK 3 1000 340.0 340.0 38.0 Pack Materials-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 27-Feb-2023 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) UA78L02ACD D SOIC 8 75 507 8 3940 4.32 UA78L02ACDG4 D SOIC 8 75 507 8 3940 4.32 UA78L05ACD D SOIC 8 75 507 8 3940 4.32 UA78L05ACDE4 D SOIC 8 75 507 8 3940 4.32 UA78L05ACDG4 D SOIC 8 75 507 8 3940 4.32 UA78L05AID D SOIC 8 75 507 8 3940 4.32 UA78L05CD D SOIC 8 75 507 8 3940 4.32 UA78L05CDG4 D SOIC 8 75 507 8 3940 4.32 UA78L08ACD D SOIC 8 75 507 8 3940 4.32 UA78L09ACD D SOIC 8 75 507 8 3940 4.32 UA78L10ACD D SOIC 8 75 507 8 3940 4.32 UA78L12ACD D SOIC 8 75 507 8 3940 4.32 UA78L12ACDG4 D SOIC 8 75 507 8 3940 4.32 UA78L15ACD D SOIC 8 75 507 8 3940 4.32 Pack Materials-Page 5

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE 3X 2.67 2.03 5.21 4.44 5.34 4.32

12.7 MIN

2X 1.27 0.13 3X 0.55 0.38 4.19 3.17

3.43 MIN

3X 0.43 0.35 (2.54) NOTE 3 2.6 0.2

4 MAX

0.076 MAX

(0.51) TYP (1.5) TYP TO-92 - 5.34 mm max heightLP0003A TO-92 4215214/B 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Lead dimensions are not controlled within this area. 4. Reference JEDEC TO-226, variation AA. 5. Shipping method: a. Straight lead option available in bulk pack only. b. Formed lead option available in tape and reel or ammo pack. c. Specific products can be offered in limited combinations of shipping medium and lead options. d. Consult product folder for more information on available options. EJECTOR PIN OPTIONAL PLANE SEATING STRAIGHT LEAD OPTION 3 2 1 SCALE 1.200 FORMED LEAD OPTION OTHER DIMENSIONS IDENTICAL TO STRAIGHT LEAD OPTION SCALE 1.200

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

(1.07) (1.5) 2X (1.5) 2X (1.07) (1.27) (2.54) FULL R TYP ( 1.4)0.05 MAX ALL AROUND TYP (2.6) (5.2) (R0.05) TYP 3X ( 0.9) HOLE 2X ( 1.4) METAL 3X ( 0.85) HOLE (R0.05) TYP 4215214/B 04/2017 TO-92 - 5.34 mm max heightLP0003A TO-92 LAND PATTERN EXAMPLE FORMED LEAD OPTION NON-SOLDER MASK DEFINED SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING 1 2 3 LAND PATTERN EXAMPLE STRAIGHT LEAD OPTION NON-SOLDER MASK DEFINED SCALE:15X METAL TYP SOLDER MASK OPENING SOLDER MASK OPENING METAL 1 2 3

www.ti.com TAPE SPECIFICATIONS 19.0 17.5 13.7 11.7 11.0 8.5

0.5 MIN

TYP -4.3 3.7 9.75 8.50 TYP2.9 2.4 6.75 5.95 13.0 12.4 (2.5) TYP 16.5 15.5 4215214/B 04/2017 TO-92 - 5.34 mm max heightLP0003A TO-92 FOR FORMED LEAD OPTION PACKAGE

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Product Information

PUA78L033AIPK specifications and overview.

Summary

UA78L Series Positive-Voltage Linear Regulators REVISED APRIL 2023

Description

UA78L Series Positive-Voltage Linear Regulators REVISED APRIL 2023

Source title PUA78L033AIPK Datasheet(PDF) - Texas Instruments

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