PTXS0104EQWBQARQ1

TXS0104E-Q1_V01 TI | Alldatasheet

Document overview

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Technical content

TXS0104E-Q1 Automotive 4-Bit Bidirectional Voltage-Level Translator for Open-Drain and Push-Pull Applications

1 Features

• Qualified for automotive applications
• AEC-Q100 qualified with the following results: – Device temperature grade 1: –40°C to +125°C ambient operating temperature range – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C6
• No direction-control signal required
• Maximum data rates: – 24 Mbps maximum (push pull) – 2 Mbps (open drain)
• 1.65 V to 3.6 V on A port and 2.3 V to 5.5 V on B port (VCCA ≤ VCCB)
• No power-supply sequencing required—VCCA or VCCB can be ramped first
• ESD protection exceeds JESD 22: – A Port
• 2000-V Human-Body Model (A114-B)
• 1000-V Charged-Device Model (C101) – B Port
• 15-kV Human-Body Model (A114-B)
• 1000-V Charged-Device Model (C101)
• IEC 61000-4-2 ESD (B port) – ±8-kV Contact Discharge – ±10-kV Air-Gap Discharge

2 Applications

• Automotive infotainment, advance driver assistance systems (ADAS)
• Isolates and level translates between main processor and peripheral modules
• I2C or 1-wire voltage-level translation 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.2 2.4 2.6 2.8 3.2 3.4 0 1 2 3 4 5 Output Voltage (V) Input Voltage (V) VGATE = 4.3 V VGATE = 3.5 V VGATE = 2.8 V VGATE = 2.5 V VGATE = 2.2 V C001 VGATE = 4.3 V VGATE = 3.5 V VGATE = 2.8 V VGATE = 2.5 V VGATE = 2.2 V Transfer Characteristics of an N-Channel Transistor

3 Description

The TXS0104E-Q1 device connects an incompatible logic communication from chip-to-chip due to voltage mismatch. This auto-direction translator can be conveniently used to bridge the gap without the need of direction control from the host. Each channel can be mixed and matched with different output types (open-drain or push-pull) and mixed data flows (transmit or receive) without intervention from the host. This 4-bit noninverting translator uses two separate configurable power-supply rails. The A and B ports are designed to track V CCA and V CCB respectively. The VCCB pin accepts any supply voltage from 2.3 V to 5.5 V while the V CCA pin accepts any supply voltage from 1.65 V to 3.6 V such that V CCA is less than or equal to V CCB. This tracking allows for low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. When the output-enable (OE) input is low, all outputs are placed in the high-impedance state. The TXS0104E-Q1 device is designed so that the OE input circuit is supplied by VCCA. To be in the high-impedance state during power up or power down, the OE pin must be tied to the GND pin through a pull down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TXS0104E-Q1 PW (TSSOP, 14) 5 mm × 6.4 mm BQA (WQFN, 14)(3) 3 mm × 2.5 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) Preview package TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

10.2 Receiving Notification of Documentation Updates..20

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (January 2017) to Revision D (June 2023) Page Changes from Revision B (May 2014) to Revision C (January 2017) Page

• Moved Tstg back to the Absolute Maximum Ratings table and changed the Handling Ratings table to ESD Changes from Revision A (April 2014) to Revision B (May 2014) Page TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 www.ti.com

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5 Pin Configuration and Functions

NC - No internal connection Figure 5-1. PW Package, 14-Pin TSSOP (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. A1 2 I/O Input-output 1 for the A port. This pin is referenced to VCCA. A2 3 I/O Input-output 2 for the A port. This pin is referenced to VCCA. A3 4 I/O Input-output 3 for the A port. This pin is referenced to VCCA. A4 5 I/O Input-output 4 for the A port. This pin is referenced to VCCA. B1 13 I/O Input-output 1 for the B port. This pin is referenced to VCCB. B2 12 I/O Input-output 2 for the B port. This pin is referenced to VCCB. B3 11 I/O Input-output 3 for the B port. This pin is referenced to VCCB. B4 10 I/O Input-output 4 for the B port. This pin is referenced to VCCB. GND 7 — Ground NC — No connection OE 8 I Tri-state output-mode enable. Pull the OE pin low to place all outputs in tri-state mode. This pin is referenced to VCCA. VCCA 1 I A-port supply voltage. 1.65 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB. VCCB 14 I B-port supply voltage. 2.3 V ≤ VCCB ≤ 5.5 V. (1) I = input, O = output www.ti.com TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TXS0104E-Q1

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage VCCA –0.5 4.6 V VCCB –0.5 6.5 Input-output pin voltage, VIO (2) A1, A2, A3, A4 A port –0.5 4.6 V B1, B2, B3, B4 B port –0.5 6.5 Output voltage, VO Voltage range applied to any output in the high- impedance or power-off state(2) A port –0.5 4.6 V B port –0.5 6.5 Voltage range applied to any output in the high or low state(2) (3) A port –0.5 VCCA + 0.5 V B port –0.5 VCCB + 0.5 Input clamp current, IIK VI < 0 –50 mA Output clamp current, IOK VO < 0 –50 mA Continuous output current, IO ±50 mA Continuous current through each VCCA, VCCB, or GND ±100 mA Storage temperature range, Tstg –65 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The value of VCCA and VCCB are provided in the recommended operating conditions table.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2500 V Charged-device model (CDM), per AEC Q100-011 ±1500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) VCCA VCCB MIN MAX UNIT VCCA Supply voltage(1) 1.65 3.6 V VCCB Supply voltage(1) 2.3 5.5 VIH(Ax) High-level input voltage A-port I/Os 1.65 to 1.95 V 2.3 to 5.5 V VCCA – 0.2 VCCA V 2.3 to 3.6 V VCCA – 0.4 VCCA VIH(Bx) High-level input voltage B-port I/Os 1.65 to 3.6 V 2.3 to 5.5 V VCCB – 0.4 VCCB VIH(OE) High-level input voltage OE input VCCA × 0.65 5.5 VIL(Ax) Low-level input voltage A-port I/Os 1.65 to 3.6 V 2.3 to 5.5 V 0 0.15 VVIL(Bx) Low-level input voltage B-port I/Os 0 0.15 VIL(OE) Low-level input voltage OE input 0 VCCA × 0.35 Δt/Δv(Ax) Input transition rise or fall rate A-port I/Os, push-pull driving 1.65 to 3.6 V 2.3 to 5.5 V ns/VΔt/Δv(Bx) Input transition rise or fall rate B-port I/Os, push-pull driving 10 Δt/Δv(OE) Input transition rise or fall rate OE input 10 TA Operating free-air temperature –40 125 °C (1) VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V. TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 www.ti.com

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6.4 Thermal Information

over operating free-air temperature range (unless otherwise noted) THERMAL METRIC(1) TXS0104E-Q1 UNITPW (TSSOP)

14 PINS

RθJA Junction-to-ambient thermal resistance 120.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 49.1 °C/W RθJB Junction-to-board thermal resistance 61.8 °C/W ψJT Junction-to-top characterization parameter 6.2 °C/W ψJB Junction-to-board characterization parameter 61.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCCA VCCB MIN TYP MAX UNIT VOH(Ax) High-level output voltage, A port IOH = –20 μA, VOL(Ax) Low-level output voltage, A port IOL = 1 mA, VOH(Bx) High-level output voltage, B port IOH = –20 μA, VOL(Bx) Low-level output voltage, B port IOL = 1 mA, II(OE) Input current, OE VI = VCCI or GND 1.65 to 3.6 V 2.3 to 5.5 V μAVI = VCCI or GND, TA = 25°C ±1 IOZ Off-state output current, A or B port OE = VIL 1.65 to 3.6 V 2.3 to 5.5 V μAOE = VIL, TA = 25°C ±1 ICCA Supply current, A port VI = VO = Open, IO = 0 1.65 to VCCB 2.3 to 5.5 V 4 μA3.6 V 0 2.2 0 5.5 V –1 ICCB Supply current, B port VI = VO = Open, IO = 0 1.65 to VCCB 2.3 to 5.5 V 21 μA3.6 V 0 –1 0 5.5 V 5 ICCA+ICCB Supply current, A port plus B port supply current VI = VO = Open, IO = 0 1.65 V to VCCB 2.3 to 5.5 V 25 μA CI(OE) Input capacitance, OE 3.3 V 3.3 V pF TA = 25°C 2.5 CIO(Ax) Input-output capacitance, A port 3.3 V 3.3 V 6.5 pF TA = 25°C 5 CIO(Bx) Input-output capacitance, B port 16.5 TA = 25°C 12 (1) VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V. www.ti.com TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TXS0104E-Q1

6.6 Timing Requirements—VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Data rate Push-pull driving VCCB = 2.5 V ± 0.2 V 18 Mbps VCCB = 3.3 V ± 0.3 V 21 VCCB = 5 V ± 0.5 V 23 Open-drain driving VCCB = 2.5 V ± 0.2 V 2 VCCB = 3.3 V ± 0.3 V 2 VCCB = 5 V ± 0.5 V 2 tw Pulse duration, data inputs See Figure 7-4 Push-pull driving VCCB = 2.5 V ± 0.2 V 55 ns VCCB = 3.3 V ± 0.3 V 47 VCCB = 5 V ± 0.5 V 43 Open-drain driving VCCB = 2.5 V ± 0.2 V 500 VCCB = 3.3 V ± 0.3 V 500 VCCB = 5 V ± 0.5 V 500 6.7 Timing Requirements—VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Data rate Push-pull driving VCCB = 2.5 V ± 0.2 V 20 Mbps VCCB = 3.3 V ± 0.3 V 22 VCCB = 5 V ± 0.5 V 24 Open-drain driving VCCB = 2.5 V ± 0.2 V 2 VCCB = 3.3 V ± 0.3 V 2 VCCB = 5 V ± 0.5 V 2 tw Pulse duration, data inputs See Figure 7-4 Push-pull driving VCCB = 2.5 V ± 0.2 V 50 ns VCCB = 3.3 V ± 0.3 V 45 VCCB = 5 V ± 0.5 V 41 Open-drain driving VCCB = 2.5 V ± 0.2 V 500 VCCB = 3.3 V ± 0.3 V 500 VCCB = 5 V ± 0.5 V 500 6.8 Timing Requirements—VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Data rate Push-pull driving VCCB = 3.3 V ± 0.3 V 22 Mbps VCCB = 5 V ± 0.5 V 24 Open-drain driving VCCB = 3.3 V ± 0.3 V 2 VCCB = 5 V ± 0.5 V 2 tw Pulse duration, Data inputs See Figure 7-4 Push-pull driving VCCB = 3.3 V ± 0.3 V 45 ns VCCB = 5 V ± 0.5 V 41 Open-drain driving VCCB = 3.3 V ± 0.3 V 500 VCCB = 5 V ± 0.5 V 500 TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 www.ti.com

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6.9 Switching Characteristics—VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tPHL(A-B) Propagation delay time (high to low), from A (input) to B (output) See Figure 7-5 Push-pull driving VCCB = 2.5 V ± 0.2 V 6 ns VCCB = 3.3 V ± 0.3 V 5.8 VCCB = 5 V ± 0.5 V 5.8 Open-drain driving VCCB = 2.5 V ± 0.2 V 8.8 VCCB = 3.3 V ± 0.3 V 9.6 VCCB = 5 V ± 0.5 V 10 tPHL(B-A) Propagation delay time (high to low), from B (input) to A (output) See Figure 7-5 Push-pull driving VCCB = 2.5 V ± 0.2 V 4.4 VCCB = 3.3 V ± 0.3 V 4.5 VCCB = 5 V ± 0.5 V 4.7 Open-drain driving VCCB = 2.5 V ± 0.2 V 5.3 VCCB = 3.3 V ± 0.3 V 4.4 VCCB = 5 V ± 0.5 V 4 tPLH(A-B) Propagation delay time (low to high), from A (input) to B (output) See Figure 7-5 Push-pull driving VCCB = 2.5 V ± 0.2 V 7.7 ns VCCB = 3.3 V ± 0.3 V 6.8 VCCB = 5 V ± 0.5 V 7 Open-drain driving VCCB = 2.5 V ± 0.2 V 50 VCCB = 3.3 V ± 0.3 V 26 VCCB = 5 V ± 0.5 V 33 tPLH(B-A) Propagation delay time (low to high), from B (input) to A (output) See Figure 7-5 Push-pull driving VCCB = 2.5 V ± 0.2 V 5.3 VCCB = 3.3 V ± 0.3 V 4.5 VCCB = 5 V ± 0.5 V 0.5 Open-drain driving VCCB = 2.5 V ± 0.2 V 36 VCCB = 3.3 V ± 0.3 V 16 VCCB = 5 V ± 0.5 V 20 ten(OE-A) ten(OE-B) Enable time, from OE (input) to A or B (output) VCCB = 2.5 V ± 0.2 V 200 nsVCCB = 3.3 V ± 0.3 V 200 VCCB = 5 V ± 0.5 V 200 tdis(OE-A) tdis(OE-B) Disable time, from OE (input) to A or B (output) VCCB = 2.5 V ± 0.2 V 200 nsVCCB = 3.3 V ± 0.3 V 200 VCCB = 5 V ± 0.5 V 200 tr(Ax) Rise time, A port Push-pull driving VCCB = 2.5 V ± 0.2 V 9.5 ns VCCB = 3.3 V ± 0.3 V 9.3 VCCB = 5 V ± 0.5 V 15 Open-drain driving VCCB = 2.5 V ± 0.2 V 38 199 VCCB = 3.3 V ± 0.3 V 30 150 VCCB = 5 V ± 0.5 V 22 109 tr(Bx) Rise time, B port Push-pull driving VCCB = 2.5 V ± 0.2 V 10.8 ns VCCB = 3.3 V ± 0.3 V 9.1 VCCB = 5 V ± 0.5 V 7.6 Open-drain driving VCCB = 2.5 V ± 0.2 V 34 186 VCCB = 3.3 V ± 0.3 V 23 112 VCCB = 5 V ± 0.5 V 10 58 www.ti.com TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TXS0104E-Q1

6.9 Switching Characteristics—VCCA = 1.8 V ± 0.15 V (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tf(Ax) Fall time, A port Push-pull driving VCCB = 2.5 V ± 0.2 V 5.9 ns VCCB = 3.3 V ± 0.3 V 6 VCCB = 5 V ± 0.5 V 13.3 Open-drain driving VCCB = 2.5 V ± 0.2 V 6.9 VCCB = 3.3 V ± 0.3 V 6.4 VCCB = 5 V ± 0.5 V 6.1 tf(Bx) Fall time, B port Push-pull driving VCCB = 2.5 V ± 0.2 V 7.6 VCCB = 3.3 V ± 0.3 V 7.5 VCCB = 5 V ± 0.5 V 8.8 Open-drain driving VCCB = 2.5 V ± 0.2 V 13.8 VCCB = 3.3 V ± 0.3 V 16.2 VCCB = 5 V ± 0.5 V 16.2 tsk Channel-to-channel skew VCCB = 2.5 V ± 0.2 V 1 nsVCCB = 3.3 V ± 0.3 V 1 VCCB = 5 V ± 0.5 V 1 Maximum data rate Push-pull driving VCCB = 2.5 V ± 0.2 V 18 Mbps VCCB = 3.3 V ± 0.3 V 21 VCCB = 5 V ± 0.5 V 23 Open-drain driving VCCB = 2.5 V ± 0.2 V 2 VCCB = 3.3 V ± 0.3 V 2 VCCB = 5 V ± 0.5 V 2 TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 www.ti.com

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6.10 Switching Characteristics—VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tPHL(A-B) Propagation delay time (high to low), from A (input) to B (output) See Figure 7-5 Push-pull driving VCCB = 2.5 V ± 0.2 V 3.2 ns VCCB = 3.3 V ± 0.3 V 3.3 VCCB = 5 V ± 0.5 V 3.4 Open-drain driving VCCB = 2.5 V ± 0.2 V 6.3 VCCB = 3.3 V ± 0.3 V 6 VCCB = 5 V ± 0.5 V 5.8 tPHL(B-A) Propagation delay time (high to low), from B (input) to A (output) See Figure 7-5 Push-pull driving VCCB = 2.5 V ± 0.2 V 3 VCCB = 3.3 V ± 0.3 V 3.6 VCCB = 5 V ± 0.5 V 4.3 Open-drain driving VCCB = 2.5 V ± 0.2 V 4.7 VCCB = 3.3 V ± 0.3 V 4.2 VCCB = 5 V ± 0.5 V 4 tPLH(A-B) Propagation delay time (low to high), from A (input) to B (output) See Figure 7-5 Push-pull driving VCCB = 2.5 V ± 0.2 V 3.5 ns VCCB = 3.3 V ± 0.3 V 4.1 VCCB = 5 V ± 0.5 V 4.4 Open-drain driving VCCB = 2.5 V ± 0.2 V 3.5 VCCB = 3.3 V ± 0.3 V 4.1 VCCB = 5 V ± 0.5 V 4.4 tPLH(B-A) Propagation delay time (low to high), from B (input) to A (output) See Figure 7-5 Push-pull driving VCCB = 2.5 V ± 0.2 V 2.5 VCCB = 3.3 V ± 0.3 V 1.6 VCCB = 5 V ± 0.5 V 0.7 Open-drain driving VCCB = 2.5 V ± 0.2 V 2.5 VCCB = 3.3 V ± 0.3 V 1.6 VCCB = 5 V ± 0.5 V 1 ten(OE-A) ten(OE-B) Enable time, from OE (input) to A or B (output) VCCB = 2.5 V ± 0.2 V 200 nsVCCB = 3.3 V ± 0.3 V 200 VCCB = 5 V ± 0.5 V 200 tdis(OE-A) tdis(OE-B) Disable time, from OE (input) to A or B (output) VCCB = 2.5 V ± 0.2 V 200 nsVCCB = 3.3 V ± 0.3 V 200 VCCB = 5 V ± 0.5 V 200 tr(Ax) Rise time, A port Push-pull driving VCCB = 2.5 V ± 0.2 V 7.4 ns VCCB = 3.3 V ± 0.3 V 6.6 VCCB = 5 V ± 0.5 V 5.6 Open-drain driving VCCB = 2.5 V ± 0.2 V 34 180 VCCB = 3.3 V ± 0.3 V 28 150 VCCB = 5 V ± 0.5 V 24 105 tr(Bx) Rise time, B port Push-pull driving VCCB = 2.5 V ± 0.2 V 8.3 ns VCCB = 3.3 V ± 0.3 V 7.2 VCCB = 5 V ± 0.5 V 6.1 Open-drain driving VCCB = 2.5 V ± 0.2 V 35 170 VCCB = 3.3 V ± 0.3 V 24 120 VCCB = 5 V ± 0.5 V 12 64 tf(Ax) Fall time, A port Push-pull driving VCCB = 2.5 V ± 0.2 V 5.7 ns VCCB = 3.3 V ± 0.3 V 5.5 VCCB = 5 V ± 0.5 V 5.3 Open-drain driving VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V 5.8 www.ti.com TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TXS0104E-Q1

6.10 Switching Characteristics—VCCA = 2.5 V ± 0.2 V (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tf(Bx) Fall time, B port Push-pull driving VCCB = 2.5 V ± 0.2 V 7.8 ns VCCB = 3.3 V ± 0.3 V 6.7 VCCB = 5 V ± 0.5 V 6.6 Open-drain driving VCCB = 2.5 V ± 0.2 V 8.8 VCCB = 3.3 V ± 0.3 V 9.4 VCCB = 5 V ± 0.5 V 10.4 tsk Channel-to-channel skew VCCB = 2.5 V ± 0.2 V 1 nsVCCB = 3.3 V ± 0.3 V 1 VCCB = 5 V ± 0.5 V 1 Maximum data rate Push-pull driving VCCB = 2.5 V ± 0.2 V 20 Mbps VCCB = 3.3 V ± 0.3 V 22 VCCB = 5 V ± 0.5 V 24 Open-drain driving VCCB = 2.5 V ± 0.2 V 2 VCCB = 3.3 V ± 0.3 V 2 VCCB = 5 V ± 0.5 V 2 TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 www.ti.com

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6.11 Switching Characteristics—VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tPHL(A-B) Propagation delay time (high to low), from A (input) to B (output) See Figure 7-5 Push-pull driving VCCB = 3.3 V ± 0.3 V 2.4 ns VCCB = 5 V ± 0.5 V 3.1 Open-drain driving VCCB = 3.3 V ± 0.3 V 4.2 VCCB = 5 V ± 0.5 V 4.6 tPHL(B-A) Propagation delay time (high to low), from B (input) to A (output) See Figure 7-5 Push-pull driving VCCB = 3.3 V ± 0.3 V 2.5 VCCB = 5 V ± 0.5 V 3.3 Open-drain driving VCCB = 3.3 V ± 0.3 V 124 VCCB = 5 V ± 0.5 V 97 tPLH(A-B) Propagation delay time (low to high), from A (input) to B (output) See Figure 7-5 Push-pull driving VCCB = 3.3 V ± 0.3 V 4.2 ns VCCB = 5 V ± 0.5 V 4.4 Open-drain driving VCCB = 3.3 V ± 0.3 V 4.2 VCCB = 5 V ± 0.5 V 4.4 tPLH(B-A) Propagation delay time (low to high), from B (input) to A (output) See Figure 7-5 Push-pull driving VCCB = 3.3 V ± 0.3 V 2.5 VCCB = 5 V ± 0.5 V 2.6 Open-drain driving VCCB = 3.3 V ± 0.3 V 2.5 VCCB = 5 V ± 0.5 V 3.3 ten(OE-A) ten(OE-B) Enable time, from OE (input) to A or B (output) VCCB = 3.3 V ± 0.3 V 200 ns VCCB = 5 V ± 0.5 V 200 tdis(OE-A) tdis(OE-B) Disable time,from OE (input) to A or B (output) VCCB = 3.3 V ± 0.3 V 200 ns VCCB = 5 V ± 0.5 V 200 tr(Ax) Rise time, A port Push-pull driving VCCB = 3.3 V ± 0.3 V 5.6 ns VCCB = 5 V ± 0.5 V 5 Open-drain driving VCCB = 3.3 V ± 0.3 V 25 140 VCCB = 5 V ± 0.5 V 19 102 tr(Bx) Rise time, B port Push-pull driving VCCB = 3.3 V ± 0.3 V 6.4 ns VCCB = 5 V ± 0.5 V 7.4 Open-drain driving VCCB = 3.3 V ± 0.3 V 26 130 VCCB = 5 V ± 0.5 V 14 75 tf(Ax) Fall time, A port Push-pull driving VCCB = 3.3 V ± 0.3 V 5.4 ns VCCB = 5 V ± 0.5 V 5 Open-drain driving VCCB = 3.3 V ± 0.3 V 6.1 VCCB = 5 V ± 0.5 V 5.7 tf(Bx) Fall time, B port Push-pull driving VCCB = 3.3 V ± 0.3 V 7.4 ns VCCB = 5 V ± 0.5 V 7.6 Open-drain driving VCCB = 3.3 V ± 0.3 V 7.6 VCCB = 5 V ± 0.5 V 8.3 tsk Channel-to-channel skew VCCB = 3.3 V ± 0.3 V 1 ns VCCB = 5 V ± 0.5 V 1 Maximum data rate Push-pull driving VCCB = 3.3 V ± 0.3 V 22 Mbps VCCB = 5 V ± 0.5 V 24 Open-drain driving VCCB = 3.3 V ± 0.3 V 2 VCCB = 5 V ± 0.5 V 2 www.ti.com TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TXS0104E-Q1

6.12 Typical Characteristics

Low-Level Current (mA) Low-Level Output Voltage (mV) 0 2 4 6 8 10 12 14 16 18 20 100 200 300 400 500 600 700 D001 VCCB = 2.7 V VCCB = 3.3 V VCCB = 5 V VCCA = 1.8 V VIL(A) = 150 mV Figure 6-1. Low-Level Output Voltage (VOL(Ax)) vs Low-Level Current (IOL(Ax)) Low-Level Current (mA) Low-Level Output Voltage (mV) 0 2 4 6 8 10 12 14 16 18 20 100 200 300 400 500 600 700 D003 VCCB = 3.3 V VCCB = 5 V VCCA = 2.7 V VIL(A) = 150 mV Figure 6-2. Low-Level Output Voltage (VOL(Ax)) vs Low-Level Current (IOL(Ax)) Low-Level Current (mA) Low-Level Output Voltage (mV) 0 2 4 6 8 10 12 14 16 18 20 100 200 300 400 500 600 700 D002 VCCB = 3.3 V VCCA = 3.3 V VIL(A) = 150 mV Figure 6-3. Low-Level Output Voltage (VOL(Ax)) vs Low-Level Current (IOL(Ax)) TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 www.ti.com

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7 Parameter Measurement Information

7.1 Load Circuits

Figure 7-1. Data Rate, Pulse Duration, Propagation Delay, Output Rise-Time and Fall-Time Measurement Using a Push-Pull Driver 1 M 15 pF VCCOVCCI DUT IN OUT Figure 7-2. Data Rate, Pulse Duration, Propagation Delay, Output Rise-Time and Fall-Time Measurement Using an Open-Drain Driver From Output Under Test 2 × VCCO 50 k 50 k 15 pF Open TEST S1 tPZL / tPLZ (tdis) 2 × VCCO tPHZ / tPZH (ten) Open Figure 7-3. Load Circuit for Enable-Time and Disable-Time Measurement 1. tPLZ and tPHZ are the same as tdis. 2. tPZL and tPZH are the same as ten. 3. VCCI is the VCC associated with the input port. 4. VCCO is the VCC associated with the output port. www.ti.com TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TXS0104E-Q1

7.2 Voltage Waveforms

Figure 7-4. Pulse Duration tPLH tPHL VCCI 0 V V / 2CCO VOH VOL Input Output V / 2CCI V / 2CCI 0.9 × VCCOV / 2CCO tr 0.1 × VCCO tf Figure 7-5. Propagation Delay Times Output Waveform 1 S1 at 2 × V (see Note 2) CCO VOH VOL OE input Output Waveform 2 S1 at GND (see Note 2) tPZL tPZH tPLZ tPHZ V / 2CCAV / 2CCA 0 V VOH × 0.1 V / 2CCO VOH × 0.9 V / 2CCO 0 V VCCA VOH 1. CL includes probe and jig capacitance. 2. Waveform 1 in Figure 7-6 is for an output with internal such that the output is high, except when OE is high (see Figure 7-3). Waveform 2 in Figure 7-6 is for an output with conditions such that the output is low, except when OE is high. 3. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns. 4. The outputs are measured one at a time, with one transition per measurement. 5. tPLZ and tPHZ are the same as tdis. 6. tPZL and tPZH are the same as ten. 7. tPLH and tPHL are the same as tpd. 8. VCCI is the VCC associated with the input port. 9. VCCO is the VCC associated with the output port. Figure 7-6. Enable and Disable Times TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 www.ti.com

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8 Detailed Description

8.1 Overview

The TXS0104E-Q1 device is a directionless voltage-level translator specifically designed for translating logic voltage levels. The A port is able to accept I/O voltages ranging from 1.65 V to 3.6 V, while the B port can accept I/O voltages from 2.3 V to 5.5 V. The device is a pass gate architecture with edge rate accelerators (one shots) to improve the overall data rate. 10-k Ω pullup resistors, commonly used in open drain applications, have been conveniently integrated so that an external resistor is not needed. While this device is designed for open drain applications, the device can also translate push-pull CMOS logic outputs.

8.2 Functional Block Diagram

Copyright © 2016, Texas Instruments Incorporated www.ti.com TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TXS0104E-Q1

8.3 Feature Description

8.3.1 Architecture

The TXS0104E-Q1 architecture (see Figure 8-1) does not require a direction-control signal in order to control the direction of data flow from A to B or from B to A. VCCA A B 10 kΩ10 kΩ T2T1 VCCB One-shot One-shot Gate Bias Figure 8-1. Architecture of a TXS01xx Cell Each A-port I/O has an internal 10-k Ω pullup resistor to V CCA, and each B-port I/O has an internal 10-k Ω pullup resistor to VCCB. The output one-shots detect rising edges on the A or B ports. During a rising edge, the one-shot turns on the PMOS transistors (T1, T2) for a short duration which speeds up the low-to-high transition.

8.3.2 Input Driver Requirements

The fall time (tfA, tfB) of a signal depends on the output impedance of the external device driving the data I/Os of the TXS0104E-Q1 device. Similarly, the t PHL and maximum data rates also depend on the output impedance of the external driver. The values for tfA, tfB, tPHL, and maximum data rates in the data sheet assume that the output impedance of the external driver is less than 50 Ω.

8.3.3 Power Up

During operation, ensure that V CCA ≤ VCCB at all times. During power-up sequencing, V CCA ≥ VCCB does not damage the device, so any power supply can be ramped up first.

8.3.4 Enable and Disable

The TXS0104E-Q1 device has an OE input that disables the device by setting OE low, which places all I/Os in the high-impedance state. The disable time (tdis) indicates the delay between the time when the OE pin goes low and when the outputs actually enter the high-impedance state. The enable time (ten) indicates the amount of time the user must allow for the one-shot circuitry to become operational after the OE pin is taken high.

8.3.5 Pull Up and Pull Down Resistors on I/O Lines

Each A-port I/O has an internal 10-k Ω pullup resistor to V CCA, and each B-port I/O has an internal 10-k Ω pullup resistor to VCCB. If a smaller value of pullup resistor is required, an external resistor must be added from the I/O to VCCA or VCCB (in parallel with the internal 10-kΩ resistors).

8.4 Device Functional Modes

The TXS0104E-Q1 device has two functional modes, enabled and disabled. To disable the device set the OE input low, which places all I/Os in a high impedance state. Setting the OE input high will enable the device. TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TXS0104E-Q1 device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. The TXS0104E-Q1 device is optimal for use in applications where an open-drain driver is connected to the data I/Os. The TXS0104E-Q1 device can also be used in applications where a push-pull driver is connected to the data I/Os, but the TXB0104-Q1 device might be a better option for such push-pull applications.

9.2 Typical Application

TXS0104E-Q1 3.3-V System 1.8-V System Controller Data Data OE VCCA VCCB 1.8 V 3.3 V GND 0.1 µF 0.1 µF Copyright © 2016, Texas Instruments Incorporated Figure 9-1. Application Schematic

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-1. Table 9-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 1.65 to 3.6 V Output voltage range 2.3 to 5.5 V

9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

• Input voltage range – Use the supply voltage of the device that is driving the TXS0104E-Q1 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port.
• Output voltage range – Use the supply voltage of the device that the TXS0104E-Q1 device is driving to determine the output voltage range. – The TXS0104E-Q1 device has 10-kΩ internal pullup resistors. External pullup resistors can be added to reduce the total RC of a signal trace if necessary. www.ti.com TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TXS0104E-Q1

• An external pull down resistor decreases the output VOH and VOL. Use Equation 1 to calculate the VOH as a result of an external pull down resistor. V O H = V C Cx × R P D / R P D + 10 k Ω (1) where
• VCCx is the supply voltage on either VCCA or VCCB
• RPD is the value of the external pull down resistor

9.2.3 Application Curve

2 V/div

VCCA = 1.8 V VCCB = 5 V Figure 9-2. Level-Translation of a 2.5-MHz Signal

9.3 Power Supply Recommendations

The TXS0104E-Q1 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCB accepts any supply voltage from 2.3 V to 5.5 V and V CCA accepts any supply voltage from 1.65 V to 3.6 V as long as Vs is less than or equal to V CCB. The A port and B port are designed to track V CCA and VCCB respectively allowing for low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. The TXS0104E-Q1 device does not require power sequencing between V CCA and VCCB during power-up so the power-supply rails can be ramped in any order. A V CCA value greater than or equal to V CCB (VCCA ≥ VCCB) does not damage the device, but during operation, V CCA must be less than or equal to V CCB (VCCA ≤ V CCB) at all times. The output-enable (OE) input circuit is designed so that it is supplied by V CCA and when the (OE) input is low, all outputs are placed in the high-impedance state. To enable the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to GND through a pull down resistor and must not be enabled until VCCA and VCCB are fully ramped and stable. The minimum value of the pull down resistor to ground is determined by the current-sourcing capability of the driver. TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 www.ti.com

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9.4 Layout

9.4.1 Layout Guidelines

For reliability of the device, following common printed-circuit board layout guidelines is recommended.

• Bypass capacitors should be used on power supplies.
• Short trace lengths should be used to avoid excessive loading.
• PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than the one shot duration, approximately 30 ns, ensuring that any reflection encounters low impedance at the source driver.
• Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of signals depending on the system requirements

9.4.2 Layout Example

VIA to GND Plane (Inner Layer) Polygonal Copper Pour To System To System To System To System To Controller To Controller To Controller To Controller Keep OE low until VCCA and VCCB are powered up Pads on signal paths for potential rise and fall time adjustments Bypass Capacitors Figure 9-3. TXS0104E-Q1 Layout Example www.ti.com TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TXS0104E-Q1

10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Introduction to Logic application note

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

11 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TXS0104E-Q1 SCES853D – NOVEMBER 2013 – REVISED JUNE 2023 www.ti.com

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www.ti.com 11-Jun-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTXS0104EQWBQARQ1 ACTIVE WQFN BQA 14 3000 TBD Call TI Call TI -40 to 125 Samples TXS0104EQPWRQ1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 04EQ1 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 11-Jun-2023 OTHER QUALIFIED VERSIONS OF TXS0104E-Q1 :

• Catalog : TXS0104E NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TXS0104EQPWRQ1 TSSOP PW 14 2000 356.0 356.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightBQA 14 PLASTIC QUAD FLATPACK - NO LEAD2.5 x 3, 0.5 mm pitch 4227145/A

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