PTXG4042QRUCRQ1

TXG4041-Q1 TI | Alldatasheet

Document overview

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Technical content

TXG404x-Q1 4-Bit, ±40V Ground-Level Translator

1 Features

• Supports DC ground shifts up to ±40V
• AC Noise Rejection up to 130VPP at 1MHz and CMTI of 1kV/µs
• Low Prop Delay (8.5ns max) and Ch-Ch Skew (2ns max)
• 100Mbps data rate
• Low power consumption (0.7mA per channel at 1Mbps, 1.8V)
• Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
• 4, 2, 1 channel devices with multiple configurations will be available
• Two device variants: – TXG4041: 3 forward, 1 reverse – TXG4042: 2 forward, 2 reverse
• Supports VCC disconnect feature (I/Os are forced into high-Z)
• Schmitt-trigger inputs allows for slow and noisy signals
• Inputs with integrated static pull-down resistors prevent channels from floating
• Operating temperature from –40°C to +125°C
• Latch-up performance exceeds 100mA per JESD 78, class II
• ESD protection exceeds JESD 22 – 2000V human-body model – 500V charged-device model
• Package option: RUC (X2QFN-14)

2 Applications

• Electric Power Steering
• Vehicle Control Unit
• Automotive Display
• Head Unit and Digital Cockpit
• Test and Measurement
• Factory Automation
• Appliances

3 Description

The TXG404x-Q1 is a 4-bit, fixed direction, non- galvanic based voltage and ground-level translator that can support both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ±40V. Compared to traditional level shifters, the TXG404x-Q1 family can solve the challenges of voltage translation across different ground levels. The Simplified Block Diagram shows a common use case where there is a DC shift between GNDA to GNDB due to parasitic resistance or capacitance. VCCA is referenced to GNDA and V CCB is referenced to GNDB. Ax pins are referenced to V CCA logic levels while Bx pins are referenced to V CCB logic levels. Both A port and B port can accept voltages from 1.71V to 5.5V. This device includes two enable pins that can place the respective outputs in a high- impedance state when the OE pin is connected to GND or left floating. In the event of input power or signal loss, the output is default low when OE is High (refer to Table 7-1). The max leakage between GNDA and GNDB is 2µA when VCC to GND is shorted. The TXG404x-Q1 device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency and channel-to-channel skew. It can supress noise levels at 130V PP up to 1MHz ( Figure 6-1 ). This device can support multiple interfaces such as SPI, UART, GPIO, and I2S.

Package Information

PART NUMBER PACKAGE (1) BODY SIZE (NOM) TXG4041-Q1 TXG4042-Q1 RUC (X2QFN-14) 2.00mm × 2.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. System #1 System #2INx OUTx VccA GndA VccB GndB TXG VccA GndA VccB GndB Parasi c capacitance/ resistance <40V Simplified Block Diagram ADVANCE INFORMATION TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

11 Mechanical, Packaging, and Orderable

TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 www.ti.com

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4 Pin Configuration and Functions

5OE_A VCCBVCCA

12 OUTA

11 OUTB

10 OUTC

9 IND

8 OE_B

Figure 4-1. TXG4041RUC Package 14-Pin X2QFN Top View 1INA 3OUTC 4OUTD 5OE_A VCCBVCCA

10 INC

Figure 4-2. TXG4042RUC Package 14-Pin X2QFN Top View Table 4-1. TXG404x RUC Pin Functions PIN I/O DESCRIPTION Name TXG4041 TXG4042 INA 1 1 I Input Channel A INB 2 2 I Input Channel B INC 3 10 I Input Channel C IND 9 9 I Input Channel D OUTA 12 12 O Output Channel A OUTB 11 11 O Output Channel B OUTC 10 3 O Output Channel C OUTD 4 4 O Output Channel D OE_A 5 5 I Active-High Output Enable (A side). Pull to GND to place all outputs in high- impedance mode. OE_B 8 8 I Active-High Output Enable (B side). Pull to GND to place all outputs in high- impedance mode. VCCA 14 14 — A side supply voltage. 1.71 V ≤ VCCA ≤ 5.5 V VCCB 13 13 — B side supply voltage. 1.71 V ≤ VCCB ≤ 5.5 V GNDA 6 6 — Ground reference for VCCA GNDB 7 7 — Ground reference for VCCB www.ti.com TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 ADVANCE INFORMATION

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCCA to VGNDA Supply voltage A to Ground voltage A –0.5 6.5 V VCCB to VGNDB Supply voltage B to Ground voltage B –0.5 6.5 V VGNDA to VGNDB Ground voltage B to Ground voltage A -42 42 V VI Input Voltage(2) I/O Ports (A Port) to VGNDA –0.5 6.5 V I/O Ports (B Port) to VGNDB –0.5 6.5 OE –0.5 6.5 V VO Voltage applied to any output in the high-impedance or power-off state(2) A Port to VGNDA –0.5 6.5 V B Port to VGNDB –0.5 6.5 VO Voltage applied to any output in the high or low state(2) (3) A Port to VGNDA –0.5 VCCA + 0.5 V B Port to VGNDB –0.5 VCCB + 0.5 IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –20 mA IO Continuous output current –25 25 mA Continuous current through VCC or GND –100 100 mA Tj Junction Temperature 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Section 5.1 may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 5.3 Exposure beyond the limits listed in Section 5.3 may affect device reliability. (2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 6.5V maximum if the output current rating is observed.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2500 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002 ±500 TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 www.ti.com

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5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN TYP MAX UNIT VCCA Supply voltage A - Relative to GNDA 1.71 5.5 V VCCB Supply voltage B - Relative to GNDB 1.71 5.5 V VGNDA - VGNDB Voltage Between GNDA and GNDB -40 40 V IOH High-level output current VCCO = 1.71 V -4.5 mA VCCO = 2.3 V -8 VCCO = 3 V -10 VCCO = 4.5 V -12 IOL Low-level output current VCCO = 1.71V 4.5 mA VCCO = 2.3 V 8 VCCO = 3 V 10 VCCO = 4.5 V 12 VI Input voltage - Relative to GNDx 0 5.5 V VIH High-level input voltage 0.7 x VCCI V VIL High-level output voltage 0.3 x VCCI V VO Output voltage - Relative to GNDx 0 VCCO V TA Operating free-air temperature –40 125 °C (1) VCCI is the VCC associated with the input port. (2) VCCO is the VCC associated with the output port. (3) All control inputs and data I/Os of this device have weak pulldowns to ensure the line is not floating when undefined external to the device. The input leakage from these weak pulldowns is defined by the II specification indicated under Section 5.4. www.ti.com TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 ADVANCE INFORMATION

5.4 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 125°C MIN TYP MAX VOH High-level output voltage (3) IOH = –4.5 mA 1.71 V 1.71 V 1.5 V IOH = –8 mA 2.3 V 2.3 V 2.0 IOH = –10 mA 3 V 3 V 2.7 IOH = –12 mA 4.5 V 4.5 V 4.1 VOL Low-level output voltage (4) IOL = 4.5 mA 1.71 V 1.71 V 0.16 V IOL = 8 mA 2.3 V 2.3 V 0.27 IOL = 10 mA 3 V 3 V 0.34 IOL = 12 mA 4.5 V 4.5 V 0.41 VT+ Positive-going input-threshold voltage Data Inputs (Ax, Bx) (Referenced to VCCI) 1.71 V 1.71 V 1.11 V 2.3 V 2.3 V 1.40 3 V 3 V 1.73 4.5 V 4.5 V 2.45 5.5 V 5.5 V 3.0 VT+ Positive-going input-threshold voltage OE (Referenced to VCCA or VCCB) 1.71 V 1.71 V 1.10 V 2.3 V 2.3 V 1.40 3 V 3 V 1.72 4.5 V 4.5 V 2.45 5.5 V 5.5 V 2.96 VT- Negative-going input-threshold voltage Data Inputs (Ax, Bx) (Referenced to VCCI) 1.71 V 1.71 V 0.56 V 2.3 V 2.3 V 0.80 3 V 3 V 1.15 4.5 V 4.5 V 1.61 5.5 V 5.5 V 2.0 VT- Negative-going input-threshold voltage OE (Referenced to VCCA or VCCB) 1.71 V 1.71 V 0.5 0.72 V 2.3 V 2.3 V 0.80 0.87 3 V 3 V 1.1 1.23 4.5 V 4.5 V 1.7 1.96 5.5 V 5.5 V 2.2 2.43 ΔVT Input-threshold hysteresis (VT+ – VT-) Data Inputs (Ax, Bx) (Referenced to VCCI) 1.71 V 1.71 V 0.3 0.50 V 2.3 V 2.3 V 0.36 0.60 3 V 3 V 0.38 0.54 4.5 V 4.5 V 0.41 0.82 5.5 V 5.5 V 0.40 0.96 ΔVT Input-threshold hysteresis (VT+ – VT-) OE (Referenced to VCCA or VCCB) 1.71 V 1.71 V 0.29 0.45 V 2.3 V 2.3 V 0.35 0.58 3 V 3 V 0.38 0.54 4.5 V 4.5 V 0.41 0.58 5.5 V 5.5 V 0.43 0.62 II Input leakage current Data Inputs (Ax, Bx) VI = VCCI or GND TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 www.ti.com

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over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 125°C MIN TYP MAX Ioff Partial power down current A Port or B Port VI = 1.71 V - 5.5 V 0 V 0 V - 5.5 V –5 5 µA 0 V - 5.5 V 0 V –5 5 µA Ioff-float Floating supply Partial power down current A Port or B Port VI = GND Floating(5) 0 V - 5.5 V –2.5 2.5 µA 0 V - 5.5 V Floating(5) –2.5 2.5 IO Tri-state output Output current A or B Port: VI = VCCA or VGNDA OE = GND 1.71V – 5.5V 1.1V – 5.5V –5 5 µA Ci Control Input Capacitance VI = 3.3 V or VGNDA 3.3 V 3.3 V 1 2 pF Cio Data I/O Capacitance OE = GND, VO = 1.71V DC +1 MHz -16 dBm sine wave 3.3 V 3.3 V 1 3 pF CGND Cap between grounds All channels combined (VCC both sides are powered on) 46 pF CGND Cap between grounds All channels combined (VCC to GND shorted) 53 pF Leakage Current Leakage between GndA to GndB All channels combined (VCC both sides are powered on and inputs are all low) 1.71V – 5.5V 1.71V – 5.5V 2 µA Leakage Current Leakage between GndA to GndB All channels combined (VCC both sides are powered on and inputs are all high) 1.71V – 5.5V 1.71V – 5.5V 44 µA Leakage Current Leakage between GndA to GndB All channels combined (VCC to GND shorted) 1.71V – 5.5V 1.71V – 5.5V 2 µA CMTI Common Mode Transient Immunity Input toggling at 100Mbps Ground shift up to 40V 1.71V – 5.5V 1.71V – 5.5V 1 kV/µs ICCA VCCA supply current VI = VCCI or GND IO = 0 1.71V – 5.5V 1.71V – 5.5V 546 1220 µA 0 V 5.5 V -3 13

5.5 V 0 V 509 1050

VI = GND IO = 0 5.5 V Floating(5) 509 1050 ICCB VCCB supply current VI = VCCI or GND IO = 0 1.71V – 5.5V 1.71V – 5.5V 760 1836 µA 0 V 5.5 V 654 1350

5.5 V 0 V -3 36

VI = GND IO = 0 Floating(5) 5.5 V 656 1350 ICCA + ICCB Supply Current - Disable EN = 0 1.8V 1.8V 1.9 3.1 mA 2.5V 2.5V 1.9 3.1 3.3V 3.3V 2.0 3.1 5V 5V 2.1 3.3 www.ti.com TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 ADVANCE INFORMATION

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 125°C MIN TYP MAX ICCA + ICCB Supply Current - DC Signal VI = VCCI 1.8V 1.8V 1 2.65 mA 2.5V 2.5V 1.3 2.7 3.3V 3.3V 1.3 2.8 5V 5V 1.4 3.1 VI = GND 1.8V 1.8V 1.2 2.7 mA 2.5V 2.5V 1.3 2.7 3.3V 3.3V 1.3 2.8 5V 5V 1.4 3.1 ICCA + ICCB Supply Current - AC Signal All channels switching with square wave clock input; CL = 15 pF, 1Mbps 1.8V 1.8V 1.5 2.6 mA 2.5V 2.5V 1.6 2.7 3.3V 3.3V 1.6 2.8 5V 5V 1.9 3.3 All channels switching with square wave clock input; CL = 15 pF, 50Mbps 1.8V 1.8V 9.2 12.1 mA 2.5V 2.5V 10.8 14 3.3V 3.3V 12.4 16.2 5V 5V 17.6 20.6 All channels switching with square wave clock input; CL = 15 pF, 100Mbps 1.8V 1.8V 16.5 20.1 mA 2.5V 2.5V 20.2 24.7 3.3V 3.3V 24.1 29 5V 5V 35 38 VUVLO+ Positive-Going Undervoltage Lockout Voltage A Supply 1.71V – 5.5V 1548 mV B Supply 1.71V – 5.5V 1548 VUVLO- Negative-Going Undervoltage Lockout Voltage A Supply 1.71V – 5.5V 1492 mV B Supply 1.71V – 5.5V 1492 VUVLO_Hys Undervoltage Lockout Hysteresis A Supply 1.71V – 5.5V 35 132 mV B Supply 1.71V – 5.5V 35 132 (1) VCCI is the VCC associated with the input port and referenced to GNDA (2) VCCO is the VCC associated with the output port and referenced to GNDB (3) Tested at VI = VT+(MAX) (4) Tested at VI = VT-(MIN) (5) Floating is defined as a node that is both not actively driven by an external device and has leakage not exeeding 10nA TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 www.ti.com

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5.5 Switching Characteristics, VCCA = 1.8 ± 0.15 V PARAMETER TEST CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay 1Mbps all 4 channels toggling ns tdis Disable time ns OE B -40°C to 85°C 16.1 35 16.1 35 16.1 35 16.1 35 ten Enable time ns PWD Pulse width distortion |tphl - tplh| A B -40°C to 85°C 1.6 1.5 1.4 1.3 ns A B -40°C to 125°C 1.6 1.5 1.4 1.3 B A -40°C to 85°C 1.6 1.5 1.4 1.3 B A -40°C to 125°C 1.6 1.5 1.4 1.4 tr Output signal rise time A B -40°C to 85°C 1.1 1.2 1.5 1.8 ns tf Output signal fall time ns tDO Default output delay time from input power loss Measured from the time VCC goes below 1.49V µs tPU Time from ULVO to valid output data µs www.ti.com TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 ADVANCE INFORMATION Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9

5.6 Switching Characteristics, VCCA = 2.5 ± 0.2 V PARAMETER TEST CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay 1Mbps all 4 channels toggling ns tdis Disable time ns ten Enable time ns PWD Pulse width distortion |tphl - tplh| A B -40°C to 85°C 0.9 0.8 0.8 0.7 ns A B -40°C to 125°C 0.9 0.8 0.8 0.7 B A -40°C to 85°C 0.9 0.8 0.8 0.7 B A -40°C to 125°C 0.9 0.8 0.8 0.7 tr Output signal rise time ns B A -40°C to 85°C 0.5 1 0.5 1 0.5 1 0.5 1 tf Output signal fall time ns tDO Default output delay time from input power loss Measured from the time VCC goes below 1.49V) µs tPU Time from ULVO to valid output data -40°C to 85°C 26 61 26 61.1 26 61 26 61 µs TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 www.ti.com

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5.7 Switching Characteristics, VCCA = 3.3 ± 0.3 V PARAMETER TEST CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay 1Mbps all 4 channels toggling ns tdis Disable time ns ten Enable time ns OE B -40°C to 85°C 3 8 3.1 8 3.1 8 3 8 PWD Pulse width distortion |tphl - tplh| A B -40°C to 85°C 0.7 0.6 0.5 0.5 ns A B -40°C to 125°C 0.7 0.6 0.5 0.5 B A -40°C to 85°C 0.7 0.6 0.5 0.5 B A -40°C to 125°C 0.7 0.6 0.5 0.5 tr output signal rise time ns tf output signal fall time ns tDO Default output delay time from input power loss Measured from the time VCC goes below 1.49V µs tPU Time from ULVO to valid output data -40°C to 85°C 26 61 26 61.1 26 61 26 61 µs www.ti.com TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 ADVANCE INFORMATION Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11

5.8 Switching Characteristics, VCCA = 5.0 ± 0.5 V PARAMETER TEST CONDITIONS FRO M TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay 1Mbps all 4 channels toggling ns tdis Disable time ns ten Enable time ns PWD Pulse width distortion |tphl - tplh| A B -40°C to 85°C 0.5 0.4 0.3 0.3 ns A B -40°C to 125°C 0.5 0.4 0.3 0.3 B A -40°C to 85°C 0.5 0.4 0.3 0.3 B A -40°C to 125°C 0.5 0.4 0.3 0.3 tr Output signal rise time ns tf Output signal fall time ns tDO Default output delay time from input power loss Measured from the time VCC goes below 1.49V µs tPU Time from ULVO to valid output data µs TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 www.ti.com

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5.9 Switching Characteristics: Tsk, TMAX

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCI VCCO Operating free-air temperature (TA) UNIT-40°C to 125°C MIN TYP MAX TMAX Maximum Data Rate 50% Duty Cycle Input One channel switching 20% of pulse > 0.7*VCCO 20% of pulse < 0.3*VCCO No Translation 1.65 V - 1.95 V 1.65 V - 1.95 V 100 Mbps 2.3 V - 2.7 V 2.3 V - 2.7 V 100 Mbps 3.0 V - 3.6 V 3.0 V - 3.6 V 100 Mbps 4.5 V - 5.5 V 4.5 V - 5.5 V 100 Mbps Up Translation 1.65 V - 1.95 V 2.3 V - 2.7 V 100 Mbps 1.65 V - 1.95 V 3.0 V - 3.6 V 100 Mbps 1.65 V - 1.95 V 4.5 V - 5.5 V 100 Mbps 2.3 V - 2.7 V 3.0 V - 3.6 V 100 Mbps 2.3 V - 2.7 V 4.5 V - 5.5 V 100 Mbps 3.0 V - 3.6 V 4.5 V - 5.5 V 100 Mbps Down Translation 2.3 V - 2.7 V 1.65 V - 1.95 V 100 Mbps 3.0 V - 3.6 V 2.3 V - 2.7 V 100 Mbps 3.0 V - 3.6 V 1.65 V - 1.95 V 100 Mbps 4.5 V - 5.5 V 3.0 V - 3.6 V 100 Mbps 4.5 V - 5.5 V 2.3 V - 2.7 V 100 Mbps 4.5 V - 5.5 V 1.65 V - 1.95 V 100 Mbps www.ti.com TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 ADVANCE INFORMATION Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCI VCCO Operating free-air temperature (TA) UNIT-40°C to 125°C MIN TYP MAX tsk Output skew Timing skew between any switching outputs on the rising or falling edge (same direction channels) No Translation 1.65 V - 1.95 V 1.65 V - 1.95 V 2 ns 2.3 V - 2.7 V 2.3 V - 2.7 V 2 ns 3.0 V - 3.6 V 3.0 V - 3.6 V 2 ns 4.5 V - 5.5 V 4.5 V - 5.5 V 2 ns Up Translation 1.65 V - 1.95 V 2.3 V - 2.7 V 2 ns 1.65 V - 1.95 V 3.0 V - 3.6 V 2 ns 1.65 V - 1.95 V 4.5 V - 5.5 V 2 ns 2.3 V - 2.7 V 3.0 V - 3.6 V 2 ns 2.3 V - 2.7 V 4.5 V - 5.5 V 2 ns 3.0 V - 3.6 V 4.5 V - 5.5 V 2 ns Down Translation 2.3 V - 2.7 V 1.65 V - 1.95 V 2 ns 3.0 V - 3.6 V 2.3 V - 2.7 V 2 ns 3.0 V - 3.6 V 1.65 V - 1.95 V 2 ns 4.5 V - 5.5 V 3.0 V - 3.6 V 2 ns 4.5 V - 5.5 V 2.3 V - 2.7 V 2 ns 4.5 V - 5.5 V 1.65 V - 1.95 V 2 ns TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 www.ti.com

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6 AC Noise Tolerance

TXG404x supports I/O voltage translation in environments with noisy grounds. The plot below illustrates the amount of noise that TXG404x can reject in terms of peak-to-peak voltage over frequency. F r e q u e n c y ( k H z ) Amplitude (VPP) 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 E + 7 1 E + 8 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 8 0 Figure 6-1. AC Noise Rejection Plot www.ti.com TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 ADVANCE INFORMATION

7 Detailed Description

7.1 Overview

The TXG404x-Q1 is a 4-bit translating transceiver that uses two individually configurable power-supply rails. The device is operational with V CCA and VCCB supplies as low as 1.71V and as high as 5.5V. The A port is designed to track V CCA, and the B port is designed to track V CCB. In addition to I/O level shifting, the device supports ground mismatch between two systems up to +/-40V. The TXG404x-Q1 device is designed for asynchronous communication between data buses, and transmits data with fixed direction from the A bus to the B bus on some channels and from the B bus to the A bus on the remaining channels. The output-enable input (OE) is used to disable the outputs so the buses are effectively isolated. The output-enable pin (OE) can be referenced to either VCCA or VCCB. The OE pin can be left floating or externally pulled down to ground to keep the level shifter outputs in a high-impedance state during power-up or power-down. This device is fully specified for partial-power-down applications using the I off current. The Ioff protection circuitry ensures that no excessive current is drawn from or sourced into an input or output while the device is powered down. The V CC disconnect feature ensures that if V CC is disconnected with the complementary supply within recommended operating conditions, outputs are disabled and set to the high-impedance state while the supply current is maintained. The I off-float circuitry ensures that no excessive current is drawn from or sourced into an input or output while the supply is floating. Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing robust power sequencing performance.

7.2 Functional Block Diagram

VCC(MIN) TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 www.ti.com

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7.3 Device Functional Modes

Table 7-1. Function Table Power Supply (1) Control Inputs Port Status VCCI VCCO OE Input Output PU PU H H H PU PU H L L PU PU L or Open X Hi-Z PU PU H Open L PD PU H X L X PU L or Open X High-Z X PU H X L X PD X X Undetermined (1) In the table above: PU = Powered Up; PD = Powered Down; X = Irrelevant; H = High Level; L = Low Level; Open = Floating www.ti.com TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 ADVANCE INFORMATION

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TXG404x-Q1 device is used for level translation, enabling communication between devices or systems operating at different interface voltages and ground voltages. Figure 8-1 is an example of two systems that translate from 3.3V to 1.8V across an SPI interface while also experiencing a ground shift of 5V. The ground shift occurs due to the parasitic resistance of the cable used to connect the 48V battery ground and 12V battery ground to the chassis of the car. The TXG404x-Q1 device is ideal for use in applications where a push-pull driver is connected to the data inputs.

8.2 Typical Application

3.3 V 1.8 V 0.1 µF 0.1 µF TXG4041-Q1 CS CS OUT2IN2SCLK SCLK OEA IN3 OUT4 OUT3 IN4 SDO SDI SDI SDO Amplifier 3.3 V GNDA GNDB Chassis GND OEB 1.8 V 48V Battery GND 12V Battery GND 0V -5V Figure 8-1. TXG404x SPI Interface Application in Automotive

8.2.1 Design Requirements

Use the parameters listed in Table 8-1 for this design example. Table 8-1. Design Parameters DESIGN PARAMETERS EXAMPLE VALUES Input voltage range 1.71V to 5.5V Output voltage range 1.71V to 5.5V TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 www.ti.com

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8.2.2 Application Curve

Figure 8-2. Waveform showing -40V (top) and +40V (bottom) Ground Shift with 2.25V to 5V I/O Translation Figure 8-3. Waveform showing 5V to 2.5V I/O Translation with AC Ground Noise of 10kHz at 2VPP www.ti.com TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 ADVANCE INFORMATION

8.3 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing without any supply sequencing requirements such as ramp order or ramp rate. Please make sure the difference between VCC and GND remains at 6.5V max at all times.

8.4 Layout

8.4.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:

• Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1µF capacitor is recommended, but transient performance can be improved by having 1µF and 0.1µF capacitors in parallel as bypass capacitors.
• The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
• A 0.1µF capacitor can be added between GNDA and GNDB to improve performances of CMTI.

8.4.2 Layout Example

B G Legend TXG4041 (RUC Package) IN2 VCCA 0.1uF Power Domain A Power Domain B B 14 13IN1 IN3 OUT4 5OE_A 7 A VCCB GNDA GNDB G G OUT2 OUT1 OUT3 IN4 OE_B G A B G 0.1uF Figure 8-4. Layout Example TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 www.ti.com

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9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Understanding Schmitt Triggers application report
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application report

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES February 2025 * Initial APL Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TXG4041-Q1, TXG4042-Q1 SCES977 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 ADVANCE INFORMATION

www.ti.com 21-Feb-2025 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTXG4041QRUCRQ1 ACTIVE QFN RUC 14 3000 TBD Call TI Call TI -40 to 125 Samples PTXG4042QRUCRQ1 ACTIVE QFN RUC 14 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 21-Feb-2025 Addendum-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. X2QFN - 0.4 mm max heightRUC 14 PLASTIC QUAD FLATPACK - NO LEAD2 x 2, 0.4 mm pitch 4229871/A

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