PTXB0104QWBQARQ1

TXB0104-Q1_V01 TI | Alldatasheet

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Technical content

TXB0104-Q1 4-Bit Bidirectional Voltage-Level Translator with Automatic Direction Sensing and ±15-kV ESD Protection

1 Features

• Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range
• 1.2 V to 3.6 V on A Port and 1.65 V to 5.5 V on B Port (VCCA ≤ VCCB)
• VCC Isolation Feature – If Either VCC Input is at GND, All Outputs are in the High-Impedance State
• OE Input Circuit Referenced to VCCA
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22 – A port
• ±2500-V Human-Body Model (A114-B)
• ±1000-V Charged-Device Model (C101) – B port
• ±15000-V Human-Body Model (A114-B)
• ±1000-V Charged-Device Model (C101)

2 Applications

• Automotive infotainment
• Advanced Driver Assistance System (ADAS)
• Telematics

3 Description

Voltage-level translators address the challenges posed by simultaneous use of different supply-voltage levels on the same circuit board. This 4-bit non- inverting translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V CCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. V CCA should not exceed VCCB. When the output-enable (OE) input is low, all outputs are placed in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. The TXB0104 is designed so that the OE input circuit is supplied by VCCA. This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Device Information PART NUMBER(1) PACKAGE BODY SIZE (NOM) TXB0104-Q1 TSSOP (14) 5.00 mm x 4.40 mm VQFN (14) 3.50 mm x 3.50 mm UQFN (12) 2.00 mm x 1.70 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Processor Peripheral VCCA VCCB Typical Application Block Diagram for TXB010X TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

12.1 Receiving Notification of Documentation Updates..17

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision A (October 2014) to Revision B (June 2023) Page Changes from Revision * (June 2008) to Revision A (October 2014) Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 www.ti.com

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5 Pin Configuration and Functions

14 PINS

(TOPVIEW) GND NC VCCA NC VCCB RGY PACKAGE (TOP VIEW) VCCA VCCB RUT PACKAGE

12 PINS

(TOP VIEW) OE 5A4 OEGND Exposed Center Pad VCCB 7 8 NC NC VCCA A3 4 6 7 1112 7 8 GND NC − No internal connection For RGY, if the exposed center pad is used, it must be connected only to as a secondary ground or left electrically open. Table 5-1. Pin Functions PIN I/O DESCRIPTION NO. NAME 1 VCCA I A-port supply voltage 1.2 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB. 2 A1 I/O Input/output 1. Referenced to VCCA. 3 A2 I/O Input/output 2. Referenced to VCCA. 4 A3 I/O Input/output 3. Referenced to VCCA. 5 A4 I/O Input/output 4. Referenced to VCCA. 6 NC – No connection. Not internally connected.

7 GND – Ground

8 OE I 3-state output-mode enable. Pull OE low to place all outputs in 3-state mode. Referenced to VCCA. 9 NC – No connection. Not internally connected. 10 B4 I/O Input/output 4. Referenced to VCCB. 11 B3 I/O Input/output 3. Referenced to VCCB. 12 B2 I/O Input/output 2. Referenced to VCCB. 13 B1 I/O Input/output 1. Referenced to VCCB. 14 VCCB I B-port supply voltage 1.65 V ≤ VCCB ≤ 5.5 V. www.ti.com TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TXB0104-Q1

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCCA Supply voltage –0.5 4.6 V VCCB –0.5 6.5 VI Input voltage A port –0.5 4.6 V B port –0.5 6.5 VO Voltage applied to any output in the high-impedance or power- off state A port –0.5 4.6 V B port -0.5 6.5 VO Voltage applied to any output in the high or low state(2) A port –0.5 VCCA + 0.5 V B port –0.5 VCCB + 0.5 IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCCA, VCCB, or GND ±100 mA Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The value of VCCA and VCCB are provided in the recommended operating conditions table.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per JEDEC A Port ±2500 V B Port ±15000 Charged-device model (CDM), per JEDEC A Port ±1000 B Port ±1000

6.3 Recommended Operating Conditions

(1) (2) VCCA VCCB MIN MAX UNIT VCCA Supply voltage 1.2 3.6 V VCCB 1.65 5.5 VIH High-level input voltage V VIL Low-level input voltage V VO Voltage range applied to any output in the high- impedance or power-off state A-port 1.2 V to 3.6 V 1.65 V to 5.5 V 0 3.6 V B-port 0 5.5 Δt/Δv Input transition rise or fall rate A-port inputs 1.2 V to 3.6 V 1.65 V to 5.5 V 40 ns/V B-port inputs 1.2 V to 3.6 V 1.65 V to 3.6 V 40 4.5 V to 5.5 V 30 TA Operating free-air temperature –40 125 °C (1) The A and B sides of an unused data I/O pair must be held in the same state, i.e., both at VCCI or both at GND. (2) VCCA must be less than or equal to VCCB and must not exceed 3.6 V. (3) VCCI is the supply voltage associated with the input port. TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 www.ti.com

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6.4 Thermal Information

THERMAL METRIC(1) TXB0104-Q1 UNITPW RGY RUT

14 PINS 14 PINS 12 PINS

RθJA Junction-to-ambient thermal resistance 121 52.8 119.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50 67.7 42.6 RθJB Junction-to-board thermal resistance 62.8 28.9 52.5 ψJT Junction-to-top characterization parameter 6.4 2.6 0.7 ψJB Junction-to-board characterization parameter 62.2 29.0 52.3 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 9.3 N/A (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (1) (2) PARAMETER TEST CONDITIONS VCCA VCCB TA = 25°C –40°C to 125°C UNIT MIN TYP MAX MIN TYP MAX VOHA IOH = –20 μA 1.2 V 1.1 V 1.4 V to 3.6 V VCCA – 0.4 VOLA IOL = 20 μA 1.2 V 0.9 V 1.4 V to 3.6 V 0.4 VOHB IOH = –20 μA 1.65 V to 5.5 V VCCB – 0.4 V VOLB IOL = 20 μA 1.65 V to 5.5 V 0.4 V II OE VI = VCCI or GND 1.2 V to 3.6 V 1.65 V to 5.5 V ±1 ±5 μA Ioff A port VI or VO = 0 to 3.6 V 0 V 0 V to 5.5 V ±1 ±10 μA B port VI or VO = 0 to 5.5 V 0 V to 3.6 V 0 V ±1 ±10 IOZ A or B port OE = GND 1.2 V to 3.6 V 1.65 V to 5.5 V ±1 ±10 μA ICCA VI = VCCI or GND, IO = 0 1.2 V 1.65 V to 5.5 V 0.06 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 20

3.6 V 0 V 15

0 V 5.5 V –15 ICCB VI = VCCI or GND, IO = 0 1.2 V 1.65 V to 5.5 V 3.4 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 20

3.6 V 0 V –15

0 V 5.5 V 15 ICCA + ICCB VI = VCCI or GND, IO = 0 1.2 V 1.65 V to 5.5 V 3.5 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 40 ICCZA VI = VCCI or GND, IO = 0, OE = GND 1.2 V 1.65 V to 5.5 V 0.05 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 15 ICCZB VI = VCCI or GND, IO = 0, OE = GND 1.2 V 1.65 V to 5.5 V 3.3 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 15 Ci OE PW, RGY package 1.2 V to 3.6 V 1.65 V to 5.5 V 3 pF RUT package 1.2 V to 3.6 V 1.65 V to 5.5 V 4 pF www.ti.com TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TXB0104-Q1

6.5 Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted) (1) (2) PARAMETER TEST CONDITIONS VCCA VCCB TA = 25°C –40°C to 125°C UNIT MIN TYP MAX MIN TYP MAX Cio A port PW, RGY package 1.2 V to 3.6 V 1.65 V to 5.5 V 5 pF RUT package 6 pF B port PW, RGY package 11 pF RUT package 13 pF (1) VCCI is the supply voltage associated with the input port. (2) VCCO is the supply voltage associated with the output port. 6.6 Timing Requirements: VCCA = 1.2 V TA = 25°C, VCCA = 1.2 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V UNIT TYP TYP TYP TYP Data rate For PW, RGY, RUT package 20 20 20 20 Mbps tw Pulse duration Data inputs 50 50 50 50 ns 6.7 Timing Requirements: VCCA = 1.5 V ± 0.1 V over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted) VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX Data rate For PW, RGY package 40 40 40 40 Mbps For RUT package 37 37 40 40 Mbps tw Pulse duration Data inputs, For PW, RGY package 25 25 25 25 ns Data inputs, For RUT package 27 27 25 25 ns 6.8 Timing Requirements: VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX Data rate For PW, RGY package 55 55 55 55 Mbps For RUT package 37 37 55 55 Mbps tw Pulse duration Data inputs, For PW, RGY package 18 18 18 18 ns Data inputs, For RUT package 27 27 18 18 ns 6.9 Timing Requirements: VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX Data rate For PW, RGY package 75 80 100 Mbps For RUT package 65 80 85 Mbps TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 www.ti.com

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6.9 Timing Requirements: VCCA = 2.5 V ± 0.2 V (continued) over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX tw Pulse duration Data inputs, For PW, RGY package 13 12 10 ns Data inputs, For RUT package 15 12 11 ns 6.10 Timing Requirements: VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX Data rate For PW, RGY package 100 100 Mbps For RUT package 90 90 Mbps tw Pulse duration Data inputs, For PW, RGY package 10 10 ns Data inputs, For RUT package 11 11 ns 6.11 Switching Characteristics: VCCA = 1.2 V TA = 25°C, VCCA = 1.2 V PARAMETER FROM (INPUT) TO (OUTPUT) VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V UNIT TYP TYP TYP TYP tpd A B 6.9 5.7 5.3 5.5 ns B A 7.4 6.4 6 5.8 ten OE A 1 1 1 1 μs B 1 1 1 1 tdis OE A 320 320 320 330 ns B 150 110 150 110 trA, tfA A-port rise and fall times 4.2 4.2 4.2 4.2 ns trB, tfB B-port rise and fall times 2.1 1.5 1.2 1.1 ns 6.12 Switching Characteristics: VCCA = 1.5 V ± 0.1 V over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX tpd A B 15.9 13.1 13 12.9 ns B A 17.2 15 14.7 16.7 ten OE A 1 1 1 1 μs B 1 1 1 1 tdis OE A 340 280 280 300 ns B 220 220 220 220 trA, tfA A-port rise and fall times 7.1 7.1 7.1 7.1 ns trB, tfB B-port rise and fall times 6.5 5.2 4.8 4.7 ns www.ti.com TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TXB0104-Q1

6.13 Switching Characteristics: VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX tpd A B 14 10.7 9.8 9.5 ns B A 15 11.4 10.6 10.1 ten OE A 1 1 1 1 μs B 1 1 1 1 tdis OE A 280 250 250 250 ns B 220 220 220 220 trA, tfA A-port rise and fall times 6.2 6.1 6.1 6.1 ns trB, tfB B-port rise and fall times 5.8 5.2 4.8 4.7 ns 6.14 Switching Characteristics: VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX tpd A B 9.3 8.2 7.7 ns B A 9.6 8.1 7.4 ten OE A 1 1 1 μs B 1 1 1 tdis OE A 220 220 220 ns B 220 220 220 trA, tfA A-port rise and fall times 5 5 5 ns trB, tfB B-port rise and fall times 4.6 4.8 4.7 ns 6.15 Switching Characteristics: VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX tpd A B 7.7 7 ns B A 7.9 6.8 ten OE A 1 1 μs B 1 1 tdis OE A 280 280 ns B 220 220 trA, tfA A-port rise and fall times 4.5 4.5 ns trB, tfB B-port rise and fall times 4.1 4.7 ns TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 www.ti.com

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6.16 Operating Characteristics

TA = 25°C (1) PARAMETER TEST CONDITIONS VCCA UNIT VCCB 5 V 1.8 V 1.8 V 1.8 V 2.5 V 5 V 3.3 V to 5 V TYP TYP TYP TYP TYP TYP TYP CpdA A-port input, B-port output CL = 0, f = 10 MHz, tr = tf = 1 ns, OE = VCCA (outputs enabled) 7.8 10 9 8 8 8 9 pF B-port input, A-port output 12 11 11 11 11 11 11 CpdB A-port input, B-port output 38.1 28 28 28 29 29 29 B-port input, A-port output 25.4 19 18 18 19 21 22 CpdA A-port input, B-port output CL = 0, f = 10 MHz, tr = tf = 1 ns, OE = GND (outputs disabled) pF CpdB (1) Cpd parameter is the capacitance used to determine the no-load dynamic power dissipation per logic function for CMOS devices as per the formula: PD = Cpd (VCC)2 + ICCVCC. For more details about the use of Cpd to calculate power dissipation, refer to SCAA035.

6.17 Typical Characteristics

Figure 6-1. Input capacitance for OE pin (CI) vs Power Supply (VCCA) for VCCB = 3.3 V (RUT package) Figure 6-2. Capacitance for A port I/O pins (CiO) vs Power Supply (VCCA) for VCCB = 3.3 V (RUT package) Figure 6-3. Capacitance for B port I/O pins (CiO) vs Power Supply (VCCB) for VCCA = 3.3 V (RUT package) www.ti.com TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TXB0104-Q1

7 Parameter Measurement Information

/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr Under Test LOAD CIRCUIT FOR ENABLE/DISABLE TIME MEASUREMENT 2 × VCCO Open 50 k/C0087 VCCI 0 V VCCI/2 V CCI/2 tw VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS PULSE DURATION Input tPZL/tPLZ tPHZ/tPZH 2 × VCCO Open TEST S1 A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR/C011810 MHz, ZO = 50 Ω, dv/dt ≥/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr 1 V/ns. C. The outputs are measured one at a time, with one transition per measurement. D. t PLH and tPHL are the same as tpd. E. V CCI is the VCC associated with the input port. F. V CCO is the VCC associated with the output port. G. All parameters and waveforms are not applicable to all devices. 50 k/C0087 From Output /charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr Under Test

1 M/C008715 pF 15 pF

LOAD CIRCUIT FOR MAX DATA RATE, PULSE DURATION PROPAGATION DELAY OUTPUT RISE AND FALL TIME MEASUREMENT tPLH tPHL 0 V VCCO/2 VCCI/2 V CCI/2 0.9 /C0121 VCCO VCCO/2 tr 0.1 /C0121 VCCO tf VCCI Input Output VOH VOL Figure 7-1. Load Circuits and Voltage Waveforms TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 www.ti.com

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8 Detailed Description

8.1 Overview

The TXB0104 device is a 4-bit, bi-directional voltage-level translator specifically designed for translating logic voltage levels. The A port is able to accept I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. The device is a buffered architecture with edge-rate accelerators (one-shots) to improve the overall data rate. This device can only translate push-pull CMOS logic outputs. If for open-drain signal translation, please refer to TI’s TXS010X products.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Architecture

The TXB0104 architecture (see Section 8.2) does not require a direction-control signal to control the direction of data flow from A to B or from B to A. In a DC state, the output drivers of the TXB0104 can maintain a high or low, but are designed to be weak, so that they can be overdriven by an external driver when data on the bus starts flowing the opposite direction. The output one-shots detect rising or falling edges on the A or B ports. During a rising edge, the one-shot turns on the PMOS transistors (T1, T3) for a short duration, which speeds up the low-to-high transition. Similarly, during a falling edge, the one-shot turns on the NMOS transistors (T2, T4) for a short duration which speeds up www.ti.com TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TXB0104-Q1

the high-to-low transition. The typical output impedance during output transition is 70 Ω at VCCO = 1.2 V to 1.8 V, 50 Ω at VCCO = 1.8 V to 3.3 V, and 40 Ω at VCCO = 3.3 V to 5 V. A B VCCA VCCB One Shot One Shot One Shot One Shot Figure 8-1. Architecture of TXB0104 I/O Cell

8.3.2 Input Driver Requirements

Typical IIN vs V IN characteristics of the TXB0104 are shown in Figure 8-2 . For proper operation, the device driving the data I/Os of the TXB0104 must have drive strength of at least ±2 mA. IIN VIN VT /4 k ±(VD ± VT)/4 k Figure 8-2. Typical IIN vs VIN Curve

8.3.3 Output Load Considerations

TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading and to ensure that proper one shot (O.S.) triggering takes place. PCB signal trace-lengths should be kept short enough such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay on for approximately 10 ns. The maximum capacitance of the lumped load that can be driven also depends directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic I CC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the capacitance that the TXB0104 output sees, so it is recommended that this lumped-load TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 www.ti.com

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capacitance be considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level affects.

8.3.4 Enable and Disable

The TXB0104 has an OE input that is used to disable the device by setting OE = low, which places all I/Os in the high-impedance (Hi-Z) state. The disable time (t dis) indicates the delay between when OE goes low and when the outputs actually get disabled (Hi-Z). The enable time (t en) indicates the amount of time the user must allow for the one-shot circuitry to become operational after OE is taken high.

8.3.5 Pullup or Pulldown Resistors on I/O Lines

The TXB0104 is designed to drive capacitive loads of up to 70 pF. The output drivers of the TXB0104 have low DC drive strength. If pullup or pulldown resistors are connected externally to the data I/Os, their values must be kept higher than 50 kΩ to ensure that they do not contend with the output drivers of the TXB0104. For the same reason, the TXB0104 should not be used in applications such as I 2C or 1-Wire where an open-drain driver is connected on the bidirectional data I/O. For these applications, use a device from the TI TXS01xx series of level translators.

8.4 Device Functional Modes

The TXB0104 device has two functional modes, enabled and disabled. To disable the device, set the OE input to low, which places all I/Os in a high impedance state. Setting the OE input to high will enable the device. www.ti.com TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TXB0104-Q1

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TXB0104 can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. It can only translate push-pull CMOS logic outputs. If for open- drain signal translation, please refer to TI TXS010X products. Any external pulldown or pullup resistors are recommended larger than 50 kΩ.

9.2 Typical Application

Figure 9-1. Typical Application Schematic

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-1. And make sure the VCCA ≤VCCB. Table 9-1. Design Parameters DESIGN PARAMETERS EXAMPLE VALUE Input voltage range 1.2 V to 3.6 V Output voltage range 1.65 V to 5.5 V

9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

• Input voltage range - Use the supply voltage of the device that is driving the TXB0104 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port.
• Output voltage range - Use the supply voltage of the device that the TXB0104 device is driving to determine the output voltage range. - It is not recommended to have the external pullup or pulldown resistors. If mandatory, it is recommended the value should be larger than 50 kΩ.
• An external pulldown or pullup resistor decreases the output V OH and V OL. Use the below equations to draft estimate the VOH and VOL as a result of an external pulldown and pullup resistor. TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 www.ti.com

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VOH = VCCx × RPD / (RPD + 4.5 kΩ) (1) VOL = VCCx × 4.5 kΩ / (RPU + 4.5 kΩ) (2) where

• VCCx is the output port supply voltage on either VCCA or VCCB
• RPD is the value of the external pull down resistor
• RPU is the value of the external pull up resistor
• 4.5 kΩ is the counting the variation of the serial resistor 4 kΩ in the I/O line

9.2.3 Application Curve

Figure 9-2. Example of Level Translation of a 2.5-MHz 1.8 V Signal (Green) to a 3.3 V Signal (Pink) www.ti.com TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TXB0104-Q1

10 Power Supply Recommendations

During operation, ensure that V CCA ≤ VCCB at all times. During power-up sequencing, V CCA ≥ VCCB does not damage the device, so any power supply can be ramped up first. The TXB0104 has circuitry that disables all output ports when either V CC is switched off (V CCA/B = 0 V). The output-enable (OE) input circuit is designed so that it is supplied by VCCA and when the (OE) input is low, all outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to GND through a pulldown resistor and must not be enabled until V CCA and VCCB are fully ramped and stable. The minimum value of the pulldown resistor to ground is determined by the current-sourcing capability of the driver.

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:

• Bypass capacitors should be used on power supplies. And should be placed as close as possible to the VCCA, VCCB pin, and GND pin
• Short trace-lengths should be used to avoid excessive loading.
• PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than the one-shot duration, approximately 10 ns, ensuring that any reflection encounters low impedance at the source driver.

11.2 Layout Example

Figure 11-1. Layout Example Schematic TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 www.ti.com

16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TXB0104-Q1

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TXB0104-Q1 SCES727B – JUNE 2008 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TXB0104-Q1

www.ti.com 18-Jan-2025 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTXB0104QWBQARQ1 ACTIVE WQFN BQA 14 3000 TBD Call TI Call TI -40 to 125 Samples TXB0104QPWRQ1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 YE04Q1 Samples TXB0104QRGYRQ1 ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 YE04Q1 Samples TXB0104QRUTRQ1 ACTIVE UQFN RUT 12 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 SIG Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

www.ti.com 18-Jan-2025 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TXB0104-Q1 :

• Catalog : TXB0104 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 7-Jun-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 7-Jun-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TXB0104QPWRQ1 TSSOP PW 14 2000 356.0 356.0 35.0 TXB0104QRGYRQ1 VQFN RGY 14 3000 356.0 356.0 35.0 TXB0104QRUTRQ1 UQFN RUT 12 3000 202.0 201.0 28.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRGY 14 PLASTIC QUAD FLATPACK - NO LEAD3.5 x 3.5, 0.5 mm pitch 4231541/A

www.ti.com PACKAGE OUTLINE C 14X 0.30 0.18 14X 0.5 0.3

1 MAX

0.05 0.00 8X 0.5 2.05 0.1 2X 1.5 A 3.65 3.35 B 3.65 3.35 (0.2) TYP VQFN - 1 mm max heightRGY0014A PLASTIC QUAD FLATPACK - NO LEAD 4219040/A 09/2015 PIN 1 INDEX AREA 0.08 SEATING PLANE 1 14 (OPTIONAL) PIN 1 ID

0.1 C A B

0.05 7 8 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.200

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

(3.3) (3.3) 8X (0.5) 14X (0.6) 14X (0.24) ( 2.05) (0.775) (0.775) 2X (1.5) ( ) VIA TYP 0.2 (R ) TYP0.05 VQFN - 1 mm max heightRGY0014A PLASTIC QUAD FLATPACK - NO LEAD 4219040/A 09/2015 SYMM1 14 SYMM LAND PATTERN EXAMPLE SCALE:20X 7 8 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 14X (0.24) 14X (0.6) (3.3) (3.3) 8X (0.5) 4X ( 0.92) (0.56) (0.56) 2X (1.5) (R ) TYP0.05 VQFN - 1 mm max heightRGY0014A PLASTIC QUAD FLATPACK - NO LEAD 4219040/A 09/2015 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 80% PRINTED SOLDER COVERAGE BY AREA SCALE:20X SYMM 1 14 7 8

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightBQA 14 PLASTIC QUAD FLATPACK - NO LEAD2.5 x 3, 0.5 mm pitch 4227145/A

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com PACKAGE OUTLINE C 12X 0.25 0.15 12X 0.6 0.4 1.6 10X 0.4

0.55 MAX

0.05 0.00 B 1.8 1.6 A 2.1 1.9 0.6 0.4 0.25 0.15 (0.15) (0.15) TYP 4220310/A 11/2016 UQFN - 0.55 mm max heightRUT0012A PLASTIC QUAD FLATPACK - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.08 C (OPTIONAL) PIN 1 ID

0.1 C B A

0.05 C SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SCALE 6.800 OPTIONAL TERMINAL & PIN 1 ID PIN 1 ID

www.ti.com EXAMPLE BOARD LAYOUT 12X (0.2) (1.4) 8X (0.4) (1.7) 4220310/A 11/2016 UQFN - 0.55 mm max heightRUT0012A PLASTIC QUAD FLATPACK - NO LEAD SYMM SYMM LAND PATTERN EXAMPLE SCALE:30X NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 12X (0.7) 12X (0.2) 8X (0.4) (1.7) (1.4) (R0.05) TYP 4220310/A 11/2016 UQFN - 0.55 mm max heightRUT0012A PLASTIC QUAD FLATPACK - NO LEAD NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 30X

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