PTX130RDQ56D13

PTX130R RENESAS | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 26

Technical content

Datasheet sections

1.1 Pin Diagram
1.2 Pin Description
2.1 Absolute Maximum Ratings
2.2 Electrical Characteristics
3.1 System Architecture
3.2 Power Management
3.3 Clock Concept
3.4 Contactless Interface
3.5 Other Supported Features
3.6 Programmable Control Logic
3.7 Host Interface
3.8 FW/SW Functionality

Features

The architecture enables:

Efficient power transmission with accurate digital programmability of RF carrier and modulation shape
EMC filter removal due to sinewave output driver and Direct Antenna Connection (DiRAC)
-80dBc RX sensitivity with full dynamic range due to DiRAC
SDK composed of FW and SW integrated in a Split Stack architecture with PTX130R firmware update capability over the host processor: - Modular SW stack running on the Host architecture - Integrated FW running on the on -chip MCU for time-critical operations
SDK support for Android TM 2 Integration
Fractional-N PLL to support any reference input clock frequency from 13.15MHz to 52MHz

1 Receiver input dynamic range and sensitivity are defined

in Table 5.

2 Android is a trademark of Google LLC

EMVCo® 3.0/3.1 PCD L1 compliancy 3
ISO/IEC14443-A reader/writer mode up to 848kBit/s
ISO/IEC14443-B reader/writer mode up to 848kBit/s
NFC Forum Reader/Writer mode
Supports reading/writing of NFC Tag Type 2, 3, 4A/4B and 5
FeliCa reader/writer mode 212&424kBit/s
ISO/IEC 15693 reader/writer mode
Support reading/writing of Mifare® card family including Mifare Classic ® (without crypto)4
Support Apple ECP “Enhanced Contactless Polling”(feature only available for customers with valid Apple MFi licence)
Transparent mode allowing implementation of customer protocols based on low -level commands
NFC Forum P2P Passive Initiator
NFC Card Emulation Mode for Tag Type 4A (106kBit/s)
Low Power Card Detection (LPCD)
Low Power Field Detection (LPFD)
Programmable GPIOs
Supported host interfaces : UART, I2C, SPI System features supported by Android Integration Stack (AIS)
EMVCo® 3.0/3.1 PCD L1 compliancy
ISO/IEC14443-A reader/writer mode 106kBit/s
ISO/IEC14443-B reader/writer mode 106kBit/s
NFC Forum Reader /Writer mode
Supports reading/writing of NFC Tag Type 2, 3, 4A/4B and 5
FeliCa reader/writer mode 212&424kBit/s
ISO/IEC 15693 reader/writer mode
Support reading/writing of Mifare® card family including Mifare Classic ® (without crypto)

3 Depending on the Software Stack, EMVCo® L1 or full

NFC Forum Reader functionality is supported by PTX130R. 4 MIFARE is a registered trademark of NXP B.V

PTX130R Datasheet v1.1 Nov 12, 2024 Page 2

Support Apple ECP “Enhanced Contactless Polling”(feature only available for customers with Apple formal authorization)
NFC Forum P2P Passive Initiator
Low Power Card Detection (LPCD)
Supported host interfaces : I2C, SPI PTX130R reader IC enables key improvements in customer care -about such as: RF performance: Patented groundbreaking architecture enables efficient power transmission and -80dBc RX sensitivity, state of the art reader performance even in challenging and complex integration environments. Interoperability:
Digitized architecture enables accurate shape control of the modulated signal.
Elimination of the EMC filter results in well - behaved signal shape avoiding overshoot and undershoot (especially important for compliance with EMVCo® 3.0/3.1)
DiRAC allows high output power and high input sensitivity which translates to substantially larger operating volume. Manufacturability:
No need for bulky and performance -limiting external components of the EMC filter (no tolerances issue introduced) minimizing the performance variation between final devices.
Reduced number of matching components allow lower antenna matching impedance, resulting in higher output power.
Accurate adjustment of transmitter and receiver parameters due to digital architecture enabling tighter production control giving more margin for new use cases. PTX130R is optimized for applications such as Point-Of-Sales (POS), Mobile POS, Access Control, Wearables, Android handheld s and PDAs etc.

PTX130R Datasheet v1.1 Nov 12, 2024 Page 3 Antenna Matching Transmit- ter Receiver Card Detect Host Interface (SPI/I2C/ UART) BAT or PMU Power Mgmt TXp TXn VCC VDDIO I/F- pins RD-Tx Low Power Oscillator Crystal Oscillator XIN XOUT Phase Locked Loop RD-Rx On-chip MCU Delay- / guard timing EMD handling etc. L4 handling (chaining, WTX) Host Processor NSC Software NSC API NSC Stack L3/L4 Activation Field Detect RXp RXn Prog. GPIO Figure 1: Block Diagram

PTX130R Datasheet v1.1 Nov 12, 2024 Page 5

PTX130R Datasheet v1.1 Nov 12, 2024 Page 7 1. Pinning Information

1.1 Pin Diagram

56 55 54 53 52 51 49 48 47 46 45 44 43 15 16 17 18 19 20 21 22 23 24 25 26 27 VCC VCC VCC VCC SEN VCC NC VDDIO IRQ SIF1 SIF2 D18VD GPIO12 GPIO11 GPIO10 GPIO9 HIF1 DNC DNC XIN XOUT HIF2 GPIO3 HIF3 DNC DNC GPIO8 GPIO7 DNC DAC_O VCC VCC DNC DNC TXp TXp TXn TXn VCC VCC RXp RXn DNC DNC ATEST_0 ATEST_1 ATEST_2 ATEST_3 VDDIO DNC DNC DNC DNC HIF4 GPIO5 GPIO6 PTX130R QFN56 Figure 2: Pin Diagram

1.2 Pin Description

Signal Name Signal Type QFN56 Pin Description DNC - 1 Do n ot connect DAC_O Analog out 2 AUX-DAC o utput voltage VCC Supply 3 NFC IC Supply VCC Supply 4 NFC IC Supply DNC - 5 Do n ot connect DNC - 6 Do n ot connect TXp Analog out 7 Transmitter pin p TXp Analog out 8 Transmitter pin p TXn Analog out 9 Transmitter pin n TXn Analog out 10 Transmitter pin n VCC Supply 11 NFC IC Supply VCC Supply 12 NFC IC Supply RXp Analog in 13 Receiver pin p RXn Analog in 14 Receiver pin n DNC - 15 Do n ot connect DNC - 16 Do n ot connect ATEST_0 Analog out 17 Analog test mux ATEST_1 Analog out 18 Analog test mux ATEST_2 Analog out 19 Analog test mux ATEST_3 Analog out 20 Analog test mux

PTX130R Datasheet v1.1 Nov 12, 2024 Page 8 Signal Name Signal Type QFN56 Pin Description VDDIO Supply 21 IO Pad supply DNC - 22 Do n ot connect DNC - 23 Do n ot connect DNC - 24 Do n ot connect DNC - 25 Do n ot connect HIF4 Digital inout 26 SPI: MISO, I2C: SCL, UART: TXD GPIO5 Digital inout 27 General purpose digital IO pin GPIO6 Digital inout 28 General purpose digital IO pin GPIO7 Digital inout 29 General purpose digital IO pin GPIO8 Digital inout 30 General purpose digital IO pin DNC - 31 Do n ot connect DNC - 32 Do n ot connect HIF3 Digital inout 33 SPI: MOSI, I2C: SDA, UART: RXD DNC - 34 Do n ot connect HIF2 Digital inout 35 SPI: SCK, I2C: ADDR1, UART: RTS XOUT Analog out 36 Xtal oscillator output XIN Analog in 37 Xtal oscillator input / Reference clock input DNC - 38 Do n ot connect DNC - 39 Do n ot connect HIF1 Digital inout 40 SPI: NSS, I2C: ADDR0, UART: CTS GPIO9 Digital inout 41 General purpose digital IO pin GPIO10 Digital inout 42 General purpose digital IO pin GPIO11 Digital inout 43 General purpose digital IO pin GPIO12 Digital inout 44 General purpose digital IO pin D18VD Supply 45 Decoupling of core supply SIF2 Digital in 46 Select interface type bit 2 SIF1 Digital in 47 Select interface type bit 1 IRQ Digital out 48 Interrupt request to host VDDIO Supply 49 IO Pad supply DNC - 50 Do n ot connect VCC Supply 51 NFC IC Supply SEN Analog in 52 System enable input VCC Supply 53 NFC IC Supply VCC Supply 54 NFC IC Supply VCC Supply 55 NFC IC Supply VCC Supply 56 NFC IC Supply GND Supply - The exposed pad at the back of QFN is used as GND Requires good thermal connection to ensure low thermal resistance for power dissipation Table 1: Pin Description

PTX130R Datasheet v1.1 Nov 12, 2024 Page 9 2. Electrical Characteristics

2.1 Absolute Maximum Ratings

Symbol Parameter Conditions Min Typ Max Unit Remarks VCC Supply voltage at VCC -0.5 5.5 V TJ Junction temperature -40 125 °C TS Storage temperature -40 150 °C Rth(ja) Thermal resistance junction to air

35 K/W Based on

PTOT Total power dissipation allowed in the chip 1.5 W VESD(HBM) electrostatic discharge voltage; Human Body Model (HBM)

1500 Ohm, 100 pF;

1000 V All pins except

VESD(HBM), RX electrostatic discharge voltage; Human Body Model (HBM)

750 V RXp/RXn

VESD(CDM) electrostatic discharge voltage (Charge Device model) Field induced model; JEDEC JS-002 -2018 750 V ILU Latch up AEC-Q100 (Transient current) 100 mA Vinmax Maximum input voltage at digital IO pins -0.3 VDDIO+0.3 V Iiomax Maximum current into digital IO pins 4 mA Table 2: Absolute Maximum Ratings

2.2 Electrical Characteristics

Unless noted otherwise, typical condition TA=25°C, VCC= 5.4V, Fref_clk = 27.12MHz, Vref_clk=1.8Vpp . Symbol Parameter Conditions Min Typ Max Unit Remarks TA Ambient temperature -40 70 °C Full output power range -40 85 °C IVCC < 500mA TX Pout < 1W TJ Junction temperature -40 120 °C VCC Supply voltage 2.7 5.5 V VDDIO Pad supply voltage 1.62 5.5 V VSEN_H System Enable (SEN) pin high-level voltage range 1.62 VCC V

PTX130R Datasheet v1.1 Nov 12, 2024 Page 10 Symbol Parameter Conditions Min Typ Max Unit Remarks VIH GPIO pins high level input voltage 0.75*VDDIO VDDIO V VIL GPIO pins low level input voltage 0 0.15*VDDIO V VOH GPIO pins high level output voltage5 VDDIO-0.5 VDDIO V VOL GPIO pins low level output voltage 0 0.45 V Table 3: Operating Range Symbol Parameter Conditions Min Typ Max Unit Remarks IPD Power down current consumption VCC = 3.6V SEN=0 3 uA ISTBY Standby current consumption VCC = 3.6V 15 uA ICD_rd Low power c ard detection current consumption VCC = 5.5V 100 uA 2Hz polling frequency with optimized reading distance IVCC Supply current 680 mA Table 4: DC characteristics Symbol Parameter Conditions Min Typ Max Unit Remarks Vin_rx_rd RX carrier signal reader 100m 50 Vpp differential Sin_RX_rd RX sensitivity AM -806 dBc Vin_rx_rd ≥25Vpp Hout_tx_rd Transmitter output harmonics -60 dBc Cout_tx Transmitter serial output capacitance 440 pF Table 5: Receiver / Transmitter Characteristics 6 To achieve -80dBc RX sensitivity, VCC shall not have voltage ripple higher than 500u Vrms (VCC = 5V) around the carrier frequency (±1MHz).

PTX130R Datasheet v1.1 Nov 12, 2024 Page 11 Symbol Parameter Conditions Min Typ Max Unit Remarks Fref_clk Reference clock input frequency 13.15 27.12 52 MHz Vref_clk_low Reference clock input voltage low 0 400 mV Vref_clk_high Reference clock input voltage high 1.4 1.95 V Δfref_clk Reference clock frequency tolerance -50 +50 ppm DC_fref_clk Reference clock duty cycle 40 50 60 % Table 6: Reference Input Frequency Requirements Symbol Parameter Conditions Min Typ Max Unit Remarks Fxtal_clk Reference clock input frequency 27.12 MHz Δfxtal_clk Reference clock frequency tolerance -50 +50 ppm ESR Equivalent serial resistance 150 Ohm CL Load capacitance 6 pF On chip available Table 7: Crystal Requirements

PTX130R Datasheet v1.1 Nov 12, 2024 Page 12 3. Functional Description

3.1 System Architecture

PTX130R is a highly integrated reader IC using a split -stack SW architecture, allowing flexible adaptation of SW to the needs of the application system such as POS, IoT/NFC Reader etc. This flexibility is achieved by an optimized software interface and ready to use SW -stack for the host - controller. The portable SW stack written in C, implements high level NFC functionality and provides easy to use APIs for integration into the Host system. As shown in Figure 3, on the Host Controller, the EMVCo® main application (typically EMV L2 Stack) makes use of the EMVCo® L1 stack; this one abstracts the interaction to the NFC Hardware through a very intuitive L1 API. The PTX solution is modular and runs on different platforms, providing additional facilities for custom features in case needed. Application processorApplication Data EMVCo Application Application Data Partioning EMVCo Level2EMVCo Level1 NFC-HW NFC-FW PTX130R Split-Stack-Solution Split-Stack - Implementation Application view L4-Protocol L3-Protocol L2-Interface PHY-RF-Interface PTX130R IC Host Figure 3: System Architecture to show Interface with PTX1 30R for EMVCo® Application

PTX130R Datasheet v1.1 Nov 12, 2024 Page 13

3.2 Power Management

The power management unit is the central circuit of the PTX130R responsible for providing all necessary reference voltages and currents, generating the internal supply domains, implementing the power-up sequence, and controlling the transitions between different energy states. 3.2.1. Power Supply Concept PTX130R has 3 externally accessible supply domains which are described as follows: 3.2.1.1. VCC VCC is the main supply domain from which all functional blocks are supplied. To operate PTX130R this supply must always be present. 3.2.1.2. D18VD The internally generated core supply is routed to pin D18VD for external supply blocking. Hence external supplies are not allowed to be connected. For recommended blocking components please refer to the relevant application note. 3.2.1.3. VDDIO Pad supply for all GPIO- and HIF/SIF-pins. It must be present during start-up for proper host-interface selection and afterward for host interface communication. In power-down mode, the voltage may be removed from this domain, but the pin shall not be pull ed to VS (i.e. to be put to HiZ). If for power saving reasons at any point in time the VCC domain is switched off, then VDDIO must also be removed. 3.2.2. SEN-Pin The SEN-pin is used to boot up the PTX130R (logic-high level) or to bring the IC into power -down state (logic -low level). Detailed ranges for the logic -levels are given in Table 3. Note that SEN-input voltage must never exceed VCC. For safe operation, SEN shall change to a logic low before V CC drops below V CC_min (value defined in Table 3). Logic -low level pulses with smaller than 3.4 us pulse width on SEN-pin will not change the current energy state of the IC. Negative pulses that are slightly longer will first reset the internal state and for even longer negative pulses the IC changes the energy state to power-down mode. The exact pulse width below which a reset is triggered, and above which power-down mode is entered depends on the blocking capacitor value on D18VD -pin. 3.2.3. Supply Ramp-Up Sequence For the supply ramp-up two sequences are proposed: a default sequence with SEN pin at logic-low for relaxed timing constraints between VCC and VDDIO, and a sequence with SEN pin connected to VCC for simpler configuration and faster start -up. Ramp-up sequence with SEN at logic -low (transition into power -down mode):

First, the battery supply V CC shall be ramped up – the IC remains in power-down mode
VDDIO shall be ramped up. V DDIO may ramp concurrently to V CC.
VDDIO supply and a stable state of SIF1/SIF2 pins shall latest be available when the SEN pin voltage reaches a valid logic -high level. These timings also apply when leaving power-down mode with disabled V DDIO.

PTX130R Datasheet v1.1 Nov 12, 2024 Page 15 3.2.4.1. Full-Power Mode This is the main operating mode of PTX130R, in which all internal supply domains are ramped up and all internal clocks are running. This mode is activated by applying a logic -high level at SEN -pin. In this mode, PTX1 30R is fully active and can communicate with the host controller via the host interface. 3.2.4.2. Power-Down (PD) mode For maximum power saving, PTX130R can be set to power-down mode by applying a logic-low level at SEN-pin. In this mode PTX130R consumes its lowest power and does not react to any external events. All GPIO-pins and the SIF1/SIF2 -pins are switched to HiZ -state. After leaving this mode the internal state of PTX1 30R is reset. 3.2.4.3. Standby (STBY) Mode PTX130R supports Standby Mode for low power applications, with the possibility to wake up in response to selected events such as Low Power Card Detection or Host-interface activities. In this mode, a logic- high level shall be maintained on SEN -pin and the internal state of PTX1 30R is fully maintained. Depending on the application, different wake-up sources (e.g. execution of Polling loop, LPCD/LPFD procedure) can be defined by the customer. Once configured, it runs autonomously and no interaction with the Host is required. Events triggering the wakeup of the IC from standby mode include:

Activity on Host -interface
Execution of Polling
LPCD/LPFD procedure

3.3 Clock Concept

In PTX130R a low-power oscillator (LPO), a crystal oscillator (XO) and a phase-locked loop (PLL) are the main blocks responsible for generating the necessary internal clocks in the various modes. The reference clock for PTX130R can either be provided from an external clock source or the internal crystal oscillator can be employed. Out of this clock, the PLL subsequently derives the system frequency of 13.56MHz. 3.3.1. Low Power Oscillator (LPO) The low-power oscillator is the lifeline of PTX130R, and its 125kHz-clock is particularly employed during IC ramp-up and in standby mode, when the internal PLL is powered down to save energy. 3.3.2. Crystal Oscillator (XTAL) The internal crystal oscillator is designed for crystal types with a resonant frequency of 27.12MHz, which shall be externally connected between XIN- and XOUT pins. The oscillator will also work with other crystals around this frequency - please contact Panthronics for support. The PTX130R features internal caps of 6pF each from XIN- and XOUT-pins to GND to act as crystal load capacitors. 3.3.3. External Reference Clock An external reference clock with frequency between 13.15MHz and 52MHz can be applied to XIN pin. Detailed requirement on the external reference clock is specified in Table 6.

PTX130R Datasheet v1.1 Nov 12, 2024 Page 16 3.3.4. Phase Lock Loop (PLL) A fractional -N PLL produces the core clock that is used to derive all the needed internal clocks. A Delta-Sigma Modulator (DSM) is used to program the N division word of the fractional-N PLL. This allows very fine frequency resolution of all clocks and output frequencies.

3.4 Contactless Interface

Lower-level functionality up to communication framing is available through the Contactless Frontend, higher level functionality is implemented via the RF-Subsystem of the on-chip MCU (see chapter 3.6.1) Figure 6 gives a block level overview of the Contactless Interface. At TXp&TXn/ RXp&RXn pins the device is connected via a matching network to the antenna of the system. Analog Receiver Digital Receiver Analog Transmitter Digital Transmitter Low Power Card Detection Contactless Interface On-chip MCU RF- Subsystem Low Power Field Detection TXp TXn RXp RXn Figure 6: Contactless Interface 3.4.1. Analog/Digital Transmitter In PCD mode, the transmitter generates the RF-field and consequently amplitude-modulates the PCD commands on the RF -carrier according to the selected communication type. The analog transmitter itself consists of a digital-like topology, which allows to directly output sinusoidal carriers with high spectral purity and high efficiency. Therefore, EMC -filters, which are required in conventional products in the matching network of Reader-antennas, can be omitted. Additionally, direct antenna connection allows to shape the modulation in a very fine granularity. PTX130R offers dynamic wave-shaping feature, which optimizes the modulation shapes to fulfill the requirements of the f inal application – see chapter 3.4.6 for details. The digital transmitter is responsible for encoding the command/data to be sent, applying the respective modulation according to the selected communication type and synchronization of the modulation with the carrier. The output power of the transmitter can be adapted directly by adjusting the sinusoidal amplitude based on the Received Signal Strength Indicator (RSSI). The RSSI level to trigger the switch of output power can be simply defined as parameter and used as input for the software API. More details on Digital Dynamic Power Control (DDPC) are explained in chapter 3.4.7.

PTX130R Datasheet v1.1 Nov 12, 2024 Page 17 3.4.2. Analog/Digital Receiver The receiver, consisting of an analog and a digital part, is responsible for reception, demodulation and signal processing of incoming commands and data from the communication counterpart of PTX130R. The analog receiver is based on an I/Q-architecture in the RF-domain, which is followed by a baseband chain with programmable gain amplifiers and filters to properly adjust the received signal from varied sized antennas to the full -scale range of the ADC. The digital receiver provides means to configure the digital detection threshold on a fine granularity to optimize sensitivity while ensuring good noise immunity. The received information is then extracted on a bit- and frame-level to finally obtain the transmitted command/data. For easy integration into the customer application, parameters such as PGA gain and digital RX - threshold can be adapted based on the target applications, while RF-protocol related parameters such as filter frequency settings stay pre -defined and unmodified . 3.4.3. Polling Loop Polling loop is the center of all NFC -applications. In a loop PTX130R executes polling sequences through the defined RF-protocol following well-defined timing specifications. Depending on the use-case and SDK variant , PTX130R can be configured to execute one of the three different scenarios:

EMVCo payment polling loop which permanently polls for TypeA and TypeB RF-technology; optionally Felica can be included as preliminary protocol
Standard NFC applications, which polls for selected technologies in defined intervals. Between the polling cycles PTX130R either stays idle or enters standby to reduce power consumption
Low-Power application. For Reader applications, the Low-Power-Card-Detection mechanism is used to significantly reduce power consumption (see chapter 3.4.4 for more information) . For applications where Host-Card-Emulation functionality is required, Low-Power-Field-Detection can be enabled during Standby mode to detect the existence of an external RF field (see Chapter 3.4.5 for more information). Polling interval together with the above -mentioned RF-protocol configurations can configured by the customer based on the target application and used as input parameters of the SW API. 3.4.4. Low Power Card Detection (LPCD) To optimize the power consumption for low power applications, PTX130R supports Low Power Card Detection (LPCD) feature. LPCD is used to check if a PICC is within the communication range without immediately starting a power-hungry communication. Only when a PICC is present, normal polling will be initiated, otherwise PTX1 30R goes back to standby. The interval for LPCD is a configurable parameter which can be optimized for different applications. To check the amplitude and phase of the antenna and determine if a PICC is present, only a reduced set of the hardware blocks are enabled in LPCD mode. Additionally, the active time of Transmitter, the most power consuming block, is kept to minimum. Comparing with normal polling mode which executes communication commands according to standard and requires Transmitter to be active for at least several milliseconds, in LPCD mode the transmitter is only active for less than 10 0us. The power consumption in LPCD mode can be further optimized by adjusting the output amplitude. Thanks to the split -stack architecture, the Low Power Card Detection is performed by PTX1 30R autonomously. Once LPCD mode is configured, the Host MCU is not required anymore, thus can go to lower power mode. In case a PICC is discovered, the host will be notified by PTX1 30R.

PTX130R Datasheet v1.1 Nov 12, 2024 Page 19

3.5 Other Supported Features

3.5.1. Temperature Sensor and Over-Temperature Protection PTX130R features an on-chip temperature sensor that continuously monitors the die temperature. In case the temperature exceeds a configurable threshold, the transmitter is automatically disabled. 3.5.2. Auxiliary Digital-to-Analog Converter (AUX-DAC) PTX130R comprises a 5-bit general-purpose digital-to-analog converter (DAC), which operates from the VCC domain and whose output is available at the DAC_O pin. 3.5.3. GPIO Customer Usage PTX130R provides customer access to 8 GPIOs. These GPIOs can be configured as input or output separately, depending on the customer application. Specially for system with small MCU, this feature releases the load on the Host greatly.

3.6 Programmable Control Logic

PTX130R is a highly integrated NFC device greatly unloading the host device in respect to contactless communication effort. This is achieved by handling major parts of the contactless protocols up to NFC- Forum ISO -DEP protocol or EMVCo Block Transmission Protocol directly on the IC using the Panthronics NSC (NFC Soft Controller) interface. On top the Panthronics SW stacks takes care of data aggregation and management, providing easy to use APIs to the user. Time-critical high -level functions, such as ISO-DEP frame de -/composition, automatic frame re - transmission, WTX handling, EMD handling, etc, are implemented by a programmable control logic circuit – the on-chip MCU – guaranteeing great execution speed. 3.6.1. On-chip MCU The on-chip MCU executes the program downloaded to the PTX130R code-memory. It has access to all internal status information as well as the configuration mechanisms. After downloading the micro-code (uCode) the on-chip MCU can be enabled. Subsequently, it accepts NSC commands for handling all t asks. 3.6.2. PTX130R Device Control Firmware 3.6.2.1. uCode Download Mechanism Before enabling the on-chip MCU, the devices uCode must be downloaded. This is done via the host- interface by utilizing the Write -Instruction functionality. 3.6.2.2. Accelerator Enable Activating the on -chip MCU is achieved by writing the corresponding command to the device. 3.6.2.3. Soft-Reset PTX130R provides a Soft-Reset functionality that resets all digital blocks and disables all analog blocks (same condition as after boot).

PTX130R Datasheet v1.1 Nov 12, 2024 Page 20

3.7 Host Interface

PTX130R supports the most used industry standard host interfaces, namely SPI up to 10Mbps, I2C up to 3.4Mbps and UART with data -rates from 9.6kbps up to 3.4Mbps. The host interface is designed for typical interface supply voltages used by micro-controllers in the range of 1. 8V to 5V which must be supplied by the host via the VDDIO pin. 3.7.1. Host-Interface Selection Only one interface type is available at a time and the configuration can only be changed when PTX130R is in power -down state. Host interface selection is done via the configuration pins SIF1 and SIF2 at startup. A change of the pin state after boot does not have any effect on the selected interface type. The following table describes the selection of host interface with respect to the value at the SIF pins: {SIF2, SIF1} HIF 2’b00 SPI 2’b01 I2C 2’b10 UART 2’b11 Reserved for test Table 8: Host Interface Selection 3.7.2. Host-Interface Lines 4 pins (HIF1 -HIF4) are utilized for the host interface communication, depending on the selection, configuration, and application at least 2 HIF pins and up to all 4 are used. Table 9 specifies the pin assignment for the chosen interface type. For SPI, all HIF-interface pins are used during the communication. In contrast, for I2C HIF1 and HIF2 (corresponding to the ADDR0 and ADDR1 pins) are only needed at startup to define the last two bits of the I2C-address. For UART mode HIF1 and HIF2 (CTS and RTS) are used for flow control. PIN SPI I2C UART HIF1 NSS ADDR0 1) CTS 2) HIF2 SCK ADDR1 1) RTS 2) HIF3 MOSI SDA RXD HIF4 MISO SCL TXD Table 9: Pin Assignment for HIF Selection 1) LSBs of I2C address, evaluated at boot 2) Flow -control pins 3.7.3. IRQ Line PTX130R has an exclusive IRQ line used to signal the host a communication request. For SPI and I2C interface asserting an IRQ is the only possibility to initialize a transmission from PTX130R to the host. The UART interface in contrast, provides a special “push” mode, allowing PTX130R to initiate a transfer and transmit notifications to the host directly without the host starting the transfer. This mode is only usable with hardware flow -control enabled. In this mode, no IRQ line is needed.

PTX130R Datasheet v1.1 Nov 12, 2024 Page 22 PTX130R supports 7-bit addressing, where the 2 LSBs of the devices I2C-address can be configured via the pins HIF1 and HIF2 at start-up. In contrast, the upper 5 bits are fixed to 10011(b), resulting in an address between 0x4C and 0x4F (see Table 11). 7bit I2C Address HIF2 pin HIF1 pin 0x4C 0 0 0x4D 0 1 0x4E 1 0 0x4F 1 1 Table 11: I2C Address Selection depending on HIF Pin Setting Clock-stretching is not used by the PTX130R, i.e. no delaying of the communication is necessary. 3.7.6. UART PTX130R supports serial communication UART communication mode with flow-control up to a data- rates of 3.4 Mbps. As there is no common clock reference for the UART interface the data-rate reference must be very accurate. A transaction starts with a Start-of-Frame (SOF) symbol, i.e. one byte with value 0x55, followed by a byte indicating the length of transmission payload (TXL). The TXL specifies the number of payload bytes following. A TXL == 0x00 specifies a length of 256 byte. Every response from PTX1 30R starts with the length of reception payload (RXL). As for the transmission, the RXL specifies the number of bytes to follow, but only values from 1 to 255 are possible. In case no response is expected (write only transactions) the device sends a one byte acknowledge putting RXL to 0x00. After boot, baud-rate detection is enabled and accepts data rates of 9.6kbps or 115.2kbps. Once the clock system is configured correctly, data rates up to 3.4Mbps can be used. As mentioned above, hardware flow control (RTS/CTS – both polarities are possible) must be enabled as TX-push mode is used for communicating with PTX1 30R. To further improve communication stability, stop bit can be extended to 2 bits instead of 1 bit.

3.8 FW/SW Functionality

3.8.1. NSC-Interface To access PTX130R, an optimized high-level software interface is implemented providing functions for device configuration as well as all data communications. The interface is based on messages which carry commands, responses, and notifications. Commands are always sent by the host; responses are generated by the PTX130R as reactions to commands. Notifications are transmitted by the PTX130R to indicate the host an event has occurred and is usually asynchronous to commands. Data packages between PTX130R and the host are called NSC Data messages, and the RF/NFC specific protocol related header bytes are managed by the on-chip MCU automatically.

PTX130R Datasheet v1.1 Nov 12, 2024 Page 23 3.8.2. SW Split Stack Panthronics provides additional SW-stacks on top of the NSC interface to further ease the integration of the PTX130R into the target application. The SW stacks manage all interactions with the PTX130R on NSC level, by setting up and configuring the device, consolidating status information, handling error messages, and establishing a data channel between the host and the NFC controller. Three versions of SW stacks are available for PTX130R:

IoT stack is suitable for standard NFC reader use -cases, easing the creation of full NFC applications.
POS stack is intended for EMVCo® payment applications, providing a full, ready to use Level 1 layer.
Android Integration Stack AIS (based on NCI standard according to NFC forum) enables integration into Android system for applications such as handhelds and PDAs. Demos/Example Applications On-Chip MCU NSC Command Interpreter Software Interface Commands Responses Notifications Hardware/Platform Abstraction Layer (HAL) NSC Core Stack Components RF/Sys Config PTX Software Stack PTX130R Host Processor/Target System Firmware image Product APIs + Support Libraries IoT-API POS-API AIS/NCI Figure 9: PTX130R SW Stack Integration View For more details on the PTX130R SW integration, please refer to the integration manual accordingly.

PTX130R Datasheet v1.1 Nov 12, 2024 Page 24 4. Reference Schematic VCC VCC VCC VCC VCC VDDIO D18VD HIF1 XIN XOUT HIF2 HIF3 VCC VCC TXp TXp TXn TXn VCC VCC RXp RXn PTX130R QFN56 26HIF4 48IRQ SEN SIF1 SIF2 VDDIO HOST µC Interface Select C2 C3 Antenna C12C11 VBAT C10C9 VBAT C14C13 C17 VDDIO C16C15 VBAT Figure 10: Exemplary Reference Schematic Designator Component type Component value Description C1, C2, C3, C4 Ceramic capacitor - Matching capacitors C5, C6, C7, C8 Ceramic capacitor - Optional depending on RX input voltage C9, C11, C13 Ceramic capacitor 10µF Note that capacitor shall have at least 2.2µF effective capacitance at applied voltage C10, C12, C14, C15, C17 Ceramic capacitor 100nF C16 Ceramic capacitor 10µF Optional, depending upon VDDIO supply noise/impedance Y1 Crystal oscillator 27.12MHz According to Table 7 Table 12: Reference Schematic Components

PTX130R Datasheet v1.1 Nov 12, 2024 Page 25 5. Package Information

5.1 Ordering Information

Part Number Package Size (mm) Shipment Form Pack Quantity PTX130RDQ56D13 HVQFN56 7x7 Tape & Reel 3000 Table 13: Ordering Information

5.2 Package Marking

Figure 11: Package Marking Symbol Description PTX130R Device Name XXXXXX.X Wafer Lot No. YYWW Production year/week Table 14: Marking code HVQFN56

PTX130R Datasheet v1.1 Nov 12, 2024 Page 26

5.3 Package Drawing and Dimension

Figure 12: Package Drawings and Dimensions

Summary

NFC Reader IC PTX130R Nov 12, 2024

Description