PTVS0500DRVR

TVS0500 TI1 | Alldatasheet

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3.55mm x 5.3mm Copyright © 2018, Texas Instruments Incorporated Voltage Time ( Traditional TVS TI Flat-Clamp 2010 30 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TVS0500 SLVSED2B –DECEMBER 2017–REVISED FEBRUARY 2018 TVS05005-VFlat-ClampSurgeProtectionDevice

1 Features

1• Protection Against 2 kV, 42 Ω IEC 61000-4-5 Surge Test for Industrial Signal Lines

• Max Clamping Voltage of 9.2 V at 43 A of 8/20 µs Surge Current
• Standoff Voltage: 5 V
• Tiny 4 mm2 Footprint
• Survives over 5,000 Repetitive Strikes of 35 A 8/20 µs Surge Current at 125°C
• Robust Surge Protection: – IEC61000-4-5 (8/20 µs): 43 A – IEC61643-321 (10/1000 µs): 22 A
• Low Leakage Current – 70 pA typical at 27°C – 6.5 nA typical at 85°C
• Low Capacitance: 155 pF
• Integrated Level 4 IEC 61000-4-2 ESD Protection

2 Applications

• Industrial Sensors
• PLC I/O Modules
• 5 V Power Lines
• Appliances
• Medical Equipment
• Smart Meters

3 Description

The TVS0500 robustly shunts up to 43 A of IEC 61000-4-5 fault current to protect systems from high power transients or lightning strikes. The device offers a solution to the common industrial signal line EMC requirement to survive up to 2 kV IEC 61000-4- 5 open circuit voltage coupled through a 42 Ω impedance. The TVS0500 uses a unique feedback mechanism to ensure precise flat clamping during a fault, assuring system exposure below 10 V. The tight voltage regulation allows designers to confidently select system components with a lower voltage tolerance, lowering system costs and complexity without sacrificing robustness. In addition, the TVS0500 is available in a small 2 mm × 2 mm SON footprint which is ideal for space constrained applications, offering a 70 percent reduction in size compared to industry standard SMA and SMB packages. The extremely low device leakage and capacitance ensure a minimal effect on the protected line. To ensure robust protection over the lifetime of the product, TI tests the TVS0500 against 5000 repetitive surge strikes at high temperature with no shift in device performance. The TVS0500 is part of TI's Flat-Clamp family of surge devices. For more information on the other devices in the family, see the Device Comparison Table Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TVS0500 SON (6) 2.00 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Footprint Comparison Voltage Clamp Response to 8/20 µs Surge Event

SLVSED2B –DECEMBER 2017–REVISED FEBRUARY 2018 www.ti.com Product Folder Links: TVS0500 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Table of Contents

12.1 Receiving Notification of Documentation Updates 14

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision A (February 2018) to Revision B Page

• Changed Break-down Voltage MIN from 7.6 to 7.5 and MAX from 8.2 to 8.4 in the Specifications Electrical Changes from Original (December 2017) to Revision A Page

www.ti.com SLVSED2B –DECEMBER 2017–REVISED FEBRUARY 2018 Product Folder Links: TVS0500 Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated

5 Device Comparison Table

Device Vrwm Vclamp at Ipp Ipp (8/20 µs) Vrwm leakage (nA) Package Options Polarity TVS0500 5 9.2 43 0.07 SON Unidirectional TVS1400 14 18.4 43 2 SON Unidirectional TVS1800 18 22.8 40 0.5 SON Unidirectional TVS2200 22 27.7 40 3.2 SON Unidirectional TVS2700 27 32.5 40 1.7 SON Unidirectional TVS3300 33 38 35 19 WCSP, SON Unidirectional

SLVSED2B –DECEMBER 2017–REVISED FEBRUARY 2018 www.ti.com Product Folder Links: TVS0500 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated

6 Pin Configuration and Functions

NAME No. IN 4, 5, 6 I ESD and surge protected channel GND 1, 2, 3, exposed thermal pad GND Ground

www.ti.com SLVSED2B –DECEMBER 2017–REVISED FEBRUARY 2018 Product Folder Links: TVS0500 Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

TA = 27℃ (unless otherwise noted)(1) MIN MAX UNIT Maximum Surge IEC 61000-4-5 Current (8/20 µs) 43 A IEC 61000-4-5 Power (8/20 µs) 400 W IEC 61643-321 Current (10/1000 µs) 20 A IEC 61643-321 Power (10/1000 µs) 180 W Maximum Forward Surge IEC 61000-4-5 Current (8/20 µs) 50 A IEC 61000-4-5 Power (8/20 µs) 80 W IEC 61643-321 Current (10/1000 µs) 23 A IEC 61643-321 Power (10/1000 µs) 60 W EFT IEC 61000-4-4 EFT Protection 80 A IBR DC Breakdown Current 50 mA IF DC Forward Current 500 mA TA Ambient Operating Temperature -40 125 °C Tstg Storage Temperature -65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings - JEDEC

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500

7.3 ESD Ratings - IEC

V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±24 kV IEC 61000-4-2 air-gap discharge ±30

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT VRWM Reverse Stand-off Voltage 5 V (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Thermal Information

THERMAL METRIC(1) TVS0500 UNITDRV (SON)

6 PINS

RqJA Junction-to-ambient thermal resistance 70.4 °C/W RqJC(top) Junction-to-case (top) thermal resistance 73.7 °C/W RqJB Junction-to-board thermal resistance 40 °C/W YJT Junction-to-top characterization parameter 2.2 °C/W

SLVSED2B –DECEMBER 2017–REVISED FEBRUARY 2018 www.ti.com Product Folder Links: TVS0500 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Thermal Information (continued) THERMAL METRIC(1) TVS0500 UNITDRV (SON) YJB Junction-to-board characterization parameter 40.3 °C/W RqJC(bot) Junction-to-case (bottom) thermal resistance 11 °C/W

7.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ILEAK Leakage Current Measured at VIN = VRWM, TA = 27°C 0.07 5.5 nA Measured at VIN = VRWM, TA = 85°C 6.5 220 nA Measured at VIN = VRWM, TA = 105°C 38 755 nA VF Forward Voltage IIN = 1 mA from GND to IO 0.25 0.5 0.65 V VBR Break-down Voltage IIN = 1 mA from IO to GND 7.5 7.9 8.4 V VFCLAMP Forward Clamp Voltage 35 A IEC 61000-4-5 Surge (8/20 µs) from GND to IO, 27°C 2 5 V VCLAMP Clamp Voltage

24 A IEC 61000-4-5 Surge (8/20 µs)

from IO to GND, VIN = 0 V before surge, 27°C 8.6 8.8 V

43 A IEC 61000-4-5 Surge (8/20 µs) from

IO to GND, VIN = 0 V before surge, 27°C 9.2 9.5 V

35 A IEC 61000-4-5 Surge (8/20 µs)

from IO to GND, VIN = VRWM before surge, TA = 125°C 9.2 9.5 V RDYN 8/20 µs surge dynamic resistance Calculated from VCLAMP at .5*Ipp and Ipp surge current levels, 27°C 30 50 mΩ CIN Input pin capacitance VIN = 5 V, f = 1 MHz, 30 mVpp, IO to GND 155 pF SR Maximum Slew Rate 0-VRWM rising edge, sweep rise time and measure slew rate when IPEAK = 1 mA, 27°C

2.5 V/µs

0-VRWM rising edge, sweep rise time and measure slew rate when IPEAK = 1 mA, 105°C

0.7 V/µs

0 V Bias

2.5 V Bias

5 V Vias

7.7 Typical Characteristics

Figure 1. 8/20 µs Surge Response at 43 A Figure 2. 8/20 µs Surge Response at 35 A Across Figure 3. Capacitance vs Temperature Across Bias Figure 4. Leakage Current vs Temperature at 5 V Figure 5. I/V Curve Across Temperature Figure 6. Forward Voltage vs Temperature

Copyright © 2017, Texas Instruments Incorporated TVS0500 www.ti.com SLVSED2B –DECEMBER 2017–REVISED FEBRUARY 2018 Product Folder Links: TVS0500 Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TVS0500 is a precision clamp with a low, flat clamping voltage during transient overvoltage events like surge and protecting the system with zero voltage overshoot.

8.2 Functional Block Diagram

8.3 Feature Description

The TVS0500 is a precision clamp that handles 43 A of IEC 61000-4-5 8/20 µs surge pulse. The flat clamping feature helps keep the clamping voltage very low to keep the downstream circuits from being stressed. The flat clamping feature can also help end-equipment designers save cost by opening up the possibility to use lower- cost, lower voltage tolerant downstream ICs. The TVS0500 has minimal leakage under the standoff voltage of 5 V, making it an ideal candidate for applications where low leakage and power dissipation is a necessity. IEC 61000-4-2 and IEC 61000-4-4 ratings make it a robust protection solution for ESD and EFT events. Wide ambient temperature range of –40°C to +125°C a good candidate for most applications. Compact packages enable it to be used in small devices and save board area.

8.4 Reliability Testing

To ensure device reliability, the TVS0500 is characterized against 5000 repetitive pulses of 35 A IEC 61000-4-5 8/20 µs surge pulses at 125°C. The test is performed with less than 10 seconds between each pulse at high temperature to simulate worst case scenarios for fault regulation. After each surge pulse, the TVS0500 clamping voltage, breakdown voltage, and leakage are recorded to ensure that their is no variation or performance degradation. By ensuring robust, reliable, high temperature protection, the TVS0500 enables fault protection in applications that must withstand years of continuous operation with no performance change.

8.5 Device Functional Modes

8.5.1 Protection Specifications

The TVS0500 is specified according to both the IEC 61000-4-5 and IEC 61643-321 standards. This enables usage in systems regardless of which standard is required in relevant product standards or best matches measured fault conditions. The IEC 61000-4-5 standards requires protection against a pulse with a rise time of 8 µs and a half length of 20 µs, while the IEC 61643-321 standard requires protection against a much longer pulse with a rise time of 10 µs and a half length of 1000 µs.

SLVSED2B –DECEMBER 2017–REVISED FEBRUARY 2018 www.ti.com Product Folder Links: TVS0500 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Device Functional Modes (continued) The positive and negative surges are imposed to the TVS0500 by a combinational waveform generator (CWG) with a 2-Ω coupling resistor at different peak voltage levels. For powered on transient tests that need power supply bias, inductances are usually used to decouple the transient stress and protect the power supply. The TVS0500 is post tested by assuring that there is no shift in device breakdown or leakage at Vrwm. In addition, the TVS0500 has been tested according to IEC 61000-4-5 to pass a ±2 kV surge test through a 42-Ω coupling resistor and a 0.5 µF capacitor. This test is a common test requirement for industrial signal I/O lines and the TVS0500 will serve an ideal protection solution for applications with that requirement. The TVS0500 allow integrates IEC 61000-4-2 level 4 ESD Protection and 80 A of IEC 61000-4-4 EFT Protection. These combine to ensure that the device can protect against most transient conditions regardless of length or type. For more information on TI's test methods for Surge, ESD, and EFT testing, reference TI's IEC 61000-4-x Testing Application Note

8.5.2 Minimal Derating

Unlike traditional diodes the TVS0500 has very little derating of max power dissipation and ensures robust performance up to 125°C, shown in Figure 8. Traditional TVS diodes lose up to 50% of their current carrying capability when at high temperatures, so a surge pulse above 85°C ambient can cause failures that are not seen at room temperature. The TVS0500 prevents this and ensures that you will see the same level of protection regardless of temperature.

8.5.3 Transient Performance

During large transient swings, the TVS0500 will begin clamping the input signal to protect downstream conditions. While this prevents damage during fault conditions, it can cause leakage when the intended input signal has a fast slew rate. In order to keep power dissipation low and remove the chance of signal distortion, it is recommended to keep the slew rate of any input signal on the TVS0500 below 2.5 V/µs at room temperature and below 0.7 V/µs at 125°C shown in Figure 9. Faster slew rates will cause the device to clamp the input signal and draw current through the device for a few microseconds, increasing the rise time of the signal. This will not cause any harm to the system or to the device, however if the fast input voltage swings occur regularly it can cause device overheating.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

by the environment or other electrical components.

9.2 Typical Application

Figure 10. TVS0500 Application Schematic

9.2.1 Design Requirements

9.2.2 Detailed Design Procedure

resistance of the TVS0500, large amounts of surge current will have minimal impact on the clamping voltage. voltage. This ensures robust protection of your circuit. efficiency metrics or add heating concerns.

SLVSED2B –DECEMBER 2017–REVISED FEBRUARY 2018 www.ti.com Product Folder Links: TVS0500 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Typical Application (continued)

9.2.3 Configuration Options

The TVS0500 can be used in either unidirectional or bidirectional configuration. Figure 10 shows unidirectional usage to protect an input. By placing two TVS0500's in series with reverse orientation, bidirectional operation can be used, allowing a working voltage of ±5 V. TVS0500 operation in bidirectional will be similar to unidirectional operation, with a minor increase in breakdown voltage and clamping voltage. The TVS3300 bidirectional performance has been characterized in the TVS3300 Configurations Characterization. While the TVS0500 in bidirectional configuration has not specifically been characterized, it will have similar relative changes to the TVS3300 in bidirectional configuration.

10 Power Supply Recommendations

The TVS0500 is a clamping device so there is no need to power it. To ensure the device functions properly do not violate the recommended VIN voltage range (0 V to 5 V) .

11 Layout

11.1 Layout Guidelines

between the TVS and the connector. Route the protected traces straight. corners with the largest radii possible. Electric fields tend to build up on corners, increasing EMI coupling.

11.2 Layout Example

Figure 11. TVS0500 Layout

SLVSED2B –DECEMBER 2017–REVISED FEBRUARY 2018 www.ti.com Product Folder Links: TVS0500 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 20-Feb-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTVS0500DRVR ACTIVE WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TVS0500DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1HRH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 15-Feb-2018 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TVS0500DRVR WSON DRV 6 3000 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 15-Feb-2018 Pack Materials-Page 2

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. DRV 6 WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4206925/F

www.ti.com PACKAGE OUTLINE C 6X 0.35 0.25 1.6±0.1 6X 0.3 0.2 1.3 1±0.1 4X 0.65

0.8 MAX

0.05 0.00 B 2.1 1.9 A 2.1 1.9 (0.2) TYP WSON - 0.8 mm max heightDRV0006A PLASTIC SMALL OUTLINE - NO LEAD 4222173/A 12/2015 PIN 1 INDEX AREA SEATING PLANE 0.08 C 3 4 (OPTIONAL) PIN 1 ID

0.1 C A B

0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 5.500

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

(1) 4X (0.65) (1.95) 6X (0.3) 6X (0.45) (1.6) (R ) TYP0.05 ( ) VIA TYP 0.2 (1.1) WSON - 0.8 mm max heightDRV0006A PLASTIC SMALL OUTLINE - NO LEAD 4222173/A 12/2015 SYMM 3 4 SYMM LAND PATTERN EXAMPLE SCALE:25X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 6X (0.3) 6X (0.45) 4X (0.65) (0.7) (1) (1.95) (R ) TYP0.05 (0.45) WSON - 0.8 mm max heightDRV0006A PLASTIC SMALL OUTLINE - NO LEAD 4222173/A 12/2015 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD #7 88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:30X SYMM 3 4 SYMM METAL

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