TSM24A-Q1 TI | Alldatasheet
Document overview
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Technical content
TSM24A-Q1 24 V Unidirectional Surge Diode for Automotive Networks in SOT-23 Package
1 Features
- Robust surge protection: – IEC61000-4-5 (8/20 µs): 60 A
- Low clamping voltage of 38 V (typical) at 60 A for 8/20 µs surge current protects downstream components
- Unidirectional polarity for optimized clamping performance on single ended data lines and power rails
- 24 V working voltage for protecting signals on 12-V systems
- Low leakage current of 100 nA (maximum)
- Low I/O capacitance of 54 pF (typical)
- Integrated level 4 IEC 61000-4-2 ESD protection – 30-kV ESD protection (IEC 61000-4-2)
- Small SOT-23 leaded package to minimize board space and allow for automatic optical inspection (AOI)
- AEC-Q101 qualified for automotive applications
2 Applications
- Industrial sensors
- USB Type-C™ VBUS
- PLC I/O modules
- 24-V power lines or digital input or output lines
- Appliances
- Medical equipment
- Motor drivers
3 Description
The TSM24A-Q1 is a part of TI's surge protection device family. The TSM24A-Q1 robustly shunts up to
60 A of IEC 61000-4-5 fault current to protect systems
from high power transients or lightning strikes. The device offers a solution to the common industrial signal line EMC requirement to survive up to 2.5 kV IEC 61000-4-5 open circuit voltage coupled through a 42 Ω impedance. The TSM24A-Q1 clamps during a surge event, keeping system exposure below 38 V (typical) at I PP = 60 A. Additionally, the TSM24A-Q1 is available in a small leaded SOT-23 (DBZ) package which is reduced in size by approximately 50 percent compared to the industry standard SMA package. The device is designed to have a minimal effect on the protected line due to extremely low device leakage. For the bidirectional version of this device, please see TSM24CA-Q1.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TSM24A-Q1 DBZ (SOT-23, 3) 2.92 mm × 2.37 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. TSM24A-Q1 IO GND Functional Block Diagram ADVANCE INFORMATION TSM24A-Q1 SLVSH76 – JUNE 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.
9 Mechanical, Packaging, and Orderable Information....7
4 Revision History
June 2023 * Initial Release TSM24A-Q1 SLVSH76 – JUNE 2023 www.ti.com ADVANCE INFORMATION
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5 Pin Configuration and Functions
Figure 5-1. DBZ Package, 3-Pin SOT-23 (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. IO 3 I/O Surge and ESD protected IO GND 1, 2 G Connect to ground. To achieve the rated performance, it is required to connect pin 1 and 2 together on the PCB as close to the device as possible. (1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power www.ti.com TSM24A-Q1 SLVSH76 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TSM24A-Q1
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) Parameter MIN MAX UNIT PPPM IEC 61000-4-5 Surge (tp = 8/20 µs) Peak Pulse Power at 25 °C (2) 2800 W IPPM IEC 61000-4-5 Surge (tp = 8/20 µs) Peak Pulse Current at 25 °C (2) 60 A TA Operating free-air temperature –55 150 °C Tstg Storage temperature –65 155 °C (1) Operation outside the Absolute Maximum Rating may cause permanent device damage. Absolute Maximum Rating do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Condition. If used outside the Recommended Operating Condition but within the Absolute Maximum Rating, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Voltages are with respect to GND unless otherwise noted.
6.2 ESD Ratings - AEC Specifications
Parameter Test Conditions VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q101-001(1) ±2500 VCharged device model (CDM), per AEC Q101-005(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings - IEC Specifications
Parameter Test Conditions VALUE UNIT V(ESD) Electrostatic discharge IEC 61000-4-2 Contact Discharge, all pins ±30000 V IEC 61000-4-2 Air Discharge, all pins ±30000
6.4 ESD Ratings - ISO Specifications
Parameter Test Conditions VALUE UNIT V(ESD) ISO 10605 Electrostatic Discharge C = 150 pF; R = 330 Ω Contact Discharge, all pins ±30000 V Air-gap Discharge, all pins ±30000 C = 330 pF; R = 330 Ω Contact Discharge, all pins ±30000 Air-gap Discharge, all pins ±30000
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage 0 24 V TA Operating Free Air Temperature –55 150 °C TSM24A-Q1 SLVSH76 – JUNE 2023 www.ti.com ADVANCE INFORMATION
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6.6 Electrical Characteristics
At TA = 25°C unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO < 100 nA 24 V ILEAK Leakage current at VRWM VIO = 24 V, I/O to GND 50 100 nA VBR Breakdown voltage, I/O to GND (1) IIO = 10 mA 24.8 29 V VFWD Forward Voltage, GND to I/O (1) IIO = 10 mA 0.7 V VCLAMP Surge clamping voltage, tp = 8/20 µs (2) IPP = 60 A, I/O to GND 38 V VCLAMP Surge clamping voltage, tp = 8/20 µs (2) IPP = 60 A, GND to I/O 7 V CLINE Line capacitance, IO to GND VIO = 0 V, f = 1 MHz 54 pF (1) VBR is defined as the voltage obtained at 10 mA when sweeping the voltage up, before the device latches into the snapback state (2) Device stressed with 8/20 µs exponential decay waveform according to IEC 61000-4-5 www.ti.com TSM24A-Q1 SLVSH76 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TSM24A-Q1
7 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
7.1 Application Information
The TSM24A-Q1 is a diode type TVS which provides a path to ground for dissipating transient voltage spikes, such as ESD or surge, on signal lines and power lines. The device should be connected in parallel to the down stream circuitry it is protecting. As the current from the transient passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage (VCLAMP) to a safe level for the protected IC. For more information on how to properly use this device, refer to the ESD Packaging and Layout Guide. TSM24A-Q1 SLVSH76 – JUNE 2023 www.ti.com ADVANCE INFORMATION
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8 Device and Documentation Support
8.1 Documentation Support
8.1.1 Related Documentation
For related documentation, see the following:
- Texas Instruments, TI's IEC 61000-4-x Testing application note
- Texas Instruments, ESD Layout Guide user's guide
- Texas Instruments, ESD Protection Diodes EVM user's guide
- Texas Instruments, Generic ESD Evaluation Module user's guide
- Texas Instruments, Reading and Understanding an ESD Protection data sheet
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
Type-C™ is a trademark of USB Implementers Forum. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TSM24A-Q1 SLVSH76 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TSM24A-Q1
9.1 Tape and Reel Information
Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TSM24A-Q1 SLVSH76 – JUNE 2023 www.ti.com ADVANCE INFORMATION
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TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSM24AQDBZR SOT-23 DBZ 3 3000 2.10.0 185.0 35.0 www.ti.com TSM24A-Q1 SLVSH76 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TSM24A-Q1
9.2 Mechanical Data
www.ti.com PACKAGE OUTLINE C TYP0.20 0.08 0.25 2.64 2.10
1.12 MAX
TYP0.10 0.01 3X 0.5 0.3 TYP0.6 0.2 1.9 0.95 TYP-80 A 3.04 2.80 B1.4 1.2 (0.95) SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration TO-236, except minimum foot length.
0.2 C A B
0.1 C SCALE 4.000 TSM24A-Q1 SLVSH76 – JUNE 2023 www.ti.com ADVANCE INFORMATION
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www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
3X (1.3) 3X (0.6) (2.1) 2X (0.95) (R0.05) TYP 4214838/C 04/2017 SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE SCALE:15X PKG SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS www.ti.com TSM24A-Q1 SLVSH76 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TSM24A-Q1
www.ti.com EXAMPLE STENCIL DESIGN (2.1) 2X(0.95) 3X (1.3) 3X (0.6) (R0.05) TYP SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM PKG TSM24A-Q1 SLVSH76 – JUNE 2023 www.ti.com ADVANCE INFORMATION
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www.ti.com 22-Jun-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTSM24ADBZRQ1 ACTIVE SOT-23 DBZ 3 3000 TBD Call TI Call TI -55 to 150 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com PACKAGE OUTLINE C 0.20
0.08 TYP
0.25 2.64 2.10 0.10
0.01 TYP
3X 0.5 0.3 0.6
0.2 TYP
1.9 0.95 0 -8 TYP A 3.04 2.80 B1.4 1.2 (0.95) (0.15) (0.125) SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/D 03/2023 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration TO-236, except minimum foot length. 4. Support pin may differ or may not be present. 0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT 3X (1.3) 3X (0.6) (2.1) 2X (0.95) (R0.05) TYP 4214838/D 03/2023 SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE SCALE:15X PKG SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS
www.ti.com EXAMPLE STENCIL DESIGN (2.1) 2X(0.95) 3X (1.3) 3X (0.6) (R0.05) TYP SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/D 03/2023 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM PKG
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