TSD05C TI | Alldatasheet
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Technical content
TSD05C 5-V Bidirectional TVS Diode in SOD-323 Package
1 Features
- IEC 61000-4-2 level 4 ESD protection: – ±30 kV contact discharge – ±30 kV air gap discharge
- IEC 61000-4-5 surge protection: – 30 A (8/20 µs) – Low clamping voltage: 14 V at 30 A (8/20 μs)
- Low IO capacitance: – 6 pF (typical)
- DC breakdown voltage: ±7 V (typical)
- Ultra low leakage current: 1 μA (maximum)
- Low ESD clamping voltage: 9.3 V at 16 A TLP
- Industrial temperature range: –40°C to +125°C
- Industry standard SOD-323 leaded package (2.5 mm × 1.2 mm)
2 Applications
- 5-V power rails
- USB VBUS
- GPIO
- Push buttons
- Grid infrastructure
- EPOS
- Portable electronics
3 Description
The TSD05C is a bidirectional TVS protection diode designed for clamping harmful transients such as ESD and surge. The TSD05C is rated to dissipate ESD strikes up to ±30 kV (contact and air gap discharge) and also meets the maximum level specified in the IEC 61000-4-2 international standard (Level 4). For surges, the device can clamp 8/20 μs surges with peak pulse currents up to 30 A in accordance with the IEC 61000-4-5 standard. This device also features a 6 pF (typical) IO capacitance enabling it to protect high-speed data lines. The low dynamic resistance and low clamping voltage provides system level protection against transient events. Combining the robust clamping performance and low capacitance of this device, TSD05C is an excellent TVS diode to protect both data lines and power lines in many different applications. The TSD05C is offered in the industry standard, leaded SOD-323 package to enable easy solderability.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TSD05C DYF (SOD-323, 2) 2.65 mm × 1.3 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. IO GND Functional Block Diagram ADVANCE INFORMATION TSD05C SLVSH42 – JUNE 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.
9 Mechanical, Packaging, and Orderable Information....7
4 Revision History
June 2023 * Initial Release TSD05C SLVSH42 – JUNE 2023 www.ti.com ADVANCE INFORMATION
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5 Pin Configuration and Functions
Figure 5-1. DYF Package, 2-Pin SOD-323 (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME 1 IO I/O Protected Channel. If used as IO, connect pin 2 to ground 2 IO I/O Protected Channel. If used as IO, connect pin 1 to ground (1) I = input, O = output www.ti.com TSD05C SLVSH42 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TSD05C
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Electrical Fast Transient (3) IEC 61000-4-4 Peak Current (tp - 5/50 ns) 80 A Peak Pulse (2) (3) IEC 61000-4-5 power (tp - 8/20 µs) 400 W IEC 61000-4-5 Current (tp - 8/20 µs) 30 A TA Ambient Operating Temperature -55 125 °C Tstg Storage Temperature -65 155 °C (1) Operation outside the Absolute Maximum Rating may cause permanent device damage. Absolute Maximum Rating do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Condition. If used outside the Recommended Operating Condition but within the Absolute Maximum Rating, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Voltages are with respect to GND unless otherwise noted. (3) Measured at 25℃
6.2 ESD Ratings—JEDEC Specification
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001 (1) ±2500 V Charged device model (CDM), per JEDEC specification JS-002 (2) ±1000 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings—IEC Specification
V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±30000 V IEC 61000-4-2 air-gap discharge ±30000
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIO Input pin voltage IO to GND -5.5 5.5 V TA Operating free-air temperature -55 125 °C TSD05C SLVSH42 – JUNE 2023 www.ti.com ADVANCE INFORMATION
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6.5 Electrical Characteristics
At TA=25℃ (unless otherwise noted) (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO <1 µA, across operating temperature range -5.5 5.5 V ILEAK Reverse leakage current VIO = 5.5 V, IO to GND or GND to IO 5 50 nA VBRR Break-down voltage IIO = 1 mA, IO to GND 7 8 9 V VBRF Break-down voltage IIO = 1 mA, GND to IO 7 8 9 V VHOLD Holding voltage (1) TLP, IO to GND or GND to IO 7.5 V VCLAMP Surge clamping voltage, tp = 8/20 µs (4) IPP = 1 A, IO to GND or GND to IO 8 V IPP = 24 A, IO to GND or GND to IO 11 V IPP = 30 A, IO to GND or GND to IO 14 V TLP clamping voltage, tp = 100 ns IPP = 16 A, IO to GND or GND to IO 9.3 V CL Line capacitance VIO = 0 V; ƒ = 1 MHz, IO to GND 6 pF (1) Typical parameters are measured at 25℃. (2) Transition line pulse with 100 ns width and 10 ns rise and fall time. (3) Non-repetitive current pulse 8 to 20 µs exponentially decaying waveform according to IEC 61000-4-5. www.ti.com TSD05C SLVSH42 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TSD05C
7 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
7.1 Application Information
The TSD05C is a diode type TVS which provides a path to ground for dissipating transient voltage spikes, such as ESD or surge, on signal lines and power lines. The device should be connected in parallel to the down stream circuitry it is protecting. As the current from the transient passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low R DYN of the triggered TVS holds this voltage (VCLAMP) to a safe level for the protected IC. For more information on how to properly use this device, refer to the ESD Packaging and Layout Guide. TSD05C SLVSH42 – JUNE 2023 www.ti.com ADVANCE INFORMATION
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8 Device and Documentation Support
8.1 Documentation Support
8.1.1 Related Documentation
For related documentation, see the following:
- Texas Instruments, ESD Packaging and Layout Guide application reports
- Texas Instruments, ESD Layout Guide application reports
- Texas Instruments, Generic ESD Evaluation Module user's guide
- Texas Instruments, Picking ESD Diodes for Ultra High-Speed Data Lines application reports
- Texas Instruments, Reading and Understanding an ESD Protection data sheet
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation www.ti.com TSD05C SLVSH42 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TSD05C
9.1 Tape and Reel Information
Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TSD05C SLVSH42 – JUNE 2023 www.ti.com ADVANCE INFORMATION
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TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSD05CDYFR SOT DYF 2 3000 210.0 200.0 42.0 www.ti.com TSD05C SLVSH42 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TSD05C
9.2 Mechanical Data
www.ti.com PACKAGE OUTLINE 0.15
0.08 TYP
0.2 2.75 2.55
1 MAX
0.1
0.0 TYP
2X 0.35 0.25 1.8 1.6 1.4 1.2 0.40
0.25 TYP
(0.475) (0.85) SOT(SOD-323) - 1 mm max heightDYF0002A SMALL OUTLINE TRANSISTOR 4228484/A 02/2022 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 1 (-) 2 (+) PIN 1 ID GAGE PLANE SCALE 6.000 TSD05C SLVSH42 – JUNE 2023 www.ti.com ADVANCE INFORMATION
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www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
2X (0.9) 2X (0.5) (2.6) (R0.05) TYP 4228484/A 02/2022 SOT(SOD-323) - 1 mm max heightDYF0002A SMALL OUTLINE TRANSISTOR NOTES: (continued) 3. Publication IPC-7351 may have alternate designs. 4. Solder mask tolerances between and around signal pads can vary based on board fabrication site. PKG LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:25X PKG 1 2 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL www.ti.com TSD05C SLVSH42 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TSD05C
www.ti.com EXAMPLE STENCIL DESIGN (2.6) 2X (0.9) 2X (0.5) (R0.05) TYP SOT(SOD-323) - 1 mm max heightDYF0002A SMALL OUTLINE TRANSISTOR 4228484/A 02/2022 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 6. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:25X PKG PKG 1 2 TSD05C SLVSH42 – JUNE 2023 www.ti.com ADVANCE INFORMATION
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www.ti.com 11-Jun-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTSD05CDYFR ACTIVE SOT DYF 2 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com PACKAGE OUTLINE 0.15 0.2 2.75 2.55 0.1 2X 0.35 0.25 1.8 1.6 1.4 1.2 0.40 (0.475) (0.85) SOT(SOD-323) - 1 mm max heightDYF0002A SMALL OUTLINE TRANSISTOR 4228484/A 02/2022 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 1 (-) 2 (+) PIN 1 ID GAGE PLANE SCALE 6.000
www.ti.com EXAMPLE BOARD LAYOUT 2X (0.9) 2X (0.5) (2.6) (R0.05) TYP 4228484/A 02/2022 SOT(SOD-323) - 1 mm max heightDYF0002A SMALL OUTLINE TRANSISTOR NOTES: (continued) 3. Publication IPC-7351 may have alternate designs. 4. Solder mask tolerances between and around signal pads can vary based on board fabrication site. PKG LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:25X PKG 1 2 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.6) 2X (0.9) 2X (0.5) (R0.05) TYP SOT(SOD-323) - 1 mm max heightDYF0002A SMALL OUTLINE TRANSISTOR 4228484/A 02/2022 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 6. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:25X PKG PKG 1 2
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