TRF0208-SEP TI | Alldatasheet
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Technical content
TRF0208-SEP Radiation-Tolerant, Near-DC to 11GHz, Fully Differential RF Amplifier
1 Features
- Vendor item drawing available, VID V62/23605
- Radiation: – Total ionizing dose (TID)
- Radiation hardness assurance (RHA) up to 30krad (Si) TID
- Enhanced low dose rate sensitivity (ELDRS) free process
- High dose rate radiation lot acceptance testing (HDR RLAT) up to 30krad (Si) TID – Single event effects (SEE)
- Single event latch-up (SEL) immune to linear energy transfer (LET) of 43MeV‑cm2/mg
- Single event transient (SET) characterized to LET of 43MeV‑cm2/mg
- Space-enhanced plastic (SEP) – Lead-free construction – Extended temperature range: –55°C to +125°C
- Excellent performance driving RF ADCs
- Fixed power gain of 16dB in single-ended-to- differential mode
- Bandwidth: 11GHz, 3dB
- Gain flatness: 8GHz, 1dB
- OIP3: 36dBm (2GHz), 32dBm (6GHz)
- P1dB: 14.5dBm (2GHz), 11dBm (6GHz)
- NF: 6.8dB (2GHz), 6.8dB (6GHz)
- Gain and phase imbalance: ±0.3dB and ±3º
- Power-down feature
- Single-supply operation: 3.3V
- Active current: 138mA
2 Applications
- RF sampling or GSPS ADC driver
- Aerospace and defense
- Phased array radar
- Communications payload
- Radar imaging payload
- Radiation tolerant applications
3 Description
The TRF0208-SEP is a very high performance fully differential amplifier (FDA) optimized for radio frequency (RF) applications. This device is excellent for ac-coupled applications that require a single- ended to differential conversion when driving an analog-to-digital converter (ADC) such as the high-performance ADC12DJ5200-SEP. The on-chip matching components simplify printed circuit board (PCB) implementation and provide the highest performance over the usable bandwidth. The device is fabricated in Texas Instruments’ advanced complementary BiCMOS process and is available in a space-saving, WQFN-FCRLF package. The TRF0208-SEP operates on a single-rail supply and consumes about 138mA of active current. A power-down feature is available for power saving. Device Information PART NUMBER(1) GRADE BODY SIZE(2) TRF0208RPVTNSP(3) Flight grade SEP 2.00mm × 2.00mm Mass = 7.558mgTRF0208RPVT/EM Engineering samples(4) (1) For more information, see Section 10. (2) The body size (length × width) is a nominal value and does not include pins. Mass is a nominal value. (3) Preview device. (4) These units are intended for engineering evaluation only. These samples are processed to a non-compliant flow. These units are not for qualification, production, radiation testing, or flight use. Parts are not warranted for performance over the full MIL specified temperature range, or operating life. TRF0208-SEP RS PD AFE7950-SEP or ADC12DJ5200-SEP VDD TRF0208-SEP Driving a High-Speed ADC ADVANCE INFORMATION TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.
10 Mechanical, Packaging, and Orderable
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4 Pin Configuration and Functions
1 GND
3 TP2
4 GND
7 GND
8 TP1
9 VDD
10 GND
11 OUTP
12 OUTM
Figure 4-1. RPV Package, 12-Pin WQFN-FCRLF (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. GND 1, 4, 7, 10 GND Ground INM 5 I Differential signal input, negative INP 6 I Differential signal input, positive OUTM 12 O Differential signal output, negative OUTP 11 O Differential signal output, positive PD 2 I Power-down signal. Supports 1.8V and 3.3V logic. 0 = Chip enabled 1 = Power down TP1 8 — Test pin. Short to ground. TP2 3 — Test pin. Short to ground. VDD 9 P 3.3V supply Thermal pad Pad — Thermal pad. Connect to ground on board. (1) I = input, O = output, P = power, GND = ground www.ti.com TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TRF0208-SEP ADVANCE INFORMATION
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD Supply voltage –0.3 3.7 V INP, INM Input pin power 20 dBm VPD Power-down pin voltage –0.3 3.7 V TJ Junction temperature 150 ºC Tstg Storage temperature –65 150 ºC Continuous power dissipation See Thermal Information (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
5.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±1000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) ±250 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage 3.2 3.3 3.45 V TA Ambient air temperature –55 25 °C TJ Junction temperature 125 °C
5.4 Thermal Information
THERMAL METRIC(1) TRF0208-SEP UNITRPV (WQFN-FCRLF)
12 PINS
RθJA Junction-to-ambient thermal resistance 66.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 64.3 °C/W RθJB Junction-to-board thermal resistance 17.4 °C/W ΨJT Junction-to-top characterization parameter 1.7 °C/W ΨJB Junction-to-board characterization parameter 17.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 9.0 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 www.ti.com
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5.5 Electrical Characteristics
at TA = 25°C, VDD = 3.3V, 50Ω single-ended input, and 100Ω differential output (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE SSBW Small-signal 3dB bandwidth VO = 0.1VPP 11 GHz LSBW Large-signal 3dB bandwidth VO = 1VPP 11 GHz 1dB BW Bandwidth for 1dB flatness 8 GHz S21 Power gain f = 2GHz 16 dB S11 Input return loss f = 10MHz to 8GHz –10 dB S12 Reverse isolation f = 2GHz –35 dB ImbGAIN Gain imbalance f = 10MHz to 8GHz ± 0.3 dB ImbPHASE Phase imbalance f = 10MHz to 8GHz ± 3 degrees CMRR Common-mode rejection ratio(1) f = 2GHz –45 dB HD2 Second-order harmonic distortion f = 0.5GHz, PO = 3dBm –70 dBc f = 2GHz, PO = 3dBm –65 f = 6GHz, PO = 3dBm –52 f = 8GHz, PO = 3dBm –50 HD3 Third-order harmonic distortion f = 0.5GHz, PO = 3dBm –68 dBc f = 2GHz, PO = 3dBm –63 f = 6GHz, PO = 3dBm –54 f = 8GHz, PO = 3dBm –60 IMD2 Second-order intermodulation distortion f = 0.5GHz, PO = –4dBm per tone (10MHz spacing) –72 dBc f = 2GHz, PO = –4dBm per tone (10MHz spacing) –64 f = 6GHz, PO = –4dBm per tone (10MHz spacing) –54 f = 8GHz, PO = –4dBm per tone (10MHz spacing) –48 IMD3 Third-order intermodulation distortion f = 0.5GHz, PO = –4dBm per tone (10MHz spacing) –77 dBc f = 2GHz, PO = –4dBm per tone (10MHz spacing) –80 f = 6GHz, PO = –4dBm per tone (10MHz spacing) –70 f = 8GHz, PO = –4dBm per tone (10MHz spacing) –48 OP1dB Output 1dB compression point f = 0.5GHz 11 dBm f = 2GHz 14.5 f = 6GHz 11 f = 8GHz 7.5 OIP2 Output second-order intercept point f = 0.5GHz, Po = –4dBm per tone (10MHz spacing) 68 dBm f = 2GHz, Po = –4dBm per tone (10MHz spacing) 60 f = 6GHz, Po = –4dBm per tone (10MHz spacing) 50 f = 8GHz, Po = –4dBm per tone (10MHz spacing) 45 www.ti.com TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TRF0208-SEP ADVANCE INFORMATION
5.5 Electrical Characteristics (continued)
at TA = 25°C, VDD = 3.3V, 50Ω single-ended input, and 100Ω differential output (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OIP3 Output third-order intercept point f = 0.5GHz, Po = –4dBm per tone (10MHz spacing) 34 dBm f = 2GHz, Po = –4dBm per tone (10MHz spacing) 36 f = 4GHz, Po = –4dBm per tone (10MHz spacing) 35 f = 6GHz, Po = –4dBm per tone (10MHz spacing) 32 f = 8GHz, Po = –4dBm per tone (10MHz spacing) 21 NF Noise Figure f = 0.5GHz 6.5 dB f = 2GHz 6.8 f = 6GHz 6.8 f = 8GHz 8.5 IMPEDANCE ZO-DIFF Differential output impedance f = dc (internal to the device) 3 Ω ZIN Single-ended input impedance INM pin terminated with 50Ω 50 Ω TRANSIENT VOMAX Maximum output voltage (differential) 2 VPP VOSAT Output saturated voltage level (differential) f = 2GHz 3.9 VPP tREC Overdrive recovery time Using a –0.5VP input pulse of 2ns duration 0.2 ns POWER SUPPLY IQA Active current Current on VDD pin, PD = 0 138 mA IQPD Power-down quiescent current Current on VDD pin, PD = 1 7 mA ENABLE VPDHIGH PD pin logic high 1.45 V VPDLOW PD pin logic low 0.8 V IPDBIAS PD bias current (current on PD pin) PD = high (1.8V logic) 50 100 µA PD = high (3.3V logic) 200 250 CPD PD pin capacitance 2 pF tON Turn-on time 50% VPD to 90% RF 200 ns tOFF Turn-off time 50% VPD to 10% RF 50 ns (1) Calculated using the formula (S21 – S31) / (S21 + S31). Port-1: INP, Port-2: OUTP, Port-3: OUTM. TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 www.ti.com
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5.6 Typical Characteristics
at TA = 25°C, temperature curves specify ambient temperature, VDD = 3.3V, 50Ω single-ended input, and 100Ω differential output (unless otherwise noted) Frequency (MHz) S21 (dB) 0 2000 4000 6000 8000 10000 12000 -55 C -40 C 25 C 85 C 105 C Figure 5-1. Power Gain Across Temperature Frequency (MHz) S21 (dB) 0 2000 4000 6000 8000 10000 12000 3.15 V 3.3 V 3.45 V Figure 5-2. Power Gain Across VDD Frequency (MHz) S11 (dB) 0 2000 4000 6000 8000 10000 12000 -50 -45 -40 -35 -30 -25 -20 -15 -10 -55 C -40 C 25 C 85 C 105 C Figure 5-3. Return Loss Across Temperature Frequency (MHz) S11 (dB) 0 2000 4000 6000 8000 10000 12000 -50 -45 -40 -35 -30 -25 -20 -15 -10 3.15 V 3.3 V 3.45 V Figure 5-4. Return Loss Across VDD Frequency (MHz) S12 (dB) 0 2000 4000 6000 8000 10000 12000 -55 -50 -45 -40 -35 -30 -25 -20 -55 C -40 C 25 C 85 C 105 C Figure 5-5. Reverse Isolation Across Temperature Frequency (MHz) S12 (dB) 0 2000 4000 6000 8000 10000 12000 -55 -50 -45 -40 -35 -30 -25 -20 3.15 V 3.3 V 3.45 V Figure 5-6. Reverse Isolation Across VDD www.ti.com TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TRF0208-SEP ADVANCE INFORMATION
5.6 Typical Characteristics (continued)
at TA = 25°C, temperature curves specify ambient temperature, VDD = 3.3V, 50Ω single-ended input, and 100Ω differential output (unless otherwise noted) Frequency (MHz) OIP3 (dBm) 0 2000 4000 6000 8000 10000 -55 C -40 C 25 C 85 C 105 C PO /tone = –4dBm, 10MHz tone spacing Figure 5-7. OIP3 Across Temperature Frequency (MHz) OIP3 (dBm) 0 2000 4000 6000 8000 10000 3.15 V 3.3 V 3.45 V PO /tone = –4dBm, 10MHz tone spacing Figure 5-8. OIP3 Across VDD Frequency (MHz) IMD3 Lower freq (dBc) 0 2000 4000 6000 8000 10000 -100 -90 -80 -70 -60 -50 -40 -30 -55 C -40 C 25 C 85 C 105 C At (2f1-f2) frequency, f1 < f2; PO /tone = –4dBm, 10MHz tone spacing Figure 5-9. IMD3 Lower Across Temperature Frequency (MHz) IMD3 Lower freq (dBc) 0 2000 4000 6000 8000 10000 -100 -90 -80 -70 -60 -50 -40 -30 3.15 V 3.3 V 3.45 V At (2f1-f2) frequency, f1 < f2; PO /tone = –4dBm, 10MHz tone spacing Figure 5-10. IMD3 Lower Across VDD Frequency (MHz) IMD3 Higher freq (dBc) 0 2000 4000 6000 8000 10000 -100 -90 -80 -70 -60 -50 -40 -30 -55 C -40 C 25 C 85 C 105 C At (2f2-f1) frequency, f1 < f2; PO /tone = –4dBm, 10MHz tone spacing Figure 5-11. IMD3 Higher Across Temperature Frequency (MHz) IMD3 Higher freq (dBc) 0 2000 4000 6000 8000 10000 -100 -90 -80 -70 -60 -50 -40 -30 3.15 V 3.3 V 3.45 V At (2f2-f1) frequency, f1 < f2; PO /tone = –4dBm, 10MHz tone spacing Figure 5-12. IMD3 Higher Across VDD TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 www.ti.com
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at TA = 25°C, temperature curves specify ambient temperature, VDD = 3.3V, 50Ω single-ended input, and 100Ω differential output (unless otherwise noted) Frequency (MHz) OIP2 Lower freq (dBm) 0 2000 4000 6000 8000 10000 -55 C -40 C 25 C 85 C 105 C At (f2-f1) frequency, f2 > f1; PO /tone = –4dBm, 10MHz tone spacing Figure 5-13. OIP2 Lower Across Temperature Frequency (MHz) OIP2 Lower freq (dBm) 0 2000 4000 6000 8000 10000 3.15 V 3.3 V 3.45 V At (f2-f1) frequency, f2 > f1; PO /tone = –4dBm, 10MHz tone spacing Figure 5-14. OIP2 Lower Across VDD Frequency (MHz) OIP2 Higher freq (dBm) 0 2000 4000 6000 8000 10000 -55 C -40 C 25 C 85 C 105 C At (f2+f1) frequency, f2 > f1; PO /tone = –4dBm, 10MHz tone spacing Figure 5-15. OIP2 Higher Across Temperature Frequency (MHz) OIP2 Higher freq (dBm) 0 2000 4000 6000 8000 10000 3.15 V 3.3 V 3.45 V At (f2+f1) frequency, f2 > f1; PO /tone = –4dBm, 10MHz tone spacing Figure 5-16. OIP2 Higher Across VDD Frequency (MHz) IMD2 Lower freq (dBc) 0 2000 4000 6000 8000 10000 -80 -75 -70 -65 -60 -55 -50 -45 -55 C -40 C 25 C 85 C 105 C At (f2-f1) frequency, f2 > f1; PO /tone = –4dBm, 10MHz tone spacing Figure 5-17. IMD2 Lower Across Temperature Frequency (MHz) IMD2 Lower freq (dBc) 0 2000 4000 6000 8000 10000 -80 -75 -70 -65 -60 -55 -50 -45 3.15 V 3.3 V 3.45 V At (f2-f1) frequency, f2 > f1; PO /tone = –4dBm, 10MHz tone spacing Figure 5-18. IMD2 Lower Across VDD www.ti.com TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TRF0208-SEP ADVANCE INFORMATION
at TA = 25°C, temperature curves specify ambient temperature, VDD = 3.3V, 50Ω single-ended input, and 100Ω differential output (unless otherwise noted) Frequency (MHz) IMD2 Higher freq (dBc) 0 2000 4000 6000 8000 10000 -85 -80 -75 -70 -65 -60 -55 -50 -45 -55 C -40 C 25 C 85 C 105 C At (f2+f1) frequency, f2 > f1; PO /tone = –4dBm, 10MHz tone spacing Figure 5-19. IMD2 Higher Across Temperature Frequency (MHz) IMD2 Higher freq (dBc) 0 2000 4000 6000 8000 10000 -85 -80 -75 -70 -65 -60 -55 -50 -45 3.15 V 3.3 V 3.45 V At (f2+f1) frequency, f2 > f1; PO /tone = –4dBm, 10MHz tone spacing Figure 5-20. IMD2 Higher Across VDD Frequency (MHz) HD2 (dBc) 0 2000 4000 6000 8000 10000 -75 -70 -65 -60 -55 -50 -45 -40 -55 C -40 C 25 C 85 C 105 C PO = +3dBm Figure 5-21. HD2 Across Temperature Frequency (MHz) HD2 (dBc) 0 2000 4000 6000 8000 10000 -75 -70 -65 -60 -55 -50 -45 -40 3.15 V 3.3 V 3.45 V PO = +3dBm Figure 5-22. HD2 Across VDD Frequency (MHz) HD3 (dBc) 0 2000 4000 6000 8000 10000 -85 -80 -75 -70 -65 -60 -55 -50 -45 -55 C -40 C 25 C 85 C 105 C PO = +3dBm Figure 5-23. HD3 Across Temperature Frequency (MHz) HD3 (dBc) 0 2000 4000 6000 8000 10000 -85 -80 -75 -70 -65 -60 -55 -50 -45 3.15 V 3.3 V 3.45 V PO = +3dBm Figure 5-24. HD3 Across VDD TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 www.ti.com
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at TA = 25°C, temperature curves specify ambient temperature, VDD = 3.3V, 50Ω single-ended input, and 100Ω differential output (unless otherwise noted) Output Power (dBm) HD2 (dBc) -4 -2 0 2 4 6 8 -80 -75 -70 -65 -60 -55 -50 -45 -40
1800 MHz
4000 MHz
6000 MHz
8000 MHz
Figure 5-25. HD2 vs Output Power Output Power (dBm) HD3 (dBc) -4 -2 0 2 4 6 8 -80 -75 -70 -65 -60 -55 -50 -45 Figure 5-26. HD3 vs Output Power Frequency (MHz) Output P1dB (dBm) 0 2000 4000 6000 8000 10000 -55 C -40 C 25 C 85 C 105 C Figure 5-27. Output P1dB Across Temperature Frequency (MHz) Output P1dB (dBm) 0 2000 4000 6000 8000 10000 3.15 V 3.3 V 3.45 V Figure 5-28. Output P1dB Across VDD Frequency (MHz) NF (dB) 0 2000 4000 6000 8000 10000 -55 C -40 C 25 C 85 C 105 C Figure 5-29. NF Across Temperature Frequency (MHz) NF (dB) 0 2000 4000 6000 8000 10000 6.5 7.5 8.5 9.5 3.15 V 3.3 V 3.45 V Figure 5-30. NF Across VDD www.ti.com TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TRF0208-SEP ADVANCE INFORMATION
at TA = 25°C, temperature curves specify ambient temperature, VDD = 3.3V, 50Ω single-ended input, and 100Ω differential output (unless otherwise noted) Frequency (MHz) Gain Imbalance (dB) 0 2000 4000 6000 8000 10000 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 -55 C -40 C 25 C 85 C 105 C Figure 5-31. Gain Imbalance Frequency (MHz) Phase Imbalance (degrees) 0 2000 4000 6000 8000 10000 -55 C -40 C 25 C 85 C 105 C Figure 5-32. Phase Imbalance Frequency (MHz) CMRR (dB) 0 2000 4000 6000 8000 10000 -65 -60 -55 -50 -45 -40 -35 -30 -55 C -40 C 25 C 85 C 105 C Figure 5-33. CMRR Across Temperature Frequency (MHz) CMRR (dB) 0 2000 4000 6000 8000 10000 -65 -60 -55 -50 -45 -40 -35 -30 3.15 V 3.3 V 3.45 V Figure 5-34. CMRR Across VDD Time (ns) Amplitude (V) -1.5 -0.5 0.5 1.5 V_measured V_ideal Input = –2dBm, f = 500MHz Figure 5-35. Overdrive Recovery Frequency (MHz) Saturation level (Vpp) 0 2000 4000 6000 8000 10000 0.5 1.5 2.5 3.5 Input = +6dBm Figure 5-36. Saturation Voltage (Differential) TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 www.ti.com
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at TA = 25°C, temperature curves specify ambient temperature, VDD = 3.3V, 50Ω single-ended input, and 100Ω differential output (unless otherwise noted) Figure 5-37. Single-Ended S11 Figure 5-38. Differential S22 www.ti.com TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TRF0208-SEP ADVANCE INFORMATION
6 Detailed Description
6.1 Overview
The TRF0208-SEP is a very high-performance amplifier optimized for radio frequency (RF) and intermediate frequency (IF) with signal bandwidths up to 11GHz. The device is designed for ac-coupled applications that require a single-ended-to-differential conversion when driving an analog-to-digital converter (ADC). The low frequency response is limited only by the ac ‑coupling capacitor on the PCB. If the lowest signal frequency is 10MHz, use 100nF ac-coupling capacitors. If the lowest signal frequency is 9kHz, use a 4.7µF capacitor in parallel with 100nF capacitor on each input-output pin. The device has a two-stage architecture and provides approximately 16dB of gain in single-ended-to-differential mode, when driving a differential 100 Ω load for single- ended inputs driven from a 50Ω source. This device also works as a fully-differential amplifier. This device does not require any pullup or pulldown components on the PCB, and thereby simplifies the layout and provides the highest performance over the entire bandwidth. The input and output are ac coupled. The TRF0208-SEP is powered with 3.3V supply. A power-down feature is also available.
6.2 Functional Block Diagram
The following figure shows the functional block diagram of TRF0208-SEP. The device essentially has two stages with a voltage-feedback configuration. – + TRF0208-SEP TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 www.ti.com
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6.3 Feature Description
6.3.1 Fully-Differential Amplifier
The TRF0208-SEP is a voltage-feedback fully differential amplifier (FDA) with a fixed gain by architecture. The TRF0208-SEP operates best as a single-ended to differential amplifier by terminating the INM pin with a 50 Ω resistor and driving the INP pin directly with no external components. This amplifier has nonlinearity cancellation circuits that provide excellent linearity performance over a wide range of frequencies. The output of the amplifier has a low dc impedance. Therefore, if required, the output of the amplifier can be matched to a load by adding the appropriate series resistors or attenuator pad.
6.3.2 Single Supply Operation
The TRF0208-SEP operates on a single 3.3V supply. The input and output bias voltages are set internally. Therefore, ac-couple the signal path on the board at all four RF input and output pins. Single-supply operation simplifies the board design.
6.4 Device Functional Modes
TRF0208-SEP has two functional modes: active and power-down. The functional modes are controlled by the PD pin as described below.
6.4.1 Power Down Mode
The device features a power-down option. The PD pin is used to power down the amplifier. This pin supports both 1.8V and 3.3V digital logic, and is referenced to ground. A logic 1 turns the device off and places the device into a low-quiescent-current state. When disabled, the signal path is still present through the internal circuits. Input signals applied to a disabled device still appear at the outputs at a lower level through this path, as is the case for any disabled feedback amplifier. www.ti.com TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TRF0208-SEP ADVANCE INFORMATION
7 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
7.1 Application Information
7.1.1 Driving a High-Speed ADC
A common application for the TRF0208-SEP is driving a high-speed ADC that has a differential input (such as the ADC12DJ5200-SEP or AFE7950-SEP). Conventionally passive baluns are used to drive giga-samples-per- second (GSPS) ADCs as a result of the low availability of high-bandwidth, linear amplifiers. The TRF0208-SEP is typically configured as a single-ended to differential (S2D) RF amplifier that has excellent bandwidth flatness, gain, and phase imbalance comparable to or exceeding costly passive RF baluns. Figure 7-1 shows a typical interface circuit for ADC12DJ5200-SEP. Depending on the ADC and system requirement, this circuit can be simplified or can be more complex. TRF0208-SEP ADC12DJ5200-SEP Resistive Matching Pad Antialiasing Filter 50Ω 50Ω Figure 7-1. Interfacing With the ADC12DJ5200-SEP Figure 7-1 shows two sections of the circuit between the driver amp and the ADC: namely, the matching pad (or attenuator pad) and the antialiasing filter. Use small-form-factor, RF-quality, passive components for these circuits. The output swing of the TRF0208-SEP is designed to drive these ADCs full-scale, while at the same time not overdrive the ADC. This functionality avoids the need for any voltage limiting device at the ADC. Figure 7-2 shows a typical interface circuit for the AFE7950-SEP, where the TRF0208-SEP is the S2D amplifier. VDD INP INM PD TP1 TP2 OUTP OUTM GND GND TPAD TRF0208-SEP 3.3V RFC To AFE7950-SEP RX (See NOTE A) 120 10 10 120 100pF 100pF1μF 1μF 100pF 100pF GND GND A. AFE matching network – component type (L or C) and values depend on channel (A, B, C, D, FB1, and FB2) and frequency band. Figure 7-2. Interfacing With the AFE7950-SEP TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 www.ti.com
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7.1.2 Calculating Output Voltage Swing
This section gives a quick reference of the output voltage swings for different input power levels. In this example, the output is terminated with a 100Ω differential load and a power gain of 16dB is assumed. TRF0208-SEP Pi, Vi 50Ω Po, Vo 50Ω 100Ω Figure 7-3. Power and Voltage Levels Voltage gain = 20 × log(VO / VI) (1) Power gain = 10 × log(PO / PI) = 10 × log((VO 2 / 100) / (VI 2 / 50)) = 20 × log(VO / VI) – 3dB (2) Table 7-1. Output Voltage Swings for Different Input Power Levels INPUT OUTPUT (TRF0208-SEP) PI (dBm50) VI (VPP) PO (dBm100) VO (VPP) –20 0.063 –4 0.564 –15 0.112 1 1.004 –10 0.2 6 1.785 –9 0.224 7 2.002
7.1.3 Thermal Considerations
The TRF0208-SEP is available in a 2mm × 2mm, WQFN-FCRLF package that has excellent thermal properties. Connect the thermal pad underneath the chip to a ground plane. Short the ground plane to the other ground pins of the chip at four corners, if possible, to allow heat propagation to the top layer of PCB. Use a thermal via that connects the thermal pad plane on the top layer of the PCB to the inner layer ground planes to allow heat propagation to the inner layers. www.ti.com TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TRF0208-SEP ADVANCE INFORMATION
7.2 Typical Applications
An example of the TRF0208-SEP acting as an S2D amplifier for the AFE7950-SEP is explained in this section.
7.2.1 TRF0208-SEP in Receive Chain
This section describes an RF receiver chain in which the TRF0208-SEP operates as a single-ended-to-differential (S2D) amplifier and drives a receive channel of AFE7950-SEP. Figure 7-4 shows a generic schematic of a design in which TRF0208-SEP drives an AFE7950-SEP receive channel. The exact values of the components depend on the frequency band for which the AFE7950-SEP front-end is matched. Figure 7-4. TRF0208-SEP in a Receive Chain With the AFE7950-SEP TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 www.ti.com
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7.2.1.1 Design Requirements
The AFE7950-SEP channel is required to be matched to 8.2GHz.
7.2.1.2 Detailed Design Procedure
The TRF0208-SEP is configured as an S2D amplifier. The section close to TRF0208-SEP output is an attenuator pad that is meant for robust matching. The section close to the AFE7950-SEP is the matching network for the AFE7950-SEP ADC input that is channel dependent. The matching components are chosen based on the AFE7950-SEP return-loss data and some final optimization because the manufactured board parameters can influence the exact component values needed. Table 7-2 shows the bill of materials (BOM) values of the design for a channel that is matched to center frequency of 8.2GHz. Table 7-2. Component Values of RX Chain With Center Frequency = 8.2GHz SECTION DESIGNATOR TYPE VALUE INSTALL OR DO NOT INSTALL DC block cap C117 Capacitor 100nF Install DC block cap C115 Capacitor 100nF Install DC block cap C111 Capacitor 100nF Install DC block cap C122 Capacitor 100nF Install Attenuator R74 Resistor 10Ω Install Attenuator R70 Resistor 10Ω Install Attenuator R69 Resistor 10Ω Install Attenuator R67 Resistor 10Ω Install Attenuator R71 Resistor 140Ω Install Attenuator R68 Resistor 140Ω Install INM term R82 Resistor 50Ω Install Matching C91 — — Do not install Matching L20 — — Do not install Matching C103 — — Do not install Matching C83 — — Do not install Matching L22 Inductor 0.1nH Install Matching L18 Inductor 0.1nH Install Matching C96 Inductor 0.1nH Install Matching C87 Inductor 0.1nH Install Matching C97 Capacitor 0.8pF Install Matching C88 Capacitor 0.8pF Install Matching C92 Inductor 0.3nH Install www.ti.com TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TRF0208-SEP ADVANCE INFORMATION
7.3 Power Supply Recommendations
The TRF0208-SEP requires a single 3.3V supply. Supply decoupling is critical to high-frequency performance. Typically two or three capacitors are used for supply decoupling. For the lowest-value capacitor, use a small, form-factor component that is placed closest to the V DD pin of the device. Use a bulk decoupling capacitor of a larger value and size that can be placed next to the small capacitor. See also Section 7.4.
7.4 Layout
7.4.1 Layout Guidelines
TRF0208-SEP is a wide-band, voltage-feedback amplifier with approximately 16dB of gain. When designing with a wide-band RF amplifier with relatively high gain, make sure to take certain board layout precautions to maintain stability and optimized performance. Use a multilayer board to maintain signal and power integrity and thermal performance. Figure 7-5 shows an example of a good layout. In this figure, only the top layer is shown. Route the RF input and output lines as grounded coplanar waveguide (GCPW) lines. For the second layer, use a continuous ground layer without any ground-cuts near the amplifier area. Match the output differential lines in length to minimize phase imbalance. Use small footprint passive components wherever possible. Also take care of the input side layout. Use a 50 Ω line for the INP routing, and make sure the termination on INM pin has low parasitics by placing the ac-coupling capacitor and the 50 Ω resistor very close to the device. Use an RF-quality, 50Ω resistor for termination. Ensure that the ground planes on the top and internal layers are well stitched with vias. Place thermal vias under the device that connect the top thermal pad with ground planes in the inner layers of the PCB. For improved heat dissipation, connect the thermal pad to the top layer ground plane through the ground pins (see the Layout Example in the next section).
7.4.2 Layout Example
dc-blocking caps (0402) placed very close to the device 50Ω termination resistor (0201) on INM pin very close to the cap Supply decoupling caps (0201 & 0402) placed very close to the device Matched differential output routing with symmetric ground vias Thermal via under the device, connected to top layer ground for improved heat dissipation TRF0208-SEP device Figure 7-5. Layout Example – Placement and Top Layer Layout The TRF0208-SEP device can be evaluated using the TRF0208-SEP EVM board. Additional information about the evaluation board construction and test setup is given in the TRF0208SEP/SP EVM user's guide. TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 www.ti.com
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8 Device and Documentation Support
8.1 Device Support
8.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
8.2 Documentation Support
8.2.1 Related Documentation
For related documentation, see the following:
- Texas Instruments, TRF0208SEP/SP EVM user's guide
8.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
8.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
8.5 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
8.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (March 2023) to Revision A (June 2024) Page
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TRF0208-SEP ADVANCE INFORMATION
10.1 Package Option Addendum
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball Finish(6) MSL Peak Temp(3) Op Temp (°C) Device Marking(4) (5) PTRF0208RPVT/EM PREVIEW WQFN-FCRLF RPV 12 Call TI Call TI Call TI Level-2-260C-1 YEAR Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 www.ti.com
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10.2 Mechanical Data
www.ti.com PACKAGE OUTLINE C 2.1 1.9 2.1 1.9 0.7 0.6 0.01 0.00 2X 1.5 8X 0.5 2X 0.5 12X 0.5 0.3 12X 0.3 0.2 0.75 0.1 (0.055) TYP 12X (0.18) WQFN-FCRLF - 0.7 mm max heightRPV0012A PLASTIC QUAD FLATPACK - NO LEAD 4225258/B 04/2020 0.08 C
0.1 C A B
0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMM EXPOSED THERMAL PAD SYMM 5 6 1112 SCALE 6.000 AB www.ti.com TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TRF0208-SEP ADVANCE INFORMATION
www.ti.com EXAMPLE BOARD LAYOUT 8X (0.5) (R0.05) TYP
0.05 MAX
0.05 MIN
12X (0.6) 12X (0.25) (1.8) (1.8) ( 0.75) ( 0.2) TYP VIA WQFN-FCRLF - 0.7 mm max heightRPV0012A PLASTIC QUAD FLATPACK - NO LEAD 4225258/B 04/2020 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 30X SEE SOLDER MASK DETAIL 5 6 1112 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 www.ti.com
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www.ti.com EXAMPLE STENCIL DESIGN 12X (0.6) 12X (0.25) 8X (0.5) (1.8) (1.8) 1X ( 0.71) (R0.05) TYP WQFN-FCRLF - 0.7 mm max heightRPV0012A PLASTIC QUAD FLATPACK - NO LEAD 4225258/B 04/2020 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 30X EXPOSED PAD 13 90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 5 6 1112 www.ti.com TRF0208-SEP SBOSAA9A – MARCH 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TRF0208-SEP ADVANCE INFORMATION
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