PTPUL1G113DCUQ

TPUL1G113-Q1 TI | Alldatasheet

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Technical content

TPUL1G113-Q1 Automotive Single Retriggerable Pulse Generator With RC Timing, Rising And Falling Edge Triggers, And Asynchronous Clear

1 Features

• AEC-Q100 qualified for automotive applications: – Device temperature grade 1: -40°C to +125°C – Device HBM ESD classification level 2 – Device CDM ESD classification level C4B
• RC configurable from 1µs to 860ms
• For pulses longer than 860ms, use TPUL1G313-
• 1% typical, 10% maximum pulse width variation
• Wide operating range from 1.5V to 5.5V
• Inputs accept voltages up to 5.5V
• Schmitt-trigger architecture on all inputs

2 Applications

• Generate a positive fixed-width digital pulse
• Detect a digital signal rising edge
• Detect a digital signal falling edge
• Debounce a switch

3 Description

The TPUL1G113-Q1 device is a single RC configurable retriggerable monostable multivibrator designed for operation from 1.5V to 5.5V. The output pulse duration is configured by selecting external resistance and capacitance values with an approximate output pulse width of tw = R × C. This device features three trigger inputs, allowing for rising edge (T) and falling edge ( T) triggers and a clear input ( CLR) that can be used asynchronously to stop an active output pulse, forcing the output low and resetting device. All trigger inputs include Schmitt-trigger architecture to allow for slow input transition rates and improve noise immunity.

Package Information

NUMBER PACKAGE (1) PACKAGE SIZE(2) BODY SIZE TPUL1G113-Q1 DCU (VSSOP, 8) 3.1mm × 2mm 2.3mm × 2mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. Control Logic Cint Vrefh VCC Vrefl T T CLR Q RC C Power-on Reset Functional Block Diagram ADVANCE INFORMATION TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

T T CLR 5GND RC VCC C Q See mechanical drawings for dimensions. Figure 4-1. DCU Package 8-Pin VSSOP Top View Table 4-1. Pin Functions PIN I/O(1) DESCRIPTION NAME NO. T 1 I Falling edge trigger input; requires T and CLR to be held high T 2 I Rising edge trigger input; requires T to be held low and CLR to be held high CLR 3 I Asynchronous clear input, active low; also can operate as rising edge trigger input if T is held low and T is held high GND 4 G Ground Q 5 O Output C 6 G External timing capacitor negative connection; provides a return path for discharge current of the external timing capacitor; internally connected to ground RC 7 I/O External timing node connection; see Application Information section for detailed operation instructions VCC 8 P Positive supply (1) I = Input, O = Output, G = Ground, P = Power www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Digital input voltage range(2) –0.5 6.5 V VO Digital output voltage range in the active state –0.5 VCC + 0.5 V VO Digital output voltage range in the high-impedance state(3) –0.5 6.5 V VRC RC pin voltage range –0.5 VCC + 0.5 V IIK Input clamp diode current, continuous VI < -0.5V –20 mA Input clamp diode current, pulsed 1µs VI < -0.5V –200 mA IOK Output clamp diode current, continuous VO < -0.5V –20 mA Output clamp diode current, pulsed 1µs VO < -0.5V –200 mA IO Digital output current, continuous VO = 0 to VCC ±50 mA Digital output current, pulsed 1µs VO = 0 to VCC ±200 mA Continuous current through VCC or GND ±200 mA Rext External timing resistance 1 kΩ Cext External timing capacitance 1(3) µF TJ Junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. (2) The voltage ratings may be exceeded if the associated clamp current ratings are observed. (3) The timing capacitance maximum value can be exceeded if an external diode is added. See Application and Implementation section for details.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2(1) ±2000 VCharged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B ±1000 (1) AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage 1.5 5.5 V VI Input Voltage(1) 0 5.5 V VO Output Voltage 0 VCC V IOH (2) High-level output current VCC = 1.5V –4 mA VCC = 1.8V –6 mA VCC = 2.5V –26 mA VCC = 3V –50 mA VCC = 4.5V to 5.5V –50 mA TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT IOL (2) Low-level output current VCC = 1.5V 4 mA VCC = 1.8V 6 mA VCC = 2.5V 26 mA VCC = 3V 50 mA VCC = 4.5V to 5.5V 50 mA Rext (3) External timing resistance VCC = 1.5V to 5.5V 6.5 1000 kΩ Cext (3) External timing capacitance VCC = 1.5V to 5.5V 0.1 1000 nF two Configured output pulse width VCC = 1.5V to 5.5V 0.001 860 ms CL Digital output load capacitance VCC = 1.5V to 5.5V 50 pF VPOR Power-on reset ramp voltage Δt/ΔVCC ≥ 20µs/V 0.3 1.5 V Δt/ΔVCC Power-on ramp rate VCC = 0.3V to 1.5V 20 µs/V Δt/Δv Input transition rise or fall rate VCC = 1.5V to 5.5V 100 ms/V TA Operating free-air temperature –40 125 °C (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. (2) Recommended maximum output current for continuous operation; see Electrical Characteristics for test current values to maintain VOH and VOL specifications. Operating with average output current greater than 12mA may impact device reliability and shorten the device lifetime. (3) Recommended Rext and Cext values maintain maximum error provided as Δtwo in the Switching Characteristics table.

5.4 Thermal Information

THERMAL METRIC(1) UNIT RθJA RθJC(top) RθJB ΨJT ΨJB RθJC(bot) DCU (VSSOP) 8 TBD TBD TBD TBD TBD N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

5.5 Electrical Characteristics

Over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VT+ Positive switching threshold 1.5V 0.65 0.84 0.96 V 1.8V 0.73 0.95 1.11 2.5V 0.88 1.11 1.33 3.3V 1.03 1.27 1.5 5V 1.33 1.58 1.82 5.5V 1.41 1.67 1.91 VT- Negative switching threshold 1.5V 0.32 0.41 0.5 V 1.8V 0.36 0.46 0.53 2.5V 0.45 0.55 0.63 3.3V 0.54 0.65 0.74 5V 0.7 0.85 0.96 5.5V 0.74 0.89 1.02 www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

Over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT ΔVT Hysteresis (VT+ - VT-) 1.5V 0.33 0.45 0.6 V 1.8V 0.36 0.5 0.65 2.5V 0.42 0.56 0.72 3.3V 0.49 0.62 0.78 5V 0.61 0.74 0.91 5.5V 0.65 0.77 0.95 VOH High-level output voltage IOH = -50µA 1.5V to 5.5V VCC – 0.1 VCC – 0.01 V IOH = -1mA 1.65V 1.2 1.61 IOH = -2mA 2.3V 2.1 2.24 IOH = -8mA 3V 2.4 2.78 IOH = -12mA 4.5V 3.94 4.21 IOH = -12mA 5.5V 4.94 5.23 VOL Low-level output voltage IOL = 50µA 1.5V to 5.5V 0.01 0.1 V IOL = 1mA 1.65V 0.03 0.45 IOL = 2mA 2.3V 0.04 0.2 IOL = 8mA 3V 0.13 0.4 IOL = 12mA 4.5V 0.15 0.5 IOL = 12mA 5.5V 0.13 0.5 II Input leakage current VI = 5.5V or GND 0V to 5.5V ±50 nA ICEXT Capacitor pin current Monitor state, VCEXT = 5.5V 1.5V to 5.5V ±50 nA Active state, discharging, VCEXT = 1.5V 1.5V 11 mA Active state, discharging, VCEXT = 2.3V 2.3V 29 mA Active state, discharging, VCEXT = 3V 3V 45 mA Active state, discharging, VCEXT = 4.5V 4.5V 95 mA Active state, discharging, VCEXT = 5.5V 5.5V 138 mA Ioff Partial power- off current VI or VO = VCC or GND 0V to 0.3V 0.25 10 µA ICC Supply current Standby state, VI = VCC or GND, IO = 0 5.5V 0.19 2 µA ICC Supply current Active state, VI = VCC or GND, IO = 0 1.5V 40 µA 1.65V 50 2.3V 75 3V 100 4.5V 155 5.5V 195 ΔICC Supply-current change One input, 0 ≤ Vi ≤ VCC, all other inputs at VCC or GND, IO = 0 1.5V to 5.5V 2.1 mA CI VI = 5.5V or GND 5.5V 2 pF CO VO = 5.5V or GND 0V 4 pF Cint Internal capacitance Cext = 0pF; Vcext = 0 to VCC 1.5V 16 17.9 20 pF 1.65V 14 15.5 17 2.3V 7 9.7 13 3V 6 9.9 14 4.5V 5 7.7 10 5.5V 4 5.7 7 TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER DESCRIPTION CONDITION VCC MIN MAX UNIT twi Pulse duration Any trigger input 1.5V 18.2 ns 1.8V ± 0.15V 9.9 2.5V ± 0.2V 7.8 3.3V ± 0.3V 5.8 5V ± 0.5V 4.1 tsu Setup time between trigger inputs T low before T↑ or CLR↑ 1.5V 9.6 ns 1.8V ± 0.15V 8 2.5V ± 0.2V 6.9 3.3V ± 0.3V 6.6 5V ± 0.5V 6.5 T high before T↓ or CLR↑ 1.5V 5 ns 1.8V ± 0.15V 5 2.5V ± 0.2V 5 3.3V ± 0.3V 5 5V ± 0.5V 5 CLR high before T↓ or T↑ 1.5V 9.2 ns 1.8V ± 0.15V 7.8 2.5V ± 0.2V 6.7 3.3V ± 0.3V 6.5 5V ± 0.5V 6.4 th Hold time Any trigger input 1.5V 9.3 ns 1.8V ± 0.15V 7.8 2.5V ± 0.2V 6.7 3.3V ± 0.3V 6.5 5V ± 0.5V 6.4 trr (1) Retrigger time Any trigger input, Cext = 100pF 1.5V 240 ns 1.8V ± 0.15V 184 2.5V ± 0.2V 93 3.3V ± 0.3V 66 5V ± 0.5V 46 Any trigger input, Cext = 0.1µF 1.5V 54 µs 1.8V ± 0.15V 44 2.5V ± 0.2V 26 3.3V ± 0.3V 20 5V ± 0.5V 15 Any trigger input, Cext = 10µF 1.5V 5.4 ms 1.8V ± 0.15V 4.3 2.5V ± 0.2V 2.5 3.3V ± 0.3V 1.9 5V ± 0.5V 1.4 tstartup (2) Startup time 1.5V to 5.5V 0 µs (1) Triggering the clear input (CLR) more often than 11.4 × trr may affect long-term reliability of the device. Repeated fast triggering of the clear input causes excessive average current at the RC pin. www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

(2) Triggers received during device startup may be ignored. The external timing capacitor requires time to charge after startup. For optimal first pulse accuracy, wait a minimum of one retrigger time (trr) after supply voltage has reached stable operating conditions before applying the first trigger. T T CLR RC Q Rising Edge Trigger Falling Edge Trigger Clear Clear Release Trigger Ignore Falling Edge Trigger Retrigger Ignore Clear Release Figure 5-1. Timing Diagram

5.7 Switching Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter Measurement Information PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC MIN TYP MAX UNIT tpd T, T, or CLR Q CL = 15pF 1.5V 9.6 28.6 58.4 ns 1.65V 8.1 23.1 46.3 ns 2.3V 5.4 13.7 24.5 ns 3V 4.4 9.8 16.9 ns 4.5V 3.7 7.1 11.1 ns 5.5V 3.4 6.3 9.6 ns CL = 50pF 1.5V 11.2 31.8 61.6 ns 1.65V 9.4 24.8 49.1 ns 2.3V 6.3 14.3 26.1 ns 3V 5.2 10.8 18.2 ns 4.5V 4.2 7.9 12.2 ns 5.5V 3.9 7 10.4 ns tt Q CL = 15pF 1.5V 4.3 8.3 ns 1.65V 3.9 7 ns 2.3V 3 5.6 ns 3V 2.5 5 ns 4.5V 2.4 4.9 ns 5.5V 2.7 5.8 ns CL = 50pF 1.5V 8.2 34.4 ns 1.65V 7 28 ns 2.3V 4.5 24.6 ns 3V 3.9 17.4 ns 4.5V 3.1 12.6 ns 5.5V 2.9 8.7 ns TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter Measurement Information PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC MIN TYP MAX UNIT two (1) Q Rext = 10kΩ; Cext = 0; CL = 50pF 1.5V 129 405 ns 1.65V 116 311 ns 2.3V 87 161 ns 3V 75 118 ns 4.5V 62 96 ns 5.5V 58 88 ns Rext = 10kΩ; Cext = 0.1µF; CL = 50pF 1.5V 814 996 µs 1.65V 815 997 µs 2.3V 815 997 µs 3V 815 997 µs 4.5V 805 985 µs 5.5V 793 971 µs Δtwo (2) Q CL = 50pF 1.5V to 5.5V ±1 ±10 % Cpd (3) Q T = VCC, T = GND, fI = 10MHz, CL = 50pF, Cext = 0pF, Rext = 1MΩ 1.5V 31.6 pF 1.65V 33.3 pF 2.3V 32.8 pF 3V 22.3 pF 4.5V 22.2 pF 5.5V 23.3 pF (1) Output pulse width (2) Variation in output pulse width excluding external timing components as compared to typical characteristics for K factor. (3) Power dissipation capacitance is calculated in accordance with CMOS Power Consumption and Cpd Calculation. www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

5.8 Typical Characteristics

TA = 25°C (unless otherwise noted) Note The TPUL family of devices are in early release. Preliminary data is provided. Table 5-1. Pulse Width Using Common RC, VCC = 3.3V Resistor Value Capacitor Value 10µF 1µF 100nF 10nF 1nF 100pF 10pF 1kΩ 9.89ms 989µs 103µs 10.7µs 1.19µs 175ns 60ns 15kΩ 139ms 13.9ms 1.40ms 146µs 15.7µs 1.87µs 275ns 22kΩ 204ms 20.4ms 2.07ms 213µs 22.9µs 2.73µs 378ns 33kΩ 306ms 30.6ms 3.09ms 319µs 34.4µs 4.05µs 539ns 47kΩ 434ms 43.4ms 4.40ms 453µs 48.7µs 5.74µs 745ns 100kΩ 924ms 92.4ms 9.36ms 962µs 104µs 12.2µs 1.52µs Supply Voltage (V) Supply Current ( 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -40C 25C 85C 125C Figure 5-2. Supply Current vs Supply Voltage Supply Voltage (V) Supply Current (mA) -0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.5V 1.65V 2.5V 3.3V 4.5V 5.5V Figure 5-3. Supply Current vs Input Voltage TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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E x t e r n a l T i m in g C a p a c it a n c e , C e x t ( F ) K Factor 1 E - 1 1 2 E - 1 1 5 E - 1 1 1 E - 1 0 2 E - 1 0 5 E - 1 0 1 E - 9 2 E - 9 5 E - 9 1 E - 8 2 E - 8 5 E - 8 1 E - 7 2 E - 7 5 E - 7 1 E - 6 0 . 8 1 . 2 1 . 4 1 . 6 1 . 8 2 . 2 2 . 4 2 . 6 2 . 8 1 0 k  2 0 k  5 0 k  1 0 0 k  2 0 0 k  5 0 0 k 

1 M 

Figure 5-9. K Factor, VCC = 1.5V, Rext = 10kΩ to 1MΩ E x t e r n a l T i m in g C a p a c it a n c e , C e x t ( F ) K Factor 1 E - 1 1 2 E - 1 1 5 E - 1 1 1 E - 1 0 2 E - 1 0 5 E - 1 0 1 E - 9 2 E - 9 5 E - 9 1 E - 8 2 E - 8 5 E - 8 1 E - 7 2 E - 7 5 E - 7 1 E - 6 1 0 1 1 1 2 1 3 1 k  2 k  5 k  1 0 k  Figure 5-10. K Factor, VCC = 1.8V, Rext = 1kΩ to 10kΩ E x t e r n a l T i m in g C a p a c it a n c e , C e x t ( F ) K Factor 1 E - 1 1 2 E - 1 1 5 E - 1 1 1 E - 1 0 2 E - 1 0 5 E - 1 0 1 E - 9 2 E - 9 5 E - 9 1 E - 8 2 E - 8 5 E - 8 1 E - 7 2 E - 7 5 E - 7 1 E - 6 0 . 8 0 . 9 1 . 1 1 . 2 1 . 3 1 . 4 1 . 5 1 . 6 1 . 7 1 . 8 1 . 9 2 . 1 2 . 2 2 . 3 2 . 4 2 . 5 2 . 6 1 0 k  2 0 k  5 0 k  1 0 0 k  2 0 0 k  5 0 0 k  Figure 5-11. K Factor, VCC = 1.8V, Rext = 10kΩ to 1MΩ TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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E x t e r n a l T i m in g C a p a c it a n c e , C e x t ( F ) K Factor 1 E - 1 1 2 E - 1 1 5 E - 1 1 1 E - 1 0 2 E - 1 0 5 E - 1 0 1 E - 9 2 E - 9 5 E - 9 1 E - 8 2 E - 8 5 E - 8 1 E - 7 2 E - 7 5 E - 7 1 E - 6 1 0 1 1 1 k  2 k  5 k  1 0 k  Figure 5-12. K Factor, VCC = 2.5V, Rext = 1kΩ to 10kΩ E x t e r n a l T i m in g C a p a c it a n c e , C e x t ( F ) K Factor 1 E - 1 1 2 E - 1 1 5 E - 1 1 1 E - 1 0 2 E - 1 0 5 E - 1 0 1 E - 9 2 E - 9 5 E - 9 1 E - 8 2 E - 8 5 E - 8 1 E - 7 2 E - 7 5 E - 7 1 E - 6 0 . 8 0 . 9 1 . 1 1 . 2 1 . 3 1 . 4 1 . 5 1 . 6 1 . 7 1 . 8 1 . 9 2 . 1 1 0 k  2 0 k  5 0 k  1 0 0 k  2 0 0 k  5 0 0 k  Figure 5-13. K Factor, VCC = 2.5V, Rext = 10kΩ to 1MΩ E x t e r n a l T i m in g C a p a c it a n c e , C e x t ( F ) K Factor 1 E - 1 1 2 E - 1 1 5 E - 1 1 1 E - 1 0 2 E - 1 0 5 E - 1 0 1 E - 9 2 E - 9 5 E - 9 1 E - 8 2 E - 8 5 E - 8 1 E - 7 2 E - 7 5 E - 7 1 E - 6 0 . 5 1 . 5 2 . 5 3 . 5 4 . 5 5 . 5 1 k  2 k  5 k  1 0 k  Figure 5-14. K Factor, VCC = 3.3V, Rext = 1kΩ to 10kΩ www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

E x t e r n a l T i m in g C a p a c it a n c e , C e x t ( F ) K Factor 1 E - 1 1 2 E - 1 1 5 E - 1 1 1 E - 1 0 2 E - 1 0 5 E - 1 0 1 E - 9 2 E - 9 5 E - 9 1 E - 8 2 E - 8 5 E - 8 1 E - 7 2 E - 7 5 E - 7 1 E - 6 0 . 8 0 . 9 1 . 1 1 . 2 1 . 3 1 . 4 1 . 5 1 . 6 1 . 7 1 . 8 1 . 9 1 0 k  2 0 k  5 0 k  1 0 0 k  2 0 0 k  5 0 0 k  Figure 5-15. K Factor, VCC = 3.3V, Rext = 10kΩ to 1MΩ E x t e r n a l T i m in g C a p a c it a n c e , C e x t ( F ) K Factor 1 E - 1 1 2 E - 1 1 5 E - 1 1 1 E - 1 0 2 E - 1 0 5 E - 1 0 1 E - 9 2 E - 9 5 E - 9 1 E - 8 2 E - 8 5 E - 8 1 E - 7 2 E - 7 5 E - 7 1 E - 6 0 . 8 1 . 2 1 . 4 1 . 6 1 . 8 2 . 2 2 . 4 2 . 6 2 . 8 3 . 2 3 . 4 3 . 6 3 . 8 4 . 2 4 . 4 4 . 6 1 k  2 k  5 k  1 0 k  Figure 5-16. K Factor, VCC = 5V, Rext = 1kΩ to 10kΩ E x t e r n a l T i m in g C a p a c it a n c e , C e x t ( F ) K Factor 1 E - 1 1 2 E - 1 1 5 E - 1 1 1 E - 1 0 2 E - 1 0 5 E - 1 0 1 E - 9 2 E - 9 5 E - 9 1 E - 8 2 E - 8 5 E - 8 1 E - 7 2 E - 7 5 E - 7 1 E - 6 0 . 8 0 . 9 1 . 1 1 . 2 1 . 3 1 . 4 1 . 5 1 . 6 1 . 7 1 . 8 1 0 k  2 0 k  5 0 k  1 0 0 k  2 0 0 k  5 0 0 k  Figure 5-17. K Factor, VCC = 5V, Rext = 10kΩ to 1MΩ TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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E x t e r n a l T i m in g C a p a c it a n c e , C e x t ( F ) K Factor 1 E - 1 1 2 E - 1 1 5 E - 1 1 1 E - 1 0 2 E - 1 0 5 E - 1 0 1 E - 9 2 E - 9 5 E - 9 1 E - 8 2 E - 8 5 E - 8 1 E - 7 2 E - 7 5 E - 7 1 E - 6 0 . 8 1 . 2 1 . 6 2 . 4 2 . 8 3 . 2 3 . 6 4 . 4 4 . 8 5 . 2 1 k  2 k  5 k  1 0 k  Figure 5-18. K Factor, VCC = 5.5V, Rext = 1kΩ to 10kΩ E x t e r n a l T i m in g C a p a c it a n c e , C e x t ( F ) K Factor 1 E - 1 1 2 E - 1 1 5 E - 1 1 1 E - 1 0 2 E - 1 0 5 E - 1 0 1 E - 9 2 E - 9 5 E - 9 1 E - 8 2 E - 8 5 E - 8 1 E - 7 2 E - 7 5 E - 7 1 E - 6 0 . 8 0 . 9 1 . 1 1 . 2 1 . 3 1 . 4 1 . 5 1 . 6 1 . 7 1 0 k  2 0 k  5 0 k  1 0 0 k  2 0 0 k  5 0 0 k  Figure 5-19. K Factor, VCC = 5.5V, Rext = 10kΩ to 1MΩ External Timing Capacitance (Cext) Minimum Retrigger Time (trr) 5pF 100pF 1nF 10nF 100nF 1 F 10 F 20ns 100ns s 10 s 100 s 1ms 5ms 1.5V 1.65V 2.3V 4.5V 5.5V Figure 5-20. Minimum Retrigger Time vs External Timing Capacitor Value External Timing Resistance (Rext) Maximum Retrigger Time Error (%) 1k 2k 5k 10k 100k 1M 0.02 0.05 0.1 0.2 0.5 100 200 1.5V 2.3V 4.5V 5.5V Figure 5-21. Maximum Retrigger Time Error as a Percentage of Total Pulse Width Versus External Timing Resistor Value Error data in the following plots indicates changes from typical behavior (nominal material, T A = 25°C) due to variation in manufacturing process and operating free-air temperature. www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

External Timing Capacitance (Cext) Output Pulse Width (two) 100pF 1nF 10nF 100nF 1 F 100ns s 10 s 100 s 1ms 10ms 100ms Rext = 1k Rext = 10k Rext = 100k Rext = 1M Error bars Figure 5-22. Typical Output Pulse Width vs Timing Capacitance Value With Error Bar Overlay Supply Voltage (V) Maximum Error Percentage ( two) 10% 6.5k Rext 100pF Cext 1 F(100k , 1 F) (10k , 1nF) (85k , 100pF) Figure 5-23. Maximum Output Pulse Width Error (Absolute Value) Across Supply Voltage Each Line: One Timing Component Combination Shaded Area: All Timing Component Combinations External Timing Resistance (Rext) Maximum Error Percentage ( two) 5k 10k 20k 50k 100k 200k 1M 10% 1.5V 1.8V 2.5V 3.3V 5.5V 500k Figure 5-24. Maximum Output Pulse Width Error (Absolute Value) Versus Timing Resistor Values With Cext = 100pF External Timing Resistance (Rext) Maximum Error Percentage ( two) 0.5% 1.5% 2.5% 3.5% 4.5% 5.5% 1.5V 1.8V 2.5V 3.3V 5.5V 5kΩ 10kΩ 20kΩ 50kΩ 100kΩ 200kΩ 1MΩ500kΩ Figure 5-25. Maximum Output Pulse Width Error (Absolute Value) Versus Timing Resistor Values With Cext = 1nF TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt < 2.5ns. The outputs are measured individually with one input transition per measurement. CL (1) From Output Under Test Test Point (1) CL includes probe and test-fixture capacitance. Figure 6-1. Load Circuit for Push-Pull Outputs 50%Input 50% VCC 0 V 50% 50% VOH VOL tPLH (1) tPHL (1) VOH VOL tPHL (1) tPLH (1) Output Output 50% 50% (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-2. Voltage Waveforms Propagation Delays VOH VOL Output VCC 0 V Input tf (1)tr (1) 90% 10% 90% 10% tr (1) 90% 10% tf (1) 90% 10% (1) The greater between tr and tf is the same as tt. Figure 6-3. Voltage Waveforms, Input and Output Transition Times Trigger Input VCC 0 V trr 0.5VCC Trigger Event Trigger Event Figure 6-4. Voltage Waveforms, Retrigger Time Supply Voltage VCC t VPOR(max) VPOR(min) VCC Figure 6-5. Voltage Waveforms, Supply Ramp Trigger Input VCC 0 V Vt Trigger Event Supply Voltage VCC 0 V tstartup 1.5V Figure 6-6. Voltage Waveforms, Startup Time www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

7 Detailed Description

7.1 Overview

The TPUL1G113-Q1 device contains one retriggerable monostable multivibrator circuit. A monostable multivibrator, also commonly known as a one shot, produces a single digital pulse when triggered and otherwise maintains a constant output state. The TPUL1G113-Q1 device features three gated trigger inputs for each channel. For a rising edge trigger, the T or CLR input is used. For a falling edge trigger the T input is used. The TPUL1G113-Q1 device includes an asynchronous clear input ( CLR) that can be used to terminate an ongoing output pulse. When triggered, the TPUL1G113-Q1 outputs a positive digital pulse with pulse width defined as t wo = K × R ext × C ext, with R ext and C ext being the external timing resistor and external timing capacitor component values measured in Ω and F, respectively, and K being a unitless nonlinearity correction factor provided in the Typical Characteristics section. The external timing components must be connected as shown in Figure 7-1 . The external ground connection to the C terminal is optional. RC C VCC Rext Cext VCC GND Figure 7-1. Timing Component Connection, With External Ground RC C VCC Rext Cext VCC GND Figure 7-2. Timing Component Connection, Without External Ground

7.1.1 State Machine Description

The TPUL1G113-Q1 contains a simple state machine as shown in the State Machine Diagram with only three states: ready, discharge, monitor. Ready Discharge Trigger Monitor VRC Vrefl VRC Vrefh Trigger VRC < VrefhVRC > Vrefl Clear or POR Figure 7-3. State Machine Diagram In the ready state, the TPUL1G113-Q1 shorts the RC pin to VCC and holds the digital output inactive. When triggered, the state machine changes to the discharge state. The digital output is immediately set to active and the device internally shorts the RC pin to ground, discharging the external timing capacitor. TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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The state machine changes from the discharge state to the monitor state when the RC pin reaches the low reference voltage (Vrefl = 0.25VCC). The RC pin is then set to high impedance, allowing the external timing circuit to naturally charge the timing capacitor back to V CC. When the RC voltage reaches the high reference voltage (Vrefh = 0.69VCC), the state machine returns to the ready state. Table 7-1. State Descriptions State Name Inputs Outputs(1) Trigger VRC ≤ Vrefl VRC ≥ Vrefh CLR RC Q Q Ready Discharge Ready Ready Ready H L H Discharge Discharge Monitor Discharge Ready L H L Monitor Discharge Monitor Ready Ready Z H L (1) H = Driving high, L = Driving low, Z = High impedance

7.2 Functional Block Diagram

V re f h = 0.69 × V C C (1) V re f l = 0 . 25 × V CC (2) Cint indicates total internal parasitic capacitance and can be found in the Electrical Characteristics table. Control Logic Cint Vrefh VCC Vrefl T T CLR Q RC C Power-on Reset Figure 7-4. Functional Block Diagram

7.3 Feature Description

7.3.1 Naming Convention

1 G 1 1 3 Q 1

G : Standard T : Reduced Timing Type 1 : RC 1x, Retrig 2 : RC 1x, Non-retrig 3 : RC 1000x, Retrig 4 : RC 1000x, Non-retrig 5 : Digital, Retrig 6 : Digital, Non-retrig Output(s) 0 : Active low 1 : Active high 2 : Both 6 : Open drain, active low Input(s) 0 : Falling edge (FE) 1 : Rising edge (RE) 2 : FE, RE, async clear 3 : FE, RE, async clear, and trigger on clear release Rating [none] : Commercial / Industrial -Q1 : Automotive, AEC-Q100 Figure 7-5. Device name meaning

7.3.2 Retriggerable One-Shot

This device includes a retriggerable monostable multivibrator (one-shot) circuit that produces a fixed-width output pulse. The output pulse width for a retriggerable one-shot is extended by additional input triggers while www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

the output is active. The output pulse will expire after the configured time period if no other triggers have been received. The output pulse width after a retrigger event is always shorter than the normal output pulse width because the timing capacitor does not need to be fully discharged for a retrigger event. The maximum error due to this change is the time to discharge the selected timing capacitor. The error due to retrigger timing can be minimized by selecting larger resistor values and smaller capacitor values for a given pulse width. See retrigger plots in the Typical Characteristics section for more details.

7.3.3 Timing Mechanism and Accuracy

The output pulse width (t wo) is controlled by the selection of external timing components R ext and C ext. The TPUL1G113-Q1 has been designed to target a typical output pulse width of t wo ≅ Rext × Cext, however the actual pulse width changes with multiple variables, and thus a nonlinearity correction factor, K, is added to provide the system designer with a more accurate pulse width estimation. Equation 3 is used to most accurately predict the output pulse width. t wo = K × R ext × C ext (3) The output pulse width is dependent on multiple variables:

• External timing components (Rext, Cext)
• Voltage
• Temperature
• Manufacturing and design The external timing component values directly control the output pulse width, and any variations in component values due to manufacturing, voltage, aging, or temperature will directly impact the output pulse width. Most resistors maintain very consistent values during operation, and thus tend to have little impact on accuracy. Most capacitors have a wide variation of manufacturing values, and additionally can vary due to age, temperature, and operating voltage. Typically, the timing capacitor is the largest single source of error for RC timed monostable multivibrators. There is also some error introduced by the TPUL1G113-Q1. This error is provided as Δtwo in the Switching Characteristics section and includes variations due to design, manufacturing, and temperature. Estimating the percent error of the output pulse width (e Δtwo) requires multiple inputs. Equation 4 provides the best method to estimate total pulse width error due to tolerance of components, with e R being the error introduced by the timing resistor, e C being the error introduced by the timing capacitor, and Δtwo being the error introduced by the TPUL1G113-Q1. There is additionally some randomness inherent to the pulse width even with all other factors held constant which is typically less than 1% and is accounted for in the Δtwo specification. e Δ tw o = e R + e C + e R e C + Δ t w o 1 + e R + e C + e R e C (4) For a quick estimate, the sum of the error values can be used (e Δtwo ≅ e R + e C + Δ two). For example, a TPUL1G113-Q1 application circuit using a very good Class I (C0G) capacitor with 2% manufacturing tolerance + 0.3% (30ppm/°C) temperature variation, 0.1% resistor, and Δtwo(max) of 10% would have a quickly estimated maximum error of 12.4%. With the more accurate equation, the maximum error is actually 12.64%.

7.3.4 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink and source similar currents. The drive capability of this device may create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important to limit the output power of the device to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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Unused push-pull CMOS outputs must be left disconnected.

7.3.5 CMOS Schmitt-Trigger Inputs

This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics table, using Ohm's law (R = V ÷ I). The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs with slow transitioning signals will increase dynamic current consumption of the device with the maximum value per input defined as ΔICC in the Electrical Characteristics table. For additional information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers. Do not leave inputs floating at any time during operation. Unused inputs must be terminated at a valid high or low voltage level. If a system is not actively driving an input at all times, then a pull-up or pull-down resistor can be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; however, a 10kΩ resistor is recommended and will typically meet all requirements.

7.3.6 Latching Logic with Known Power-Up State

This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type flip-flops, but include all logic circuits that act as volatile memory. In typical logic devices, the output state of each latching circuit is unknown after power is initially applied; however, this device includes an added Power On Reset (POR) circuit which sets the states of all included latching circuits during the power-up ramp prior to the device starting normal functionality. VPOR(min) VPOR(max) t VCC Figure 7-6. Supply (VCC) Ramp Characteristics for Known Power-Up State Figure 7-6 shows a correct supply voltage turn-on ramp and defines values used in the Recommended Operating Conditions and Electrical Characteristics tables. Prior to starting the power-on ramp, the supply must be completely off (VCC ≤ VPOR(min)). The supply voltage must ramp at a rate within the range provided in the Recommended Operating Conditions table. The output state of each latching logic circuit only remains stable as long as power is applied to the device (V CC ≥ VPOR(max)). Variation from these recommendations will result in the device having an unknown power-up state.

7.3.7 Partial Power Down (Ioff)

This device includes circuitry to disable all outputs when the supply pin is held at 0V. When disabled, the outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage current at each output is defined by the Ioff specification in the Electrical Characteristics table.

7.3.8 Clamp Diode Structure

Figure 7-7 shows the inputs and outputs to this device have negative clamping diodes only. www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clamp- current ratings are observed. Figure 7-7. Electrical Placement of Clamping Diodes for Each Input and Output TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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7.4 Device Functional Modes

7.4.1 Off-State Operation

The TPUL1G113-Q1 includes partial-power-down (I off) protection, which forces the outputs into a high- impedance state when the supply voltage is approximately 0V. In the powered-off state, voltages can be applied to the digital inputs and outputs and the device will not respond or have any back-powering. This protection does not apply to the RC pin.

7.4.2 Startup Operation

The TPUL1G113-Q1 includes an internal power-on reset (POR) circuit that prevents erroneous triggers from occurring during startup. There are details on the supply ramp requirements provided in Latching Logic with Known Power-Up State . Normal operation can be started after the startup time (t startup) has expired per the Timing Requirements table. While active, the POR circuit holds the TPUL1G113-Q1 in the Ready state.

7.4.3 On-State Operation

The table below lists the on-state functional modes for the TPUL1G113-Q1. Table 7-2. Function Table INPUTS(1) OUTPUT(2) CLR T T Q L X X L H H X L(3) H X L L(3) H L ↑ (4) H ↓ H (4) ↑ L H (1) H = high voltage level, L = low voltage level, X = don't care (2) L = driving low, H = driving high, = driving high for the defined pulse width time, = driving low for the defined pulse width time (3) These outputs are based on the assumption that the indicated steady-state conditions at the inputs have been set up long enough to complete any output pulse. (4) If an output pulse is triggered while a previous output pulse is still active, the output continues to drive high for one additional pulse width. www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TPUL1G113-Q1 is used to generate a fixed-width pulse from an input trigger event. This device is retriggerable, meaning that input triggers received while the output is active will cause the output pulse to extend and it will not expire until one configured time period after the most recent trigger. The input trigger event comes from three gated inputs: T, T, and CLR. These inputs are combined in a 3-input AND gate, with T internally inverted such that the logic follows the boolean equation Y = !( T) • T • CLR. Each input has a Schmitt-trigger architecture, and thus includes hysteresis allowing for slow transitioning or noisy signals. An input signal is detected as a logic high if the signal is larger than V T+, and a low if the input signal is smaller than V T-. Between V T+ and V T-, the input signal is detected as the last valid state until one of those values is crossed. An output pulse is triggered on the rising edge of the aforementioned internal Y signal. The output pulse width is controlled by the selection of external timing components R ext and C ext. Plots are provided in the Typical Characteristics section to easily select appropriate component values for a desired pulse width. See the Features section for additional information regarding the impact of external components on the timing accuracy of the TPUL1G113-Q1.

8.2 Typical Applications

8.2.1 1ms Pulse Generator In this application, the TPUL1G113-Q1 is used to produce a 1ms output pulse from a falling edge input trigger. The circuit configuration is shown in Figure 8-3. T T CLR QOne-Shot tw ≅ RextCext RC C GND 10k 0.1 F VCC VCC VCC 0.1 F Optional de-glitch filterFalling-edge trigger source VCC 50pF Active-high output pulse Rf Cf VCC Figure 8-1. Pulse Generation Using the TPUL1G113-Q1 TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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8.2.1.1 Design Requirements

8.2.1.1.1 Timing Components

The external timing components will directly determine the output pulse width of the TPUL1G113-Q1. The range of supported values for Rext and Cext are provided in the Recommended Operating Conditions table. The TPUL1G113-Q1 can be used with the C ext pin left disconnected, which is described as C ext = 0pF. In this condition, the output pulse width is determined by the operating voltage and external timing resistor, R ext, only. See detailed plots in Typical Characteristics for expected output pulse width in this condition.

8.2.1.1.2 Input Considerations

Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do not exceed the maximum input voltage range found in the Absolute Maximum Ratings. Unused inputs must be terminated to either V CC or ground. The unused inputs can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The drive current of the controller, leakage current into the TPUL1G113-Q1 (as specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10k Ω resistor value is often used due to these factors. The TPUL1G113-Q1 has no input signal transition rate requirements because it has Schmitt-Trigger inputs, however it is characterized for operation within the limits provided in the Recommended Operating Conditions table. Schmitt-Trigger inputs also provide significant noise rejection, however noise with a large enough amplitude can still cause issues. Refer to the hysteresis value, ΔVT(min) in the Electrical Characteristics, which will provide the peak-to-peak noise rejection limit. Unlike what happens with standard CMOS inputs, Schmitt-Trigger inputs can be held at any valid voltage value without causing huge increases in power consumption. The typical additional current caused by holding an input at a value other than VCC or ground is plotted in the Typical Characteristics. Refer to the Feature Description section for additional information regarding the inputs for this device.

8.2.1.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH-state voltage. Drawing current from the output will decrease the output voltage as specified by the V OH specification in the Electrical Characteristics . The ground voltage is used to produce the output LOW-state voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics. Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected directly together. This can cause excessive current and damage to the device. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to the Feature Description section for additional information regarding the outputs for this device.

8.2.1.1.4 Power Considerations

Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions . The supply voltage sets the device's electrical characteristics of the device as described in the Electrical Characteristics section. The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the TPUL1G113-Q1 plus the maximum static supply current, I CC, listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only source as much current that is provided by the positive supply source. Ensure the maximum total current through V CC listed in the Absolute Maximum Ratings is not exceeded. After the output pulse is complete, the external capacitor is quickly recharged to VCC using the supply with maximum current draw as described by I Cext(max) in the Electrical www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

Characteristics. Additionally, the external timing circuitry will draw power from the supply with a maximum current draw of I ext(max) = V CC / R ext, which is pulled directly from the supply and thus is not part of the I CC value for the TPUL1G113-Q1. The dynamic power consumption from the external circuit can be estimated by P RC = Cext VCC 2 / tw. The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the TPUL1G113-Q1 plus the maximum supply current, I CC, listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only sink as much current that can be sunk into its ground connection. Ensure the maximum total current through GND listed in the Absolute Maximum Ratings is not exceeded. The TPUL1G113-Q1 can drive a load with a total capacitance less than or equal to 50pF while still meeting all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50pF. The TPUL1G113-Q1 can drive a load with total resistance described by R L ≥ VO / IO, with the output voltage and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state, the output voltage in the equation is defined as the difference between the measured output voltage and the supply voltage at the VCC pin. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. CAUTION The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device. TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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8.2.1.2 Detailed Design Procedure

1. Using the plots provided in Typical Characteristics, select a timing resistor, Rext, and timing capacitor, Cext, value to meet the system pulse width requirements. TI recommends starting with a resistor value near the midpoint of the range provided in the Recommended Operating Conditions, as this will allow for maximum flexibility for adjustments in the final system. 2. Connect the selected timing resistor from RC to VCC. 3. Connect the selected capacitor from RC (positive) to C (negative). The C pin can additionally be connected to ground, however it is not required for normal operation. 4. Add a 0.1µF decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section. 5. Ensure the capacitive load at the output is ≤ 50pF. This is not a hard limit; by design, however, it will optimize performance. This can be accomplished by providing short, appropriately sized traces from the TPUL1G113-Q1 to one or more of the receiving devices. 6. Ensure the resistive load at the output is larger than (VCC / IO(max))Ω. Doing this will prevent the maximum output current from the Absolute Maximum Ratings from being violated. Most CMOS inputs have a resistive load measured in MΩ; much larger than the minimum calculated previously. 7. Thermal issues are rarely a concern for TPUL family devices; the power consumption and thermal increase, however, can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation.

8.2.1.3 Application Curves

T Q two twotrr Figure 8-2. Output Pulse Timing Diagram

8.2.2 Edge Detector

In this application, the TPUL1G113-Q1 is used to detect rising or falling edges on an input signal, producing short pulses at the output for each edge detected. The circuit configuration for a rising edge detector is shown in Figure 8-3, and the circuit configuration for a falling edge detector is shown in Figure 8-4. T T CLR QOne-Shot RC C GND 10k VCC VCC VCC 0.1 F 50pF Active-high output pulse VCC Using internal capacitance only Input signal Figure 8-3. Rising Edge Detection Using the TPUL1G113-Q1 www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

T T CLR QOne-Shot RC C GND 10k VCC VCC VCC 0.1 F 50pF Active-high output pulse VCC Using internal capacitance only Input signal Figure 8-4. Falling Edge Detection Using the TPUL1G113-Q1

8.2.3 Switch Debounce

In this application, the TPUL1G113-Q1 is used to debounce a switch, producing one consistent output pulse from multiple short pulses at the input. For this design, it is assumed that the switch will have a maximum bounce time of 25ms. The circuit configuration for debounce circuit is shown in Figure 8-5. The high input impedance of the TPUL1G113-Q1 allows for a very large pull-up resistor to be used with the switch, reducing power consumption. This circuit also provides a much faster response when compared to a traditional RC based debounce circuit, as the initial output will happen within only a few nanoseconds of the first switch connection. Because the device is retriggerable, multiple bounces will only extend the output pulse and will not produce multiple output signals. T T CLR QOne-Shot tw ≅ RextCext RC C GND 33k 1 F VCC VCC VCC 0.1 F VCC 50pF Active-high output pulse VCC Figure 8-5. Debounce a switch using the TPUL1G113-Q1

8.3 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the Recommended Operating Conditions. During startup, the power supply should ramp within the provided power-up ramp rate range in the Recommended Operating Conditions table. TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For normal operation of the TPUL1G113-Q1, a 0.1 μF bypass capacitor is recommended. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors with values of 0.1μF and 1μF are commonly used in parallel.

8.4 Layout

8.4.1 Layout Guidelines

• Timing component placement – Place near the device – Provide an electrically short path to the device terminal connections
• Bypass capacitor placement – Place near the positive supply terminal of the device – Provide an electrically short ground return path – Use wide traces to minimize impedance – Keep the device, capacitors, and traces on the same side of the board whenever possible
• Signal trace geometry – 8mil to 12mil trace width – Lengths less than 12cm to minimize transmission line effects – Avoid 90° corners for signal traces – Use an unbroken ground plane below signal traces – Flood fill areas around signal traces with ground – For traces longer than 12cm
• Use impedance controlled traces
• Source-terminate using a series damping resistor near the output
• Avoid branches; buffer signals that must branch separately

8.4.2 Layout Example

T T GND GND V CC RC C VCC Q CLR 0.1 F Unused input tied to GND Avoid 90° corners for signal lines Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation Cext Rext Bypass capacitor placed close to the device Figure 8-6. Layout Example www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, CMOS Power Consumption and Cpd Calculation application note
• Texas Instruments, Designing With Logic application note
• Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices application note

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES February 2026 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/Ball material (4) MSL rating/Peak reflow (5) Op temp (°C) Part marking (6) PTPUL1G113DCUQ Active Preproduction VSSOP (DCU) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (C23Q, C23R) (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 ADVANCE INFORMATION Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TPUL1G113-Q1

11.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PTPUL1G113DCUQ VSSOP DCU 8 3000 353 353 32 www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

11.2 Mechanical Data

www.ti.com PACKAGE OUTLINE C B 2.42.2NOTE 3 A 2.11.9NOTE 3 0.350.20 6X 0.52X1.58X 0.250.17

3.23.0 TYP SEATINGPLANE

VSSOP - 0.9 mm max heightDCU0008ASMALL OUTLINE PACKAGE 4225266/A 09/2014 4 5 0.08CAB PIN 1 INDEX AREA SEE DETAIL A 0.1C A 30 SCALE 6.000 DETAIL ATYPICAL TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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www.ti.com EXAMPLE BOARD LAYOUT 0.05 MAXALL AROUND0.05 MINALL AROUND (3.1) (R0.05) TYP VSSOP - 0.9 mm max heightDCU0008ASMALL OUTLINE PACKAGE 4225266/A 09/2014NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 25X SYMM SYMM1 4 5 8SEE SOLDER MASKDETAILS 15.000 METALSOLDER MASKOPENINGMETAL UNDERSOLDER MASKSOLDER MASKOPENINGEXPOSED METALEXPOSED METALNON-SOLDER MASKSOLDER MASK DETAILSDEFINED(PREFERRED)SOLDER MASKDEFINED www.ti.com TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TPUL1G113-Q1 ADVANCE INFORMATION

www.ti.com EXAMPLE STENCIL DESIGN (3.1) (R0.05) TYP VSSOP - 0.9 mm max heightDCU0008ASMALL OUTLINE PACKAGE SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCILSCALE: 25X SYMM SYMM1 4 5 TPUL1G113-Q1 SLVSLA0 – FEBRUARY 2026 www.ti.com

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