PTPS259827LNRGET

Texas Instruments

2.7 V to 24 V, 15-A, 3-m廓 Smart eFuse With Accurate Load Monitoring and Adjustable Transient Fault Management

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ADVANCE□INFORMATION IN EN/UVLO OUT dVdt GND Power Supply C IN C L C dVdt TPS25982 R VL1 R VL2 R L R ILIM ILIM PG VPG R PG R IMON IMONNRETRY C NRETRY LDSTRT RETRY_DLY C ITIMER ITIMER C RETRY_DLY C LDSTRT * Optional components for extended functionality Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPS25982 SLVSEI3 –OCTOBER 2018 TPS259822.7Vto24V,15-A,3-mΩSmarteFuseWithAccurateLoadMonitoringand AdjustableTransientFaultManagement

1 Features

1• Wide Input Voltage Range: 2.7 V to 24 V – 30 V Absolute Maximum

Low On-Resistance: RON = 3-mΩ Typical
Adjustable Current Limit Threshold – Range: 3 A to 15 A – Accuracy: ± 5% (Typical for IOUT > 5 A)
Circuit Breaker and Current Limiter Options
Programmable Overcurrent Fault Response Timer – Handles Transient Currents Without Tripping
Accurate Current Monitor Output – Accuracy: ±1% (Typical, for IOUT > 2 A)
User Configurable Fault Response – Latch-off and Auto-Retry – Number of Retries – Delay Between Retries
Fast Short Circuit Protection < 400-ns Typical
Adjustable Output Slew Rate (dVdt) Control
Adjustable Undervoltage Lockout
Over Voltage Protection (3.7 V, 7.6 V, 16.7 V Options)
Over Temperature Protection
Power Good Output
Programmable Load Handshake Timer
Low Current Consumption – Active: 1.5-mA Typical – Shutdown: 5-μA Typical
Small Footprint: 4-mm × 4-mm QFN Package

2 Applications

Hot-Swap, Hot-Plug
Server Standby Rail, Add-On Card and Fan Module Protection
Routers and Switches
Optical Modules
Industrial PC
Digital TV

3 Description

The TPS25982 device family of eFuses is a highly integrated circuit protection and power management solution in a small package. The devices are operational over a wide input voltage range. A single part caters to low-voltage systems needing minimal IR voltage drop as well as higher voltage, high current systems needing low power dissipation. They are a robust defense against overloads, short- circuits, voltage surges, and excessive inrush current. Overvoltage events are limited by internal cutoff circuits, with multiple device options to choose the overvoltage threshold. Multiple device options exist to choose between the response to overcurrent conditions, circuit breaker or active current limiter. The overcurrent limit and fast trip (short-circuit) threshold can be set with a single external resistor. The devices intelligently manage the overcurrent response by distinguishing between transient events and actual faults, thereby allowing the system to function uninterrupted during line and load transients without compromising on the robustness of the protection against faults. The device can be configured to stay latched off or retry automatically after a fault shutdown. The number of auto-retries as well as the retry delay are configurable with capacitors. This enables remote systems to automatically recover from temporary faults while ensuring that power supplies are not stressed indefinitely due to a persistent fault. The TPS25982 devices are available in a small 4 mm × 4 mm QFN package. The devices are characterized for operation over a junction temperature range of –40˚C to 125˚C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS25982xyNRGE (PREVIEW) QFN (24) 4.0 mm × 4.0 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematics

11.1 Device Behavior Dependence on EN, IN

11.2 Device Behavior if VIN Dips Below VUVP

11.3 Device Behavior if EN Dips Below VUVLO

11.4 Power Good (PG) Behavior While Charging a Large

11.5 Power Good (PG) Behavior While Recovering from

13.2 Receiving Notification of Documentation Updates 34

14 Mechanical, Packaging, and Orderable

4 Revision History

October 2018 * Initial release.

5 Device Comparison Table

THRESHOLD OVER CURRENT RESPONSE TYPICAL (V) TPS259822LNRGE 3.7 Active Current Limiter TPS259823LNRGE 7.6 Active Current Limiter TPS259824LNRGE 16.7 Active Current Limiter TPS259827LNRGE No OVP Active Current Limiter TPS259822ONRGE 3.7 Circuit Breaker TPS259823ONRGE 7.6 Circuit Breaker TPS259824ONRGE 16.7 Circuit Breaker TPS259827ONRGE No OVP Circuit Breaker

ADVANCE□INFORMATION IN IN IN GND EN/UVLO ITIMER LDSTRT PG OUT GND OUT OUT ILIM IMON NRETRY RETRY_DLY GND dVdt IN OUT OUT OUT OUT OUT IN Thermal Pad 1 GND Thermal Pad 2 121110987 TPS25982 SLVSEI3 –OCTOBER 2018 www.ti.com Product Folder Links: TPS25982 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

6 Pin Configuration and Functions

NAME NO. OUT 17, 18, 19, 20, 21, 22, 23, 24 Power Power Output IN 1, 2, 3, 16, Pad 1 Thermal / Power Power Input. The exposed pad must be soldered to input power plane uniformly to ensure proper heat dissipation and to maintain optimal current distribution through the device. GND 4, 5, 14, Pad 2 Ground Connect to System Ground EN/UVLO 6 Analog Input Active High Enable for the device. A resistor divider from input supply to GND can be used to adjust the Undervoltage Lockout threshold. Do not leave floating. ITIMER 7 Analog Output A capacitor from this pin to GND sets the time for which output current is allowed to exceed set current limit before the device overcurrent response takes action. Leave this pin open for fastest response to overcurrent events. Refer to Table 1 for more details. ILIM 8 Analog Output An external resistor from this pin to GND sets the output current limit threshold. IMON 9 Analog Output Analog output load current monitor. This pin sources a scaled down ratio of the current through the internal FET. A resistor from this pin to GND converts the current to a proportional voltage which can be fed into an ADC input for monitoring. RETRY_DLY 10 Analog Output A capacitor from this pin to GND sets the time period that has to elapse after a fault shutdown before the device attempts to restart automatically. Connect this pin to GND for latch-off operation i.e. no auto-retries after a fault. Refer to Fault Response section for more details. NRETRY 11 Analog Output A capacitor from this pin to GND sets the number of times the part attempts to restart automatically after shutdown due to fault. Connect this pin to GND if the part should infinitely retry. Refer to Fault Response section for more details. LDSTRT 12 Analog I/O A capacitor from this pin to GND sets the time period after PG assertion within which the pin has to be pulled below 1.2 V for VOUT to remain high. Connect to GND if the load handshake feature is not used. Do not leave floating.

ADVANCE□INFORMATION TPS25982 www.ti.com SLVSEI3 –OCTOBER 2018 Product Folder Links: TPS25982 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE DESCRIPTION NAME NO. PG 13 Digital Output Active High Power Good Indication. A high indicates the FET is fully enhanced and output has reached maximum voltage. It is an open drain output that requires an external pull up resistor to an external supply. PG remains logic low when VIN < UVP dVdt 15 Analog Output A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating for the fastest slew rate during start up. (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) Parameter Pin MIN MAX UNIT VIN Maximum Input Voltage Range IN –0.3 30 V VOUT Maximum Output Voltage Range OUT –0.3 min (30V, VIN + 0.3) V VEN/UVLO Maximum Enable Pin Voltage Range EN/UVLO 7 V VLDSTRT Maximum LDSTRT Pin Voltage Range LDSTRT Internally Limited V VdVdt Maximum dVdt Pin Voltage Range dVdt Internally Limited V VPG Maximum PG Pin Voltage Range PG –0.3 7 V VITIMER Maximum ITIMER Pin Voltage Range ITIMER Internally Limited V VNRETRY Maximum NRETRY Pin Voltage Range NRETRY Internally Limited V VRETRY_DLY Maximum RETRY_DLY Pin Voltage Range RETRY_DLY Internally Limited V IMAX Maximum Continuous Switch Current IN to OUT Internally Limited A Tj Junction temperature Internally Limited °C TLEAD Maximum Soldering Temperature 300 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ± 1000 V Charged device model (CDM), per JEDEC specificationJESD22-C101, all pins(2) ± 500

ADVANCE□INFORMATION TPS25982 SLVSEI3 –OCTOBER 2018 www.ti.com Product Folder Links: TPS25982 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) For supply voltages below 6V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 6V, it is recommended to use an appropriate resistor divider between IN, EN and GND to ensure the voltage at the EN pin is within the specified limits. (2) For supply voltages below 6V, it is okay to pull up the PG pin to IN/OUT through a resistor. For supply voltages greater than 6V, it is recommended to use a stepped down power supply to ensure the voltage at the PG pin is within the specified limits.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) Parameter Pin MIN MAX UNIT VIN Input Voltage Range IN 2.7 24 V VOUT Output Voltage Range OUT VIN + 0.3 V VEN/UVLO Enable Pin Voltage Range EN/UVLO 6(1) V VLDSTRT LDSTRT Pin Capacitor Voltage Rating LDTSRT 4 V VdVdT dVdT Pin Capacitor Voltage Rating dVdt VIN + 4 V VPG PG Pin Voltage Range PG 6(2) V VITIMER ITIMER Pin Capacitor Voltage Rating ITIMER 4 V VNRETRY NRETRY Pin Capacitor Voltage Rating NRETRY 4 V VRETRY_DLY RETRY_DLY Pin Capacitor Voltage Rating RETRY_DLY 4 V IMAX Continuous Switch Current IN to OUT 15 A TJ Junction temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with minimum recommended pad size (2 oz Cu) and 3x2 via array.

7.4 Thermal Information

THERMAL METRIC(1) (2) TPS25982X UNITRGE (QFN)

24 PINS

RθJA Junction-to-ambient thermal resistance 34.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 36.7 °C/W RθJB Junction-to-board thermal resistance 11.2 °C/W ΨJT Junction-to-top characterization parameter 3 °C/W ΨJB Junction-to-board characterization parameter 11.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.6 °C/W

7.5 Electrical Characteristics

(Test conditions unless otherwise noted) –40°C ≤ Tj ≤ 125°C, VIN = 12 V for TPS259824x/7x, 5 V for TPS259823x, 3.3 V for TPS259822x, VEN/UVLO = 2 V, RILIM = 1650 Ω , CdVdT = Open, OUT = Open. All voltages referenced to GND. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY (IN) VIN Input voltage range 2.7 24 V IQ IN quiescent current VEN ≥ VUVLO(R) 1500 2000 µA ISD IN shutdown current VSD < VEN < VUVLO 70 120 µA VEN < VSD 5 15 µA VUVP IN Undervoltage Protection Threshold VIN Rising 2.55 V VIN Falling 2.46 V OVERVOLTAGE PROTECTION (IN) VOVP Overvoltage Protection Threshold TPS259822x, VIN Rising 3.7 V TPS259823x, VIN Rising 7.6 V TPS259824x, VIN Rising 16.7 V TPS259822x, VIN Falling 3.6 V TPS259823x, VIN Falling 7.4 V TPS259824x, VIN Falling 16.3 V OUTPUT CURRENT MONITOR (IMON) GIMON Current Monitor Gain (IIMON:IOUT) IOUT > 3 A, IOUT < ILIM 243 µA/A OUTPUT CURRENT LIMIT (ILIM) ILIM IOUT Current Limit Threshold RILIM = 787 Ω 1.97 A RILIM = 300 Ω 4.99 A RILIM = 182 Ω 8.16 A RILIM = 100 Ω 14.76 A RILIM = Open 0 A ICB IOUT Circuit Breaker Threshold During RILIM Short Condition RILIM = Short to GND 5 A ISC Short Circuit Fast Trip Threshold 210 % ILIM ON-RESISTANCE (IN - OUT) RON ON State Resistance VIN < 5 V, IOUT = 2 A 3.5 4.5 mΩ VIN > 5 V, IOUT = 2 A 3 4 mΩ ENABLE / UNDERVOLTAGE LOCKOUT (EN/UVLO) VUVLO EN/UVLO Pin Voltage Threshold VIN Rising 1.2 V VIN Falling 1.15 V VSD EN/UVLO Pin Voltage Threshold for Lowest Shutdown Current VIN Falling 0.7 V IENLKG EN/UVLO Pin Leakage Current 0.1 µA POWER GOOD INDICATION (PG) VPGD PG Pin Low Voltage (De-asserted) VIN < VUVP(R), VEN < VSD, IPG = 242 µA 875 mV VIN < VUVP(R), VEN < VSD, IPG = 26 µA 720 mV VIN > VUVP(R), IPG ≤ 5 mA 600 mV IPGLKG PG Pin Leakage Current (Asserted) PG pulled up to 5 V through 10 kΩ 3 µA VPGTHA VGD Threshold when PG is asserted 3.6 V VPGTHD VDS Threshold when PG is de- asserted 0.32 V AUTO-RETRY DELAY INTERVAL (RETRY_DLY) VRETDLY_THR RETRY_DLY Oscillator Comparator Threshold Rising 1.1 V Falling 0.35 V IRETRY_DLY RETRY_DLY Pin Bias Current 2 µA

ADVANCE□INFORMATION TPS25982 SLVSEI3 –OCTOBER 2018 www.ti.com Product Folder Links: TPS25982 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) (Test conditions unless otherwise noted) –40°C ≤ Tj ≤ 125°C, VIN = 12 V for TPS259824x/7x, 5 V for TPS259823x, 3.3 V for TPS259822x, VEN/UVLO = 2 V, RILIM = 1650 Ω , CdVdT = Open, OUT = Open. All voltages referenced to GND. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NUMBER OF AUTO-RETRIES (NRETRY) VNRETRY NRETRY Oscillator Comparator Threshold Rising 1.1 V Falling 0.35 V INRETRY NRETRY Pin Bias Current 2 µA CURRENT FAULT TIMER (ITIMER) IITIMER ITIMER Discharge Current IOUT > ILIM 2 µA RITIMER ITIMER Charging Resistance 20 kΩ VITIMER ITIMER Comparator Threshold 1.5 V LDSTRT VLDSTRT LDSTRT Threshold Voltage 1.2 V ILDSTRT LDSTRT Charging Current PG asserted 2 µA RLDSTRT LDSTRT Discharging Resistance 26 Ω OVERTEMPERATURE PROTECTION TSD Thermal shutdown Tj Rising 150 °C TSDHys Thermal shutdown hysteresis Tj Falling 10 °C dVdt IdVdt dVdt Pin Charging Current 5 µA RdVdt dVdt Pin Discharge Resistance 13 Ω (1) Please refer to Fig. 18 (2) Please refer to Fig. 20 (3) Please refer to Fig. 22

7.6 Timing Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tOVP Overvoltage Protection Response Time (1) VIN Rising, TPS259822x 1.5 µs VIN Rising, TPS259823x 5 µs VIN Rising, TPS259824x 5 µs tLIM Current Limit Response Time (2) IOUT > ILIM + 30% and ITIMER expired to IOUT ≤ ILIM 270 µs tSC Short Circuit Response Time IOUT > 3 x ILIM to VOUT turned OFF 400 ns tPGD PG Assertion/De-assertion De-glitch (3) VG > (VIN + VPGTHA) to PG↑ or VDS > VPGTHD to PG↓ 120 µs SRON Output Rising slew rate VIN = 12 V, COUT = 1 mF, CdVdt = 6.8 nF 0.71 mV/µs VIN = 12 V, COUT = 220 µF, CdVdt = 3.3 nF 1.23 mV/µs VIN = 12 V, COUT = 0.1 µF, CdVdt = 1 nF 2.56 mV/µs

7.7 Typical Characteristics

Figure 1. Hotplug Figure 2. Startup With EN - dVdt Limited Figure 3. Startup With EN Into Resistive Load - dVdt Limited Figure 4. Overvoltage Protection Figure 5. Current Limit Without Transient Fault Blanking Figure 6. Current Limit With Transient Fault Blanking

ADVANCE□INFORMATION OUT dVdt EN/UVLO GND PG IN 2.55 V 1.2 V Charge Pump ILIM NRETRY ITIMER RETRY_DLY LDSTRT Retry Logic IMON FET Temperature Sense & Overtemperature Protection 2 µA 3.7 V/7.6 V/16.7 V 2 µA 3.6 V/7.4 V/16.3 V 2.46 V 1.1 V S R TSD RETRY TSD RETRY ILIM pin fault ITIMER pin fault ILIM pin fault ITIMER pin fault 0.7 V 5 µA 1.2 V PG_int CB** SD 320 mV GHI SD /Q S R SD SWEN LDSTRT_FLTb UVPb OVPb# UVLOb FLTb PG_int 100 µs deglitch R S ITRIP 1.5 V CL* or CB** Short detect Open/Short detect GHI 13 O x 243 µA/A 350 mV 735 mV ITRIP SCP CL* * TPS25982xL (CL variants) only ** TPS25982xO (CB variants) only # Not applicable for TPS259827x (no-OVP variant) Gate control Current Limit Amplifier* LDSTRT_FLTb GHI Q FLT Q TPS25982 VINT Q 20 kO VINT 100 µs deglitch 3.6 V GHI TPS25982 SLVSEI3 –OCTOBER 2018 www.ti.com Product Folder Links: TPS25982 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TPS25982 device is a smart eFuse with integrated power switch that is used to manage load voltage and load current. The device starts its operation by monitoring the IN bus. When VIN is above the Undervoltage Protection threshold (VUVP) and below the Overvoltage Protection threshold (VOVP), the device samples the EN/UVLO pin. A high level on this pin enables the internal MOSFET to start conducting and allow current to flow from IN to OUT. When EN/UVLO is held low, the internal MOSFET is turned off. After a successful start-up sequence, the device now actively monitors its load current and input voltage and protects the load from harmful overcurrent and overvoltage conditions. The device also relies on a built-in thermal sense circuit to shut down and protect in case the device internal temperature (Tj) exceeds the safe operating conditions.

8.2 Functional Block Diagram

8.3 Feature Description

and indication in the event of system faults.

8.3.1 Undervoltage Protection (UVLO and UVP)

Figure 17. Programmable Supply UVLO Threshold the leakage current on the EN/UVLO pin to minimize the error in the resistor divider ratio.

8.3.2 Overvoltage Protection (OVP)

Figure 18. Overvoltage Response

8.3.3 Inrush Current, Overcurrent, and Short Circuit Protection

Adjustable slew rate (dVdt) for inrush current control
Circuit breaker and active current limiting (with programmable fault timer) for overcurrent protection
A fast short-circuit response to quickly protect against severe overcurrent faults

8.3.3.1 Slew Rate and Inrush Current Control (dVdt)

The fastest output slew rate is achieved by leaving the dVdt pin open.

8.3.3.2 Circuit Breaker

immediately. The following equation can be used to calculate the RILIM value for a desired current limit. details on the device behavior after a fault. Figure 19. Circuit Breaker Response ITIMER pin. Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay.

device behavior after a fault. Table 1. Device ITIMER Functional Modes automatically. Refer to the Fault Response section for details.

8.3.3.3 Active Current Limiting

details on the device behavior after a fault.

Figure 20. Active Current Limiter Response delay. Refer to Table 1 for more details.

Current limiting based on RILIM is active during startup for both Current Limit and Circuit
Shorting the ITIMER pin to ground is detected as a fault and the part shuts down. Refer

to the Fault Response section for details on the device behavior after a fault. FET. If the device internal temperature (Tj) reaches the thermal shutdown threshold (TSD), the FET is turned off. See Overtemperature Protection (OTP) for more details on device response to overtemperature.

8.3.3.4 Short Circuit Protection

details on the device response to overtemperature. Figure 21. Input Line Transient and Output Short Circuit Response Table 1 for more details on ITIMER.

ADVANCE□INFORMATION IMON IMON OUT IMONV V G A / A I A R P u u : TPS25982 www.ti.com SLVSEI3 –OCTOBER 2018 Product Folder Links: TPS25982 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

8.3.4 Overtemperature Protection (OTP)

The device monitors the internal FET temperature (Tj) at all times and shuts down the part as soon as the temperature exceeds a safe operating level (TSD) thereby protecting the device from damage. The device will not turn back on until the FET cools down sufficiently, that is the temperature that falls below (TSD - TSDHys). Thereafter, the part can be configured to either remain latched off or restart automatically. Refer to the Fault Response section for details.

8.3.5 Analog Load Current Monitor (IMON)

The device allows the system to monitor the output load current accurately by providing an analog current on the IMON pin which is proportional to the current through the FET. The user can connect a resistor from IMON to ground to convert this signal to a voltage which can be fed to the input of an Analog-to-Digital Converter. The internal amplifier on the IMON employs chopper based offset cancellation techniques to provide accurate measurement even at lower currents over time and temperature. (6) TI recommends to add a RC low pass filter on the IMON output to filter out any glitches and get a smooth average current measurement. TI recommends a series resistance of 10 kΩ or higher.

8.3.6 Power Good (PG)

PG is an active high open drain output which indicates whether the FET is fully turned ON and the output voltage has reached the maximum value. After power up, PG is pulled low initially. The gate driver circuit starts charging the gate capacitance from the internal charge pump. When the FET gate voltage reaches (VIN + 3.6 V), PG is asserted after a 120-μs de-glitch time. During normal operation, if at any time VOUT falls below (VIN - 320 mV), PG is de-asserted after a 120-μs de-glitch time.

Figure 22. Power Good Assertion and De-assertion indication of internal MOSFET failure. this pin voltage low enough not to be detected as a logic HIGH by associated external circuits.

8.3.7 Load Handshake (LDSTRT)

the FET to power down the load. Tie the LDSTRT pin to ground if this functionality is not needed. Figure 23. Successful LDSTRT Handshake Figure 24. Unsuccessful LDSTRT Handshake

8.4 Fault Response

Overtemperature Protection
Circuit Breaker Operation
ITIMER pin Short to GND
ILIM pin Open
ILIM pin Short to GND
LDSTRT handshake unsuccessful Once the device shuts down due to a fault, even if the associated external fault is cleared, the fault stays latched internally and the output cannot turn on again until the latch is reset. The fault latch can be externally reset by one of the following methods:
Input supply power is cycled
EN/UVLO is pulled below VSD and then pulled above VUVLO(R) Except the LDSTRT fault, all the other faults can also be reset by an internal auto-retry logic which can be either disabled or configured by user to perform a limited or infinite number of retries with a programmable delay between retries. The auto-retry behaviour is controlled by the connections on the RETRY_DLY and NRETRY pins.

Table 2. Pin Configurable Fault Response Table 3. NRETRY and RETRY_DLY Combination Examples Figure 25. Auto-Retry After Fault as a fresh sequence and not as a continuation of the previous fault.

8.5 Device Functional Modes

The TPS25982 can be pin strapped to support various configurable functional modes.

Table 4. LDSTRT Handshake Functional Modes Table 5. Fault Response Functional Modes Refer to Table 3 for more details.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.2 Typical Application

Figure 26. Typical Application Schematic - Protection for Server Standby Rail

9.2.1 Design Requirements

For this design example, use the parameters shown in Table 6. Table 6. Design Parameters

ADVANCE□INFORMATION P INRUSH mA OUT F ISR V / ms C IMON 3.3R 905 15 243 10 u u IMONmax IMON OUTmax V (V)R ( ) I (A) 243 10 : u u VL1 VL2UVLO R UVLO VL2 V R R VIN R u ILIM LIM A 1465R I 0.11 TPS25982 www.ti.com SLVSEI3 –OCTOBER 2018 Product Folder Links: TPS25982 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

9.2.2 Detailed Design Procedure

9.2.2.1 Device Selection

This design example, 12 V system operating voltage with a tolerance of ±10 %. The rated load current is 14 A. If the current exceeds 15 A, then the device must allow overload current for 2 ms interval before breaking the circuit and then restart. Accordingly, the TPS259824O variant is chosen. (Refer to Device Comparison Table for device options.) Ambient temperatures may range from 20 °C to 85 °C. The load has a minimum input capacitance of 2 mF and is turned on only after the PG signal is asserted.

9.2.2.2 Setting the Current Limit Threshold: RILIM Selection

The RILIM resistor at the ILIM pin sets the overload current limit, whose value can be calculated using Equation 7. (7) For ILIM = 15 A, RILIM value works out to be 98.3 Ω. Choose the closest available standard value: 100 Ω, 1%.

9.2.2.3 Setting the Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of RVL1 and RVL2 connected between IN, EN/UVLO and GND pins of the device. The resistor values required for setting the undervoltage are calculated using Equation 8. (8) For minimizing the input current drawn from the power supply, TI recommends to use higher values of resistance for RVL1 and RVL2. However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, IRVL12 must be 20 times greater than the leakage current (IENLKG). From the device electrical specifications, UVLO rising threshold VUVLO(R) = 1.2 V. From design requirements, VINUVLO = 10.8 V. First choose the value of RVL1 = 1 MΩ and use Equation 8 to calculate RVL2 = 125 kΩ. Use the closest standard 1% resistor values: RVL1 = 1 MΩ, and RVL2 = 125 kΩ

9.2.2.4 Choosing the Current Monitoring Resistor: RIMON

Voltage at IMON pin VIMON is proportional to the output load current. This can be connected to an ADC of the downstream system for monitoring the operating condition and health of the system. The RIMON must be selected based on the maximum load current and the input voltage range of the ADC used. RIMON is set using Equation 9. (9) For ILIM = 15 A and considering the operating range of ADC to be 0 V to 3.3 V, RIMON can be calculated as (10) Selecting RIMON value less than shown in Equation 10 ensures that ADC limits are not exceeded for maximum value of load current. Choose closest available standard value: 900 Ω, 1 %.

9.2.2.5 Setting the Slew Rate and Inrush Current Control (dVdt)

The inrush current is directly proportional to the load capacitance and output rising slew rate (dVdt). Equation 11 can be used to calculate the slew rate (SR) required to limit the inrush current (IINRUSH) for a given load capacitance (COUT): (11)

ADVANCE□INFORMATION LDSTRT LDSTRT LDSTRT LDSTRT t 600msC I 2 A F V 1.2V u P u P dVdt 5300C pF SR V / ms TPS25982 SLVSEI3 –OCTOBER 2018 www.ti.com Product Folder Links: TPS25982 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated For design example under discussion, target IINRUSH is 1 A for COUT of 2 mF. From Equation 11, the required output slew rate (dVdt) can be calculated to be 0.5 V/ms. The required capacitance on dVdt pin (CdVdt) to set a 0.5 V/ms slew rate can be calculated using Equation 12. (12) Choose closest available standard value: 10 nF, 1 %.

9.2.2.6 Setting the Load Handshake (LDSTRT) Delay

For proper handshaking between the load and the TPS25982 eFuse, the load circuit must pull down the LDSTRT pin within the time set by the capacitor on the LDSTRT pin (CLDSTRT). Once the PG asserts, the device sources 2 μA current into CLDSTRT. For a successful handshake, the load circuit must pull-down the LDSTRT pin before CLDSTRT charges up to 1.2 V. For the design requirement of 600 ms handshake delay, use Equation 13 to calculate CLDSTRT (13)

9.2.2.7 Setting the Auto-Retry Delay and Number of Retries

Leave RETRY_DLY and NRETRY pins OPEN to set minimum auto-retry delay of 200 μs and number of auto- retries to 4. (Refer to Table 3 for details.)

9.2.3 Application Curves

Figure 27. Hotplug - Inrush Current Limit (dVdt) Figure 28. Input Overvoltage Protection Figure 29. Circuit Breaker With 2 ms Transient Fault Figure 30. Circuit Breaker - Auto-Retry

10 Power Supply Recommendations

overcurrent and short-circuit conditions.

10.1 Transient Protection

Minimize lead length and inductance into and out of the device.
Use a large PCB GND plane.
Use a Schottky diode across the output to absorb negative spikes.
Use a low value ceramic capacitor CIN = 0.001 μF to 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated using Equation 14. where
VIN is the nominal supply voltage
ILOAD is the load current
LIN equals the effective inductance seen looking into the source
CIN is the capacitance present at the input (14) Some of the applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from exceeding the absolute maximum ratings of the device. The circuit implementation with optional protection components (a ceramic capacitor, TVS and Schottky diode) is shown in Figure 33.

Figure 33. Circuit Implementation With Optional Protection Components

10.2 Output Short-Circuit Measurements

It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in results:

Source bypassing
Input leads
Board layout
Component selection
Output shorting method
Relative location of the short
Instrumentation The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure that configuration and methods are used to obtain realistic results. NOTE Do not expect to see waveforms exactly like the waveforms in this data sheet because every setup is different. This section highlights some limitations in the application which were identified during bench evaluation of the existing TPS25982 silicon on the evaluation module (EVM).

11.1 Device Behavior Dependence on EN, IN Sequencing

If EN is pulled high before input voltage (VIN) comes up OR the input voltage ramps up slowly, the TPS25982 asserts internal fault. If the device is configured for fault latch-off mode of operation (RETRY_DLY connected to GND), the output load will stay powered off. If the device is configured for auto-retry mode of operation, the system would see an additional delay before the output voltage starts to ramp up.

Devices affected: All variants Suggested Workaround:
Ensure VIN comes up to > 3 V before EN is asserted.
If VIN < 3 V, do not use the latch-off configuration. The auto-retry mode will ensure the output comes up eventually, but after a fixed delay. A design fix will be included in the final release of the IC.

11.2 Device Behavior if VIN Dips Below VUVP Temporarily

If input voltage (VIN) dips just below VUVP temporarily and comes up again, the TPS25982 asserts internal fault. If the device is configured for fault latch-off mode of operation (RETRY_DLY connected to GND), the output load will stay powered off. If the device is configured for auto-retry mode of operation, the system would see an additional delay before the output voltage starts to ramp up.

Devices affected: All variants Suggested Workaround:
Ensure VIN is driven all the way to 0 V before it comes up again. This ensures all latched faults are cleared internally.
Do not use the latch-off configuration. The auto-retry mode will ensure the output comes up eventually, but after a fixed delay. A design fix will be included in the final release of the IC.

11.3 Device Behavior if EN Dips Below VUVLO Temporarily

If EN pin dips just below VUVLO temporarily and comes up again, the TPS25982 asserts internal fault. If the device is configured for fault latch-off mode of operation (RETRY_DLY connected to GND), the output load will stay powered off. If the device is configured for auto-retry mode of operation, the system would see an additional delay before the output voltage starts to ramp up.

Devices affected: All variants Suggested Workaround:
Add a small filter capacitor on EN to prevent any system noise from triggering this condition.
Ensure EN is driven all the way to 0 V before it comes up again. This ensures all latched faults are cleared internally.
Do not use the latch-off configuration. The auto-retry mode will ensure the output comes up eventually, but after a fixed delay. A design fix will be included in the final release of the IC.

11.4 Power Good (PG) Behavior While Charging a Large Output Cap

While charging a big output cap, the device may hit thermal shutdown and need multiple restarts before the output reaches full voltage. PG may remain de-asserted in such cases. The downstream load won’t get a valid power good indication even if the output voltage has come up fully.

Devices affected: All variants Suggested Workaround:
Use a larger CdVdt to lower the inrush current and thereby minimize thermal stress during start-up. This issue is not observed if the device starts up without hitting thermal shutdown. A design fix will be included in the final release of the IC.

11.5 Power Good (PG) Behavior While Recovering from a Fast Trip Event

If the device fast trips due to a transient overcurrent and then recovers using fast gate charge, the PG may remain de-asserted. The downstream load won’t get a valid power good indication even if the output voltage has come up fully.

Devices affected: All variants Suggested Workaround: None A design fix will be included in the final release of the IC.

12 Layout

12.1 Layout Guidelines

The IN Exposed Thermal Pad is used for Heat Dissipation. Connect to as much copper area as possible.
For all applications, TI recommends a ceramic decoupling capacitor of 0.01 μF or greater between IN and GND terminals. For hot-plug applications, where input power-path inductance is negligible, this capacitor can be eliminated or minimized.
The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the IC.
High current carrying power path connections must be as short as possible and must be sized to carry at least twice the full-load current.
The GND terminal is the reference for all internal signals and must be isolated from any bounce due to large switching currents in the system power ground plane. TI recommends to connect the device GND to a signal ground island on the board, which in turn is connected to the system power GND plane at one point.
Locate the support components for the following signals close to their respective connection pins - ILIM, IMON, ITIMER, RETRY_DLY, NRETRY and dVdT with the shortest possible trace routing to reduce parasitic effects on the respective associated functions. These traces must not have any coupling to switching signals on the board.
The ILIM pin is highly sensitive to capacitance and TI recommends to pay special attention to the layout to maintain the parasitic capacitance below 30 pF for stable operation.
Use short traces on the RETRY_DLY and NRETRY pins to ensure the Auto-retry timer delay and number of Auto-retries is not altered by the additional parasitic capacitance on these pins.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads, and it must be physically close to the OUT pins.
Obtaining acceptable performance with alternate layout schemes is possible; the Layout Example is intended as a guideline and shown to produce good results.

12.2 Layout Example

Figure 34. TPS25982 Example PCB Layout

13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

TPS259824OEVM eFuse Evaluation Board
TPS259827LEVM eFuse Evaluation Board

13.1.1.1 Related Links

resources, tools and software, and quick access to order now. Table 7. Related Links

13.2 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

13.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

13.4 Trademarks

E2E is a trademark of Texas Instruments.

13.5 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

ADVANCE□INFORMATION TPS25982 SLVSEI3 –OCTOBER 2018 www.ti.com Product Folder Links: TPS25982 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. space (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) space (3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. space (4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. space (5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device space (6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

14.1 Package Option Addendum

14.1.1 Packaging Information

Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish(3) MSL Peak Temp (4) Op Temp (°C) Device Marking(5)(6) PTPS259824ONRGET PREVIEW VQFN RGE 24 250 TBD Call TI Call TI –40 TO 125 PTPS259827LNRGET PREVIEW VQFN RGE 24 250 TBD Call TI Call TI –40 TO 125 PTPS259827ONRGET PREVIEW VQFN RGE 24 250 TBD Call TI Call TI –40 TO 125 TPS259824ONRGET PREVIEW VQFN RGE 24 250 TBD Call TI Call TI –40 TO 125 TPS259827LNRGET PREVIEW VQFN RGE 24 250 TBD Call TI Call TI –40 TO 125 TPS259827ONRGET PREVIEW VQFN RGE 24 3000 TBD Call TI Call TI –40 TO 125

ADVANCE□INFORMATION Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed TPS25982 www.ti.com SLVSEI3 –OCTOBER 2018 Product Folder Links: TPS25982 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

14.1.2 Tape and Reel Information

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant

ADVANCE□INFORMATION TAPE AND REEL BOX DIMENSIONS Width (mm) W L H TPS25982 SLVSEI3 –OCTOBER 2018 www.ti.com Product Folder Links: TPS25982 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PTPS259824ONRGET VQFN RGE 24 250 210.0 185.0 35.0 PTPS259827LNRGET VQFN RGE 24 250 210.0 185.0 35.0 PTPS259827ONRGET VQFN RGE 24 250 210.0 185.0 35.0 TPS259824ONRGET VQFN RGE 24 250 210.0 185.0 35.0 TPS259827LNRGET VQFN RGE 24 250 210.0 185.0 35.0 TPS259827ONRGET VQFN RGE 24 250 210.0 185.0 35.0

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4204104/H

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2018, Texas Instruments Incorporated

Product Information

PTPS259827LNRGET specifications and overview.

Summary

2.7 V to 24 V, 15-A, 3-m廓 Smart eFuse With Accurate Load Monitoring and Adjustable Transient Fault Management

Description

2.7 V to 24 V, 15-A, 3-m廓 Smart eFuse With Accurate Load Monitoring and Adjustable Transient Fault Management

Source title PTPS259827LNRGET Datasheet(PDF) - Texas Instruments

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