TPS25947_V02 TI | Alldatasheet
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Technical content
TPS25947xx, 2.7 - 23 V, 5.5 A, 28-mΩ True Reverse Current Blocking eFuse with Input Reverse Polarity Protection
1 Features
- Wide operating input voltage range: 2.7 V to 23 V – 28-V absolute maximum – Withstands negative voltages up to – 15 V
- Integrated back-to-back FETs with low On- Resistance: RON = 28.3 mΩ (typ)
- Ideal diode operation with true reverse current blocking
- Fast overvoltage protection – Overvoltage clamp (OVC) with pin-selectable threshold (3.8 V, 5.7 V, 13.8 V) and 5-μs (typ) response time OR – Adjustable overvoltage lockout (OVLO) with 1.2-μs (typ) response time
- Overcurrent protection with load current monitor output (ILM) – Active current limit OR circuit-breaker options – Adjustable threshold (I LIM) 0.5 A - 6 A
- ±10% accuracy for I LIM > 1 A – Adjustable transient blanking timer (ITIMER) to allow peak currents up to 2 x ILIM – Output load current monitor accuracy: ±6% (IOUT ≥ 1 A)
- Fast-trip response for short-circuit protection – 500-ns (typ) response time – Adjustable (2 x I LIM) and fixed thresholds
- Active high enable input with adjustable undervoltage lockout threshold (UVLO)
- Adjustable output slew rate control (dVdt)
- Overtemperature protection
- Digital outputs – Priority power MUX control (AUXOFF) and Fault indication (FLT) OR – Power Good indication (PG) with adjustable threshold (PGTH)
- UL 2367 recognition (pending)
- IEC 62368 CB certification (pending)
- Small footprint: QFN 2 mm x 2 mm, 0.45-mm pitch
2 Applications
- Power MUX/ORing
- Adapter input protection
- USB PD protection - PC/Notebook/Monitors/docks
- Server/PC motherboard/add-on cards
- Enterprise storage - RAID/HBA/SAN/eSSD
- Patient monitors
3 Description
The TPS25947xx family of eFuses is a highly integrated circuit protection and power management solution in a small package. The devices provide multiple protection modes using very few external components and are a robust defense against overloads, short-circuits, voltage surges, reverse polarity and excessive inrush current. With integrated back-to-back FETs, reverse current flow from output to input is blocked at all times, making the devices well suited for power MUX/ORing applications as well as systems which need load side energy hold up storage in case input power supply fails. The devices use linear ORing based scheme to ensure almost zero DC reverse current and emulate ideal diode behavior with minimum forward voltage drop and power dissipation. Output slew rate and inrush current can be adjusted using a single external capacitor. Loads are protected from input overvoltage conditions either by clamping the output to a safe fixed maximum voltage (pin selectable), or by cutting off the output if input exceeds an adjustable overvoltage threshold. The devices respond to output overload by actively limiting the current or breaking the circuit. The output current limit threshold as well as the transient overcurrent blanking timer are user adjustable. The current limit control pin also functions as an analog load current monitor. The devices are available in a 2-mm x 2-mm, 10-pin HotRod QFN package for improved thermal performance and reduced system footprint. The devices are characterized for operation over a junction temperature range of –40°C to +125°C. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) TPS25947xxRPW QFN (10) 2 mm × 2 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. TPS259470x IN OUT EN/UVLO ILMdVdt GND VIN = 2.7 to 23 V RILM VOUT COUT OVLO AUXOFF FLT ITIMER CDVDTCITIMER VLOGIC Simplified Schematic TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
12.2 Receiving Notification of Documentation Updates..62
13 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (October 2020) to Revision A (March 2021) Page TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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5 Device Comparison Table
Response AUXOFF or PG FLT or PGTH Response to Fault TPS259470ARPW Adjustable OVLO Active Current Limit AUXOFF FLT Auto-Retry TPS259470LRPW Latch-Off TPS259472ARPW Pin Selectable OVC PG PGTH Auto-Retry TPS259472LRPW Latch-Off TPS259474ARPW Adjustable OVLO Circuit Breaker Auto-Retry TPS259474LRPW Latch-Off www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS25947
6 Pin Configuration and Functions
Figure 6-1. TPS25947xx RPW Package 10-Pin QFN Top View Table 6-1. Pin Functions PIN TYPE DESCRIPTION NAME NO. EN/UVLO 1 Analog Input Active High Enable for the device. A Resistor Divider on this pin from input supply to GND can be used to adjust the Undervoltage Lockout threshold. Do not leave floating. Refer to Section 8.3.2 for details. OVLO Analog Input TPS259470x/4x: A Resistor Divider on this pin from supply to GND can be used to adjust the Overvoltage Lockout threshold. This pin can also be used as an Active Low Enable for OVCSEL Analog Input TPS259472x: Overvoltage Clamp Threshold Select Pin. Refer to Section 8.3.4 for details. PG Digital Output TPS259472x/4x: Power Good indication. This is an Open Drain signal which is asserted High when the internal powerpath is fully turned ON and PGTH input exceeds a certain threshold. Refer to Section 8.3.11 for more details. AUXOFF Digital Output TPS259470x: Auxiliary channel control signal. This is an Open Drain signal which is asserted High when the input supply is valid and channel has completed inrush sequence. This can be used to enable/disable the auxiliary supply eFuse to facilitate smooth switchover in a Priority power MUXing configuration. Refer to Section 8.3.10 for more details. FLT Digital Output TPS259470x: Active low Fault event indicator. This is an Open Drain signal which will be pulled low when a fault is detected. Refer to Section 8.3.9 for more details. PGTH Analog Input TPS259472x/4x: Power Good Threshold. Refer to Section 8.3.11 for more details. IN 5 Power Power Input. OUT 6 Power Power Output. DVDT 7 Analog Output A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating GND 8 Ground This is the ground reference for all internal circuits and must be connected to system GND. TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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Table 6-1. Pin Functions (continued) PIN TYPE DESCRIPTION NAME NO. ILM 9 Analog Output This is a dual function pin used to limit and monitor the output current. An external resistor from this pin to GND sets the output current limit threshold during start-up as well as steady state. The pin voltage can also be used as analog output load current monitor ITIMER 10 Analog Output A capacitor from this pin to GND sets the overcurrent blanking interval during which the output current can temporarily exceed set current limit (but lower than fast-trip threshold) before the device overcurrent response takes action. Leave this pin open for fastest details. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS25947
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) Parameter Pin MIN MAX UNIT VIN Maximum Input Voltage Range, -40 ℃ ≤ TJ ≤ 125 ℃ IN max(-15, VOUT - 21) 28 V Maximum Input Voltage Range, -10 ℃ ≤ TJ ≤ 125 ℃ max(-15, VOUT - 22) 28 V VOUT Maximum Output Voltage Range, -40 ℃ ≤ TJ ≤ 125 ℃ OUT –0.3 min (28, VIN + 21) Maximum Output Voltage Range, -10 ℃ ≤ TJ ≤ 125 ℃ –0.3 min (28, VIN + 22) VOUT,PLS Minimum Output Voltage Pulse (< 1 µs) OUT –0.8 VEN/UVLO Maximum Enable Pin Voltage Range (2) EN/UVLO –0.3 6.5 V VOVLO Maximum OVLO Pin Voltage Range (TPS259470x/4x) (2) OVLO –0.3 6.5 V VOVCSEL Maximum OVCSEL Pin Voltage Range (TPS259472x) OVCSEL Internally Limited V VdVdT Maximum dVdT Pin Voltage Range dVdt Internally Limited V VITIMER Maximum ITIMER Pin Voltage Range ITIMER Internally Limited V VPGTH Maximum PGTH Pin Voltage Range (TPS259472x/4x) (2) PGTH –0.3 6.5 V VAUXOFF Maximum AUXOFF Pin Voltage Range (TPS259470x) AUXOFF –0.3 6.5 V VPG Maximum PG Pin Voltage Range (TPS259472x/4x) PG –0.3 6.5 V VFLTB Maximum FLT Pin Voltage Range (TPS259470x) (2) FLT –0.3 6.5 V VILM Maximum ILM Pin Voltage Range ILM Internally Limited V IMAX Maximum Continuous Switch Current IN to OUT Internally Limited A TJ Junction temperature Internally Limited °C TLEAD Maximum Lead Temperature 300 °C TSTG Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) If this pin has a pull-up up to V IN, it is recommended to use a resistance of 350 kΩ or higher to limit the current under conditions where IN can be exposed to reverse polarity.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) Parameter Pin MIN MAX UNIT VIN Input Voltage Range IN 2.7 23 (1) V VOUT Output Voltage Range OUT min (23, VIN + 20) V VEN/UVLO Enable Pin Voltage Range EN/UVLO 5 (2) V VOVLO OVLO Pin Voltage Range (TPS259470x/4x) OVLO 0.5 1.5 V VdVdT dVdt Capacitor Voltage Rating dVdt VIN + 5 V (3) V VFLTB FLT Pin Voltage Range (TPS259470x) FLT 5 (4) V VPGTH PGTH Pin Voltage Range (TPS259472x/4x) PGTH 5 (4) V VAUXOFF AUXOFF Pin Voltage Range (TPS259470x) AUXOFF 5 (4) V VPG PG Pin Voltage Range (TPS259472x/4x) PG 5 (4) V VITIMER ITIMER Pin Capacitor Voltage Rating ITIMER 4 V RILM ILM Pin Resistance ILM 549 6650 Ω IMAX Continuous Switch Current, TJ ≤ 125 ℃ IN to OUT 5.5 A TJ Junction temperature –40 125 °C (1) For TPS259472x variants, the input operating voltage should be limited to the selected Output Voltage Clamp threshold as listed in the Electrical Characteristics section (2) For supply voltages below 5V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5V or systems which can be exposed to reverse polarity on input supply, it is recommended to use a pull-up resistor with a minimum value of 350 kΩ. (3) In a PowerMUX/ORing scenario with unequal supplies, the dVdt capacitor rating for each device should be chosen based on the highest of the 2 rails. (4) For systems which can be exposed to reverse polarity on input supply, if this pin is referred to input supply, it is recommended to use a pull-up resistor with a minimum value of 350 kΩ to limit the current through the pin.
7.4 Thermal Information
THERMAL METRIC (1) TPS25947xx UNITRPW (QFN)
10 PINS
RθJA Junction-to-ambient thermal resistance 41.7 (2) °C/W 74.5 (3) °C/W ΨJT Junction-to-top characterization parameter 1 °C/W ΨJB Junction-to-board characterization parameter 20 (2) °C/W 27.6 (3) °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Based on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device (3) Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS25947
7.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO = 0 V for TPS259470x/4x, OVCSEL = 390 kΩ to GND for TPS259472x, RILM = 549 Ω , dVdT = Open, ITIMER = Open, AUXOFF = Open for TPS259470x, FLT = Open for TPS259470x, PGTH = Open for TPS259472x/4x, PG = Open for TPS259472x/4x. All voltages referenced to GND. Test Parameter Description MIN TYP MAX UNITS INPUT SUPPLY (IN) VUVP(R) IN Supply UVP Rising threshold 2.44 2.53 2.64 V VUVP(F) IN Supply UVP Falling threshold 2.35 2.42 2.55 V IQ(ON) IN Supply Quiescent Current (TPS259470x) 428 610 µA IN Supply Quiescent Current (TPS259472x) 426 610 µA IN Supply Quiescent Current (TPS259474x) 428 610 µA IN Supply Quiescent Current during RCB, VOUT = VIN + 1 V 193 µA IN Supply Current during OVC (TPS259472x) 445 625 µA IQ(OFF) IN Supply disabled State Current (VSD(F) < VEN < VUVLO(F)) 73 130 µA ISD IN Supply Shutdown Current (VEN < VSD(F)) 4.4 28.7 µA IQ(OVLO) IN Supply OFF Current (OVLO condition), VOUT = VIN + 1 V 190 267 µA IINLKG(IRPP) IN Supply Leakage Current (VIN = -14 V, VOUT = 0 V) -3.7 µA IOUTLKG(OVLO) OUT Leakage Current (OVLO condition), VOUT > VIN 319 443 µA ON RESISTANCE (IN - OUT) RON VIN = 12 V, IOUT = 3 A, TJ = 25 ℃ 28.2 mΩ 2.7 ≤ VIN ≤ 23 V, IOUT = 3 A, –40 ℃ ≤ TJ ≤ 125 ℃ 45 mΩ ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO) VUVLO(R) UVLO Rising threshold 1.183 1.20 1.223 V VUVLO(F) UVLO Falling threshold 1.076 1.09 1.116 V VSD(F) EN/UVLO Falling Threshold for lowest shutdown current 0.45 0.74 V IENLKG EN/UVLO leakage current -0.1 0.1 µA OVERVOLTAGE LOCKOUT (OVLO) - TPS259470x/4x VOV(R) OVLO Rising threshold 1.183 1.20 1.223 V VOV(F) OVLO Falling threshold 1.076 1.09 1.116 V IOVLKG OVLO pin leakage current, 0.5 V < VOVLO < 1.5 V -0.1 0.1 µA OUTPUT VOLTAGE CLAMP (OUT) - TPS259472x VOVC Overvoltage Clamp Threshold, OVCSEL = Shorted to GND 3.65 3.88 4.1 V Overvoltage Clamp Threshold, OVCSEL = Open 5.25 5.74 6.2 V Overvoltage Clamp Threshold, OVCSEL = 390 kΩ to GND 13.2 13.85 14.5 V VCLAMP Output Voltage During Clamping, OVCSEL = Shorted to GND, IOUT = 10 mA 3.2 3.82 4.2 V Output Voltage During Clamping, OVCSEL = Open, IOUT = 10 mA 5.0 5.68 6.12 V Output Voltage During Clamping, OVCSEL = 390 kΩ to GND, IOUT = 10 mA 13.0 13.79 14.6 V OVERCURRENT PROTECTION (OUT) ILIM Overcurrent Threshold, RILM = 6.65 kΩ 0.425 0.500 0.575 A Overcurrent Threshold, RILM = 3.32 kΩ 0.850 1.007 1.150 A Overcurrent Threshold, RILM = 1.65 kΩ 1.800 2.028 2.200 A Overcurrent Threshold, RILM = 750 Ω 3.960 4.452 4.840 A Overcurrent Threshold, RILM = 549 Ω 5.400 6.068 6.600 A TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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7.5 Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO = 0 V for TPS259470x/4x, OVCSEL = 390 kΩ to GND for TPS259472x, RILM = 549 Ω , dVdT = Open, ITIMER = Open, AUXOFF = Open for TPS259470x, FLT = Open for TPS259470x, PGTH = Open for TPS259472x/4x, PG = Open for TPS259472x/4x. All voltages referenced to GND. Test Parameter Description MIN TYP MAX UNITS IFLT Circuit Breaker Threshold, ILM Pin Open (Single point failure) 0.1 A Circuit Breaker Threshold, ILM Pin Shorted to GND (Single point failure) 1.1 2.1 A ISCGain Scalable Fast Trip Threshold (ISC) : ILIM Ratio 201 % IFT Fixed Fast-trip current threshold 22.2 A VFB VOUT threshold to exit Current Limit Foldback 1.9 V OVERCURRENT FAULT TIMER (ITIMER) VINT ITIMER pin internal pull-up voltage 2.3 2.57 2.72 V RITIMER ITIMER pin internal pull-up resistance 15 kΩ IITIMER ITIMER pin internal discharge current, IOUT > ILIM 1.2 1.8 2.5 µA ΔVITIMER ITIMER discharge differential voltage threshold 1.286 1.51 1.741 V OUTPUT LOAD CURRENT MONITOR (ILM) GIMON Analog Load Current Monitor Gain (IMON : IOUT), IOUT = 0.5 A to 1 A, IOUT < ILIM 165 182 200 µA/A Analog Load Current Monitor Gain (IMON : IOUT), IOUT = 1 A to
5.5 A, IOUT < ILIM
165 182 200 µA/A REVERSE CURRENT BLOCKING (IN - OUT) VFWD VIN - VOUT Forward regulation voltage, IOUT = 10 mA 4.7 16.9 mV VREVTH VIN - VOUT threshold for fast BFET turn off (enter reverse current blocking) -36.45 -29.3 -22.3 mV VFWDTH VIN - VOUT threshold for fast BFET turn on (exit reverse current blocking) 83 104.1 125 mV IREVLKG(OFF) OUT Leakage Current during unpowered condition (VOUT = 12 V, VIN = 0 V) 4.86 µA IREVLKG Reverse leakage current, (VOUT - VIN) = 21.5 V 10.1 µA IOUTLKG(RCB) OUT Leakage Current during ON state with RCB, VOUT = VIN + 1 V 234 µA POWER GOOD INDICATION (PG) - TPS259472x/4x or AUXILIARY CHANNEL CONTROL (AUXOFF) - TPS259470x VPGD PG/AUXOFF pin voltage while de-asserted. VIN < VUVP(F), VEN < VSD(F), Weak pull-up (IPG = 26 μA) 0.67 1 V PG/AUXOFF pin voltage while de-asserted, VIN < VUVP(F), VEN < VSD(F), Strong pull-up (IPG = 242 μA) 0.79 1 V PG/AUXOFF pin voltage while de-asserted, VIN > VUVP(R) 0 V IPGLKG PG/AUXOFF Pin leakage current, PG/AUXOFF asserted 0.9 3 µA POWERGOOD THRESHOLD (PGTH) - TPS259472x/4x VPGTH(R) PGTH Rising threshold 1.183 1.20 1.223 V VPGTH(F) PGTH Falling threshold 1.076 1.09 1.116 V IPGTHLKG PGTH leakage current -0.1 0.3 µA FAULT INDICATION (FLT) - TPS259470x IFLTLKG FLT leakage current -1 1 µA RFLT FLT Internal Pull down resistance 12.3 Ω OVERTEMPERATURE PROTECTION (OTP) TSD Thermal Shutdown Rising Threshold, TJ↑ 154 °C www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS25947
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO = 0 V for TPS259470x/4x, OVCSEL = 390 kΩ to GND for TPS259472x, RILM = 549 Ω , dVdT = Open, ITIMER = Open, AUXOFF = Open for TPS259470x, FLT = Open for TPS259470x, PGTH = Open for TPS259472x/4x, PG = Open for TPS259472x/4x. All voltages referenced to GND. Test Parameter Description MIN TYP MAX UNITS TSDHYS Thermal Shutdown Hysteresis, TJ↓ 10 °C DVDT IdVdt dVdt Pin Charging Current 0.81 2.21 3.82 µA
7.6 Timing Requirements
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tOVLO Overvoltage lock-out response time (TPS259470x/4x) VOVLO > VOV(R) to VOUT↓ 1.2 µs tOVC Overvoltage clamp response time (TPS259472x) VIN > VOVC to VOUT↓ 5 µs tCB Circuit-Breaker response time (TPS259474x) IOUT > 1.2 x ILIM & ITIMER expired to IOUT↓ 2 µs tLIM Current limit response time (TPS259470x/2x) IOUT > 1.2 x ILIM & ITIMER expired to IOUT settling to within 5 % of ILIM 400 µs tSC Scalable fast-trip response time IOUT > 3 x ILIM to IOUT↓ 500 ns tFT Fixed fast-trip response time IOUT > IFT to IOUT↓ 500 ns tRST Auto-Retry Interval after fault (TPS25947xA) 110 ms tSWOV OVLO fast recovery response time (TPS259470x) VOVLO < VOV(F) to VOUT↑ 90 µs tSWRCB Reverse Current Blocking recovery time (VIN - VOUT) > VFWDTH to VOUT ↑ 50 µs tRCB Reverse Current Blocking comparator response time (VOUT - VIN) > 1.3 x VREVTH to BFET OFF 1 µs tPGA PG Assertion de-glitch (TPS259472x/4x) 12 µs tPGD PG De-assertion de-glitch (TPS259472x/4x) 12 µs TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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7.7 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin to ground. As CdVdt is increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt) section for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant of the load capacitance (COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up sequence where the supply is available in steady state condition and the load voltage is completely discharged before the device is enabled.Typical Values are taken at TJ = 25°C unless specifically noted otherwise. RL = 100 Ω, COUT = 1 µF PARAMETER VIN CdVdt = Open CdVdt = 1800 pF CdVdt = 3300 pF UNIT SRON Output Rising slew rate 2.7 V 12.14 0.87 0.5 V/ms12 V 28.1 1.09 0.61 23 V 44.78 1.25 0.71 tD,ON Turn on delay 2.7 V 0.09 0.6 0.97 ms12 V 0.1 1.32 2.35 23 V 0.11 1.99 3.69 tR Rise time 2.7 V 0.17 2.51 4.33 ms12 V 0.35 8.1 15.37 23 V 0.40 14.4 25.89 tON Turn on time 2.7 V 0.27 3.11 5.31 ms12 V 0.45 10.08 17.72 23 V 0.50 16.41 29.57 tD,OFF Turn off delay 2.7 V 64.44 64.44 64.44 µs12 V 25.32 25.32 25.32 23 V 23.02 23.02 23.02 EN/UVLO VEN/UVLO Time VUVLO(R) OUT VIN 0V 10% 90% tD,OFF tR tON SRON tF tD,ON VUVLO(F) Figure 7-1. TPS25947xx Switching Times www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS25947
7.8 Typical Characteristics
VIN (V) RON (mΩ) 27.9 28.2 28.5 28.8 29.1 29.4 29.7 30.3 30.6 30.9 IOUT (A) 5.5 Figure 7-2. ON-Resistance vs Supply Voltage Figure 7-3. Forward Voltage Drop vs Load Current TA (°C) IQ(ON) ( μ -40 -20 0 20 40 60 80 100 120 140 340 360 380 400 420 440 460 480 VIN (V) 2.7 Figure 7-4. IN Quiescent Current vs Temperature (TPS259470x/4x Variants) TA (°C) IQ(ON) ( μ -40 -20 0 20 40 60 80 100 120 140 385 390 395 400 405 410 415 420 425 430 435 440 445 VIN (V) 3.3 Figure 7-5. IN Quiescent Current vs Temperature (TPS259472x Variant) TA (°C) IQ(OFF) ( μ -40 -20 0 20 40 60 80 100 120 140 VIN (V) 2.7 Figure 7-6. IN OFF state (UVLO) Current vs Temperature TA (°C) ISD ( μ -40 -20 0 20 40 60 80 100 120 140 VIN (V) 2.7 23 Figure 7-7. IN Shutdown Current vs Temperature TA (°C) VUVP (V) -40 -20 0 20 40 60 80 100 120 140 2.4 2.42 2.44 2.46 2.48 2.5 2.52 2.54 Rising Falling Figure 7-8. IN Undervoltage Threshold vs Temperature TA (°C) VUVLO(R) (V) -40 -20 0 20 40 60 80 100 120 140 1.2 1.201 1.202 1.203 1.204 VIN (V) 2.7 23 Figure 7-9. EN/UVLO Rising Threshold vs Temperature TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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7.8 Typical Characteristics (continued)
TA (°C) VUVLO(F) (V) -40 -20 0 20 40 60 80 100 120 140 1.093 1.094 1.095 1.096 1.097 VIN (V) 2.7 Figure 7-10. EN/UVLO Falling Threshold vs Temperature TA (°C) VSD(F) (V) -40 -20 0 20 40 60 80 100 120 140 0.55 0.575 0.6 0.625 0.65 0.675 0.7 0.725 0.75 0.775 0.8 0.825 VIN (V) 2.7 23 Figure 7-11. EN/UVLO Shutdown Falling Threshold vs Temperature TA (°C) VOV(R) (V) -40 -20 0 20 40 60 80 100 120 140 1.2 1.201 1.202 1.203 1.204 VIN (V) 2.7 Figure 7-12. OVLO Rising Threshold vs Temperature TA (°C) VOV(F) (V) -40 -20 0 20 40 60 80 100 120 140 1.093 1.094 1.095 1.096 1.097 VIN (V) 2.7 23 Figure 7-13. OVLO Falling Threshold vs Temperature RILM (kΩ) ILIM (A) 1000 2000 3000 4000 5000 6000 7000 Figure 7-14. Overcurrent Threshold vs ILM resistor ILIM (mA) ILIM error (%) 0 1000 2000 3000 4000 5000 6000 -18 -12 Min Max Figure 7-15. Overcurrent Threshold accuracy (across Process, Voltage & Temperature) IOUT (A) GIMON error (%) Min Max Figure 7-16. Analog Current Monitor Gain Accuracy TA (°C) ISFT/ILIM Ratio (%) -40 -20 0 20 40 60 80 100 120 140 200 200.5 201 201.5 202 202.5 203 VIN (V) 2.7 23 Figure 7-17. Scalable Fast-Trip Threshold:Current Limit Threshold (ILIM) Ratio vs Temperature www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS25947
TA (°C) IFT (A) -40 -20 0 20 40 60 80 100 120 140 VIN (V) 2.7 Figure 7-18. Steady State Fixed Fast-Trip Current Threshold vs Temperature TA (°C) VFWD (mV) -40 -20 0 20 40 60 80 100 120 140 16.5 17.5 18.5 19.5 VIN (V) 2.7 Figure 7-19. RCB - Forward Regulation Voltage vs Temperature TA (°C) VREVTH (mV) -40 -20 0 20 40 60 80 100 120 140 -32.5 -32 -31.5 -31 -30.5 -30 -29.5 -29 -28.5 VIN (V) 2.7 Figure 7-20. RCB - Reverse Comparator Threshold vs Temperature TA (°C) VFWDTH (mV) -40 -20 0 20 40 60 80 100 120 140 100 105 110 115 120 VIN (V) 2.7 Figure 7-21. RCB - Forward Comparator Threshold vs Temperature Figure 7-22. OUT Leakage Current During ON-State Reverse Current Blocking Figure 7-23. Reverse Leakage Current During OFF-State TA (°C) VOVC (V) -40 -20 0 20 40 60 80 100 120 140 OVCSEL GND OPEN 392 kΩ to GND Figure 7-24. OVC Threshold vs Temperature IOUT (mA) VCLAMP (V) 0 100 200 300 400 500 600 700 800 900 1000 13.5 13.55 13.6 13.65 13.7 13.75 13.8 13.85 13.9 13.95 TA (°C) -40 105 125 Figure 7-25. OVC Clamping Voltage (OVCSEL = 392 kΩ to GND) vs Load Current TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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IOUT (mA) VCLAMP (V) 0 100 200 300 400 500 600 700 800 900 1000 3.6 3.65 3.7 3.75 3.8 3.85 3.9 3.95 TA (°C) -40 105 125 Figure 7-26. OVC Clamping Voltage (OVCSEL = GND) vs Load Current IOUT (mA) VCLAMP (V) 0 100 200 300 400 500 600 700 800 900 1000 5.45 5.5 5.55 5.6 5.65 5.7 5.75 5.8 5.85 TA (°C) -40 105 125 Figure 7-27. OVC Clamping Voltage (OVCSEL = Open) vs Load Current TA (°C) ΔV ITIMER (V) -40 -20 0 20 40 60 80 100 120 140 1.502 1.504 1.506 1.508 1.51 1.512 1.514 1.516 1.518 VIN (V) 2.7 Figure 7-28. ITIMER discharge Differential Voltage Threshold vs Temperature TA (°C) IITIMER ( μ -40 -20 0 20 40 60 80 100 120 140 1.785 1.79 1.795 1.8 1.805 1.81 1.815 1.82 1.825 1.83 VIN (V) 2.7 Figure 7-29. ITIMER Discharge Current vs Temperature TA (°C) RITIMER (kΩ) -40 -20 0 20 40 60 80 100 120 140 13.5 14.5 15.5 16.5 17.5 18.5 VIN (V) 2.7 Figure 7-30. ITIMER Internal Pull-Up Resistance vs Temperature TA (°C) VINT (V) -40 -20 0 20 40 60 80 100 120 140 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 VIN (V) 2.7 23 Figure 7-31. ITIMER internal Pull-Up Voltage vs Temperature TA (°C) IDVDT ( μ -40 -20 0 20 40 60 80 100 120 140 1.9 2.1 2.2 2.3 2.4 2.5 2.6
2.7 VIN (V)
2.7 Figure 7-32. DVDT Charging Current vs Temperature Figure 7-33. PGTH Threshold vs Temperature www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS25947
TA (°C) VPGD (V) -40 -20 0 20 40 60 80 100 120 140 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 IPG ( μ 242 Figure 7-34. PG Low Voltage Without Input Supply vs Temperature TA (°C) RFLTB (Ω) -40 -20 0 20 40 60 80 100 120 140 VIN (V) 2.7 Figure 7-35. FLTb Pin Pull-down Resistance vs Temperature Figure 7-36. Time to Thermal Shut-Down During Inrush State Figure 7-37. Time to Thermal Shut-Down During Steady State VIN = 12 V, COUT = 30 μF, CdVdt = Open, VEN/UVLO stepped up to 1.4 V Figure 7-38. Start Up with Enable VIN VOUT EN IIN VEN/UVLO = 3.3 V, COUT = 30 μF, CdVdt = Open, VIN ramped up to 12 V Figure 7-39. Start Up with Supply COUT = 220 μF, CdVdt = 10 nF, EN/UVLO connected to IN through resistor ladder, 12 V hot-plugged to IN Figure 7-40. Input Hot-Plug EN VOUT PG IIN VIN = 12 V, COUT = 470 μF, CdVdt = 3300 pF, VEN/UVLO stepped up to 1.4 V Figure 7-41. Inrush Current with Capacitive Load TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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VIN = 12 V, COUT = 470 μF, ROUT = 5 Ω, CdVdt = 3300 pF, VEN/UVLO stepped up to 1.4 V Figure 7-42. Inrush Current with Resistive and Capacitive Load VIN VOUT PG COUT = 220 μF, PG pulled up to 3 V, -15 V hot-plugged to IN Figure 7-43. Input Reverse Polarity Protection - Fast Ramp VIN VOUT PG COUT = 220 μF, PG pulled up to 3 V, VIN ramped down from 0 V to -15 V and then ramped up to 0 V Figure 7-44. Input Reverse Polarity Protection - Slow Ramp VIN VOUT OVLO IIN COUT = 220 μF, ROUT = 20 Ω, VIN Overvoltage threshold set to
13.2 V, VIN ramped up from 12 V to 16 V
Figure 7-45. Overvoltage Lockout Response - TPS259470x/4x VIN VOUT PG ROVCSEL = GND, COUT = 220 μF, IOUT = 120 mA, VIN ramped up from 3.3 V to 6 V Figure 7-46. Overvoltage Clamp Response - TPS259472x VIN VOUT PG ROVCSEL = Open, COUT = 220 μF, IOUT = 150 mA, VIN ramped up from 5 V to 8 V Figure 7-47. Overvoltage Clamp Response - TPS259472x VIN VOUT PG ROVCSEL = 390 kΩ, COUT = 220 μF, IOUT = 300 mA, VIN ramped up from 12 V to 16.5 V Figure 7-48. Overvoltage Clamp Response - TPS259472x VIN VOUT IIN FLTb VIN = 12 V, CITIMER = 2.2 nF, COUT = 220 μF, RILM = 549 Ω, IOUT stepped from 3 A → 9 A → 3 A within 5 ms Figure 7-49. Active Current Limit Response - TPS259470x www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS25947
VIN = 12 V, CITIMER = 2.2 nF, COUT = 220 μF, RILM = 549 Ω, IOUT stepped from 3 A → 9 A Figure 7-50. Active Current Limit Response Followed by TSD - TPS259470x VIN VOUT ITIMER IIN VIN = 12 V, CITIMER = 2.2 nF, COUT = 470 μF, RILM = 549 Ω, IOUT ramped from 4 A → 8 A→ 4 A within 1 ms Figure 7-51. Transient Overcurrent Blanking Timer Response - TPS259474x VIN VOUT PG IIN VIN = 12 V, CITIMER = 2.2 nF, COUT = 470 μF, RILM = 549 Ω, IOUT ramped from 4 A → 8 A Figure 7-52. Circuit Breaker Response - TPS259474x VIN VOUT IOUT VIN = 12 V, RILM = 549 Ω, VEN/UVLO = 3.3 V, OUT stepped from Open → Short-circuit to GND Figure 7-53. Output Short-Circuit During Steady State VIN VOUT IOUT VIN = 12 V, RILM = 549 Ω, VEN/UVLO = 3.3 V, OUT stepped from Open → Short-circuit to GND Figure 7-54. Output Short-Circuit During Steady State (zoomed In) VIN VOUT IIN FLTb VIN = 12 V, COUT = Open, OUT short-circuit to GND, RILM = 1650 Ω, VEN/UVLO stepped from 0 V to 3.3 V Figure 7-55. Power Up into Short-Circuit TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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8 Detailed Description
8.1 Overview
The TPS25947xx is an eFuse with integrated power path that is used to ensure safe power delivery in a system. The device starts its operation by monitoring the IN bus. When the input supply voltage (V IN) exceeds the Undervoltage Protection threshold (V UVP), the device samples the EN/UVLO pin. A high level (> V UVLO) on this pin enables the internal power path (BFET+HFET) to start conducting and allow current to flow from IN to OUT. When EN/UVLO is held low (< V UVLO), the internal power path is turned off. In case of reverse voltages appearing at the input, the power path remains OFF thereby protecting the output load. After a successful start-up sequence, the device now actively monitors its load current and input voltage, and controls the internal HFET to ensure that the user adjustable overcurrent limit threshold (I LIM) is not exceeded and overvoltage spikes are either safely clamped to the selected threshold voltage (V OVC) or cut-off once they cross the user adjustable overvoltage lockout threshold (VOVLO). The device also provides fast protection against severe overcurrent during short-circuit events. This keeps the system safe from harmful levels of voltage and current. At the same time, a user adjustable overcurrent blanking timer allows the system to pass moderate transient peaks in the load current profile without tripping the eFuse. This ensures a robust protection solution against real faults which is also immune to transients, thereby ensuring maximum system uptime. The device has integrated reverse current blocking FET (BFET) which operates like an ideal diode. The BFET is linearly regulated to maintain a small constant forward drop (V FWD) in forward conduction mode and turned off completely to block reverse current if output voltage exceeds the input voltage. The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device temperature (TJ) exceeds the recommended operating conditions. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS25947
8.2 Functional Block Diagram
- 10 OC DVDT ITIMER Temp Sense & Overtemperature protection AUXOFFFLT ITIMER_EXPIRED
8 GND
INRUSH_DONE 2.8V GHI 16.9 mV TSD OVLO EN/UVLO SWEN UVPb OVLOb UVLOb SD 0.74V; ITIMER_EXPIRED FFT 1.06 V; 2.57 V RCB 110 ms TIMER# R S Q FLT ILM Pin Short TSD SD UVPb RETRY# RCB ITIMER_EXPIRED INRUSH_DONE UVLOb OVLOb 2.53V9 2.42V; 1.20V9 1.09V; 1.20V9 1.09V; # Not applicable to Latch-off variants (TPS259470L) RETRY# Short Detect ILM Pin Short íXô A îXîí A 353.9 mV FFT GHI INRUSH_DONE BFET HFET íôî A/A15 kQ Figure 8-1. TPS259470x Block Diagram TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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- 10 OC DVDT ITIMER Temp Sense & Overtemperature protection PGTH ITIMER_EXPIRED
INRUSH_DONE 2.8V GHI 16.9 mV TSD OVCSEL EN/UVLO SWEN UVPb OVC UVLOb SD 0.74V; ITIMER_EXPIRED RCB 110 ms TIMER# R S Q FLT ILM Pin Short TSD SD UVPb RETRY# INRUSH_DONE 2.53V9 2.42V; 1.20V9 1.09V; # Not applicable to Latch-off variants (TPS259472L) RETRY# Short Detect ILM Pin Short 353.9 mV FFT OVC Threshold Select RCB PG_int PG_int OVC 1.2V9 PG_int FFT GHI R S Q /Q PG INRUSH_DONE BFET HFET íXô A îXîí A íôî A/A 1.06 V; 2.57 V 15 kQ 1.09V; Figure 8-2. TPS259472x Block Diagram www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS25947
- 10 OC DVDT ITIMER Temp Sense & Overtemperature protection ITIMER_EXPIRED
INRUSH_DONE 2.8V GHI 16.9 mV TSD OVLO EN/UVLO SWEN UVPb OVLOb UVLOb SD 0.74V; FFTRCB 2.53V9 2.42V; 1.20V9 1.09V; 1.20V9 1.09V; Short Detect ILM Pin Short íXô A îXîí A 353.9 mV FFT GHI PGTH PG_int 110 ms TIMER# R S Q FLTTSD SD UVPb RETRY# INRUSH_DONE RETRY# RCB PG_int PG_int ILM Pin Short ITIMER_EXPIRED R Q PG S # Not applicable to Latch-off variants (TPS259474L) INRUSH_DONE BFET HFET íôî A/A 1.06 V; 2.57 V 15 kQ 1.2V9 1.09V; Figure 8-3. TPS259474x Block Diagram TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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8.3 Feature Description
The TPS25947xx eFuse is a compact, feature rich power management device that provides detection, protection and indication in the event of system faults.
8.3.1 Input Reverse Polarity Protection
The TPS25947xx device is internally protected against steady state negative voltages applied at the input supply pin. The device blocks the negative voltage from appearing at the output, thereby protecting the load circuits. There’s no reverse current flowing from output to the input in this condition. The lowest negative voltage the device can handle at the input is limited to -15 V or VOUT – 21 V, whichever is higher. It’s also recommended that all signal pins (e.g. EN/UVLO, OVLO, PGTH) which are connected to input supply should have a sufficiently large pull-up resistor to limit the current flowing out of these pins during reverse polarity conditions. Please refer to Absolute Maximum Ratings table for more details.
8.3.2 Undervoltage Lockout (UVLO & UVP)
The TPS25947xx implements Undervoltage Protection on IN in case the applied voltage becomes too low for the system or device to properly operate. The Undervoltage Protection has a default lockout threshold of VUVP which is fixed internally. Also, the UVLO comparator on the EN/UVLO pin allows the Undervoltage Protection threshold to be externally adjusted to a user defined value. The Figure 8-4 and Equation 1 show how a resistor divider can be used to set the UVLO set point for a given voltage supply. IN EN/UVLO GND Power Supply Figure 8-4. Adjustable Undervoltage Protection VIN(UV) = VUVLO x (R1 + R2) (1)
8.3.3 Overvoltage Lockout (OVLO)
The TPS259470x/4x variants allow the user to implement Overvoltage Lockout to protect the load from input overvoltage conditions. The OVLO comparator on the OVLO pin allows the Overvoltage Protection threshold to be adjusted to a user defined value. Once the voltage at the OVLO pin crosses the OVLO rising threshold VOV(R), the device turns off the power to the output. Thereafter, the devices wait for the voltage at the OVLO pin to fall below the OVLO falling threshold VOV(F) before the output power is turned ON again. The rising and falling thresholds are slightly different to provide hysterisis. The Figure 8-5 and Equation 2 show how a resistor divider can be used to set the OVLO set point for a given voltage supply. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPS25947
Figure 8-5. Adjustable Overvoltage Protection VIN(OV) = VOV x (R1 + R2) (2) While recovering from a OVLO event, the TPS259470x variants bypass the inrush control (dVdt) and start up in a current limited manner to provide faster turn ON and minimize power supply droop. IN Time OUT tOVLO Input Overvoltage Event Input Overvoltage Removed OVLO VOV(R) VOV(F) FLT VFLT Current Limited Start-up VAUXOFF 0AUXOFF tSWOV Figure 8-6. TPS259470x Overvoltage Lockout and Recovery While recovering from a OVLO event, the TPS259474x variants start up with inrush control (dVdt). TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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Input Overvoltage Event Input Overvoltage Removed OVLO VOV(R) VOV(F) tPGD tPGA dVdt Limited Start-up Figure 8-7. TPS259474x Overvoltage Lockout and Recovery
8.3.4 Overvoltage Clamp (OVC)
The TPS259472x variants implement a voltage clamp on the output to protect the system in the event of input overvoltage. When the device detects the input has exceeded the Overvoltage Clamp Threshold (V OVC), it quickly responds within t OVC and stops the output from rising further and then regulates the HFET linearly to clamp the output voltage below VCLAMP as long as an overvoltage condition is present on the input. If the part stays in clamping state for an extended period of time, there will be higher power dissipation inside the part which may eventually lead to thermal shut-down (TSD). Once the part shuts down due to TSD fault, it would either stay latched off (TPS259472L variant) or restart automatically after a fixed delay (TPS259472A variant). See Overtemperature Protection (OTP) for more details on device response to overtemperature. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPS25947
Input Overvoltage Event Input Overvoltage Removed VOVC tPGA dVdt Limited Start-up VCLAMP TJ TSD TSDHY S Thermal Shutdown tRST Retry Timer Expired (1) (1) Applicable only for TPS259472A (Auto-retry variant) tPGD Figure 8-8. TPS259472x Overvoltage Response (Auto-Retry) There are 3 available overvoltage clamp threshold options which can be configured using the OVCSEL pin. Table 8-1. TPS259472x Overvoltage Clamp Threshold Selection OVCSEL Pin Connection Overvoltage Clamp Threshold Shorted to GND 3.8 V Open 5.7 V Connected to GND through 390-kΩ resistor 13.8 V
8.3.5 Inrush Current, Overcurrent, and Short Circuit Protection
TPS25947xx incorporates four levels of protection against overcurrent: 1. Adjustable slew rate (dVdt) for inrush current control 2. Adjustable threshold (I LIM) for overcurrent protection during start-up or steady-state 3. Adjustable threshold (I SC) for fast-trip response to severe overcurrent during start-up or steady-state 4. Fixed threshold (I FT) for fast-trip response to quickly protect against hard output short-circuits during steady- state
8.3.5.1 Slew Rate (dVdt) and Inrush Current Control
During hot-plug events or while trying to charge a large output capacitance at start-up, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and/or cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn on is directly proportional to the load capacitance and rising slew rate. Equation 3 can be used to find the slew rate (SR) required to limit the inrush current (IINRUSH) for a given load capacitance (COUT): SR (V/ms) = IINRUSH (mA) COUT (µF) (3) A capacitor can be connected to the dVdt pin to control the rising slew rate and lower the inrush current during turn on. The required CdVdt capacitance to produce a given slew rate can be calculated using Equation 4. TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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CdVdt (pF) = 2000 SR (V/ms) (4) The fastest output slew rate is achieved by leaving the dVdt pin open. Note For CdVdt > 10 nF, it's recommended to add a 100- Ω resistor in series with the capacitor on the dVdt pin.
8.3.5.2 Circuit-Breaker
The TPS259474x (Circuit-Breaker) variants respond to output overcurrent conditions by turning off the output after a user adjustable transient fault blanking interval. When the load current exceeds the set overcurrent threshold (ILIM) set by the ILM pin resistor (RILM), but stays lower than the fast-trip threshold (2 x I LIM), the device starts discharging the ITIMER pin capacitor using an internal 1.8- μA pull-down current. If the load current drops below ILIM before the ITIMER pin capacitor (C ITIMER) discharges by ΔVITIMER, the ITIMER is reset by pulling it up to V INT internally and the circuit breaker action is not engaged. This allows short load transient pulses to pass through the device without tripping the circuit. If the overcurrent condition persists, the C ITIMER continues to discharge and once it discharges by ΔVITIMER, the circuit breaker action turns off the HFET immediately. At the same time, the C ITIMER is charged up to V INT again so that it is at its default state before the next overcurrent event. This ensures the full blanking timer interval is provided for every overcurrent event. Equation 5 can be used to calculate the RILM value for a overcurrent threshold. RILM :À; = 3334 ILIM :A; (5) Note 1. Leaving the ILM pin Open sets the current limit to nearly zero and results in the part breaking the circuit with the slightest amount of loading at the output. 2. Shorting the ILM pin to ground at any point during normal operation is detected as a fault and the part shuts down. There’s a minimum current (IFLT) which the part allows in this condition before the pin short condition is detected. The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER pin to ground. The C ITIMER value needed to set the desired transient overcurrent blanking interval can be calculated using Equation 6. tITIMER (ms) = ¿VITIMER (V) x CITIMER (nF) IITIMER (µA) (6) www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPS25947
Transient Overcurrent ITIMER expiredPersistent Output Overload TSDHY S Circuit-Breaker operation PG VPG PGTH VPGTH tPGD ¨VITIMER 2 x ILIM VINT Figure 8-9. TPS259474x Overcurrent Response Note 1. Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay. 2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar to ITIMER pin open condition), but increases the device current consumption. This is not a recommended mode of operation. 3. Increasing the ITIMER cap value extends the overcurrent blanking interval, but it also extends the time needed for the ITIMER cap to recharge up to VINT. If the next overcurrent event occurs before the ITIMER cap is recharged fully, it will take lesser time to discharge to the ITIMER expiry threshold, thereby providing a shorter blanking interval than intended. Once the part shuts down due to a Circuit Breaker fault, it would either stay latched off (TPS259474L variant) or restart automatically after a fixed delay (TPS259474A variant).
8.3.5.3 Active Current Limiting
The TPS259470x/2x (Active Current Limit) variants respond to output overcurrent conditions by actively limiting the current after a user adjustable transient fault blanking interval. When the load current exceeds the set overcurrent threshold (I LIM) set by the ILM pin resistor (R ILM), but stays lower than the short-circuit threshold (2 x I LIM), the device starts discharging the ITIMER pin capacitor using an internal 1.8- μA pull-down current. If the load current drops below the overcurrent threshold before the ITIMER capacitor (C ITIMER) discharges by ΔVITIMER, the ITIMER is reset by pulling it up to V INT internally and the current limit action is not engaged. This TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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allows short load transient pulses to pass through the device without getting current limited. If the overcurrent condition persists, the CITIMER continues to discharge and once it discharges by ΔVITIMER, the current limit starts regulating the HFET to actively limit the current to the set overcurrent threshold (I LIM). At the same time, the CITIMER is charged up to V INT again so that it is at its default state before the next overcurrent event. This ensures the full blanking timer interval is provided for every overcurrent event. Equation 7 can be used to calculate the RILM value for a desired overcurrent threshold. RILM :À; = 3334 ILIM :A; (7) Note 1. Leaving the ILM pin Open sets the current limit to nearly zero and results in the part entering current limit with the slightest amount of loading at the output. 2. The current limit circuit employs a foldback mechanism. The current limit threshold in the foldback region (0 V < VOUT < VFB) is lower than the steady state current limit threshold (ILIM). 3. Shorting the ILM pin to ground at any point during normal operation is detected as a fault and the part shuts down. There’s a minimum current (IFLT) which the part allows in this condition before the pin short condition is detected. The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER pin to ground. The C ITIMER value needed to set the desired transient overcurrent blanking interval can be calculated using Equation 8 below. tITIMER (ms) = ¿VITIMER (V) x CITIMER (nF) IITIMER (µA) (8) www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TPS25947
Transient Overcurrent ITIMER expiredPersistent Output Overload Thermal shutdown TSDHY S Current limiting operation PG(1) VPG tLIM PGTH(1) 1.2 V VFLT FLT(2) tPGD ITIMER expiredPersistent Output Overload Current limiting operation tLIM tPGD Overload Removed tPGA tITIMER (1) Applicable only to TPS259472x/4x variants (2) Applicable only to TPS259470x variants ¨VITIMER 2 x ILIM VINT Figure 8-10. TPS259470x/2x Active Current Limit Response Note 1. Leave the ITIMER pin open to allow the part to limit the current with the minimum possible delay. 2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar to ITIMER pin open condition), but increases the device current consumption. This is not a recommended mode of operation. 3. Active current limiting based on R ILM is active during startup for both TPS259470x/2x (Current Limit) and TPS259474x (Circuit-Breaker) variants. In case the startup current exceeds ILIM, the device regulates the current to the set limit. However, during startup the current limit is engaged without waiting for the ITIMER delay. 4. For the TPS259472x variants, during overvoltage clamp condition, if an overcurrent event occurs, the current limit is engaged without waiting for the ITIMER delay. 5. Increasing the C ITIMER value extends the overcurrent blanking interval, but it also extends the time needed for the CITIMER to recharge up to VINT. If the next overcurrent event occurs before the CITIMER is recharged fully, it will take lesser time to discharge to the ITIMER expiry threshold, thereby providing a shorter blanking interval than intended. During active current limit, the output voltage will drop resulting in increased device power dissipation across the HFET. If the device internal temperature (TJ) exceeds the thermal shutdown threshold (TSD), the HFET is turned off. Once the part shuts down due to TSD fault, it would either stay latched off (TPS25947xL variants) or restart automatically after a fixed delay (TPS25947xA variants). See Overtemperature Protection (OTP) for more details on device response to overtemperature. TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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8.3.5.4 Short-Circuit Protection
During an output short-circuit event, the current through the device increases very rapidly. When a severe overcurrent condition is detected, the device triggers a fast-trip response to limit the current to a safe level. The internal fast-trip comparator employs a scalable threshold (I SC) which is equal to 2 × I LIM. This enables the user to adjust the fast-trip threshold rather than using a fixed threshold which can be too high for some low current systems. The device also employs a fixed fast-trip threshold (I FT) to protect fast protection against hard short-circuits during steady state. The fixed fast-trip threshold is higher than the maximum recommended user adjustable scalable fast-trip threshold. Once the current exceeds I SC or I FT, the HFET is turned off completely within t FT. Thereafter, the devices tries to turn the HFET back on after a short de-glitch interval (30 μs) in a current limited manner instead of a dVdt limited manner. This ensures that the HFET has a faster recovery after a transient overcurrent event and minimizes the output voltage droop. However, if the fault is persistent, the device will stay in current limit causing the junction temperature to rise and eventually enter thermal shutdown. See Overtemperature Protection (OTP) section for details on the device response to overtemperature. IOUT ILIM Time OUT VIN PG (1) TJ TSD TSDHYS tRST Thermal Shutdown IN 2 x ILIM Transient Severe Overcurrent Persistent Severe Overcurrent Retry Timer Elapsed (3) Overcurrent Removed tSC tSC Current Limited Start-up dVdt Limited Start-up VPG FLT (2) VFLT (1) Applicable only to TPS259472x/4x variants (2) Applicable only to TPS259470x variants (3) Applicable only to TPS25947xA variants tRST Thermal Shutdown Retry Timer Elapsed (3) Short-circuit Removed tFT dVdt Limited Start-up IFT Output Hard Short-circuit to ground tPGDtPGD tPGD VIN Figure 8-11. TPS25947xx Short-Circuit Response
8.3.6 Analog Load Current Monitor
The device allows the system to accurately monitor the output load current by providing an analog current sense output on the ILM pin which is proportional to the current through the FET. The user can sense the voltage (VILM) across the RILM to get a measure of the output load current. IOUT (A) = VILM (µV) RILM :À;x GIMON (µA/A) (9) The waveform below shows the ILM signal response to a load step at the output. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TPS25947
VIN = 12 V, COUT = 22 μF, RILM = 1150 Ω, IOUT varied dynamically between 0A and 3.5 A Figure 8-12. Analog Load Current Monitor Response Note The ILM pin is sensitive to capacitive loading. Careful design and layout is needed to ensure the parasitic capacitive loading on the ILM pin is < 50 pF for stable operation.
8.3.7 Reverse Current Protection
The device functions like an ideal diode and blocks reverse current flow from OUT to IN under all conditions. The device has integrated back-to-back MOSFETs connected in a common drain configuration. The voltage drop between the IN and OUT pins is constantly monitored and the gate drive of the blocking FET (BFET) is adjusted as needed to regulate the forward voltage drop at V FWD. This closed loop regulation scheme (linear ORing control) enables graceful turn off of the MOSFET during a reverse current event and ensures there's no DC reverse current flow. The device also uses a conventional comparator (V REVTH) based reverse blocking mechanism to provide fast response (tRCB) to transient reverse currents.Once the device enters reverse current blocking condition, it waits for the (V IN - V OUT) forward drop to exceed the V FWDTH before it performs a fast recovery to reach full forward conduction state. This provides sufficient hysterisis to prevent supply noise or ripple from affecting the reverse current blocking response. The recovery from reverse current blocking is very fast (t SWRCB). This ensures minimum supply droop which is helpful in applications such as supply MUXing/ORing and USB Fast Role Swap (FRS). IN OUT VFWD VIN - VOUT BFET regulation BFET full conductionBFET turned OFF
0 V V FWDVREVTH VFWTH
(RCB entry) BFET fast enable (RCB exit) Linear ORing loop response RCB fast comparator response IIN 0 A ForwardReverse BFET operating state IN OUT Figure 8-13. Reverse Current Blocking Response The waveforms below illustrate the reverse current blocking performance in various scenarios. TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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During fast voltage step at output (e.g. hot-plug), the fast comparator based reverse blocking mechanism ensures minimum jump/glitch on the input rail. VIN VOUT IIN FLTb Figure 8-14. Reverse Current Blocking Performance During Fast Voltage Step at Output During slow voltage ramp at output, the linear ORing based reverse blocking mechanism ensures there's no DC current flow from OUT to IN, thereby avoiding input rail from getting slowly charged up to output voltage. VIN VOUT IIN FLTb Figure 8-15. Reverse Current Blocking Performance During Slow Voltage Ramp at Output When the input supply droops or gets disconnected while the output storage element (bulk capacitor or super capacitor) is charged to the full voltage, the linear ORing scheme minimizes the self-discharge from OUT to IN. This ensures maximum hold-up time for the output storage element in critical power back-up applications. It also prevents incorrect supply presence indication in applications which sense the input voltage to detect if the supply is connected. VIN VOUT AUXOFF Figure 8-16. Reverse Current Blocking Performance During Input Supply Failure
8.3.8 Overtemperature Protection (OTP)
The device monitors the internal die temperature (T J) at all times and shuts down the part as soon as the temperature exceeds a safe operating level (TSD) thereby protecting the device from damage. The device will not turn back on until the junction cools down sufficiently, that is the die temperature falls below (TSD - TSDHYS). When the TPS25947xL (latch-off variant) detects thermal overload, it will be shut down and remain latched-off until the device is power cycled or re-enabled. When the TPS25947xA (auto-retry variant) detects thermal overload, it will remain off until it has cooled down by TSDHYS. Thereafter, it will remain off for an additional delay of tRST after which it will automatically retry to turn on if it is still enabled. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TPS25947
Table 8-2. Thermal Shutdown Device Enter TSD Exit TSD TPS25947xL (Latch-Off) TJ ≥ TSD TJ < TSD - TSDHYS VIN cycled to 0 V and then above VUVP(R) OR EN/UVLO toggled below VSD(F) TPS25947xA (Auto-Retry) TJ ≥ TSD TJ < TSD - TSDHYS VIN cycled to 0 V and then above VUVP(R) OR EN/UVLO toggled below VSD(F) OR tRST timer expired
8.3.9 Fault Response and Indication (FLT)
The following table summarizes the device response to various fault conditions. Additionally, an active low external fault indication (FLT) pin is available on the TPS259470x variants. Table 8-3. Fault Summary Event Protection Response Fault Latched Internally FLT Pin status (1) FLT Assertion Delay(1) Overtemperature Shutdown Y L Undervoltage (UVP or UVLO) Shutdown N H Input Reverse Polarity Shutdown N H Input Overvoltage Shutdown(1) (2) N H Voltage Clamp(2) N N/A Transient Overcurrent (ILIM < IOUT < 2 x ILIM) None N N Persistent Overcurrent Circuit Breaker(3) Y N/A Persistent Overcurrent Current Limit(4) N L tITIMER Output Short-Circuit to GND Circuit Breaker followed by Current Limit N H ILM Pin Open (During Steady State) Shutdown N L tITIMER ILM Pin Shorted to GND Shutdown Y L tITIMER Reverse Current ((VOUT - VIN) > VREVTH) Reverse Current Blocking N L (1) Applicable to TPS259470x variants only (2) Applicable to TPS259472x variants only (3) Applicable to TPS259474x variants only (4) Applicable to TPS259470x/2x variants only Faults which are latched internally can be cleared either by power cycling the part (pulling V IN to 0 V) or by pulling the EN/UVLO pin voltage below V SD. This also releases the FLT pin for the TPS259470x variants and resets the tRST timer for the TPS25947xA (auto-retry) variants. During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device. This is true for both TPS25947xL (latch-off) & TPS25947xA (auto-retry) variants. For TPS25947xA (auto-retry) variants, on expiry of the t RST timer after a fault, the device restarts automatically and the FLT pin is de-asserted (TPS259470A variant).
8.3.10 Auxiliary Channel Control (AUXOFF)
The TPS259470x variants provide an active high digital output (AUXOFF) which is asserted to indicate when the priority input supply is in a valid range (above UVP/UVLO and below OVLO thresholds) and the device has TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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successfully completed its inrush sequence. The AUXOFF pin is an open-drain signal which needs to be pulled up to an external supply. After power up, AUXOFF pin is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on in a controlled manner. When the FET gate voltage has reached the full overdrive indicating that the inrush sequence is complete and device is capable of delivering full power, the AUXOFF pin is asserted high. Thereafter, the AUXOFF pin is de-asserted only if the input supply becomes invalid (below UVP/UVLO or above OVLO thresholds). No load side events/faults have any control over the AUXOFF de-assertion. This pin is used to control the auxiliary channel when 2 TPS259470x devices are connected in a priority power MUX configuration. It can also be used as a supply valid status indication to the downstream load or system supervisor. Table 8-4. TPS259470x AUXOFF Indication Summary Event AUXOFF Pin Undervoltage (UVP or UVLO) L Input Reverse Polarity L Overvoltage (OVLO) L Inrush L Steady State H Overcurrent H Short-Circuit H ILM Pin Open H ILM Pin Shorted to GND H Reverse current ((VOUT - VIN) > VREVTH) H Overtemperature H When there is no supply to the device, the AUXOFF pin is expected to stay low. However, there is no active pull-down in this condition to drive this pin all the way down to 0 V. If the AUXOFF pin is pulled up to an independent supply which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the pin sink current, which is a function of the pull-up supply voltage and resistor. Minimize the sink current to keep this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition. This also ensures that the auxiliary channel is not turned off inadvertently in a priority power MUX configuration.
8.3.11 Power Good Indication (PG)
The TPS259472x/4x variants provide an active high digital output (PG) which serves as a power good indication signal and is asserted high depending on the voltage at the PGTH pin along with the device state information. The PG is an open-drain pin and needs to be pulled up to an external supply. After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush sequence is complete and the voltage at PGTH is above V PGTH(R), the PG is asserted after a de-glitch time (tPGA). PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below V PGTH(F), or the device detects a fault (except overcurrent). The PG de-assertion de-glitch time is tPGD. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TPS25947
VOUT + 2.8V EN/UVLO VUVLO(R) Slew rate (dVdt) controlled startup/Inrush current limiting VIN Overload Event Overload Removed ILIM IINRUSH tPGD tITIMER IOUT Active Current limiting (1) tPGA tPGA VIN dVdt Device Enabled PGTH VPGTH(F) VPGTH(R) (1) Applicable to TPS259472x only Overcurrent blanking timer expired Figure 8-17. TPS259472x/74x PG Timing Diagram Table 8-5. TPS259472x/4x PG Indication Summary Event Protection Response PG Pin PG Delay Undervoltage (UVP or UVLO) Shutdown L Input Reverse Polarity Shutdown L Overvoltage (OVC) (TPS259472x only) Clamp H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) tPGA tPGD Overvoltage (OVLO) (TPS259474x only) Shutdown L (If PGTH pin voltage < VPGTH(F)) tPGD TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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Table 8-5. TPS259472x/4x PG Indication Summary (continued) Event Protection Response PG Pin PG Delay Steady State NA H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) tPGA tPGD Transient overcurrent NA H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) tPGA tPGD Persistent overload (TPS259472x only) Current Limiting H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) tPGA tPGD Persistent overload (TPS259474x only) Shutdown H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) tPGA tPGD Output Short-Circuit to GND Fast trip followed by Current Limit H (If PGTH pin voltage > VPGTH(R)) L (If PGTH pin voltage < VPGTH(F)) tPGA tPGD ILM Pin Open Shutdown L (If PGTH pin voltage < VPGTH(F)) tPGD ILM Pin Shorted to GND Shutdown L (If PGTH pin voltage < VPGTH(F)) tPGD Reverse current ((VOUT - VIN) > VREVTH) Reverse current blocking L tPGD Overtemperature Shutdown L (If PGTH pin voltage < VPGTH(F)) tPGD When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pull-down in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the pin sink current, which is a function of the pull-up supply voltage and resistor. Minimize the sink current to keep this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.
8.4 Device Functional Modes
Table 8-6. TPS259472x Overvoltage Clamp Threshold Selection OVCSEL Pin Connection Overvoltage Clamp Threshold Shorted to GND 3.8 V Open 5.7 V Connected to GND through 390-kΩ resistor 13.8 V www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TPS25947
9 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
9.1 Application Information
The TPS25947xx is a 2.7 V to 23 V, 5.5-A eFuse that is typically used for power rail protection applications . It operates from 2.7 V to 23 V with adjustable overvoltage and undervoltage protection. It provides ability to control inrush current and protection against input reverse polarity as well as reverse current conditions. It can be used in a variety of systems such as Adapter Input Protection , USB PD port protection ,Server/PC Motherboard/Add-on cards , Enterprise storage - RAID/HBA/SAN/eSSD , Monitors/Docks. The design procedure explained in the subsequent sections can be used to select the supporting component values based on the application requirement. Additionally, a spreadsheet design tool TPS25947xx Design Calculator is available in the web product folder.
9.2 Single Device, Self-Controlled
VIN = 2.7 to 23 V VOUT COUT OVLO AUXOFF FLT ITIMER VLOGIC TPS259472x IN OUT EN/UVLO ILMdVdt GND VIN = 2.7 to 23 V VOUT COUT OVCSEL PGTH PG ITIMER TPS259474x IN OUT EN/UVLO ILMdVdt GND VIN = 2.7 to 23 V VOUT COUT OVLO PGTH PG ITIMER VLOGIC VLOGIC Figure 9-1. Single Device, Self-Controlled Other variations: In a Host MCU controlled system, EN/UVLO or OVLO can also be driven from the host GPIO to control the device. ILM pin can be connected to the MCU ADC input for current monitoring purpose. TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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It's recommended to keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation. For the TPS259472x/4x variants, either V IN or V OUT can be used to drive the PGTH resistor divider depending on which supply needs to be monitored for power good indication.
9.3 Typical Application
TPS259474x can be used for PCIe card input power protection. A full-sized ×16 graphics card may draw up to 5.5 A at +12 V (66 W). A typical PCIe slot has the capacity of providing current upto 6 A. During overcurrent or short-circuit event at load side, TPS259474x can quickly respond to this fault event by turning off the device and thus protect the load from damage as well as prevent input supply from drooping. The ITIMER feature allows short duration peak currents to pass through without tripping the eFuse, thereby meeting the transient load current profile of graphics cards. TPS259474L IN OUT EN/UVLO ILMdVdt GND VIN = 12 V RILM VOUT COUT OVLO PGTH PG ITIMER CdVdtCITIMER CIND1* D2* í F ñðõO3300 pF2.2 nF ðóì F470 kO 11 kO 47 kO 47 kO 5.6 kO 3.3 V 47 kO * Optional circuit components needed for transient protection depending on input and output inductance. Please refer to Transient Protection section for details. Figure 9-2. PCIe Card Input Power Protection
9.3.1 Design Requirements
Table 9-1. Design Parameters PARAMETER VALUE Input supply voltage (VIN) 12 V Undervoltage threshold (VIN(UV)) 10.8 V Overvoltage threshold (VIN(OV)) 13.2 V Output power good threshold (VPG) 11.4 V Max continuous current 5.5 A Load transient blanking interval (tITIMER) 2 ms Output capacitance (COUT) 470 μF Output rise time (tR) 20 ms www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TPS25947
Table 9-1. Design Parameters (continued) PARAMETER VALUE Overcurrent threshold (ILIM) 6 A Overcurrent response Circuit breaker Fault response Latch-off
9.3.2 Detailed Design Procedure
9.3.2.1 Device Selection
Since the application requires circuit-breaker response to overcurrent with latch-off response after a fault, the TPS259474L variant is selected after refering to the Device Comparison Table.
9.3.2.2 Setting Undervoltage and Overvoltage Thresholds
The supply undervoltage and overvoltage thresholds are set using the resistors R1, R2 & R3 whose values can be calculated using Equation 10 and Equation 11: VIN(UV) = VUVLO(R) x (R1 + R2 + R3) R2 + R3 (10) VIN(OV) = VOV(R) x (R1 + R2 + R3) (11) Where VUVLO(R) is the UVLO rising threshold and VOV(R) is the OVLO rising threshold . Because R1, R2 and R3 leak the current from input supply VIN, these resistors must be selected based on the acceptable leakage current from input power supply VIN. The current drawn by R1, R2 and R3 from the power supply is IR123 = VIN / (R1 + R2 + R3). However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the leakage current expected on the EN/UVLO and OVLO pins. From the device electrical specifications, both the EN/UVLO and OVLO leakage currents are 0.1 μA (max), the equation, first choose the value of R1 = 470 k Ω and use the above equations to solve for R2 = 10.7 k Ω and R3 = 48 kΩ. Using the closest standard 1% resistor values, we get R1 = 470 kΩ, R2 = 11 kΩ, and R3 = 47 kΩ.
9.3.2.3 Setting Output Voltage Rise Time (tR)
For a successful design, the junction temperature of device must be kept below the absolute maximum rating during both dynamic (start-up) and steady-state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and inrush current limit required with system capacitance to avoid thermal shutdown during start-up. The slew rate (SR) needed to achieve the desired output rise time can be calculated as: SR (V/ms) = VIN (V) tR (ms) = 12 V 20 ms = 0.6 V/ms (12) The CdVdt needed to achieve this slew rate can be calculated as: CdVdt :pF; = 2000 SR :V/ms; = 2000 0.6 = 3333 pF (13) Choose the nearest standard capacitor value as 3300 pF. For this slew rate, the inrush current can be calculated as: TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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IINRUSH :mA; = SR (V/ms) x COUT :µF; = 0.6 x 470 = 282 mA (14) The average power dissipation inside the part during inrush can be calculated as: PDINRUSH :W; = IINRUSH :A; x VIN :V; 2 = 0.282 x 12 2 = 1.69 W (15) For the given power dissipation, the thermal shutdown time of the device must be greater than the ramp-up time tR to avoid start-up failure. Figure 9-3 shows the thermal shutdown limit, for 1.69 W of power, the shutdown time is more than 10 s which is very large as compared to tR = 20 ms. Therefore, it is safe to use 20 ms as the startup time for this application. Figure 9-3. Thermal Shut-Down Plot During Inrush
9.3.2.4 Setting Power Good Assertion Threshold
The Power Good assertion threshold can be set using the resistors R4 & R5 connected to the PGTH pin whose values can be calculated as: VPG = VPGTH(R) x (R4 + R5) (16) Because R4 and R5 leak the current from the output rail VOUT, these resistors must be selected to minimize the leakage current. The current drawn by R4 and R5 from the power supply is IR45 = VOUT / (R4 + R5). However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the PGTH leakage current expected. From the device electrical specifications, PGTH leakage current is 1 μA (max), VPGTH(R) = 1.2 V and from design requirements, VPG = 11.4 V. To solve the equation, first choose the value of R4 = 47 kΩ and calculate R5 = 5.52 kΩ. Choose nearest 1% standard resistor value as R5 = 5.6 kΩ.
9.3.2.5 Setting Overcurrent Threshold (ILIM)
The overcurrent protection (Circuit Breaker) threshold can be set using the R ILM resistor whose value can be calculated as: RILM :À; = 3334 ILIM :A; = 3334 6 A = 555.6 À (17) Choose nearest 1% standard resistor value as 549 Ω. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TPS25947
9.3.2.6 Setting Overcurrent Blanking Interval (tITIMER)
The overcurrent blanking timer interval can be set using the CITIMER capacitor whose value can be calculated as: CITIMER (nF) = tITIMER (ms) x IITIMER (µA) ¿VITIMER (V) = 2 x 1.8 1.51 = 2.38 nF (18) Choose nearest standard capacitor value as 2.2 nF.
9.3.3 Application Curves
Figure 9-4. Power Up Figure 9-5. Transient Overload Figure 9-6. Circuit Breaker Response
9.4 Active ORing
A typical redundant power supply configuration is shown in Figure 9-7 below. Schottky ORing diodes have been popular for connecting parallel power supplies, such as parallel operation of wall adapter with a battery or a hold-up storage capacitor. The disadvantage of using ORing diodes is high voltage drop and associated power loss. The TPS259470x/4x with integrated, low-ohmic, back-to-back FETs provide a simple and efficient solution. Figure 9-7 below shows the Active ORing implementation using TPS249474x devices. TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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In addition to supply ORing, the devices protect the system from overvoltage, excessive inrush current, overload and short-circuit faults at all times. Note 1. The TPS259472x (OVC variants) are not recommended for use in ORing applications. While the device is in clamping state, if the output is forced to a higher voltage by the other channel, the device can get damaged. 2. ORing can be done either between two similar rails or between dissimilar rails. For ORing cases with skewed voltage combinations, care must be taken to design circuit components on PGTH/EN/OVLO pins for the lower voltage channel devices such that the Absolute maximum ratings on those pins are not exceeded when higher voltage is present on the other channel. Also, the dVdt pin capacitor rating should be chosen based on the highest of the 2 supplies. Refer to Recommended Operating Conditions table for more details.
9.5 Priority Power MUXing
Applications having two energy sources such as PCIe cards, Tablets and Portable battery powered equipment require preference of one source to another. For example, mains power (wall-adapter) has the priority over the internal battery back-up power. These applications demand for switchover from mains power to backup power only when main input voltage falls below a user defined threshold. The TPS25947xx devices provide a simple solution for priority power multiplexing needs. Figure 9-10 below shows a typical priority power multiplexing implementation using TPS259470x devices. When primary (priority) power source (IN1) is present and within the valid range (not in UV/OV condition), the primary path device path powers the OUT bus irrespective of whether auxiliary supply voltage (V IN2) is greater than, equal to or less than primary supply voltage (V IN1). The device in auxiliary path is held in off condition by forcing its OVLO pin to high using the AUXOFF signal from the primary path device. Once the primary supply voltage falls outside the user-defined valid operating range (UV/OV condition), the primary path device de-asserts the AUXOFF which signals the auxiliary path device to turn on and the system starts operating from the auxiliary supply. During this transition, the auxiliary path device bypasses its dVdt limited startup and performs a fast recovery to start delivering power within tSWOV. When the primary supply is restored, the primary path device turns on fully at a defined slew rate and then asserts its AUXOFF pin high to turn the auxiliary path device off, allowing a seamless transition from auxiliary to the primary supply with minimal output voltage droop and with no shoot-through current. A key consideration in power MUXing applications is the minimum voltage the output bus droops to during the switchover from one supply to another. This in turn depends on multiple factors including the output load current (ILOAD), output bus hold-up capacitance (COUT) and switchover time (tSW). While switching from primary supply (VIN1) to auxiliary supply (VIN2), the minimum bus voltage can be calculated using Equation 19. Here, the switchover time (t SW) is equal to the fast OVLO recovery time (t SWOV) taken by the TPS259470x variants to turn on fully and start delivering current to the load. SW LOAD IN1 IN2OUT min OUT t V , $V V min V , V C u (19) While switching from auxiliary supply (VIN2) to primary supply (VIN1), the minimum bus voltage can be calculated using Equation 20. Here the maximum switchover time is equal to the RCB recovery time (t SWRCB), depending on whether VIN1 is equal to or lower than VIN2 to start with. SWRCB LOAD IN1 IN2 FWDTHOUT min OUT t V , $V V min V , V V V C u (20) TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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The AUXOFF pins of the devices can be used as a digital indication to identify which of the 2 supplies is active and delivering power to the load. TPS259470x IN OUT EN/UVLO VIN1 VOUT COUT OVLO AUXOFF VLOGIC TPS259470x IN OUT EN/UVLO VIN2 OVLO AUXOFF VLOGIC FLT FLT IN1 supply active IN2 supply active ILMdVdt GNDITIMER ILMdVdt GNDITIMER Figure 9-10. Priority Power MUXing with 2 x TPS259470x - Option 1 This configuration provides the most compact priority power MUXing solution with multiple benefits, including active current limit protection on both channels as well as overvoltage protection on primary channel. It also provides the fastest switchover time from primary to auxiliary, but at the cost of a slightly increased quiescent current on the auxiliary path while primary path is active. Also, it uses the fewest external components, but at the cost of bypassing overvoltage protection on auxiliary channel. The following waveforms illustrate the TPS259470x performance in a priority power MUXing configuration. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: TPS25947
Figure 9-11. TPS259470x Power MUX - Switchover from Primary to Auxiliary Supply VIN1 VIN2 VOUT IOUT Figure 9-12. TPS259470x Power MUX - Switchover from Auxiliary to Primary Supply There's a possible variation to the above configuration in case overvoltage protection is needed on both channels. This needs an additional signal N-FET to drive the OVLO pin of the auxiliary path device as shown in Figure 9-13 below. The switchover times are similar to the previous configuration. TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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Figure 9-13. Priority Power MUXing with 2 x TPS259470x - Option 2 Another variation of the previous configuration ensures minimum quiescent current on the auxiliary chanel while primary channel is active, but at the cost of additional N-FET to drive the EN/UVLO pin of auxiliary path device as shown in Figure 9-14 below. At the same time, it has a higher switchover delay from primary to auxiliary supply as compared to the previous configuration. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: TPS25947
Figure 9-14. Priority Power MUXing with 2 x TPS259470x - Option 3 While switching from a higher supply rail to lower supply rail, the minimum bus voltage can be calculated using Equation 21. Here, the switchover time is equal to the time taken by the device to come out of reverse current blocking state (tSWRCB). SWRCB LOAD IN1 IN2 FWDTHOUT min OUT t V , $V V min V , V V V C u (21) While switching from a lower supply rail to higher supply rail, the minimum bus voltage can be calculated using Equation 22. Here, the switchover time (t SW) is the time taken by the device to turn on fully and start delivering TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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current to the load, which is equal to the device turn-on time (tON), which in turn includes the turn-on delay (tD,ON) and rise time (tR) determined by the dVdt capacitor (CdVdt) and bus voltage. SW LOAD IN1 IN2OUT min OUT t V , $V V min V , V C u (22) All the preceding configurations provide a priority power MUXing solution with active current limit protection response. In case circuit breaker response is prefered, it is possible to implement a solution using TPS259474x devices as shown in Figure 9-15 below. Here, the EN/UVLO signal of the primary path device is used to control the OVLO of the auxiliary path device. This ensures that auxiliary path device is turned on only when the primary supply falls below a user-defined undervoltage (UVLO) threshold. In this configuration, supply overvoltage protection is not available on both channels. The PG pins of the devices can be used as a digital indication to identify which of the 2 supplies is active and delivering power to the load. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: TPS25947
Figure 9-15. Priority power MUXing with 2 x TPS259474x While switching from one supply rail to the other, the minimum bus voltage can be calculated using Equation 23. Here, the maximum switchover time (tSW) is the time taken by the device to turn on and start delivering power to the load, which is equal to the device turn-on time (t ON), which in turn includes the turn-on delay (t D,ON) and rise time (tR) determined by the dVdt capacitor (CdVdt) and bus voltage. SW LOAD IN1 IN2OUT min OUT t V , $V V min V , V C u (23) TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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- The TPS259472x (OVC variants) are not recommended for use in power MUXing or ORing applications. While the device is in clamping state, if the output is forced to a higher voltage by the other channel, the device can get damaged. 2. Power MUXing can be done either between two similar rails (such as 12-V Primary & 12-V Aux, 3.3-V Primary & 3.3-V Aux) or between dissimilar rails (such as 12-V Primary & 5-V Aux or or vice versa). 3. For power MUXing cases with skewed voltage combinations, care must be taken to design circuit components on PGTH/EN/OVLO pins for the lower voltage channel devices such that the Absolute maximum ratings on those pins are not exceeded when higher voltage is present on the other channel. Also, the dVdt pin capacitor rating should be chosen based on the highest of the 2 supplies. Refer to Recommended Operating Conditions table for more details.
9.6 USB PD Port Protection
End equipments like PC, Notebooks, Docking Stations, Monitors etc.. have USB PD ports which can be configured as DFP (Source), UFP (Sink) or DRP (Source+Sink). TPS259470x can be used independently or in conjunction with LM73100 to handle the power path protection requirements of USB PD ports as shown in Figure 9-16 below. TPS259470x provides Overcurrent & Short-Circuit protection in the source path, while blocking any reverse current from the port to the internal source power rail. The fast recovery (t SWRCB) from reverse current blocking ensures minimum supply droop during Fast Role Swap (FRS) events. The PD controller can also use the OVLO pin as an active low enable signal to control the power path. Holding the OVLO pin high keeps the device in OFF state in sink mode and blocks current in both directions. Once the PD controller determines the need to start sourcing power, it can pull the OVLO pin low to trigger a fast recovery from OFF to ON state within t SWOV, meeting the FRS timing requirements. The LM73100 provides overvoltage protection on the sink path, while blocking reverse current from internal sink rail to the port. The linear ORing mechanism in TPS259470x & LM73100 ensures that there's no reverse current flowing from one power source to the other during fast or slow ramp of either supply. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: TPS25947
VBUS = 5 V to 20V OVLO PGTH PG CDVDT TPS259470L IN OUT EN/UVLO ILMdVdt GND RILM OVLO AUXOFF ITIMER CITIMER VOUT = 5 V to 20 V CDVDT VIN = 5 V to 20 V FLTFLT PD Controller Figure 9-16. USB PD Port Protection The waveform below shows the TPS259470x behavior when a 20-V source connected at the USB bus is suddenly disconnected. The TPS259470x is initially in reverse current blocking condition. As the bus voltage starts drooping, the TPS259470x exits the condition and performs a fast charge to restore the bus voltage above vSafe5V(min) within tSWRCB, thereby meeting the USB FRS (Fast Role Swap) requirements. TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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VIN = 5 V, COUT = 10 μF, ROUT = 8 Ω, VOUT = 20 V initially and then disconnected Figure 9-17. TPS259470x 5-V Source Path - USB Fast Role Swap Response
9.7 Parallel Operation
Figure 9-18 below. In this configuration, the first device turns on initially to provide the inrush current limiting. The second device is held in an OFF state by driving its EN/UVLO pin low using the AUXOFF/PG signal of the first device. Once the inrush sequence is complete, the first device asserts its AUXOFF/PG pin high and turns on the second device. The second device asserts its AUXOFF/PG signal to indicate when it has turned on fully, thereby indicating to the system that the parallel combination is ready to deliver the full steady state current. Once in steady state, both devices share current nearly equally. There could be a slight skew in the currents depending on the part-to-part variation in the RON as well as the PCB trace resistance mismatch. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: TPS25947
ILMdVdt GNDVIN = 2.7 to 23 V VOUT COUT OVLO AUXOFF ITIMER VLOGIC TPS259470x IN OUT EN/UVLO ILMdVdt GND OVLO AUXOFF ITIMER To downstream enable FLT FLT Figure 9-18. Two Devices Connected in Parallel for Higher Steady State Current Capability The waveforms below illustrate the behavior of the parallel configuration during start-up as well as during steady state. TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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9.8 Application Limitations
This section highlights some limitations in the application which were identified during bench evaluation of the existing PTPS259472L variant silicon on the evaluation module (EVM). A design fix will be included in the final release of the IC. Note This is not applicable to the other variants in the TPS25947xx family of devices. Device behavior during output hard short-circuit During a output hot-short event, the device will perform a fast-trip and protect the system and itself. After a fast-trip, the device is expected to attempt one retry in a current limited manner for fast recovery. However, if the current through the device exceeds 30 A before the fast-trip, the device may undergo a reset and will restart in a dVdt limited manner instead. This is most likely to happen at higher supply voltages and very severe shorts where the current can build up very quickly to high levels before the device can respond. This effect is more pronounced if the device is carrying no or very low load current (< ~1 A) before the short-circuit event. System Impact: For single channel eFuse use cases, there’s little/no impact on the protection response and overall functionality. After restarting into short, the device will enter current limit followed by thermal shutdown eventually. Workaround: 1. At lower supply voltages and/or in practical system conditions, multiple factors (the nature/location of the short, higher power path inductance, limtied power supply capacity, higher output capacitor) could prevent the current through the power switch from building up to very high levels and prevent this scenario. 2. This effect is also less pronounced if there’s a steady state load current of ~1 A or higher through the device at all times when it’s enabled. TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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10 Power Supply Recommendations
The TPS25947xx devices are designed for a supply voltage range of 2.7 V ≤ V IN ≤ 23 V. An input ceramic bypass capacitor higher than 0.1 μF is recommended if the input supply is located more than a few inches from the device. The power supply must be rated higher than the set current limit to avoid voltage droops during overcurrent and short-circuit conditions. The lowest negative voltage the device can handle at the input is limited to –15 V or V OUT – 21 V, whichever is higher. Any low voltage signals (e.g. EN/UVLO, OVLO, PGTH) derived from the input supply must have a sufficiently large pull-up resistor to limit the current through those pins to < 10 μA during reverse polarity conditions. Please refer to Absolute Maximum Ratings table for more details.
10.1 Transient Protection
In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients include:
- Minimize lead length and inductance into and out of the device.
- Use a large PCB GND plane.
- Connect a Schottky diode from the OUT pin ground to absorb negative spikes.
- Connect a low ESR capacitor larger than 1 μF at the OUT pin very close to the device.
- Use a low-value ceramic capacitor C IN = 1 μF to absorb the energy and dampen the transients. The capacitor voltage rating should be atleast twice the input supply voltage to be able to withstand the positive voltage excursion during inductive ringing. The approximate value of input capacitance can be estimated with Equation 24: VSPIKE(Absolute) = VIN + ILOAD x ¨LIN CIN (24) where – V IN is the nominal supply voltage. – • I LOAD is the load current. – L IN equals the effective inductance seen looking into the source. – C IN is the capacitance present at the input.
- Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude of the transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which can couple to the internal control circuits and cause unexpected behavior. Note If there's a likelihood of input reverse polarity in the system, it's recommended to use a bi- directional TVS, or a reverse blocking diode in series with the TVS.
- For applications such as USB-C ports where a powered cable can be plugged to the output of the device, there could be excess voltage stress from OUT to IN which exceeds the absolute maximum rating of the device. It's recommended to add a TVS diode from OUT to IN to clamp the voltage to a safe level. The circuit implementation with optional protection components is shown in Figure 10-1. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: TPS25947
VIN = 2.7 to 23 V RILM VOUT COUT OVLO AUXOFF FLT ITIMER CDVDTCITIMER CIND1 D3 D4 Figure 10-1. Circuit Implementation with Optional Protection Components
10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in results:
- Source bypassing
- Input leads
- Circuit layout
- Component selection
- Output shorting method
- Relative location of the short
- Instrumentation The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like those in this data sheet because every setup is different. TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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11 Layout
11.1 Layout Guidelines
- For all applications, a ceramic decoupling capacitor of 0.1 μF or greater is recommended between the IN terminal and GND terminal.
- The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the IC.
- High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current.
- The GND terminal must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. It's recommended to have a separate ground plane island for the eFuse. This plane doesn't carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane should be connected to the system power ground plane using a star connection.
- The IN and OUT pins are used for heat dissipation. Connect to as much copper area on top and bottom PCB layers using as possible with thermal vias. The vias under the device also help to minimize the voltage gradient accross the IN and OUT pads and distribute current unformly through the device, which is essential to achieve the best on-resistance and current sense accuracy.
- Locate the following support components close to their connection pins: – R ILM – C dVdT – C ITIMER – Resistors for the EN/UVLO, OVLO/OVCSEL and PGTH pins
- Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for the RILM, CITIMER and CdVdt components to the device must be as short as possible to reduce parasitic effects on the current limit , overcurrent blanking interval and soft start timing. It's recommended to keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation. These traces must not have any coupling to switching signals on the board.
- Since the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals.
- Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, a protection Schottky diode is recommended to address negative transients due to switching of inductive loads. It's also recommended to add a ceramic decoupling capacitor of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode/bypass-capacitor connection, the OUT pin and the GND terminal of the IC. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: TPS25947
11.2 Layout Example
Figure 11-1. Layout Example - Single TPS259474x with PGTH Referred to OUT TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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Figure 11-2. Layout Example - 2 x TPS259470x in PowerMUX Configuration www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: TPS25947
12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
- TPS25947EVM eFuse Evaluation Board
- TPS25947xx Design Calculator
- Application brief - eFuses for USB Type-C protection
- Application brief - eFuses in smart e-meters
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions. TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 www.ti.com
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TPS25947 SLVSFC9A – OCTOBER 2020 – REVISED MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: TPS25947
www.ti.com 30-Apr-2021 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTPS259470LRPWR ACTIVE VQFN-HR RPW 10 3000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 PTPS259472ARPWR ACTIVE VQFN-HR RPW 10 3000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 PTPS259472LRPWR ACTIVE VQFN-HR RPW 10 3000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 PTPS259474ARPWR ACTIVE VQFN-HR RPW 10 3000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 PTPS259474LRPWR ACTIVE VQFN-HR RPW 10 3000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 TPS259470ARPWR ACTIVE VQFN-HR RPW 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2A9H TPS259470LRPWR ACTIVE VQFN-HR RPW 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2A8H TPS259472ARPWR ACTIVE VQFN-HR RPW 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2ABH TPS259472LRPWR PREVIEW VQFN-HR RPW 10 3000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 TPS259474ARPWR ACTIVE VQFN-HR RPW 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2ADH TPS259474LRPWR ACTIVE VQFN-HR RPW 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2ACH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
www.ti.com 30-Apr-2021 Addendum-Page 2 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPS259470ARPWR VQFN- HR TPS259470LRPWR VQFN- HR TPS259472ARPWR VQFN- HR TPS259474ARPWR VQFN- HR TPS259474LRPWR VQFN- HR PACKAGE MATERIALS INFORMATION www.ti.com 3-Apr-2021 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS259470ARPWR VQFN-HR RPW 10 3000 210.0 185.0 35.0 TPS259470LRPWR VQFN-HR RPW 10 3000 210.0 185.0 35.0 TPS259472ARPWR VQFN-HR RPW 10 3000 210.0 185.0 35.0 TPS259474ARPWR VQFN-HR RPW 10 3000 210.0 185.0 35.0 TPS259474LRPWR VQFN-HR RPW 10 3000 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 3-Apr-2021 Pack Materials-Page 2
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PACKAGE OUTLINE 4225183/A 08/2019 www.ti.com VQFN-HR - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD RPW0010A A 0.08 C B PKG C SEATING PLANE PIN 1 IDENTIFICATION 2.1 1.9 2.1 1.9 (0.1) TYP
0.1 C A B
0.05 C 0.05 C 0.05 C 0.05 C
1 MAX
0.05 0.00 PIN 1 ID (OPTIONAL) PKG 2X 0.254X 0.475 2X 1.45 SQ (0.15) TYP 2X 2.1 1.9 4X 0.35 0.25 4X 0.3 0.2 2X 0.35 0.25 4X 0.3 0.2 8X 0.5 0.3 4X 0.475 2X 0.45 5 6
NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 4. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4225183/A 08/2019 www.ti.com VQFN-HR - 1 mm max heightRPW0010A PLASTIC QUAD FLATPACK - NO LEAD LAND PATTERN EXAMPLE SCALE: 30X PKG
0.05 MAX
(PREFERRED) EXPOSED METAL
0.05 MIN
(2.4) (1.75) 4X (0.475) (0.225) 8X (0.6) 4X (0.25)2X (0.3) 4X (0.3) 4X (0.25) 2X (0.25) (1.45) 4X (0.475) (0.65) (1.8) PKG 5 6 (R0.05) TYP
NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225183/A 08/2019 www.ti.com VQFN-HR - 1 mm max heightRPW0010A PLASTIC QUAD FLATPACK - NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.100 mm THICK STENCIL PADS 1, 4,7 & 10: 93%; PADS 5 & 6: 82% SCALE: 30X PKG (1.06) (1.75) 4X (0.4625) 4X (0.225) 8X (0.6) 4X (0.275) 4X (0.25) 2X (0.25) (1.425) 4X (0.4625) (0.65) (1.8) PKG 5 6 (R0.05) TYP (0.63) METAL TYP
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