PTPS25751SRSMR

TPS25751 TI | Alldatasheet

Document overview

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Technical content

TPS25751 USB Type-C® and USB PD Controller with Integrated Power Switches Optimized for Power Applications

1 Features

• PD Controller is certified by the USB-IF for PD3.1 – PD3.1 silicon is required for certification of new USB PD designs – TPS25751 TID#: 9977 – Article on PD2.0 vs. PD3.0
• Optimized for USB Type-C PD power applications – Integrated I2C control for TI battery chargers
• BQ25756
• BQ25792 – Web-based GUI and pre-configured firmware – Optimized for power consumer only (sink) (UFP) applications – Optimized for power provider/power consumer (DRP) applications – For a more extensive selection guide and getting started information, please refer to www.ti.com/usb-c and E2E guide
• Programmable Power Supply (PPS) – Supports PPS source & sink – Standalone PPS source control TI battery chargers – Programmable interface for PPS sink
• Liquid Detection – Measures directly at the Type-C connector – Integrated error handling and protection
• Integrated fully managed power paths – Integrated 5-V, 3-A, 36-mΩ sourcing switch (TPS25751S and TPS25751D) – Integrated 20-V, 5-A, 16-mΩ bi-directional load switch (TPS25751D only)
• Integrated robust power path protection – Integrated reverse current protection, undervoltage protection, overvoltage protection, and slew rate control the high-voltage bi- directional power path – Integrated undervoltage and overvoltage protection and current limiting for inrush current protection for the 5-V/3-A source power path – 26-V tolerant CC pins for robust protection when connected to non-compliant devices
• USB Type-C® Power Delivery (PD) controller – 10 configurable GPIOs – BC1.2 advertisement/detection support – 3.3-V LDO output for dead battery support – Power supply from 3.3 V or VBUS source – 1 I2C controller port – 1 I2C target port

2 Applications

• Power tools, power banks, retail and payment
• Wireless speakers, Cordless vacuum cleaner
• personal electronics and industrial applications
• Home health care and Personal care & fitness

3 Description

The TPS25751 is a highly integrated stand-alone USB Type-C and Power Delivery (PD) controller optimized for applications supporting USB-C PD Power. The TPS25751 integrates fully managed power paths with robust protection for a complete USB-C PD solution. The TPS25751 also integrates control for external battery charger ICs for added ease of use and reduced time to market. The intuitive web based GUI asks the user a few simple questions on the applications needs using clear block diagrams and simple multiple-choice questions. As a result, the GUI creates the configuration image for the user’s application, reducing much of the complexity associated with competitive USB PD solutions.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TPS25751D QFN (REF) 4.0 mm x 6.0 mm TPS25751S QFN (RSM) 4.0 mm x 4.0 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. TPS25751D CC VCONN VBUS GND CC1/2 5-20 V 2Type-C Rp/Rd & state machine, VCONN switches, USB PD policy engine, protocol and physical layer I2C Controller BQ Battery Charger

10 GPIO

3.3V 3.3V I2C Target Optional Embedded Controller TPS25751S CC VCONN VBUS GND CC1/2 5-20 V 2Type-C Rp/Rd & state machine, VCONN switches, USB PD policy engine, protocol and physical layer I2C Controller BQ Battery Charger LDO3.3V 3.3V I2C Target Optional Embedded Controller PP_EXT Control ADVANCE INFORMATION TPS25751 SLVSH93 – OCTOBER 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

6.9 PPHV Power Switch Characteristics - TPS25751D..12

6.10 PP_EXT Power Switch Characteristics -

10.3 Receiving Notification of Documentation Updates..74

12 Mechanical, Packaging, and Orderable

SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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4 Device Comparison Table

DEVICE NUMBER 5-V SOURCE LOAD SWITCH INTEGRATED HIGH VOLTAGE BI-DIRECTIONAL LOAD SWITCH (PPHV) HIGH VOLTAGE GATE DRIVER FOR BI-DIRECTIONAL EXTERNAL PATH (PP_EXT) TPS25751D Yes Yes No TPS25751S Yes No Yes www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS25751

5 Pin Configuration and Functions

8 9 10 11 12 14 16 1513 17 18 2729 2830313235 34 333637 ADCIN1 PPHV GPIO2 Thermal Pad (GND) Thermal Pad (DRAIN) 7 19 2638 LDO_3V3 ADCIN2 LDO_1V5 GPIO0 GPIO1 I2Ct_SDA I2Ct_SCL I2Ct_IRQ GND GPIO11 GND DRAIN GND I2Cc_SDA I2Cc_SCL I2Cc_IRQ GPIO3 PPHV PPHV VBUS_IN VBUS_IN VBUS_IN GPIO4/USB_P/ LD1 GPIO5/USB_N/ LD2 CC1 CC2 DRAIN GND VBUS VBUS PP5V PP5V GPIO7 GPIO6 VIN_3V3 Not to Scale Figure 5-1. Top View of the TPS25751D 38-pin QFN Package VIN_3V3 GPIO6 GPIO7 PP5V PP5V VBUS VBUS CC2 I2Ct_SCL I2Ct_IRQ GND GND GPIO11 GND I2Cc_SDA I2Cc_SCL LDO_3V3 ADCIN1 ADCIN2 LDO_1V5 GPIO0 GPIO1 GPIO2 I2Ct_SDA CC1 GPIO5/USB_N/LD2 GPIO4/USB_P/LD1 GATE_VBUS GATE_VSYS VSYS GPIO3 I2Cc_IRQ Thermal Pad (GND) Not to Scale Figure 5-2. Top View of the TPS25751S 32-pin QFN Package TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Table 5-1. TPS25751D Pin Functions PIN TYPE(1) RESET DESCRIPTION NAME NO. ADCIN1 2 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. ADCIN2 3 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. CC1 28 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). CC2 29 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). GND 11, 12, 14, 31 — — Ground. Connect to ground plane. GPIO0 5 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO1 6 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO2 7 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO3 19 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO4/USB_P/LD1 26 GPIO Hi-Z General purpose digital I/O. Tie to ground when unused. Pin can be connected to D+ for BC1.2 support. Pin can be connected for liquid detection on the Type-C connector. Tie to ground when pin is unused. GPIO5/USB_N/LD2 27 GPIO Hi-Z General purpose digital I/O. Tie to ground when unused. Pin can be connected to D- for BC1.2 support. Pin can be connected for liquid detection on the Type-C connector. Tie to ground when pin is unused. GPIO6 37 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO7 36 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. I2Ct_SCL 9 I Hi-Z I2C target serial clock input. Tie to pullup voltage through a resistor. May be grounded if unused. I2Ct_SDA 8 I/O Hi-Z I2C target serial data. Open-drain input/output. Tie to pullup voltage through a resistor. May be grounded if unused. I2Ct_IRQ 10 O Hi-Z I2C target interrupt. Active low. Connect to external voltage through a pull-up resistor. Pin can be re-configured to GPIO10. Tie to ground if unused. I2Cc_SCL 17 O Hi-Z I2C controller serial clock. Open-drain output. Tie to pullup voltage through a resistor. Can be grounded if unused. GPIO11 13 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. I2Cc_SDA 16 I/O Hi-Z I2C controller serial data. Open-drain input/output. Tie to pullup voltage through a resistor. Can be grounded if unused. I2Cc_IRQ 18 I Hi-Z I2C controller interrupt. Active low. Connect to external voltage through a pull-up resistor. Do NOT tie to GND when unused. Pin can be re-configured to GPIO12. LDO_1V5 4 O — Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. Pin cannot source current to external circuits. LDO_3V3 1 O — Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with capacitance CLDO_3V3 to GND. DRAIN 15, 30 N/A — Connects to drain of internal FET. PP5V 34, 35 I — 5-V System Supply to VBUS, supply for CCy pins as VCONN. PPHV 20, 21, 22 I/O High-voltage sinking node in the system. VBUS_IN 23, 24, 25 I/O 5-V to 20-V input. VBUS 32, 33 O 5-V output from PP5V input to LDO. Bypass with capacitance CVBUS to GND. VIN_3V3 38 I — Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND. (1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS25751

Table 5-2. TPS25751S Pin Functions PIN TYPE(1) RESET DESCRIPTION NAME NO. ADCIN1 2 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. ADCIN2 3 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. CC1 24 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). CC2 25 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). GATE_VSYS 20 O Hi-Z Connect to the N-ch MOSFET that has source tied to VSYS. GATE_VBUS 21 O Hi-Z Connect to the N-ch MOSFET that has source tied to VBUS. GND 11, 12, 14 — — Ground. Connect to ground plane. GPIO0 5 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO1 6 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO2 7 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO3 18 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO4/USB_P/LD1 22 GPIO Hi-Z General purpose digital I/O. Tie to ground when unused. Pin can be connected to D+ for BC1.2 support. Pin can be connected for liquid detection on the Type-C connector. Tie to ground when pin is unused. GPIO5/USB_N/LD2 23 GPIO Hi-Z General purpose digital I/O. Tie to ground when unused. Pin can be connected to D- for BC1.2 support. Pin can be connected for liquid detection on the Type-C connector. Tie to ground when pin is unused. GPIO6 31 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO7 30 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. I2Ct_SCL 9 I Hi-Z I2C target serial clock input. Tie to pullup voltage through a resistor. May be grounded if unused. I2Ct_SDA 8 I/O Hi-Z I2C target serial data. Open-drain input/output. Tie to pullup voltage through a resistor. May be grounded if unused. I2Ct_IRQ 10 O Hi-Z I2C target interrupt. Active low. Connect to external voltage through a pull-up resistor. Pin can be re-configured to GPIO10. Tie to ground when unused. I2Cc_SCL 16 O Hi-Z I2C controller serial clock. Open-drain output. Tie to pullup voltage through a resistor when used or unused. GPIO11 13 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. I2Cc_SDA 15 I/O Hi-Z I2C controller serial data. Open-drain input/output. Tie to pullup voltage through a resistor when used or unused. I2Cc_IRQ 17 I Hi-Z I2C controller interrupt. Active low. Connect to external voltage through a pull-up resistor. Do NOT tie to GND when unused. Pin can be re-configured to GPIO12. LDO_1V5 4 O — Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. Pin cannot source current to external circuits. LDO_3V3 1 O — Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with capacitance CLDO_3V3 to GND. PP5V 28, 29 I — 5-V System Supply to VBUS, supply for CCy pins as VCONN. VSYS 19 I — High-voltage sinking node in the system. Pin is used to implement reverse-current-protection (RCP) for the external sinking paths controlled by GATE_VSYS. VBUS 26, 27 I/O 5-V to 20-V input. Bypass with capacitance CVBUS to GND. VIN_3V3 32 I — Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND. (1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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6 Specifications

6.1 Absolute Maximum Ratings

6.1.1 TPS25751D and TPS25751S - Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Input voltage range (2) PP5V –0.3 6 VVIN_3V3 –0.3 4 ADCIN1, ADCIN2 –0.3 4 VBUS_IN, VBUS (4) –0.3 28 V CC1, CC2 (4) –0.5 26 GPIOx –0.3 6.0 I2Cc_SDA, I2Cc_SCL, I2Cc_IRQ, I2Ct_IRQ,I2Ct_SCL, I2Ct_SDA –0.3 4 Output voltage range (2) LDO_1V5 (3) –0.3 2 V LDO_3V3 (3) –0.3 4 Source current Source or sink current VBUS internally limited A Positive source current on CC1, CC2 1 Positive sink current on CC1, CC2 while VCONN switch is enabled 1 Positive sink current for I2Cc_SDA, I2Cc_SCL, I2Cc_IRQ, I2Ct_IRQ,I2Ct_SCL, I2Ct_SDA internally limited Positive source current for LDO_3V3, LDO_1V5 internally limited Source current GPIOx 0.005 A TJ Operating junction temperature –40 175 °C TSTG Storage temperature –55 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board. (3) Do not apply voltage to these pins. (4) A TVS with a break down voltage falling between the Recommended max and the Abs max value is recommended such as TVS2200.

6.1.2 TPS25751D - Absolute Maximum Ratings

(1) PPHV –0.3 28 V VPPHV_VBUS_IN Source-to-source voltage 28 V Sink current Continuous current to/from VBUS_IN to PPHV 7 A Pulsed current to/from VBUS_IN to PPHV (2) TJ_PPHV Operating junction temperature PP_HV switch –40 175 °C (1) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board. (2) Pulse duration ≤ 100 µs and duty-cycle ≤ 1%.

6.1.3 TPS25751S - Absolute Maximum Ratings

1 GATE_VBUS,

GATE_VSYS 2 –0.3 40 V www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS25751

6.1.3 TPS25751S - Absolute Maximum Ratings (continued)

VGATE_VBUS - VVBUS, VGATE_SYS - VVSYS –0.5 12 V (1) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board. (2) Do not apply voltage to these pins.

6.2 ESD Ratings

PARAMETER TEST CONDITIONS VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ ESDA/JEDEC JS-001, all pins(1) ±1000 V Charged-device model (CDM), per ANSI/ ESDA/JEDEC JS-002, all pins(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3.1 TPS25751D - Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VI Input voltage range (1) VIN_3V3 3.0 3.6 V PP5V 4.9 5.5 ADCIN1, ADCIN2,VBUS_IN, VBUS 4 22 PPHV 0 22 VIO I/O voltage range (1) I2Cx_SDA, I2Cx_SCL, I2Cx_IRQ, ADCIN1, ADCIN2 0 3.6 VGPIOx 0 5.5 CC1, CC2 0 5.5 IO Output current (from PP5V) VBUS 3 A CC1, CC2 315 mA IO Output current (from LDO_3V3) GPIOx 1 mA TJ Operating junction temperature –40 125 °C (1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.

6.3.2 TPS25751S - Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VI Input voltage range (1) VIN_3V3 3.0 3.6 V PP5V 4.9 5.5 VBUS 4 22 VSYS 0 22 VIO I/O voltage range (1) I2Cx_SDA, I2Cx_SCL, I2Cx_IRQ, ADCIN1, ADCIN2 0 3.6 VGPIOx 0 5.5 CC1, CC2 0 5.5 IO Output current (from PP5V) VBUS 3 A CC1, CC2 315 mA IO Output current (from LDO_3V3) GPIOx 1 mA IO Output current (from VBUS LDO) sum of current from LDO_3V3 and GPIOx 5 mA TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT TJ Operating junction temperature –40 125 °C (1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.

6.4 Recommended Capacitance

over operating free-air temperature range (unless otherwise noted) PARAMETER(1) VOLTAGE RATING MIN NOM MAX UNIT CVIN_3V3 Capacitance on VIN_3V3 6.3 V 5 10 µF CLDO_3V3 Capacitance on LDO_3V3 6.3 V 5 10 25 µF CLDO_1V5 Capacitance on LDO_1V5 4 V 4.5 12 µF CVBUS Capacitance on VBUS (4) 25 V 1 4.7 10 µF CPP5V Capacitance on PP5V 10 V 120 (2) µF CVSYS (TPS25751S) Capacitance on VSYS Sink from VBUS(5) 25 V 47 100 µF CPPHV (TPS25751D) Capacitance on PPHV Sink from VBUS(5) 25 V 47 100 µF CCCy Capacitance on CCy pins(3) 6.3 V 200 400 480 pF (1) Capacitance values do not include any derating factors. For example, if 5.0 µF is required and the external capacitor value reduces by 50% at the required operating voltage, then the required external capacitor value is 10 µF. (2) USB PD requirement (cSrcBulkShared). Keep at least 10 µF tied directly to PP5V. (3) Capacitance includes all external capacitance to the Type-C receptacle. (4) The device can be configured to quickly disable the sinking power path upon certain events. When such a configuration is used, a capacitance on the higher side of the range is recommended. (5) USB PD specification for cSnkBulkPd (100µF) is the maximum bulk capacitance allowed on a VBUS sink after a PD contract is in place. The capacitance is sufficient for all power conversion devices deriving power from the PD Controller sink path. For systems requiring greater than 100uF, VBUS surge current limiting is implemented as described in the USB3.2 specification. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS25751

6.5 Thermal Information

6.5.1 TPS25751D - Thermal Information

THERMAL METRIC(1) TPS25751D UNITQFN

38 PINS

RθJA Junction-to-ambient thermal resistance (sinking through PP_HV) 57.4 °C/W Junction-to-ambient thermal resistance (sourcing through PP_5V) 46.5 °C/W RθJC (top) Junction-to-case (top) thermal resistance (sinking through PP_HV) 30.5 °C/W Junction-to-case (top) thermal resistance (sourcing through PP_5V) 20.3 °C/W RθJB Junction-to-board thermal resistance (sinking through PP_HV) 21.1 °C/W Junction-to-board thermal resistance (sourcing through PP_5V) 11.1 °C/W ψJT Junction-to-top characterization parameter (sinking through PP_HV) 18.2 °C/W Junction-to-top characterization parameter (sourcing through PP_5V) 1.0 °C/W ψJB Junction-to-board characterization parameter (sinking through PP_HV) 21.1 °C/W Junction-to-board characterization parameter (sourcing through PP_5V) 11.1 °C/W RθJC (bot_GND) Junction-to-case (bottom GND pad) thermal resistance 1.8 °C/W RθJC (bot_DRAIN) Junction-to-case (bottom DRAIN pad) thermal resistance 4.6 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5.2 TPS25751S - Thermal Information

THERMAL METRIC(1) TPS25751S UNITQFN

32 PINS

RθJA Junction-to-ambient thermal resistance 30.5 °C/W RθJC (top) Junction-to-case (top) thermal resistance 24.5 °C/W RθJC Junction-to-board (bottom) thermal resistance 2 °C/W RθJB Junction-to-board thermal resistance 9.8 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 9.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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6.6 Power Supply Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN_3V3, VBUS VVBUS_UVLO VBUS UVLO threshold rising 3.6 3.9 Vfalling 3.5 3.8 hysteresis 0.1 VVIN3V3_UVLO Voltage required on VIN_3V3 for power on rising, VVBUS = 0 2.56 2.66 2.76 Vfalling, VVBUS = 0 2.44 2.54 2.64 hysteresis 0.12 LDO_3V3, LDO_1V5 VLDO_3V3 Voltage on LDO_3V3 VVIN_3V3 = 0 V, 10 µA ≤ ILOAD ≤ 18 mA, VBUS ≥ 3.9 V 3.0 3.4 3.6 V RLDO_3V3 Rdson of VIN_3V3 to LDO_3V3 ILDO_3V3 = 50 mA 1.4 Ω VLDO_1V5 Voltage on LDO_1V5 up to maximum internal loading condition 1.49 1.5 1.65 V

6.7 Power Consumption

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V, no GPIO loading PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVIN_3V3,ActSrc Current into VIN_3V3 Active Source mode: VVBUS = 5.0 V, VVIN_3V3 = 3.3 V 3 mA IVIN_3V3,ActSnk Current into VIN_3V3 Active Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V 3 6 mA IVIN_3V3,IdlSrc Current into VIN_3V3 Idle Source mode: VVBUS = 5.0 V, VVIN_3V3 = 3.3 V 1.0 mA IVIN_3V3,IdlSnk Current into VIN_3V3 Idle Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V 1.0 mA PMstbySnk Power drawn into PP5V and VIN_3V3 in Modern Standby Sink Mode CCm floating, VCCn = 0.4 V, VPP5V = 5 V, VVIN_3V3 = 3.3 V, VVBUS = 5.0 V, GATE_VBUS, GATE_VSYS disabled, and TJ = 25°C 4.1 mW PMstbySrc Power drawn into PP5V and VIN_3V3 in Modern Standby Source Mode CCm floating, CCn tied to GND through 5.1 kΩ, VPP5V = 5 V, VVIN_3V3 = 3.3 V, IVBUS = 0, TJ = 25°C 4.5 mW IPP5V,Sleep Current into PP5V Sleep mode: VPA_VBUS = 0 V, VVIN_3V3 = 3.3 V 2 µA IVIN_3V3,Sleep Current into VIN_3V3 Sleep mode: VVBUS = 0 V, VVIN_3V3 = 3.3 V 56 µA

6.8 PP_5V Power Switch Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RPP_5V Resistance from PP5V to VBUS ILOAD = 3 A, TJ = 25°C 36 38 mΩ RPP_5V Resistance from PP5V to VBUS ILOAD = 3 A,TJ = 125°C 36 53 mΩ IPP5V_REV VBUS to PP5V leakage current VPP5V = 0 V, VVBUS = 5.5 V, PP_5V disabled, TJ ≤ 85°C, measure IPP5V 5 µA IPP5V_FWD PP5V to VBUS leakage current VPP5V = 5.5 V, VVBUS = 0 V, PP_5V disabled, TJ ≤ 85°C, measure IVBUS 15 µA ILIM5V Current limit setting Configure to setting 0 1.15 1.36 A ILIM5V Current limit setting Configure to setting 1 1.61 1.90 A ILIM5V Current limit setting 2.3 2.70 A ILIM5V Current limit setting Configure to setting 3 3.04 3.58 A ILIM5V Current limit setting Configure to setting 4 3.22 3.78 A www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS25751

6.8 PP_5V Power Switch Characteristics (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVBUS PP5V to VBUS current sense accuracy 3.64 A ≥ IVBUS ≥ 1 A 3.05 3.5 3.75 A/V VPP_5V_RCP RCP clears and PP_5V starts turning on when VVBUS – VPP5V < VPP_5V_RCP. Measure VVBUS – VPP5V 10 20 mV tiOS_PP_5V Response time to VBUS short circuit VBUS to GND through 10 mΩ, CVBUS = 0 1.15 µs tPP_5V_ovp Response time to VVBUS > VOVP4RCP Enable PP_5V, IRpDef being drawn from PP5V, configure VOVP4RCP to setting 2, ramp VVBUS from 4V to 20 V at 100 V/ms, CPP5V = 2.5 µF, measure time from OVP detection until reverse current < 100 mA 4.5 µs tPP_5V_uvlo Response time to VPP5V < VPP5V_UVLO, PP_VBUS is deemed off when VVBUS < 0.8 V RL = 100 Ω, no external capacitance on VBUS 4 µs tPP_5V_rcp Response time to VPP5V < VVBUS + VPP_5V_RCP VPP5V = 5.5 V, IRpDef being drawn from PP5V, enable PP_5V, configure VOVP4RCP to setting 2, ramp VVBUS from 4 V to 21.5 V at 10 V/µs, measure VPP5V. CPP5V = 104 µF, CVBUS=10 µF, measure time from RCP detection until reverse current < 100 mA 0.7 µs tILIM Current clamping deglitch time 5.1 ms tON From enable signal to VBUS at 90% of final value RL = 100 Ω, VPP5V = 5 V, CL = 0 2.3 3.3 4.3 ms tOFF From disable signal to VBUS at 10% of final value RL = 100 Ω, VPP5V = 5 V, CL = 0 0.30 0.45 0.6 ms tRISE VBUS from 10% to 90% of final value RL = 100 Ω, VPP5V = 5 V, CL = 0 1.2 1.7 2.2 ms tFALL VBUS from 90% to 10% of initial value RL = 100 Ω, VPP5V = 5 V, CL = 0 0.06 0.1 0.14 ms

6.9 PPHV Power Switch Characteristics - TPS25751D

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRCP Comparator mode RCP threshold, VPPHV - VVBUS Setting 0, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 2 6 10 mV setting 1, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 4 8 12 mV Setting 2, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 6 10 14 mV Setting 3, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 8 12 16 mV TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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6.9 PPHV Power Switch Characteristics - TPS25751D (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SS Soft start slew rate for GATE_VSYS, setting 0

4 V ≤ VVBUS ≤ 22 V,

ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 0.35 0.41 0.47 V/ms Soft start slew rate for GATE_VSYS, setting 1 ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 0.67 0.81 0.95 Soft start slew rate for GATE_VSYS, setting 2 ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 1.33 1.7 2.0 Soft start slew rate for GATE_VSYS, setting 3 ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 2.8 3.3 3.80

6.10 PP_EXT Power Switch Characteristics - TPS25751S

Operating under these conditions unless otherwise noted: , 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRCP Comparator mode RCP threshold, VVSYS - VVBUS Setting 0, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 2 6 10 mV Setting 1, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 4 8 12 mV Setting 2, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 6 10 14 mV Setting 3, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 8 12 16 mV SS Soft start slew rate for GATE_VSYS, setting 0 ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 0.35 0.41 0.47 V/ms Soft start slew rate for GATE_VSYS, setting 1 ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 0.67 0.81 0.91 Soft start slew rate for GATE_VSYS, setting 2 ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 1.33 1.7 1.80 Soft start slew rate for GATE_VSYS, setting 3 ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 2.8 3.3 3.80 www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS25751

6.11 Power Path Supervisory

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOVP4RCP VBUS overvoltage protection for RCP programmable range OVP detected when VVBUS > VOVP4RCP 5.0 24 V VOVP4RCPH Hysteresis 1.75 2 2.25 % rOVP Ratio of OVP4RCP input used for OVP4VSYS comparator. rOVP × VOVP4VSYS = VOVP4RCP setting 0 1 V/V setting 1 0.95 V/V setting 2 0.90 V/V setting 3 0.875 V/V VOVP4VSYS VBUS overvoltage protection range for VSYS protection OVP detected when rOVP × VVBUS > VOVP4RCP 5 27.5 V VOVP4VSYS Hysteresis VBUS falling, % of VOVP4VSYS, rOVP setting 0 1.75 2 2.25 VBUS falling, % of VOVP4VSYS, rOVP setting 1 1.8 2.1 2.4 VBUS falling, % of VOVP4VSYS, rOVP setting 2 1.9 2.2 2.5 VBUS falling, % of VOVP4VSYS, rOVP setting 3 2 2.3 2.6 VPP5V_UVLO Voltage required on PP5V rising 3.9 4.1 4.3 Vfalling 3.8 4.0 4.2 hysteresis 0.1 IDSCH VBUS discharge current VVBUS = 22 V, measure IVBUS 4 15 mA

6.12 CC Cable Detection Parameters

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Type-C Source (Rp pullup) VOC_3.3 Unattached CCy open circuit voltage while Rp enabled, no load VLDO_3V3 > 2.302 V, RCC = 47 kΩ 1.85 V VOC_5 Attached CCy open circuit voltage while Rp enabled, no load VPP5V > 3.802 V, RCC = 47 kΩ 2.95 V IRev Unattached reverse current on CCy VCCy = 5.5 V, VCCx = 0 V, VLDO_3V3_UVLO < VLDO_3V3 < 3.6 V, VPP5V = 3.8 V, measure current into CCy µA VCCy = 5.5 V, VCCx = 0 V, VLDO_3V3_UVLO < VLDO_3V3 < 3.6 V, VPP5V = 0, TJ ≤ 85°C, measure current into CCy IRpDef Current source - USB Default 0 < VCCy < 1.0 V, measure ICCy 64 80 96 µA IRp1.5 Current source - 1.5 A 4.75 V < VPP5V < 5.5 V, 0 < VCCy <

1.5 V, measure ICCy

166 180 194 µA IRp3.0 Current source - 3.0 A 4.75 V < VPP5V < 5.5 V, 0 < VCCy <

2.45 V, measure ICCy

304 330 356 µA Type-C Sink (Rd pulldown) VSNK1 Open/Default detection threshold when Rd applied to CCy rising 0.2 0.24 V TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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6.12 CC Cable Detection Parameters (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VSNK1 Open/Default detection threshold when Rd applied to CCy falling 0.16 0.20 V Hysteresis 0.04 V VSNK2 Default/1.5-A detection threshold falling 0.62 0.68 V VSNK2 Default/1.5-A detection threshold rising 0.63 0.66 0.69 V Hysteresis 0.01 V VSNK3 1.5-A/3.0-A detection threshold when Rd applied to CCy falling 1.17 1.25 V VSNK3 1.5-A/3.0-A detection threshold when Rd applied to CCy rising 1.22 1.3 V Hysteresis 0.05 V RSNK Rd pulldown resistance 0.25 V ≤ VCCy ≤ 2.1 V, measure resistance on CCy 4.6 5.6 kΩ RVCONN_DIS VCONN discharge resistance 0V ≤ VCCy ≤ 5.5 V, measure resistance on CCy 4.0 6.12 kΩ VCLAMP Dead battery Rd clamp VVIN_3V3 = 0 V, 64 µA < ICCy < 96 µA 0.25 1.32 VVVIN_3V3 = 0 V, 166 µA < ICCy < 194 µA 0.65 1.32 VVIN_3V3 = 0 V, 304 µA < ICCy < 356 µA 1.20 2.18 ROpen Resistance from CCy to GND when configured as open VVBUS = 0, VVIN_3V3 = 3.3 V, VCCy = 5 V, measure resistance on CCy 500 kΩ VVBUS = 5 V, VVIN_3V3 = 0, VCCy =

5 V, measure resistance on CCy 500 kΩ

6.13 CC VCONN Parameters

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RPP_CABLE Rdson of the VCONN path VPP5V = 5 V, IL = 250 mA, measure resistance from PP5V to CCy 1.2 Ω ILIMVC Short circuit current limit Setting 0, VPP5V = 5 V, RL=10 mΩ, measure ICCy 350 410 470 mA ILIMVC Short circuit current limit Setting 1, VPP5V = 5 V, RL=10 mΩ, measure ICCy 540 600 660 mA ICC2PP5V Reverse leakage current through VCONN FET VCONN disabled, TJ ≤ 85°C, VCCy = 5.5 V, VPP5V = 0 V, VVBUS = 5 V, LDO forced to draw from VBUS, measure ICCy 10 µA VVC_OVP Overvoltage protection threshold for PP_CABLE VPP5V rising 5.6 5.9 6.2 V VVC_RCP Reverse current protection threshold for PP_CABLE, sourcing VCONN through CCx VPP5V ≥ 4.9 V, VCCy = VPP5V, VCCx rising 60 200 340 mV VPP5V ≥ 4.9 V, VCCy ≤ 4 V, VCCx rising 210 340 470 mV tVCILIM Current clamp deglitch time 1.3 ms tPP_CABLE_FSD Time to disable PP_CABLE after VPP5V > VVC_OVP or VCCx - VPP5V > VVC_RCP CL = 0 0.5 µs www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS25751

6.13 CC VCONN Parameters (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPP_CABLE_off From disable signal to CCy at 10% of final value IL = 250 mA, VPP5V = 5 V, CL = 0 100 200 300 µs tiOS_PP_CABLE Response time to short circuit VPP5V = 5 V, for short circuit RL = 10 mΩ 2 µs

6.14 CC PHY Parameters

Operating under these conditions unless otherwise noted: and ( 3.0 V ≤ VVIN_3V3 ≤ 3.6 V or VVBUS ≥ 3.9 V ) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Transmitter VTXHI Transmit high voltage on CCy Standard External load 1.05 1.125 1.2 V VTXLO Transmit low voltage on CCy Standard External load –75 75 mV ZDRIVER Transmit output impedance while driving the CC line using CCy measured at 750 kHz 33 54 75 Ω tRise Rise time. 10 % to 90 % amplitude points on CCy, minimum is under an unloaded condition. Maximum set by TX mask CCCy = 520 pF 300 ns tFall Fall time. 90 % to 10 % amplitude points on CCy, minimum is under an unloaded condition. Maximum set by TX mask CCCy = 520 pF 300 ns VPHY_OVP OVP detection threshold for USB PD PHY 0 ≤ VVIN_3V3 ≤ 3.6 V, 0 ≤ VPP5V ≤ 5.5 V, VVBUS ≥ 4 V. Initially VCC1 ≤ 5.5 V and VCC2 ≤ 5.5 V, then VCCx rises 5.5 8.5 V Receiver ZBMCRX Receiver input impedance on CCy Does not include pullup or pulldown resistance from cable detect. Transmitter is Hi-Z 1 MΩ CCC Receiver capacitance on CCy (1) Capacitance looking into the CC pin when in receiver mode 120 pF VRX_SNK_R Rising threshold on CCy for receiver comparator Sink mode (rising) 499 525 551 mV VRX_SRC_R Rising threshold on CCy for receiver comparator Source mode (rising) 784 825 866 mV VRX_SNK_F Falling threshold on CCy for receiver comparator Sink mode (falling) 230 250 270 mV VRX_SRC_F Falling threshold on CCy for receiver comparator Source mode (falling) 523 550 578 mV (1) CCC includes only the internal capacitance on a CCy pin when the pin is configured to be receiving BMC data. External capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications (cReceiver). Therefore, TI recommends adding CCCy externally. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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6.15 Thermal Shutdown Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TSD_MAIN Temperature shutdown threshold Temperature rising 145 160 175 °C Hysteresis 15 °C TSD_PP5V Temperature controlled shutdown threshold. The power paths for each port sourcing from PP5V and PP_CABLE power paths have local sensors that disables them when the temperature is exceeded Temperature rising 135 150 165 °C Hysteresis 10 °C

6.16 ADC Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LSB Least significant bit 3.6-V max scaling, voltage divider of 3 14 mV 25.2-V max scaling, voltage divider of 21 98 mV 4.07-A max scaling 16.5 mA GAIN_ERR Gain error 0.05 V ≤ VADCINx ≤ 3.6 V, VADCINx ≤ VLDO_3V3 –2.7 2.7 0.05 V ≤ VGPIOx ≤ 3.6 V, VGPIOx ≤ VLDO_3V3 2.7 V ≤ VLDO_3V3 ≤ 3.6 V –2.4 2.4 0.6 V ≤ VVBUS ≤ 22 V –2.1 2.1 1 A ≤ IVBUS ≤ 3 A –2.1 2.1 VOS_ERR Offset error (1) 0.05 V ≤ VADCINx ≤ 3.6 V, VADCINx ≤ VLDO_3V3 –4.1 4.1 mV 0.05 V ≤ VGPIOx ≤ 3.6 V, VGPIOx ≤ VLDO_3V3 2.7 V ≤ VLDO_3V3 ≤ 3.6 V –4.5 4.5 0.6 V ≤ VVBUS ≤ 22 V –4.1 4.1 1 A ≤ IVBUS ≤ 3 A –4.5 4.5 mA (1) The offset error is specified after the voltage divider.

6.17 Input/Output (I/O) Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT USB_P, USB_N GPIO_VIH GPIOx high-Level input voltage VLDO_3V3 = 3.3 V 1.3 V GPIO_VIL GPIOx low-level input voltage VLDO_3V3 = 3.3 V 0.54 V GPIO_HYS GPIOx input hysteresis voltage VLDO_3V3 = 3.3 V 0.09 V GPIO_ILKG GPIOx leakage current VGPIOx = 3.45 V –1 1 µA GPIO_RPU GPIOx internal pullup Pullup enabled 50 100 150 kΩ GPIO_RPD GPIOx internal pulldown Pulldown enabled 50 100 150 kΩ GPIO_DG GPIOx input deglitch 20 50 ns GPIO0-7 (Outputs) GPIO_VOH GPIOx output high voltage VLDO_3V3 = 3.3 V, IGPIOx= -2 mA 2.9 V GPIO_VOL GPIOx output low voltage VLDO_3V3 = 3.3 V, IGPIOx = 2 mA 0.4 V www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS25751

6.17 Input/Output (I/O) Characteristics (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADCIN1, ADCIN2 ADCIN_ILKG ADCINx leakage current VADCINx ≤ VLDO_3V3 –1 1 µA tBOOT Time from LDO_3V3 going high until ADCINx is read for configuration 10 ms 6.18 BC1.2 Characteristics Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DATA CONTACT DETECT IDP_SRC DCD source current VLDO_3V3 = 3.3 V 7 10 13 µA RDM_DWN DCD pulldown resistance VUSB_N = 3.6 V 14.25 20 24.8 kΩ RDP_DWN DCD pulldown resistance VUSB_P = 3.6 V 14.25 20 24.8 kΩ VLGC_HI Threshold for no connection VUSB_P ≥ VLGC_HI, VLDO_3V3 = 3.3 V, RUSB_P = 300 kΩ 2 3.6 V VLGC_LO Threshold for connection VUSB_N ≤ VLGC_LO, VLDO_3V3 = 3.3 V, RUSB_P = 24.8 kΩ 0 0.8 V Advertisement and Detection VDX_ILIM VDX_SRC current limit 250 400 µA IDX_SNK Sink Current VUSB_P ≥ 250 mV 25 75 125 µA IDX_SNK Sink Current VUSB_N ≥ 250 mV 25 75 125 µA RDCP_DAT Dedicated Charging Port Resistance 0.5 V ≤ VUSB_P ≤ 0.7 V, 25 µA ≤ IUSB_N ≤ 175 µA 200 Ω

6.19 I2C Requirements and Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I2Ct_IRQ OD_VOL_IRQ Low level output voltage IOL = 2 mA 0.4 V OD_LKG_IRQ Leakage Current Output is Hi-Z, VI2Cx_IRQ = 3.45 V –1 1 µA I2Cc_IRQ IRQ_VIH High-Level input voltage VLDO_3V3 = 3.3 V 1.3 V IRQ_VIH_THRESH High-Level input voltage threshold VLDO_3V3 = 3.3 V 0.72 1.3 V IRQ_VIL low-level input voltage VLDO_3V3 = 3.3 V 0.54 V IRQ_VIL_THRESH low-level input voltage threshold VLDO_3V3 = 3.3 V 0.54 1.08 V IRQ_HYS input hysteresis voltage VLDO_3V3 = 3.3 V 0.09 V IRQ_DEG input deglitch 20 ns IRQ_ILKG I2C3m_IRQ leakage current VI2C3m_IRQ = 3.45 V –1 1 µA SDA and SCL Common Characteristics (Controller, Target) VIL Input low signal VLDO_3V3 = 3.3 V 0.54 V IOL Max output low current VOL = 0.4 V 15 mA IOL Max output low current VOL = 0.6 V 20 mA tf Fall time from 0.7 × VDD to 0.3 × VDD VDD = 1.8 V, 10 pF ≤ Cb ≤ 400 pF 12 80 ns VDD = 3.3 V, 10 pF ≤ Cb ≤ 400 pF 12 150 ns tSP I2C pulse width suppressed 50 ns TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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6.19 I2C Requirements and Characteristics (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Cb Capacitive load for each bus line (external) 400 pF SDA and SCL Standard Mode Characteristics (Target) fSCLS Clock frequency for target VDD = 1.8 V or 3.3 V 100 kHz tVD;DAT Valid data time Transmitting Data, VDD = 1.8 V or 3.3 V, SCL low to SDA output valid 3.45 µs tVD;ACK Valid data time of ACK condition Transmitting Data, VDD = 1.8 V or

3.3 V, ACK signal from SCL low to

SDA (out) low 3.45 µs SDA and SCL Fast Mode Characteristics (Target) fSCLS Clock frequency for target VDD = 1.8 V or 3.3 V 100 400 kHz tVD;DAT Valid data time Transmitting data, VDD = 1.8 V, SCL low to SDA output valid 0.9 µs tVD;ACK Valid data time of ACK condition Transmitting data, VDD = 1.8 V or

3.3 V, ACK

signal from SCL low to SDA (out) low 0.9 µs fSCLS Clock frequency for Fast Mode Plus(1) VDD = 1.8 V or 3.3 V 400 800 kHz tVD;DAT Valid data time Transmitting data, VDD = 1.8 V or

3.3 V, SCL

0.55 µs tVD;ACK Valid data time of ACK condition Transmitting data, VDD = 1.8 V or signal from SCL low to SDA (out) low 0.55 µs tLOW Clock low time VDD = 3.3 V 1.3 µs tHIGH Clock high time VDD = 3.3 V 0.6 µs (1) Controller must control fSCLS to ensure tLOW > tVD; ACK. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS25751

6.20 Typical Characteristics

TJ (oC) RPP_5V (m:) -20 0 20 40 60 80 100 120 140 TypG Figure 6-1. PP_5V Rdson vs. Temperature. TJ (oC) RPP_CABLE (:) -20 0 20 40 60 80 100 120 140 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.05 TypG Figure 6-2. PP_CABLE Rdson vs. Temperature TJ (oC) VRCP (mV) -60 -30 0 30 60 90 120 150 5.5 6.5 7.5 TypG VPx_VBUS = 4V VPx_VBUS = 22V Figure 6-3. VRCP vs. Temperature TJ (oC) VOVP4RCP (mV) -50 0 50 100 150 5.7 5.72 5.74 5.76 5.78 5.8 TypG Figure 6-4. VOVP4RCP (Setting 2) vs. Temperature TJ (oC) RPP_HV (m:) -20 0 20 40 60 80 100 120 140 160 TypG Figure 6-5. RPPHV vs. Temperature for TPS25751D Source-to-Source Voltage (V) Source-to-Source Current (A) 0.1 0.2 0.3 0.5 0.7 100 SOAf Single Pulse Duration 100 ms 10 ms 1 ms 100 Ps 10 Ps Figure 6-6. Safe-Operating-Area (SOA) of PPHV for TPS25751D TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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6.20 Typical Characteristics (continued)

TJ (oC) VGATE (V) -40 -20 0 20 40 60 80 100 120 140 7.8 8.2 8.4 8.6 8.8 9.2 9.4 TypG GATE_VSYS: VSYS= 0 V GATE_VSYS: VSYS= 22 V GATE_VBUS Figure 6-7. VGATE_VBUS_ON vs. Temperature for TPS25751S TJ (oC) IGATE_ON (PA) -20 0 20 40 60 80 100 120 140 9.85 9.9 9.95 10.05 10.1 10.15 10.2 TypG IGATE_VBUS IGATE_VSYS Figure 6-8. VGATE_VSYS_ON vs. Temperature for TPS25751S www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS25751

7 Parameter Measurement Information

70 % 30 %SDA tf 70 % 30 % S tr 70 % 30 % 70 % 30 % t SCL HD;DAT 1 / f 1 clock cycle SCL st 70 % 30 % 70 % 30 % tr t cont. VD;DAT cont. SDA SCL tSU;STA tHD;STA Sr tSP tSU;STO tBUF P S tHIGH 9 clockthtHD;STA tLOW 70 % 30 % tVD;ACK 9 clockth tSU;DAT Figure 7-1. I2C Target Interface Timing tiOS_PP_5V, tiOS_PP_CABLE ILIM5V, ILIMVC Figure 7-2. Short-circuit Response Time for Internal Power Paths PP_5V and PP_CABLE TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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8 Detailed Description

8.1 Overview

The TPS25751 is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug and orientation detection for USB Type-C and PD receptacles. The TPS25751 communicates with the cable and another USB Type-C and PD device at the opposite end of the cable. The device also enables integrated port power switch for sourcing, and controls a high current port power switch for sinking. The TPS25751 is divided into several main sections:

• USB-PD controller
• Cable plug and orientation detection circuitry
• Port power switches
• Power management circuitry
• Digital core The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD data is output through either the CC1 pin or the CC2 pin, depending on the orientation of the reversible USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features, and more detailed circuitry, see USB-PD Physical Layer. The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug insertion the cable orientation. For a high-level block diagram of cable plug and orientation detection, a description of its features, and more detailed circuitry, see Cable Plug and Orientation Detection. The port power switches provide power to the VBUS pin and CC1 or CC2 pins based on the detected plug orientation. For a high-level block diagram of the port power switches, a description of its features, and more detailed circuitry, see Power Paths. The power management circuitry receives and provides power to the TPS25751 internal circuitry and LDO_3V3 output. See Power Management for more information. The digital core provides the engine for receiving, processing, and sending all USB-PD packets as well as handling control of all other TPS25751 functionality. A portion of the digital core contains ROM memory, which contains all the necessary firmware required to execute Type-C and PD applications. In addition, a section of the ROM, called boot code, is capable of initializing the TPS25751, loading of the device configuration information, and loading any code patches into volatile memory in the digital core. For a high-level block diagram of the digital core, a description of its features, and more detailed circuitry, see Digital Core. The TPS25751 has one I2C controller to write to and read from external target devices such as a battery charger or an optional external EEPROM memory (see I2C Interface). The TPS25751 also integrates a thermal shutdown mechanism and runs off of accurate clocks provided by the integrated oscillator. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPS25751

8.2 Functional Block Diagram

Core & Other Digital Cable Detect, Cable Power, & USB PD PHY ADCIN1 ADCIN2 I2Ct_SDA/SCL/IRQ I2Cc_SDA/SCL/IRQ GPIOx VIN_3V3 PP5V GND LDO_3V3 LDO_1V5 VBUS CC1 CC2 PPHV VBUS_IN Figure 8-1. TPS25751D TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Core & Other Digital Cable Detect, Cable Power, & USB PD PHY ADCIN1 ADCIN2 I2Ct_SDA/SCL/IRQ I2Cc_SDA/SCL/IRQ GPIOx VIN_3V3 VSYS PP5V GATE_VSYS GND LDO_3V3 LDO_1V5 VBUS CC1 CC2 GATE_VBUS Figure 8-2. TPS25751S www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPS25751

8.3 Feature Description

8.3.1 USB-PD Physical Layer

Figure 8-3 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and orientation detection block. USB-PD PHY (Rx/Tx) LDO_3V3 LDO_3V3 IVCON Fast current limit CC1 Gate Control and Current Limit Fast current limit CC1 Gate Control and Current Limit PP5V CC1 Digital Core IRp IRp RSNK RSNK CC2 Figure 8-3. USB-PD Physical Layer and Simplified Plug and Orientation Detection Circuitry TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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USB-PD messages are transmitted in a USB Type-C system using a BMC signaling. The BMC signal is output on the same pin (CC1 or CC2) that is DC biased due to the Rp (or Rd) cable attach mechanism.

8.3.1.1 USB-PD Encoding and Signaling

Figure 8-4 illustrates the high-level block diagram of the baseband USB-PD transmitter. Figure 8-5 illustrates the high-level block diagram of the baseband USB-PD receiver. 4b5b Encoder BMC Encoder CRC Data to PD_TX Figure 8-4. USB-PD Baseband Transmitter Block Diagram BMC Decoder SOP Detect 4b5b Decoder CRC from PD_RX Data Figure 8-5. USB-PD Baseband Receiver Block Diagram

8.3.1.2 USB-PD Bi-Phase Marked Coding

The USB-PD physical layer implemented in the TPS25751 is compliant to the USB-PD Specifications . The encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity (limited to 1/2 bit over an arbitrary packet, so a very low DC level). Figure 8-6 illustrates Biphase Mark Coding. 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 1 Data in BMC Figure 8-6. Biphase Mark Coding Example The USB PD baseband signal is driven onto the CC1 or CC2 pin with a tri-state driver. The tri-state driver is slew rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When sending the USB-PD preamble, the transmitter starts by transmitting a low level. The receiver at the other end tolerates the loss of the first edge. The transmitter terminates the final bit by an edge to ensure the receiver clocks the final bit of EOP.

8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks

The USB-PD driver meets the defined USB-PD BMC TX masks. Because a BMC coded “1” contains a signal edge at the beginning and middle of the UI, and the BMC coded “0” contains only an edge at the beginning, the masks are different for each. The USB-PD receiver meets the defined USB-PD BMC Rx masks. The boundaries of the Rx outer mask are specified to accommodate a change in signal amplitude due to the ground offset through the cable. The Rx masks are therefore larger than the boundaries of the TX outer mask. Similarly, the boundaries of the Rx inner mask are smaller than the boundaries of the TX inner mask. Triangular time masks are superimposed on the TX outer masks and defined at the signal transitions to require a minimum edge rate that has minimal impact on adjacent higher speed lanes. The TX inner mask enforces the maximum limits on the rise and fall times. Refer to the USB-PD Specifications for more details. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPS25751

8.3.1.4 USB-PD BMC Transmitter

The TPS25751 transmits and receives USB-PD data over one of the CCy pins for a given CC pin pair (one pair per USB Type-C port). The CCy pins are also used to determine the cable orientation and maintain the cable/device attach detection. Thus, a DC bias exists on the CCy pins. The transmitter driver overdrives the CCy DC bias while transmitting, but returns to a Hi-Z state, allowing the DC voltage to return to the CCy pin when it is not transmitting. While either CC1 or CC2 can be used for transmitting and receiving, during a given connection only, the one that mates with the CC pin of the plug is used, so there is no dynamic switching between CC1 and CC2. Figure 8-7 shows the USB-PD BMC TX and RX driver block diagram. Digitally Adjustable VREF (VRXHI, VRXLO) Level Shifter Level Shifter DriverPD_TX PD_RX LDO_3V3 CC2 CC1 USB-PD Modem Figure 8-7. USB-PD BMC TX/Rx Block Diagram Figure 8-8 shows the transmission of the BMC data on top of the DC bias. Note that the DC bias can be anywhere between the minimum and maximum threshold for detecting a Sink attach. This note means that the DC bias can be above or below the VOH of the transmitter driver. DC Bias DC Bias VOH VOL DC Bias DC BiasVOH VOL Figure 8-8. TX Driver Transmission with DC Bias The transmitter drives a digital signal onto the CCy lines. The signal peak, V TXHI, is set to meet the TX masks defined in the USB-PD Specifications. Note that the TX mask is measured at the far-end of the cable. When driving the line, the transmitter driver has an output impedance of Z DRIVER. ZDRIVER is determined by the driver resistance and the shunt capacitance of the source and is frequency dependent. Z DRIVER impacts the noise ingression in the cable. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Figure 8-9 shows the simplified circuit determining Z DRIVER. It is specified such that noise at the receiver is bounded. Driver RDRIVER CDRIVER ZDRIVER Figure 8-9. ZDRIVER Circuit

8.3.1.5 USB-PD BMC Receiver

The receiver block of the TPS25751 receives a signal that follows the allowed Rx masks defined in the USB PD specification. The receive thresholds and hysteresis come from this mask. Figure 8-10 shows an example of a multi-drop USB-PD connection (only the CC wire). This connection has the typical Sink (device) to Source (host) connection, but also includes cable USB-PD Tx/Rx blocks. Only one system can be transmitting at a time. All other systems are Hi-Z (Z BMCRX). The USB-PD Specification also specifies the capacitance that can exist on the wire as well as a typical DC bias setting circuit for attach detection. Tx Rx Pullup for Attach Detection CRECEIVER Connector CCablePlug_CC Rx Tx Tx Rx Connector Rx Tx RD for Attach Detection Cable Source System Sink System CRECEIVER 623¶3' communication only (eMarker #1) 623¶¶3' communication only (eMarker #2) CC wire CCablePlug_CC Figure 8-10. Example USB-PD Multi-Drop Configuration

8.3.1.6 Squelch Receiver

The TPS25751 has a squelch receiver to monitor for the bus idle condition as defined by the USB PD specification.

8.3.2 Power Management

The TPS25751 power management block receives power and generates voltages to provide power to the TPS25751 internal circuitry. These generated power rails are LDO_3V3 and LDO_1V5. LDO_3V3 can also be used as a low power output for external EEPROM memory. The power supply path is shown in Figure 8-11. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TPS25751

LDOLDO_1V5 LDO VREF VREF VIN_3V3 LDO_3V3 VBUS RLDO_3V3 Figure 8-11. Power Supplies The TPS25751 is powered from either VIN_3V3 or VBUS. The normal power supply input is VIN_3V3. When powering from VIN_3V3, current flows from VIN_3V3 to LDO_3V3 to power the core 3.3-V circuitry and I/Os. A second LDO steps the voltage down from LDO_3V3 to LDO_1V5 to power the 1.5-V core digital circuitry. When VIN_3V3 power is unavailable and power is available on VBUS, it is referred to as the dead-battery start-up condition. In a dead-battery start-up condition, the TPS25751 opens the VIN_3V3 switch until the host clears the dead-battery flag through I 2C. Therefore, the TPS25751 is powered from the VBUS input with the higher voltage during the dead-battery start-up condition and until the dead-battery flag is cleared. When powering from a VBUS input, the voltage on VBUS is stepped down through an LDO to LDO_3V3.

8.3.2.1 Power-On And Supervisory Functions

A power-on reset (POR) circuit monitors each supply. This POR allows active circuitry to turn on only when a good supply is present.

8.3.2.2 VBUS LDO

The TPS25751 contains an internal high-voltage LDO which is capable of converting VBUS to 3.3 V for powering internal device circuitry. The VBUS LDO is only used when VIN_3V3 is low (the dead-battery condition). The VBUS LDO is powered from VBUS.

8.3.3 Power Paths

The TPS25751 has internal sourcing power paths: PP_5V and PP_CABLE. TPS25751D has a integrated bidirectional high voltage load switch for sinking power path: PPHV. TPS25751S has a high voltage gate driver for sink path control: PP_EXT. Each power path is described in detail in this section.

8.3.3.1 Internal Sourcing Power Paths

Figure 8-12 shows the TPS25751 internal sourcing power paths available in both TPS25751D and TPS25751S. The TPS25751 features two internal 5-V sourcing power paths. The path from PP5V to VBUS is called PP_5V. The path from PP5V to CCx is called PP_CABLE. Each path contains two back-to-back common drain N-FETs, with current clamping protection, overvoltage protection, UVLO protection, and temperature sensing circuitry. PP_5V can conduct up to 3 A continuously, while PP_CABLE can conduct up to 315 mA continuously. When disabled, the blocking FET protects the PP5V rail from high-voltage that can appear on VBUS. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Fast current limit, IVCON CC2 CC2 Gate Control VBUS PP_5V Gate Control and Sense PP_5V Fast current clamp, ILIM5V PP_CABLE TSD_PP5V Temp Sensor Temp Sensor CC1 Gate Control Figure 8-12. Port Power Switches

8.3.3.1.1 PP_5V Current Clamping

The current through the internal PP_5V path are current limited to I LIM5V. The I LIM5V value is configured by application firmware. When the current through the switch exceeds I LIM5V, the current limiting circuit activates within t iOS_PP_5V and the path behaves as a constant current source. If the duration of the overcurrent event exceeds tILIM, the PP_5V switch is disabled.

8.3.3.1.2 PP_5V Local Overtemperature Shut Down (OTSD)

When PP_5V clamps the current, the temperature of the switch begin to increase. When the local temperature sensors of PP_5V or PP_CABLE detect that T J > TSD_PP5V, the PP_5V switch is disabled and the affected port enters the USB Type-C ErrorRecovery state.

8.3.3.1.3 PP_5V OVP

The overvoltage protection level is automatically configured based on the expected maximum V BUS voltage, which depends upon the USB PD contract. When the voltage on the VBUS pin of a port exceeds the configured value (VOVP4RCP) while PP_5V is enabled, then PP_5V is disabled within t PP_5V_ovp and the port enters into the Type-C ErrorRecovery state.

8.3.3.1.4 PP_5V UVLO

If the PP5V pin voltage falls below its undervoltage lock out threshold (VPP5V_UVLO) while PP_5V is enabled, then PP_5V is disabled within t PP_5V_uvlo and the port that had PP_5V enabled enters into the Type-C ErrorRecovery state.

8.3.3.1.5 PP_5Vx Reverse Current Protection

If V VBUS - V PP5V > V PP_5V_RCP, then the PP_5V path is automatically disabled within t PP_5V_rcp. If the RCP condition clears, then the PP_5V path is automatically enabled within tON.

8.3.3.1.6 PP_CABLE Current Clamp

When enabled and providing VCONN power, the TPS25751 PP_CABLE power switch clamps the current to IVCON. When the current through the PP_CABLE switch exceeds I VCON, the current clamping circuit activates within tiOS_PP_CABLE and the switch behaves as a constant current source. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TPS25751

8.3.3.1.7 PP_CABLE Local Overtemperature Shut Down (OTSD)

When PP_CABLE clamps the current, the temperature of the switch begins to increase. When the local temperature sensors of PP_5V or PP_CABLE detect that T J>TSD_PP5V, the PP_CABLE switch is disabled and latched off within tPP_CABLE_off. The port then enters the USB Type-C ErrorRecovery state.

8.3.3.1.8 PP_CABLE UVLO

If the PP5V pin voltage falls below its undervoltage lock out threshold (V PP5V_UVLO), then the PP_CABLE switch is automatically disabled within tPP_CABLE_off.

8.3.3.2 TPS25751D Internal Sink Path

The TPS25751D has internal controls for internal FETs (GATE_VSYS and GATE_VBUS as shown in Figure 8-13) that require that VBUS_IN be above V VBUS_UVLO before being able to enable the sink path. Figure 8-13 shows a diagram of the sink path. When a sink path is enabled, the circuitry includes a slew rate control loop to ensure that external switches do not turn on too quickly (SS). The TPS25751D senses the PPHV and VBUS voltages to control the gate voltages to enable or disable the FETs. The sink-path control includes overvoltage protection (OVP) and reverse current protection (RCP). PP_HV Gate Control and Sense Copyright © 2018, Texas Instruments Incorporated PPHV VBUS GATE_VSYS GATE_VBUS Figure 8-13. Internal Sink Path

8.3.3.2.1 Overvoltage Protection (OVP)

The application firmware enables the OVP and configures it based on the expected VBUS voltage. If the voltage on VBUS surpasses the configured threshold VOVP4VSYS = VOVP4RCP/rOVP, then GATE_VSYS is automatically disabled within tPPHV_FSD to protect the system. If the voltage on VBUS surpasses the configured threshold VOVP4RCP, then GATE_VBUS is automatically disabled within tPPHV_OVP. When VVBUS falls below VOVP4RCP - VOVP4RCPH, GATE_VBUS is automatically re-enabled within tPPHV_ON because the OVP condition has cleared. This action allows two sinking power paths to be enabled simultaneously and GATE_VBUS disables when necessary to ensure that VVBUS remains below VOVP4RCP. While the TPS25751D is in BOOT mode in a dead-battery scenario (that is VIN_3V3 is low), it handles an OVP condition slightly differently. As long as the OVP condition is present, GATE_VBUS and GATE_VSYS are disabled. Once the OVP condition clears, both GATE_VBUS and GATE_VSYS are re-enabled. Because this is a dead-battery condition, the TPS25751D draws approximately IVIN_3V3, ActSnk from VBUS during this time to help discharge it. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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VOVP4VSYS = VOVP4RCP / rOVP Power Path Supervisor VOVP4RCP Figure 8-14. Diagram for OVP Comparators

8.3.3.2.2 Reverse-Current Protection (RCP)

The VSYS gate control circuit monitors the PPHV and VBUS voltages and detects reverse current when the VVSYS surpasses VVBUS by more than VRCP. When the reverse current condition is detected, GATE_VBUS is disabled within tPPHV_RCP. When the reverse current condition is cleared, GATE_VBUS is re-enabled within tPPHV_ON. This action limits the amount of reverse current that can flow from PPHV to VBUS through the external N-ch MOSFETs. In reverse current protection mode, the power switch controlled by GATE_VBUS is allowed to behave resistively until the current reaches VRCP/ RPPHV and then blocks reverse current from PPHV to VBUS. -VRCP I 1/RPPHV VRCP/RPPHV V=VVBUS ± VPPHV Copyright © 2018, Texas Instruments Incorporated Figure 8-15. Switch I-V Curve for RCP on Sink-path Switches.

8.3.3.2.3 VBUS UVLO

The TPS25751D monitors VBUS voltage and detects when it falls below VVBUS_UVLO. When the UVLO condition is detected, GATE_VBUS is disabled within tPPHV_RCP. When the UVLO condition is cleared, GATE_VBUS is reenabled within tPPHV_ON.

8.3.3.2.4 Discharging VBUS to Safe Voltage

The TPS25751D has an integrated active pulldown (IDSCH) on VBUS for discharging from high voltage to VSAFE0V (0.8 V). This discharge is applied when it is in an Unattached Type-C state.

8.3.3.3 TPS25751S - External Sink Path Control PP_EXT

The TPS25751S has two N-ch gate drivers designed to control a sinking path from VBUS to VSYS. The charge pump for these gate drivers requires VBUS to be above VVBUS_UVLO. When a sink path is enabled, the circuitry includes a slew rate control loop to ensure that external switches do not turn on too quickly (SS). The www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TPS25751

TPS25751S senses the VSYS and VBUS voltages to control the gate voltages to enable or disable the external FETs. The sink-path control includes overvoltage protection (OVP), and reverse current protection (RCP). Adding resistance in series with a GATE pin of the TPS25751S and the gate pin of the N-ch MOSFET slows down the turnoff time when OVP or RCP occurs. Any such resistance must be minimized, and not allowed to exceed 3 Ω. PP_EXT PP_EXT Gate Control and Sense GATE_VSYS GATE_VBUS VBUS Copyright © 2018, Texas Instruments Incorporated VSYS Figure 8-16. PP_EXT External Sink Path Control Figure 8-17 shows the GATE_VSYS gate driver in more detail. VSYS VGATE_ON Charge Pump IGATE_ON GATE_VSYS GND Regular enable/ disable Fast disable VBUS IGATE_OFF RGATE_OFF_UVLO switch enabled when gate driver is disabled and VVIN_3V3 < VVIN_3V3_UVLO RGATE_FSD Figure 8-17. Details of the VSYS Gate Driver TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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8.3.3.3.1 Overvoltage Protection (OVP)

The application firmware enables the OVP and configures it based on the expected VBUS voltage. If the voltage on VBUS surpasses the configured threshold VOVP4VSYS = VOVP4RCP/rOVP, then GATE_VSYS is automatically disabled within tPPHV_FSD to protect the system. If the voltage on VBUS surpasses the configured threshold VOVP4RCP, then GATE_VBUS is automatically disabled within tPPHV_OVP. When VVBUS falls below VOVP4RCP - VOVP4RCPH, GATE_VBUS is automatically re-enabled within tPPHV_ON because the OVP condition has cleared. This action allows two sinking power paths to be enabled simultaneously and GATE_VBUS disables when necessary to ensure that VVBUS remains below VOVP4RCP. While the TPS25751D is in BOOT mode in a dead-battery scenario (that is VIN_3V3 is low), it handles an OVP condition slightly differently. As long as the OVP condition is present, GATE_VBUS and GATE_VSYS are disabled. Once the OVP condition clears, both GATE_VBUS and GATE_VSYS are re-enabled. Because this is a dead-battery condition, the TPS25751D draws approximately IVIN_3V3, ActSnk from VBUS during this time to help discharge it. VBUS VOVP4VSYS = VOVP4RCP / rOVP Power Path Supervisor VOVP4RCP Figure 8-18. Diagram for OVP Comparators The VSYS gate control circuit monitors the PPHV and VBUS voltages and detects reverse current when the VVSYS surpasses VVBUS by more than VRCP. When the reverse current condition is detected, GATE_VBUS is disabled within tPPHV_RCP. When the reverse current condition is cleared, GATE_VBUS is re-enabled within tPPHV_ON. This action limits the amount of reverse current that can flow from PPHV to VBUS through the external N-ch MOSFETs. In reverse current protection mode, the power switch controlled by GATE_VBUS is allowed to behave resistively until the current reaches VRCP/ RPPHV and then blocks reverse current from PPHV to VBUS. -VRCP I 1/RPPHV VRCP/RPPHV V=VVBUS ± VPPHV Copyright © 2018, Texas Instruments Incorporated Figure 8-19. Switch I-V Curve for RCP on Sink-path Switches. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TPS25751

The TPS25751D monitors VBUS voltage and detects when it falls below VVBUS_UVLO. When the UVLO condition is detected, GATE_VBUS is disabled within tPPHV_RCP. When the UVLO condition is cleared, GATE_VBUS is reenabled within tPPHV_ON. The TPS25751S has an integrated active pulldown (IDSCH) on VBUS for discharging from high voltage to VSAFE0V (0.8 V). This discharge is applied when it is in an Unattached Type-C state.

8.3.4 Cable Plug and Orientation Detection

Figure 8-20 shows the plug and orientation detection block at each CCy pin (CC1, CC2). Each pin has identical detection circuitry. VREF1 VREF2 VREF3 IRpDef IRp1.5 IRp3.0 RSNK CCy Figure 8-20. Plug and Orientation Detection Block

8.3.4.1 Configured as a Source

When configured as a source, the TPS25751 detects when a cable or a Sink is attached using the CC1 and CC2 pins. When in a disconnected state, the TPS25751 monitors the voltages on these pins to determine what, if anything, is connected. See USB Type-C Specification for more information. Table 8-1 shows the Cable Detect States for a Source. Table 8-1. Cable Detect States for a Source CC1 CC2 CONNECTION STATE RESULTING ACTION Open Open Nothing attached Continue monitoring both CCy pins for attach. Power is not applied to VBUS or VCONN. Rd Open Sink attached Monitor CC1 for detach. Power is applied to VBUS but not to VCONN (CC2). Open Rd Sink attached Monitor CC2 for detach. Power is applied to VBUS but not to VCONN (CC1). Ra Open Powered Cable-No UFP attached Monitor CC2 for a Sink attach and CC1 for cable detach. Power is not applied to VBUS or VCONN (CC1). TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Table 8-1. Cable Detect States for a Source (continued) CC1 CC2 CONNECTION STATE RESULTING ACTION Open Ra Powered Cable-No UFP attached Monitor CC1 for a Sink attach and CC2 for cable detach. Power is not applied to VBUS or VCONN (CC1). Ra Rd Powered Cable-UFP Attached Provide power on VBUS and VCONN CC1) then monitor CC2 for a Sink detach. CC1 is not monitored for a detach. Rd Ra Powered Cable-UFP attached Provide power on VBUS and VCONN (CC2) then monitor CC1 for a Sink detach. CC2 is not monitored for a detach. Rd Rd Debug Accessory Mode attached Sense either CCy pin for detach. Ra Ra Audio Adapter Accessory Mode attached Sense either CCy pin for detach. When a TPS25751 port is configured as a Source, a current I RpDef is driven out each CCy pin and each pin is monitored for different states. When a Sink is attached to the pin, a pulldown resistance of Rd to GND exists. The current IRpDef is then forced across the resistance Rd, generating a voltage at the CCy pin. The TPS25751 applies IRpDef until it closes the switch from PP5V to VBUS, at which time application firmware can change to IRp1.5A or IRp3.0A. When the CCy pin is connected to an active cable VCONN input, the pulldown resistance is different (Ra). In this case, the voltage on the CCy pin lowers the PD controller recognizes it as an active cable. The voltage on CCy is monitored to detect a disconnection depending upon which Rp current source is active. When a connection has been recognized and the voltage on CCy subsequently rises above the disconnect threshold for tCC, the system registers a disconnection.

8.3.4.2 Configured as a Sink

When a TPS25751 port is configured as a Sink, the TPS25751 presents a pulldown resistance R SNK on each CCy pin and waits for a Source to attach and pull up the voltage on the pin. The Sink detects an attachment by the presence of VBUS and determines the advertised current from the Source based on the voltage on the CCy pin.

8.3.4.3 Configured as a DRP

When a TPS25751 port is configured as a DRP, the TPS25751 alternates the CCy pins of the port between the pulldown resistance, RSNK, and pullup current source, IRp.

8.3.4.4 Dead Battery Advertisement

The TPS25751 supports booting from no-battery or dead-battery conditions by receiving power from VBUS. Type-C USB ports require a sink to present Rd on the CC pin before a USB Type-C source provides a voltage on VBUS. TPS25751 hardware is configured to present this Rd during a dead-battery or no-battery condition. Additional circuitry provides a mechanism to turn off this Rd once the device no longer requires power from VBUS.

8.3.5 Overvoltage Protection (CC1, CC2)

The TPS25751 detects when the voltage on the CC1 or CC2 pin is too high or there is reverse current into the PP5V pin and takes action to protect the system. The protective action is to disable PP_CABLE within tPP_CABLE_FSD and disable the USB PD transmitter. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TPS25751

VVC_OVP PP5V VPHY_OVP VPHY_OVP CC1 CC2 VVC_RCP max(VCC1, VCC2) - VPP5V Control Logic Disable PP_CABLE and USB PD PHY Tx Figure 8-21. Overvoltage and Reverse Current Protection for CC1 and CC2

8.3.6 Default Behavior Configuration (ADCIN1, ADCIN2)

This functionality is firmware controlled and subject to change. The ADCINx inputs to the internal ADC control the behavior of the TPS25751 in response to VBUS being supplied when VIN_3V3 is low (that is the dead-battery scenario). The ADCINx pins must be externally tied to the LDO_3V3 pin via a resistive divider as shown in the following figure. At power-up the ADC converts the ADCINx voltage and the digital core uses these two values to determine start-up behavior. The available start-up configurations include options for I 2C target address of I2Ct_SCL/SDA, sink path control in dead-battery, and default configuration. ADC Mux and Dividers LDO_3V3 ADCINx Figure 8-22. ADCINx Resistor Divider TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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The device behavior is determined in several ways depending upon the decoded value of the ADCIN1 and ADCIN2 pins. The following table shows the decoded values for different resistor divider ratios. See Pin Strapping to Configure Default Behavior for details on how the ADCINx configurations determine default device behavior. See I2C Address Setting for details on how ADCINx decoded values affects default I2C target address. Table 8-2. Decoding of ADCIN1 and ADCIN2 Pins DIV = RDOWN / (RUP + RDOWN)(1) Without Using RUP or RDOWN ADCINx Decoded Value(2) MIN Target MAX 0 0.0114 0.0228 tie to GND 0 0.0229 0.0475 0.0722 N/A 1 0.0723 0.1074 0.1425 N/A 2 0.1425 0.1899 0.2372 N/A 3 0.2373 0.3022 0.3671 N/A 4 0.3672 0.5368 0.7064 tie to LDO_1V5 5 0.7065 0.8062 0.9060 N/A 6 0.9061 0.9530 1.0 tie to LDO_3V3 7 (1) See I2C Address Setting to see the exact meaning of I2C Address Index. (2) See Pin Strapping to Configure Default Behavior for how to configure a given ADCINx decoded value.

8.3.7 ADC

The TPS25751 ADC is shown in Figure 8-23. The ADC is an 8-bit successive approximation ADC. The input to the ADC is an analog input mux that supports multiple inputs from various voltages and currents in the device. The output from the ADC is available to be read and used by application firmware. ADCInput Mux 8 bits Voltage Divider 2 Buffers & Voltage Divider 1 ADCIN1 ADCIN2 GPIO4 GPIO2 VBUS I-to-V I_VBUS LDO_3V3 Copyright © 2018, Texas Instruments Incorporated Voltage Divider 1 GPIO0 GPIO5 Figure 8-23. SAR ADC 8.3.8 BC 1.2 (USB_P, USB_N) The TPS25751 supports BC 1.2 as a Portable Device or Downstream Port using the hardware shown in Figure 8-24. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TPS25751

Figure 8-24. BC1.2 Hardware Components

8.3.9 Digital Interfaces

The TPS25751 contains several different digital interfaces which can be used for communicating with other devices. The available interfaces include one I2C controller, one I2C target and additional GPIOs.

8.3.9.1 General GPIO

GPIOn pins can be mapped to USB Type-C, USB PD, and application-specific events to control other ICs, interrupt a host processor, or receive input from another IC. This buffer is configurable to be a push-pull output, a weak push-pull, or open drain output. When configured as an input, the signal can be a de-glitched digital input . The push-pull output is a simple CMOS output with independent pull-down control allowing open-drain connections. The weak push-pull is also a CMOS output, but with GPIO_RPU resistance in series with the drain. The supply voltage to the output buffer is LDO_3V3 and LDO_1V5 to the input buffer. When interfacing with non 3.3-V I/O devices the output buffer can be configured as an open drain output and an external pull-up resistor attached to the GPIO pin. The pull-up and pull-down output drivers are independently controlled from the input and are enabled or disabled via application code in the digital core. Table 8-3. GPIO Functionality Table PIN NAME TYPE SPECIAL FUNCTIONALITY GPIO0 I/O General-purpose input or output GPIO1 I/O General-purpose input or output GPIO2 I/O General-purpose input or output GPIO3 I/O General-purpose input or output GPIO4 I/O D+, general-purpose input or output, or LD1 for Liquid Detection GPIO5 I/O D-, general-purpose input or output, or LD2 for Liquid Detection GPIO6 I/O General-purpose input or output GPIO7 I/O General-purpose input or output I2Ct_IRQ(GPIO10) O IRQ for optional I2Ct, or used as a general-purpose output GPIO11 O General-purpose output I2Cc_IRQ(GPIO12) I IRQ for I2Cc, or used as a general-purpose input

8.3.9.2 I2C Interface

The TPS25751 features two I2C interfaces that uses an I2C I/O driver like the one shown in Figure 8-25. This I/O consists of an open-drain output and an input comparator with de-glitching. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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I2C_SDA/SCL I2C_DO I2C_DI50ns Deglitch Figure 8-25. I2C Buffer

8.3.10 Digital Core

Figure 8-26 shows a simplified block diagram of the digital core. GPIOx I2Ct_SDA I2Ct_SCL I2Ct_IRQ I2Cc_IRQ Digital Core ADC Temp Sense ADC Read Thermal Shutdown CBL_DET Bias CTL and USB-PD I2Cc (Controller) I2Ct (Target) I2C to System Control OSC USB PD Phy I2Cc_SDA I2Cc_SCL I2C to Battery Charger Figure 8-26. Digital Core Block Diagram

8.3.11 I2C Interface

The TPS25751 has one I2C target interface ports: I2Ct. I2C port I2Ct is comprised of the I2Ct_SDA, I2Ct_SCL, and I2Ct_IRQ pins. This interface provide general status information about the TPS25751, as well as the ability to control the TPS25751 behavior, supporting communications to/from a connected device and/or cable supporting BMC USB-PD, and providing information about connections detected at the USB-C receptacle. When the TPS25751 is in 'APP ' mode TI recommends to use standard mode or Fast mode (that is a clock speed no higher than 400 kHz). However, in the BOOT mode when a patch bundle is loaded Fast Mode Plus can be used (see fSCLS). www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TPS25751

The TPS25751 has one I 2C controller interface port. I 2C is comprised of the I2C_SDA and I2C_SCL pins. This interface can be used to read from or write to external target devices. During boot, the TPS25751 attempts to read patch and Application Configuration data from an external EEPROM with a 7-bit target address of 0x50. The EEPROM must be at least 32 kilo-bytes. Table 8-4. I2C Summary I2C BUS TYPE TYPICAL USAGE I2Ct Target Optionally can be connected to an external MCU. Also used to load the patch and application configuration. I2Cc Controller Connect to a I2C EEPROM, Battery Charger. Use the LDO_3V3 pin as the pullup voltage. Multi- controller configuration is not supported.

8.3.11.1 I2C Interface Description

The TPS25751 supports Standard and Fast mode I 2C interfaces. The bidirectional I 2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pullup resistor. Data transfer can be initiated only when the bus is not busy. A controller sending a Start condition, a high-to-low transition on the SDA input and output, while the SCL input is high initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. On the I 2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period as changes in the data line at this time are interpreted as control commands (Start or Stop). The controller sends a Stop condition, a low-to-high transition on the SDA input and output while the SCL input is high. Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a target receiver is addressed, it must generate an ACK after each byte is received. Similarly, the controller must generate an ACK after each byte that it receives from the target transmitter. Setup and hold times must be met to ensure proper operation. A controller receiver signals an end of data to the target transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the target. The controller receiver holding the SDA line high does this. In this event, the transmitter must release the data line to enable the controller to generate a Stop condition. Figure 8-27 shows the start and stop conditions of the transfer. Figure 8-28 shows the SDA and SCL signals for transferring a bit. Figure 8-29 shows a data transfer sequence with the ACK or NACK at the last clock pulse. PS Start Condition Stop Condition SDA SCL Figure 8-27. I2C Definition of Start and Stop Conditions TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Figure 8-28. I2C Bit Transfer SCL from Controller Figure 8-29. I2C Acknowledgment

8.3.11.1.1 I2C Clock Stretching

The TPS25751 features clock stretching for the I 2C protocol. The TPS25751 target I 2C port can hold the clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The controller communicating with the target must not finish the transmission of the current bit and must wait until the clock line actually goes high. When the target is clock stretching, the clock line remains low. The controller must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for standard 100-kbps I2C) before pulling the clock low again. Any clock pulse can be stretched but typically it is the interval before or after the acknowledgment bit.

8.3.11.1.2 I2C Address Setting

The I2C controller must only use I2Ct_SCL/SDA for loading a patch bundle. Once the boot process is complete, the port has a unique target address on the I2Ct_SCL/SDA bus as selected by the ADCINx pins. Table 8-5. I2C Default Target Address for I2Ct_SCL/SDA. I2C ADDRESS INDEX (DECODED FROM ADCIN1 AND ADCIN2)(1) TARGET ADDRESS AVAILABLE DURING BOOTBIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 #1 0 1 0 0 0 0 0 R/W Yes #2 0 1 0 0 0 0 1 R/W Yes #3 0 1 0 0 0 1 0 R/W Yes #4 0 1 0 0 0 1 1 R/W Yes (1) See Pin Strapping to Configure Default Behavior details about ADCIN1 and ADCIN2 decoding.

8.3.11.1.3 Unique Address Interface

The Unique Address Interface allows for complex interaction between an I 2C controller and a single TPS25751. The I2C target sub-address is used to receive or respond to Host Interface protocol commands. Figure 8-30 and Figure 8-31 show the write and read protocol for the I 2C target interface, and a key is included in Figure 8-32 www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: TPS25751

to explain the terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated here in part. P S Unique Address Wr Register Number Byte Count = N Data Byte 1A A A A 1 7 1 8 8 8 1 1 1 1 Data Byte 2 A 8 1 Data Byte N A 8 1 Figure 8-30. I2C Unique Address Write Register Protocol ASr Unique Address Rd Byte Count = NA 1 7 1 8 1 1 S Unique Address Wr 1 7 1 1 1 A P AData Byte N AData Byte 1 8 1 AData Byte 2 Register Number A Figure 8-31. I2C Unique Address Read Register Protocol x S Wr A Target Address Data Byte x A P S SR Rd Wr X A P Start condition Repeated start condition Read (bit value of 1) Write (bit value of 0 Field is required to have the value x Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK) Stop condition Controller-to-target Target-to-controller Continuation of protocol Figure 8-32. I2C Read/Write Protocol Key

8.4 Device Functional Modes

8.4.1 Pin Strapping to Configure Default Behavior

During the boot procedure, the device reads the ADCINx pins and set the configurations based on the table below. The device then attempts to load a configuration from an external EEPROM on the I2Cc bus. If no EEPROM is detected, then the device waits for an external host to load a configuration. When an external EEPROM is used, each device is connected to a unique EEPROM, it cannot be shared for multiple devices. The external EEPROM is set at 7-bit target address 0x50. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Table 8-6. Device Configuration using ADCIN1 and ADCIN2 ADCIN1 DECODED VALUE(2) ADCIN2 DECODED VALUE(2) I2C ADDRESS INDEX(1) DEAD BATTERY CONFIGURATION 7 5 #1 AlwaysEnableSink: The device always enables the sink path regardless of the amount of current the attached source is offering. USB PD is disabled until configuration is loaded. 5 5 #2 2 0 #3 1 7 #4 7 3 #1 NegotiateHighVoltage: The device always enables the sink path during the initial implicit contract regardless of the amount of current the attached source is offering. The PD controller enters the 'APP ' mode, enable USB PD PHY and negotiate a contract for the highest power contract that is offered up to 20 V. The configuration cannot be used when a patch is loaded from EEPROM. This option is not recommended for systems that can boot from 5 V. 3 3 #2 4 0 #3 3 7 #4 7 0 #1 SafeMode: The device does not enable the sink path. USB PD is disabled until configuration is loaded. Note that the configuration can put the device into a source-only mode. This is recommended when the application loads the patch from EEPROM. 0 0 #2 6 0 #3 5 7 #4 (1) See Table 8-5 to see the exact meaning of I2C Address Index. (2) See Table 8-2 for how to configure a given ADCINx decoded value.

8.4.2 Power States

The TPS25751 can operate in one of three different power states: Active, Idle, or Sleep. The Modern Standby mode is a special case of the Idle mode. The functionality available in each state is summarized in Table 8-7. The device automatically transitions between the three power states based on the circuits that are active and required. See Figure 8-33. In the Sleep state, the TPS25751 detects a Type-C connection. Transitioning between the Active mode to Idle mode requires a period of time (T) without any of the following activity:

• Incoming USB PD message
• Change in CC status
• GPIO input event
• I2C transactions
• Voltage alert
• Fault alert Sleep State No CC connection Active State Idle State CC connected New activity CC detached & No activity for T CC attached & No new activity for T New activity Figure 8-33. Flow Diagram for Power States Table 8-7. Power Consumption States ACTIVE SOURCE MODE(1) ACTIVE SINK MODE5 IDLE SOURCE MODE IDLE SINK MODE MODERN STANDBY SOURCE MODE3 MODERN STANDBY SINK MODE4 SLEEP MODE2 PP_5V enabled disabled enabled disabled enabled disabled disabled www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: TPS25751

Table 8-7. Power Consumption States (continued) ACTIVE SOURCE MODE(1) ACTIVE SINK MODE5 IDLE SOURCE MODE IDLE SINK MODE MODERN STANDBY SOURCE MODE3 MODERN STANDBY SINK MODE4 SLEEP MODE2 PP_HV (TPS25751D) disabled enabled disabled enabled disabled disabled disabled PP_EXT (TPS25751S) disabled enabled disabled enabled disabled disabled disabled PP_CABLE enabled enabled enabled enabled disabled disabled disabled external CC1 termination Rd Rp 3.0A Rd Rp 3.0A open open open external CC2 termination open open open open open open open (1) This mode is used for: IVIN_3V3,ActSrc. (2) This mode is used for: IVIN_3V3,Sleep (3) This mode is used for: PMstbySrc (4) This mode is used for: PMstbySnk (5) This mode is used for: IVIN_3V3,ActSnk

8.5 Thermal Shutdown

The TPS25751 features a central thermal shutdown as well as independent thermal sensors for each internal power path. The central thermal shutdown monitors the overall temperature of the die and disables all functions except for supervisory circuitry when die temperature goes above a rising temperature of T SD_MAIN. The temperature shutdown has a hysteresis of T SDH_MAIN and when the temperature falls back below this value, the device resumes normal operation. The power path thermal shutdown monitors the temperature of each internal PP5V-to-VBUS power path and disables both power paths and the VCONN power path when either exceeds T SD_PP5V. Once the temperature falls by at least T SDH_PP5V, the path can be configured to resume operation or remain disabled until re-enabled by firmware. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TPS25751 is a stand-alone Type-C PD controller for power-only USB-PD applications. Initial device configuration is configured from an external EEPROM through a firmware configuration bundle loaded on to the device during boot. The bundle is loaded over I 2C from an external EEPROM. The TPS25751 firmware configuration can be customized for each specific application. The firmware configuration can be generated through the Web Tool. The TPS25751 is ideal for single port power applications supporting the following PD architectures.

• Designs for both Power Provider (Source) and Power Consumer (Sink)
• Designs for Power Consumer (Sink) An external EEPROM is required to download a pre-configured firmware on the TPS25751 device through the I2C interface. The TPS25751 firmware can be configured using the Web Tool for the application-specific PD charging architecture requirements and data roles. The tool also provides additional optional firmware configuration that integrates control for select Battery Charger Products (BQ). The TPS25751 I2C controller interfaces with the Battery Chargers with pre-configured GPIO settings and I 2C controller events. The Application Customization Tool available with the TPS25751 provides details of the supported Battery Charger Products (BQ).

9.2 Typical Application

The following show the block diagrams for various applications. Note that some of these features are GPIO usage dependent. TPS25751D I2C Controller I2Cc_SDA I2Cc_SCL I2Cc_IRQ Battery Charger USB Type-C Connector SW SW VBUS PPHV GND System 5V PP5V GND CCx/Vconn I2C Target #1 VINBAT EEPROM I2C Target #2 I2C Target I2Ct_SDA I2Ct_SCL I2Ct_IRQ Host Control I2C Controller GPIO USB SS Mux CC Control and Vconn VBUS CCx/Vconn SSTX1/RX1 SSTX2/RX2 Liquid Detection *ADC + GPIO SBU1 SBU2 GND *BC1.2 DP DM SSTX/RX Figure 9-1. TPS25751D Battery Charger & Full System Block Diagram www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: TPS25751

I2Cc_SDA I2Cc_SCL I2Cc_IRQ Battery Charger USB Type-C Connector SW VBUS PPEXT GND System 5V PP5V GND CCx/Vconn I2C Target #1 VINBAT EEPROM I2C Target #2 I2C Target I2Ct_SDA I2Ct_SCL I2Ct_IRQ Host Control I2C Controller GPIO USB SS Mux CC Control and Vconn VBUS CCx/Vconn SSTX1/RX1 SSTX2/RX2 Liquid Detection *ADC + GPIO SBU1 SBU2 GND *BC1.2 DP DM SSTX/RX SW Figure 9-2. TPS25751S Battery Charger & Full System Block Diagram TPS25751D I2C Controller I2Cc_SDA I2Cc_SCL I2Cc_IRQ Battery Charger USB Type-C Connector SW SW VBUS PPHV GND System 5V PP5V GND CCx Vconn VINBAT PG I2C Target GPIO Figure 9-3. TPS25751D Battery Charger System Block Diagram TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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I2Cc_SDA I2Cc_SCL I2Cc_IRQ Battery Charger PPEXT System 5V PP5V GND I2C Target BAT VIN PG GPIO Figure 9-4. TPS25751S Battery Charger System Block Diagram

9.2.1 Design Requirements

9.2.1.1 Programmable Power Supply (PPS) - Design Requirements

Programmable Power Supply (PPS) defines a specific voltage and current (Augmented Power Data Object) that is used in direct charging applications. A PPS source needs to meet the source voltage and current resolution required for direct charging applications. A PPS sink requests the voltage and current required for direct charging within the capabilities of PPS source. Table 9-1. PPS Source 60W/100W Requirements Power Path PD Power Source VBUS Voltage VBUS Current TPS25751D - PPHV 60W/100W 5V - 21V (20mV Steps) 3A/5A (50mA Steps) TPS25751S - PPEXT 60W/100W 5V - 21V (20mV Steps) 3A/5A (50mA Steps) Table 9-2. PPS Sink 60W/100W Requirements Power Path PD Power Sink VBUS Voltage VBUS Current TPS25751D - PPHV 60W/100W 5V - 21V 3A/5A TPS25751S - PPEXT 60W/100W 5V - 21V 3A/5A

9.2.1.2 Liquid Detection Design Requirements

Portable Type-C and PD applications are subject to environments that wet the Type-C connector. Liquid on the Type-C connector leads to corrosion or system damage. Detecting liquid leverages the SBU1/2 pins on the Type-C connector to not interfere with USB2/3 operation or PD communication. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: TPS25751

LDO_3V3 GPIOx/y GPIO4 GND GPIO5 USB Type-C Connector SBU1 SBU2 GND Liquid Detection + Protection Circuit VBUS CCx VBUS CCx 0V – 20V 0V – 3.3V (5V for Vconn) 3.3V FET Control RSaV RSaCC RSaG 3.3V Figure 9-5. Liquid Detection Cases 9.2.1.3 BC1.2 Application Design Requirements The PD controller taps the USB D+ and D- pins to provide BC1.2 detection and advertisement. The USB D+ and D- are connected to the USB Host (DFP) or USB Device (UFP) from the Type-C connector for Charging Data Port applications.

9.2.1.4 USB Data Support Design Requirements

For USB3 operation, the SSTX/RX are muxed to the Type-C connector. A SuperSpeed Mux generally has two control signals; enable and plug orientation. The PD controller determines when a connection is detected and drives the required GPIO to control the SuperSpeed Mux.

9.2.2 Detailed Design Procedure

9.2.2.1 Programmable Power Supply (PPS)

The TPS25751 supports Programmable Power Supply (PPS) source and sink. When the TPS25751 negotiates a PPS contract as a source, the device enables the high-voltage power path (PPHV for D variant, PPEXT for S variant) and communicate with the supported TI battery charger (BQ25792 and BQ25756) to supply the negotiated voltage. TPS25751 only supports PPS within a 5V to 21V range according to PD 3.1 specification and is enabled through the Application Customization Tool. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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I2Cc_SDA I2Cc_SCL I2Cc_IRQ Battery Charger USB Type-C Connector SW SW VBUS PPHV GND System 5V PP5V GND CCx Vconn VINBAT PG I2C Target GPIO Figure 9-6. TPS25751D PPS with Battery Charger TPS25751S I2C Controller USB Type-C Connector SW SW VBUS GND CCx Vconn I2Cc_SDA I2Cc_SCL I2Cc_IRQ Battery Charger PPEXT System 5V PP5V GND I2C Target BAT VIN PG GPIO Figure 9-7. TPS25751S PPS with Battery Charger

9.2.2.2 Liquid Detection

The TPS25751 supports liquid detection using the built-in internal ADC and GPIO with external circuitry. Figure 9-8 and Figure 9-9 show the hardware implementation for liquid detection with the TPS25751. The TPD2S300 is used to protect the GPIO, ADC, and LDO_3V3 pins from over voltage conditions when there is liquid shorting VBUS to the SBU1/2 pins. Table 9-3 shows the recommended components used to implement the external liquid detection circuitry. When liquid is detected, the TPS25751 takes action to protect the Type-C port. Systems using an embedded host controller, can leverage the Host Interface for additional notification and control. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: TPS25751

LDO_3V3 GPIOx GPIO4 GPIOy GND Rup Rdown GPIO5 USB Type-C Connector SBU1 SBU2 GND TPD2S300 C_CC1 C_CC2 CC1 CC2 Liquid Detection + Protection Circuit Q_P1 Q_P2 Q_N1 Q_N2 3.3V Figure 9-8. TPS25751 Liquid Detection Block Diagram - 2 GPIO Control TPS25751 Rup Rdown LDO_3V3 GPIOx GPIO4 GND Rup Rdown GPIO5 USB Type-C Connector SBU1 SBU2 GND TPD2S300 C_CC1 C_CC2 CC1 CC2 Liquid Detection + Protection Circuit Q_P1 Q_P2 Q_N1 Q_N2 3.3V Figure 9-9. TPS25751 Liquid Detection Block Diagram - 1 GPIO Control Table 9-3. Component Recommendation Q_Pn (GPIO PMOS) Q_Nn (GPIO NMOS) Rup Rdown CSD25480F3 (Vgsth -0.95V or similar) CSD15380F3 (Vgsth 1.1V or similar) 100kOhm (5%) 1MOhm (5%)

9.2.2.2.1 Liquid Detection Operation

The TPS25751 supports liquid detection by measuring the voltage level across the SBU pins of the Type-C connector. When a short occurs across the SBU pins to another Type-C pin(s), the TPS25751 takes action to protect the the Type-C port by disabling the power paths and notifies the embedded controller when applicable. Once liquid has been detected, the TPS25751 continuously monitors the SBU voltage. During the SBU voltage monitoring, if the liquid/short is no longer present the TPS25751 takes action to return to normal operation. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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LDO_3V3 GPIOx/y GPIO4 GND GPIO5 USB Type-C Connector SBU1 SBU2 GND Liquid Detection + Protection Circuit VBUS CCx VBUS CCx 0V – 20V 0V – 3.3V (5V for Vconn) 3.3V FET Control RSaV RSaCC RSaG 3.3V Figure 9-10. TPS25751 Liquid Detection Operation 9.2.2.3 BC1.2 Application The TPS25751 supports BC1.2 detection and advertisement modes and are configurable through the Web Tool. TPS25751 USB Type-C Connector VBUS GND CCx/Vconn GPIO4 GPIO5 200 SW SW 1.2 V 2.7 V CDP Detect GPIO USB2.0 MuxUSB Host VBUS CCx/Vconn Figure 9-11. BC1.2 Application Block Diargam

9.2.2.4 USB Data Support

The TPS25751 supports USB data speed up to USB 3.2 Gen 2. When entering USB enumeration, the TPS25751 controls USB SuperSpeed Mux (TUSB1142) using GPIO controls. The GPIO control is configured through using the Application Customization Tool, GPIO events are found in the Technical Reference Manual. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: TPS25751

I2Cc_SDA I2Cc_SCL I2Cc_IRQ Battery Charger USB Type-C Connector SW SW VBUS PPHV GND System 5V PP5V GND CCx/Vconn I2C Target #1 VINBAT EEPROM I2C Target #2 I2C Target I2Ct_SDA I2Ct_SCL I2Ct_IRQ Host Control I2C Controller GPIO USB SS Mux CC Control and Vconn VBUS CCx/Vconn SSTX1/RX1 SSTX2/RX2 Liquid Detection *ADC + GPIO SBU1 SBU2 GND *BC1.2 DP DM SSTX/RX Figure 9-12. TPS25751D USB Data Support TPS25751SI2C Controller I2Cc_SDA I2Cc_SCL I2Cc_IRQ Battery Charger USB Type-C Connector SW VBUS PPEXT GND System 5V PP5V GND CCx/Vconn I2C Target #1 VINBAT EEPROM I2C Target #2 I2C Target I2Ct_SDA I2Ct_SCL I2Ct_IRQ Host Control I2C Controller GPIO USB SS Mux CC Control and Vconn VBUS CCx/Vconn SSTX1/RX1 SSTX2/RX2 Liquid Detection *ADC + GPIO SBU1 SBU2 GND *BC1.2 DP DM SSTX/RX SW Figure 9-13. TPS25751S USB Data Support

9.2.3 Application Curves

9.2.3.1 Programmable Power Supply (PPS) Application Curves

The following are captured when the TPS25751 is acting as a PPS Source. The VBUS plot shows the PPS negotiation increasing and decreasing from 5V to 21V to 5V. The PD negotaition snap shot shows the VBUS requested voltage increasing by 100mV. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Figure 9-14. PPS PD Negotiation VBUS Increasing/Decreasing Figure 9-15. PPS PD Negotiation Log

9.2.3.2 Liquid Detection Application Curves

The figures below shows the VBUS and Liquid Detection GPIO behavior when liquid is present on the SBU2 pin and when liquid is no longer present on SBU2. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: TPS25751

Liquid Present on SBU2 Liquid Detected, PD Controller takes ac on CC(CC1) VCONN(CC2) Figure 9-16. Liquid Detection Behavior - Liquid Present VBUS SBU1 SBU2 Liquid Detec on GPIO Resume Normal Opera onLiquid Removed CC(CC1) VCONN(CC2) Figure 9-17. Liquid Detection Behavior - Liquid Removed Liquid Detection occurs in burst which can be configured. When the PD Controller checks for liquid it toggles the SBU1/2 circuitry, and pulls down the SBU1/2 circuitry when liquid detection is disabled. Liquid Detec on Enabled Liquid Detec on Disabled Liquid Detec on Enabled Liquid Detec on Disabled SBU Toggle SBU Low SBU Toggle SBU Low Figure 9-18. Liquid Detection and SBU1/2 Toggle TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Figure 9-21. BC1.2 DCP Detection Figure 9-22. BC1.2 CDP Detection

9.2.3.4 USB Data Support Application Curves

The following show the control signals used by a USB SuperSpeed Mux. For a normal orientation, the CC1 pin is connected. For a flipped orientation, the CC2 pin is connected. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Figure 9-23. USB SuperSpeed Mux Control - Normal Orientation Figure 9-24. USB SuperSpeed Mux Control - Flipped Orientation

9.3 Power Supply Recommendations

9.3.1 3.3-V Power

9.3.1.1 VIN_3V3 Input Switch

The VIN_3V3 input is the main supply of the TPS25751 device. The VIN_3V3 switch (see Power Management) is a uni-directional switch from VIN_3V3 to LDO_3V3, not allowing current to flow backwards from LDO_3V3 to VIN_3V3. This switch is on when the 3.3-V supply is available and the dead-battery flag is cleared. The www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: TPS25751

recommended capacitance C VIN_3V3 (see Recommended Capacitance) must be connected from the VIN_3V3 pin to the GND pin). 9.3.2 1.5-V Power 1.5-V LDO provides power to all internal low-voltage digital circuits which includes the digital core, and memory. The 1.5-V LDO also provides power to all internal low-voltage analog circuits. Connect the recommended capacitance CLDO_1V5 (see Recommended Capacitance) from the LDO_1V5 pin to the GND pin.

9.3.3 Recommended Supply Load Capacitance

Recommended Capacitance lists the recommended board capacitances for the various supplies. The typical capacitance is the nominally rated capacitance that must be placed on the board as close to the pin as possible. The maximum capacitance must not be exceeded on pins for which it is specified. The minimum capacitance is minimum capacitance allowing for tolerances and voltage derating ensuring proper operation.

9.4 Layout

9.4.1 TPS25751D - Layout

9.4.1.1 Layout Guidelines

Proper routing and placement maintain signal integrity for high speed signals and improve the heat dissipation from the power paths. The combination of power and high speed data signals are easily routed if the following guidelines are followed. Best practice is to consult with board manufacturing to verify manufacturing capabilities.

9.4.1.1.1 Recommended Via Size

Proper via stitching is recommended to carrying current for the VBUS power paths and grounding. The recommended minimum via size is shown below, but larger vias are an option for low density PCB designs. A single via is capable of carrying 1A, verify the tolerance with the board manufacturing. Vias are recommended to be tented when located close to the PD controller. 16mil8mil Figure 9-25. Recommend Minimum Via Size

9.4.1.1.2 Minimum Trace Widths

Below are the minimum trace widths for analog and digital pins. The trace width limitations are also defined by the board manufacturing process used. Consult with manufacturing for determining the minimum trace widths and tolerance. Table 9-4. Minimum Trace Width Route Minimum Width (mils) CC1, CC2 10 VIN_3V3, LDO 10 Component GND 16 TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Table 9-4. Minimum Trace Width (continued) Route Minimum Width (mils) GPIO 4

9.4.1.2 Layout Example

9.4.1.2.1 TPS25751D Schematic Layout Example

Follow the differential impedances for Super / High Speed signals defined by their specifications (USB2.0). All I/O are fanned out to provide an example for routing out all pins, not all designs utilize all of the I/O on the TPS25751D. L D O _ 3 V 3 1 V I N _ 3 V 3 38 A D C I N 1 2 A D C I N 2 3 G P I O 0 5 G P I O 1 6 G P I O 2 7 G P I O 3 19 G P I O 4 / U S B _ P / M D 1 26 G P I O 5 / U S B _ N / M D 2 2 7 G P I O 6 3 7 G P I O 7 36 G P I O 1 1 13 I 2 C t _ S C L 9 I 2 C t _ S D A 8 D R A I N 15 D R A I N 30 D R A I N _ P A D 40 I 2 C c _ I R Q 1 8 I 2 C t _ I R Q 10 L D O _ 1 V 5 4 P P 5 V 34 P P H V 2 0 I 2 C c _ S C L 17 I 2 C c _ S D A 1 6 V B U S 3 2 V B U S _ I N 2 3 C C 1 28 C C 2 2 9 G N D 11 G N D 12 G N D 1 4 G N D 3 1 G N D _ P A D 3 9 V B U S 33 V B U S _ I N 24 V B U S _ I N 25 P P 5 V 35 P P H V 2 1 P P H V 22 T P S 2 5 7 5 1 D R E F R U 1 G N D A 1 S S T X p 1 A 2 S S T X n 1 A 3 V B U S A 4 C C 1 A 5 D p 1 A 6 D n 1 A 7 S B U 1 A 8 V B U S A 9 S S R X n 2 A 1 0 S S R X p 2 A 1 1 G N D B 1 2 S S R X p 1 B 1 1 S S R X n 1 B 1 0 V B U S B 9 S B U 2 B 8 C C 2 B 5 V B U S B 4 S S T X n 2 B 3 S S T X p 2 B 2 G N D B 1 G N D A 1 2 S H I E L D S 1 S H I E L D S 2 S H I E L D S 3 S H I E L D S 4 D p 2 B 6 D n 2 B 7 J 1 D X 0 7 S 0 2 4 J J 2 R 1 3 0 0 P 3 V 3 V B U S P P 5 V L D O _ 3 V 3 L D O _ 1 V 5 0 . 0 1 u F C 2 0 . 0 1 u F C 3 0 . 0 1 u F C 4 0 . 0 1 u F C 5 G N D 1 0 u F C 9 G N D 1 0 0 u F C 6 1 0 0 u F C 7 I 2 C t _ S C L I 2 C t _ S D A I 2 C t _ I R Q I 2 C c _ S C L I 2 C c _ S D A I 2 C c _ I R Q R 6 1 0 k Ω R 3 1 0 k Ω L D O _ 3 V 3 R 5 2 . 2 k ΩR 4 2 . 2 k Ω R 2 2 . 2 k ΩR 1 2 . 2 k Ω G N D G P I O 0 G P I O 1 G P I O 2 G P I O 3 G P I O 4 G P I O 5 G P I O 6 G P I O 7 G P I O 1 1 D R A I N A D C I N 1 A D C I N 2 3 3 0 p F C 1 1 3 3 0 p F C 1 0 G N D C C 1 C C 2 2 2 u F C 1 2 2 2 u F C 1 3 G N D P P H V P 3 V 3 L D O _ 1 V 5 L D O _ 3 V 3 G N D G N D G N D G N D G N D V B U S V B U S V B U S V B U S C C 1 C C 2 4 . 7 u F C 1 1 0 u F C 1 7 1 0 u F C 1 6 1 0 u F C 1 5 1 0 u F C 8 0 . 1 u F C 1 4 I N 4 I N 5 G N D 1 G N D 2 I N 6 G N D 3 P A D 7 T V S 2 2 0 0 D R V R U 2 G N D Figure 9-26. TPS25751D Example Schematic

9.4.1.2.2 TPS25751D Layout Example - PCB Plots

The following TPS25751D PCB Layout figures show the recommended layout, placement, and routing. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: TPS25751

Figure 9-27. TPS25751D PCB Layout - Top Composite Figure 9-28. TPS25751D PCB Layout - Bottom Composite TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Figure 9-31. TPS25751D PCB Layout - GND Layer Figure 9-32. TPS25751D PCB Layout - Bottom Layer LDO_1V5 (pin 4), LDO_3V3 (pin 1), and VIN_3V3 (pin 38) TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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The decoupling capacitors for LDO_3V3, LDO_1V5, and VIN_3V3 (C15, C16, and C17 respectively) need to be placed as close as possible to TPS25751D device for optimal performance. For this example to minimize solution size, the decoupling capacitors are placed on the bottom layer with their ground pads directly underneath the ground pad of TPS25751D. Use a maximum of one via per pin from TPS25751D to the decoupling capacitors if placed on a different layer. Use a minimum of 10mil trace width to route these three traces, preferably with 16mil trace width if possible. CC1 (pin 28) and CC2 (pin 29) CC1 (C11) and CC2 (C10) capacitors need to be placed as close as possible to their respective pins and on the same layer as the TPS25751D device. When routing the CCx traces, DO NOT via to another layer in between the CCx pins of the TPS25751D to the CCx capacitors. Check to make sure the CCx capacitors are not place outside the CC trace creating an antenna, instead have the traces pass directly through the CCx capacitor pads as shown in the example layout (refer to figure 10-14 ). Use a minimum of 10mil trace width to ensure Vconn support (5V/0.6A). The 10uF decoupling capacitor (C9) need to be placed as close as possible to the PP5V pins of TPS25751D. DO NOT use traces for PP5V. The PP5V power plane needs to be sized to support up to 3.6A (up to 3A for sourcing, 600mA for Vconn). When connecting the PP5V pins (pins 34 and 35) to the 5V power plane, use a minimum of 4 vias in parallel and close to the device to improve current sharing. Minimize the bottle necks cause by other vias or traces, large bottle necks reduces the efficiency of the power plane. The bulk capacitors (C6, C7, and C8) represent capacitances from the system 5V rail, these are placed further away from TPS25751D on the same PP5V power plane. Refer to figure 10-14 and figure 10-15 for placement and trace reference. Place the PPHV decoupling capacitors (C12, C13, and C14) as close as possible to TPS25751D, these do not need to be on the same layer as the device. The PPHV power plane needs to be sized to support up to 5A of current. When connecting the PPHV plane to a different layer, use a minimum of 6 vias in parallel per layer change. It is highly recommended to have more than 6 vias if possible for layer change to improve current sharing and efficiency. VBUS (pins 32 and 33) and VBUS_IN (pins 23, 24, and 25) Place the VBUS decoupling capacitor (C1) as close as possible to TPS25751D, the capacitor does not need to be on the same layer as the device. The VBUS power plane need to be sized to support up to 5A of current if 100W application is required. When connecting the VBUS pins (pins 32 and 33) plane to a different layer, use a minimum of 3 vias per layer change. When connecting the VBUS_IN pins (pins 23, 24, and 25) plane to a different layer, use a minimum of 6 vias per layer change. Refer to figure 10-14 and figure 10-15 for capacitors and via placement. At the Type-C port/connector, it is recommended to use minimum of 6 vias from the connector VBUS pins for layer changes. Place the 10nF caps (C2, C3, C4, and C5) and the 22V TVS diode (U2) as close as possible to the connector VBUS pins as shown in figure 10-15. When routing the VBUS power plane from the Type-C connector to the TPS25751D VBUS pins, minimize bottle necks caused by other vias and traces to improve current flow. The example layout shown in figure 10-17 uses an internal layer to route the VBUS plane from the connector to TPS25751D. I2C, ADCIN1/2, and GPIO pins Fan these traces out from the TPS25751D, use vias to connect the net to a routing layer if needed. For these nets, use 4mil to 10mil trace width. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: TPS25751

I2Cc_SDA/SCL/IRQ (pins 8, 9, and 10) and I2Ct_SCL/SDA/IRQ (pins 16, 17, and 18) Minimize trace width changes to avoid I2C communication issues. ADCIN1 and ADCIN2 (pins 2 and 3) Keep the ADCINx traces away from switching elements. If a resistor divider is used, place the divider close to LDO_3V3 or LDO_1V5. GPIO (pins 5, 6, 7, 19, 26, 27, 37, 36, and 13) Separate GPIO traces running in parallel by a trace width. Keep the GPIOx traces away from switching elements. The DRAIN pad is used to dissipate heat for the internal high voltage power path (PPHV). Connect the Drain pins (pins 15 and 30) to the Drain pad underneath the TPS25751D device. Connect the through hole vias from the drain pad on the top layer to a copper pour on the bottom layer to help dissipate heat. Additional vias can be added to improve thermal dissipation. The GND pad is used to dissipate heat for the TPS25751D device. Connect the GND pins (pins 11, 12, 14 and 31) to the Ground pad underneath the TPS25751D device. Connect the through hole vias from the ground pad on the top layer to a copper pour on the bottom layer to help dissipate heat. Additional vias can be added to improve thermal dissipation. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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9.4.2 TPS25751S - Layout

9.4.2.1 Layout Guidelines

Proper routing and placement maintain signal integrity for high speed signals and improve the heat dissipation from the power paths. The combination of power and high speed data signals are easily routed if the following guidelines are followed. Best practice is to consult with board manufacturing to verify manufacturing capabilities.

9.4.2.1.1 Recommended Via Size

Proper via stitching is recommended to carrying current for the VBUS power paths and grounding. The recommended minimum via size is shown below, but larger vias are an option for low density PCB designs. A single via is capable of carrying 1A, verify the tolerance with the board manufacturing. Vias are recommended to be tented when located close to the PD controller. 16mil8mil Figure 9-33. Recommend Minimum Via Size

9.4.2.1.2 Minimum Trace Widths

Below are the minimum trace widths for analog and digital pins. The trace width limitations are also defined by the board manufacturing process used. Consult with manufacturing for determining the minimum trace widths and tolerance. Table 9-5. Minimum Trace Width Route Minimum Width (mils) CC1, CC2 10 VIN_3V3, LDO 10 Component GND 16 GPIO 4

9.4.2.2 Layout Example

9.4.2.2.1 TPS25751S Schematic Layout Example

Follow the differential impedances for Super / High Speed signals defined by their specifications (USB2.0). All I/O are fanned out to provide an example for routing out all pins, not all designs utilize all of the I/O on the TPS25751S. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: TPS25751

S H I E L D S 2 S H I E L D S 3 S H I E L D S 4 D p 2 B 6 D n 2 B 7 J 1 D X 0 7 S 0 2 4 J J 2 R 1 3 0 0 P 3 V 3 V B U S P P 5 V L D O _ 3 V 3 L D O _ 1 V 5 0 . 0 1 u F C 2 0 . 0 1 u F C 3 0 . 0 1 u F C 4 0 . 0 1 u F C 5 G N D 1 0 u F C 9 G N D 1 0 0 u F C 6 1 0 0 u F C 7 I 2 C t _ S C L I 2 C t _ S D A I 2 C t _ I R Q I 2 C c _ S C L I 2 C c _ S D A I 2 C c _ I R Q R 6 1 0 k Ω R 3 1 0 k Ω L D O _ 3 V 3 R 5 2 . 2 k ΩR 4 2 . 2 k Ω R 2 2 . 2 k ΩR 1 2 . 2 k Ω G N D G P I O 0 G P I O 1 G P I O 2 G P I O 3 G P I O 4 G P I O 5 G P I O 6 G P I O 7 G P I O 1 1 A D C I N 1 A D C I N 2 3 3 0 p F C 1 1 3 3 0 p F C 1 0 G N D C C 1 C C 2 2 2 u F C 1 2 2 2 u F C 1 3 1 0 u F C 1 4 G N D P P H V P 3 V 3 L D O _ 1 V 5 L D O _ 3 V 3 G N D G N D G N D G N D G N D V B U S V B U S V B U S V B U S C C 1 C C 2 4 . 7 u F C 1 L D O _ 3 V 3 1 V I N _ 3 V 3 32 A D C I N 1 2 A D C I N 2 3 G P I O 0 5 G P I O 1 6 G P I O 2 7 G P I O 3 18 G P I O 4 / U S B _ P / M D 1 22 G P I O 5 / U S B _ N / M D 2 23 G P I O 6 31 G P I O 7 30 G P I O 1 1 13 I 2 C t _ S C L 9 I 2 C t _ S D A 8 I 2 C c _ S C L 16 I 2 C c _ S D A 15 I 2 C c _ I R Q 1 7 I 2 C t _ I R Q 10 L D O _ 1 V 5 4 V S Y S 1 9 G A T E _ V B U S 2 1 G A T E _ V S Y S 20 C C 1 2 4 C C 2 25 V B U S 2 6 V B U S 2 7 P P 5 V 2 8 P P 5 V 2 9 G N D 11 G N D 12 G N D 1 4 G N D 3 3 T P S 2 5 7 5 1 S R S M R U 1 A 2 A 1 B 2 B 1 C 2 C 1 D 2 D 1 E 2 E 1 Q 1 C S D 8 7 5 0 1 L G A T E _ V B U S G A T E _ V S Y S V B U S P P H V G A T E _ V B U S G A T E _ V S Y S 1 0 u F C 1 7 1 0 u F C 1 6 1 0 u F C 1 5 1 0 u F C 8 I N 4 I N 5 G N D 1 G N D 2 I N 6 G N D 3 P A D 7 T V S 2 2 0 0 D R V R U 2 G N D Figure 9-34. TPS25751S Example Schematic

9.4.2.2.2 TPS25751S Layout Example - PCB Plots

The following TPS25751S PCB Layout figures show the recommended layout, placement, and routing. Figure 9-35. TPS25751S PCB Layout - Top Composite TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Figure 9-38. TPS25751S PCB Layout - Internal Power Layer Figure 9-39. TPS25751S PCB Layout - GND Layer TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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Figure 9-40. TPS25751S PCB Layout - Bottom Layer LDO_1V5 (pin 4), LDO_3V3 (pin 1), and VIN_3V3 (pin 32) The decoupling capacitors for LDO_3V3, LDO_1V5, and VIN_3V3 (C15, C16, and C17 respectively) need to be placed as close as possible to TPS25751S device for optimal performance. For this example to minimize solution size, the decoupling capacitors are placed on the bottom layer with their ground pads directly underneath the ground pad of TPS25751S. Use a maximum of one via per pin from TPS25751S to the decoupling capacitors if placed on a different layer. Use a minimum of 10mil trace width to route these three traces, preferably with 16mil trace width if possible. CC1 (pin 24) and CC2 (pin 25) CC1 (C11) and CC2 (C10) capacitors need to be placed as close as possible to their respective pins and on the same layer as the TPS25751S device. When routing the CCx traces, DO NOT via to another layer in between the CCx pins of the TPS25751S to the CCx capacitors. Check to make sure the CCx capacitors are not place outside the CC trace creating an antenna, instead have the traces pass directly through the CCx capacitor pads as shown in the example layout (refer to figure 10-21). Use a minimum of 10mil trace width to ensure Vconn support (5V/0.6A). The 10uF decoupling capacitor (C8) need to be placed as close as possible to the PP5V pins of TPS25751S. DO NOT use traces for PP5V. The PP5V power plane needs to be sized to support up to 3.6A (up to 3A for sourcing, 600mA for Vconn). When connecting the PP5V pins (pins 28 and 29) to the 5V power plane, use a minimum of 4 vias in parallel and close to the device to improve current sharing. Minimize the bottle necks cause by other vias or traces, large bottle necks reduces the efficiency of the power plane. The bulk capacitors (C6, C7, and C9) represent capacitances from the system 5V rail, these are placed further away from TPS25751S on the same PP5V power plane. Refer to figure 10-21 and figure 10-22 for placement and trace reference. Place the PP_EXT decoupling capacitors (C12, C13, and C14) as close as possible to TPS25751S, these do not need to be on the same layer as the device. The PP_EXT power plane needs to be sized to support up to www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: TPS25751

5A of current. When connecting the PP_EXT plane to a different layer, use a minimum of 6 vias in parallel per layer change. It is highly recommended to have more than 6 vias if possible for layer change to improve current sharing and efficiency. VSYS (pin 19) The VSYS pin (pin 19) can be connected with a trace (recommended 6mil trace width) to any of the vias on the PPHV plane. It is recommended to connect to a via close to the source pin of the VSYS N-ch MOSFET(pins A2, B2, D2, and E2 of the Q1 FET in the example schematic) to improve reverse current sensing protection. Refer to VBUS (pins 26 and 27) Place the VBUS decoupling capacitor (C1) as close as possible to TPS25751S, the capacitor does not need to be on the same layer as the device. The VBUS power plane need to be sized to support up to 5A of current if 100W application is required. When connecting the VBUS pins (pins 26 and 27) plane to a different layer, use a minimum of 3 vias per layer change. When connecting the VBUS power plane to a different layer, use a minimum of 6 vias per layer change. Refer to figure 10-21 and figure 10-22 for capacitors and via placement. At the Type-C port/connector, it is recommended to use minimum of 6 vias from the connector VBUS pins for layer changes. Place the 10nF caps (C2, C3, C4, and C5) and the 22V TVS diode (U2) as close as possible to the connector VBUS pins as shown in figure 10-22. When routing the VBUS power plane from the Type-C connector to the TPS25751S VBUS pins, minimize bottle necks caused by other vias and traces to improve current flow. The example layout shown in figure 10-24 uses an internal layer to route the VBUS plane from the connector to TPS25751S. I2C, ADCIN1/2, and GPIO pins Fan these traces out from the TPS25751S, use vias to connect the net to a routing layer if needed. For these nets, use 4mil to 10mil trace width. I2Cc_SDA/SCL/IRQ (pins 8, 9, and 10) and I2Ct_SCL/SDA/IRQ (pins 15, 16, and 17) Minimize trace width changes to avoid I2C communication issues. ADCIN1 and ADCIN2 (pins 2 and 3) Keep the ADCINx traces away from switching elements. If a resistor divider is used, place the divider close to LDO_3V3 or LDO_1V5. GPIO (pins 5, 6, 7, 18, 22, 23, 31, 30, and 13) Separate GPIO traces running in parallel by a trace width. Keep the GPIOx traces away from switching elements. GATE_VSYS (pin 20) The GATE_VSYS pin (pin 20) can be connected with a trace (recommended 6mil trace width) to the gate pins of the N-ch MOSFET with source tied to PPHV. It is recommended to NOT via directly to the gate pin of the N-ch MOSFET, instead use via(s) to connect the GATE_VSYS pin from the TPS25751S to the gate pin of the N-ch MOSFET. Refer to figure 10-21 and figure 10-22 for examples on how to connect the traces. GATE_VBUS (pin 21) The GATE_VBUS pin (pin 21) can be connected with a trace (recommended 6mil trace width) to the gate pins of the N-ch MOSFET with source tied to VBUS. It is recommended to NOT via directly to the gate pin of the N-ch MOSFET, instead use via(s) to connect the GATE_VBUS pin from the TPS25751S to the gate pin of the N-ch MOSFET. Refer to figure 10-21 and figure 10-22 for examples on how to connect the traces. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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The GND pad is used to dissipate heat for the TPS25751S device. Connect the GND pins (11, 12, 14 and 31) to the Ground pad (39) underneath the TPS25751S device. Connect the through hole vias from the ground pad on the top layer to a copper pour on the bottom layer to help dissipate heat. Additional vias can be added to improve thermal dissipation. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: TPS25751

10 Device and Documentation Support

10.1 Device Support

10.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

10.1.2 Firmware Warranty Disclaimer

IN ORDER FOR THE DEVICE TO FUNCTION IN ACCORDANCE WITH THE RELEVANT SPECIFICATIONS, YOU WILL NEED TO DOWNLOAD THE LATEST VERSION OF THE FIRMWARE FOR THE DEVICE (SEE SECTION ON RECEIVING NOTIFICATION OF DOCUMENTATION AND FIRMWARE UPDATES). IF YOU DO NOT DOWNLOAD AND INCORPORATE THE LATEST VERSION OF THE FIRMWARE INTO THE DEVICE, THEN THE DEVICE IS PROVIDED “AS IS” AND TI MAKES NO WARRANTY OR REPRESENTATION WHATSOEVER IN RESPECT OF SUCH DEVICE, AND DISCLAIMS ANY AND ALL WARRANTIES AND REPRESENTATIONS WITH RESPECT TO SUCH DEVICE. FURTHER, IF YOU DO NOT DOWNLOAD AND INCORPORATE THE LATEST VERSION OF THE FIRMWARE INTO THE DEVICE, TI WILL NOT BE LIABLE FOR AND SPECIFICALLY DISCLAIMS ANY DAMAGES, INCLUDING DIRECT DAMAGES, HOWEVER CAUSED, WHETHER ARISING UNDER CONTRACT, TORT, NEGLIGENCE, OR OTHER THEORY OF LIABILITY RELATING TO THE DEVICE, EVEN IF TI IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

10.2 Documentation Support

10.2.1 Related Documentation

• USB-PD Specifications
• USB Power Delivery Specification

10.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. USB Type-C® is a registered trademark of USB Implementers Forum. All trademarks are the property of their respective owners.

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES October 2023 * Advance Information

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

12.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: TPS25751

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS25751SRSMR VQFN RSM 32 3000 367.0 367.0 35.0 TPS25751DREFR WQFN REF 38 3000 367.0 367.0 35.0 TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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www.ti.com PACKAGE OUTLINE C 32X 0.25 0.15 2.8 0.05 32X 0.45 0.25

1 MAX

(0.2) TYP 0.05 0.00 28X 0.4 2.8 2X 2.8 A 4.1 3.9 B 4.1 3.9 0.25 0.15 0.45 0.25 4X (0.45) VQFN - 1 mm max heightRSM0032B PLASTIC QUAD FLATPACK - NO LEAD 4219108/A 11/2017 PIN 1 INDEX AREA 0.08 C SEATING PLANE 8 17 9 16 32 25 (OPTIONAL) PIN 1 ID

0.1 C A B

0.05 EXPOSED THERMAL PAD DETAIL SEE TERMINAL SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. OPTIONAL TERMINAL SCALE 3.000 DETAIL TYPICAL www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: TPS25751

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MIN

0.05 MAX

32X (0.2) 32X (0.55) ( 0.2) TYP VIA 28X (0.4) (3.85) (3.85) ( 2.8) (R0.05) TYP (1.15) (1.15) VQFN - 1 mm max heightRSM0032B PLASTIC QUAD FLATPACK - NO LEAD 4219108/A 11/2017 SYMM 9 16 2532 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) EXPOSED METAL TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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www.ti.com EXAMPLE STENCIL DESIGN 32X (0.55) 32X (0.2) 28X (0.4) (3.85) (3.85) 4X ( 1.23) (R0.05) TYP (0.715) (0.715) VQFN - 1 mm max heightRSM0032B PLASTIC QUAD FLATPACK - NO LEAD 4219108/A 11/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP BASED ON 0.1 mm THICK STENCIL SOLDER PASTE EXAMPLE EXPOSED PAD 33: 77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 9 16 2532 www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: TPS25751

www.ti.com PACKAGE OUTLINE C 38X 0.45 0.25 0.8 0.7 (0.2) TYP 0.05 0.00 30X 0.4 2X 4.8 1.63 1.43 2X 2.75 2.55 2.82 2.62 38X 0.25 0.15 2.2 4X 0.45 (0.2) 0.45 0.25 0.25 0.15 0.965 1.56 A 6.1 5.9 B 4.1 3.9 WQFN - 0.8 mm max heightREF0038A PLASTIC QUAD FLATPACK - NO LEAD 4226763/C 11/2021 PIN 1 INDEX AREA 0.08 C SEATING PLANE 38 26 X 0.3)(45 PIN 1 ID

0.07 C A B

0.05 EXPOSED THERMAL PAD 39SYMM PKG SEE DETAIL A NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance. DETAIL A TYPICAL SCALE 2.800 TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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www.ti.com EXAMPLE BOARD LAYOUT 30X (0.4) 30X (0.55) 38X (0.2) (1.56) (1.53) (2.72) (1.075) (0.45) 4X (0.2) (2.925) (3.2) 2X (0.55) (R0.05) TYP ( 0.2) TYP VIA (3.85)2X (2.65) (2.075) (0.145)(0.965) WQFN - 0.8 mm max heightREF0038A PLASTIC QUAD FLATPACK - NO LEAD 4226763/C 11/2021 PKG 7 19 2638 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X 39 40 SOLDER MASK OPENING METAL UNDER SOLDER MASK NOTES: (continued) 4. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED PADS 20-25 & 32-35 EXPOSED METAL METAL SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS NOT TO SCALE DEFINED EXPOSED METAL www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: TPS25751

www.ti.com EXAMPLE STENCIL DESIGN 2X (0.27) 30X (0.55) 38X (0.2) 30X (0.4) (0.45) 4X (0.2) (2.925) (3.2) 2X (0.55) (3.85) 4X (1.19) (0.69) (R0.05) TYP (1.17) 2X (1.4) WQFN - 0.8 mm max heightREF0038A PLASTIC QUAD FLATPACK - NO LEAD 4226763/C 11/2021 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. PKG METAL TYP BASED ON 0.1 mm THICK STENCIL SOLDER PASTE EXAMPLE EXPOSED PADS 39 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE EXPOSED PADS 40 80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 7 19 2638 39 40 METAL UNDER SOLDER MASK TPS25751 SLVSH93 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION

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www.ti.com 22-Nov-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTPS25751DREFR ACTIVE WQFN REF 38 3000 TBD Call TI Call TI -40 to 125 Samples PTPS25751SRSMR ACTIVE VQFN RSM 32 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 22-Nov-2023 Addendum-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRSM 32 PLASTIC QUAD FLATPACK - NO LEAD4 x 4, 0.4 mm pitch 4224982/A

www.ti.com PACKAGE OUTLINE C 32X 0.25 0.15 2.8 0.05 32X 0.45 0.25 (0.2) TYP 0.05 0.00 28X 0.4 2.8 2X 2.8 A 4.1 3.9 B 4.1 3.9 0.25 0.15 0.45 0.25 4X (0.45) (0.1) VQFN - 1 mm max heightRSM0032B PLASTIC QUAD FLATPACK - NO LEAD 4219108/B 08/2019 PIN 1 INDEX AREA 0.08 C SEATING PLANE 8 17 9 16 32 25 (OPTIONAL) PIN 1 ID 0.05 EXPOSED THERMAL PAD DETAIL SEE TERMINAL SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SEE SIDE WALL DETAIL SIDE WALL DETAIL OPTIONAL METAL THICKNESS SCALE 3.000 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT 32X (0.2) 32X (0.55) ( 0.2) TYP VIA 28X (0.4) (3.85) (3.85) ( 2.8) (R0.05) TYP (1.15) (1.15) VQFN - 1 mm max heightRSM0032B PLASTIC QUAD FLATPACK - NO LEAD 4219108/B 08/2019 SYMM 9 16 2532 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 32X (0.55) 32X (0.2) 28X (0.4) (3.85) (3.85) 4X ( 1.23) (R0.05) TYP (0.715) (0.715) VQFN - 1 mm max heightRSM0032B PLASTIC QUAD FLATPACK - NO LEAD 4219108/B 08/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 33: 77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 9 16 2532

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