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Technical content

TPS20xxE Current-Limited, Power-Distribution Switches

1 Features

  • Single power switch family
  • Pin-to-pin with existing TI Switch Portfolio
  • Rated currents of 1.5 A and 2 A
  • Supports 3.3-V and 5-V power rail
  • ±20% accurate, fixed, constant current limit
  • Fast overcurrent response: 2 µs
  • Deglitched fault reporting
  • Output discharge
  • Reverse current blocking
  • Built-in soft start
  • Ambient temperature range: –40°C to 85°C

2 Applications

  • PC and notebooks
  • Gaming
  • TV
  • Connected peripherals and printers
  • Data center and enterprise computing
  • Short-circuit protection

3 Description

The TPS20xxE power-distribution switch family is intended for applications, such as USB, where heavy capacitive loads and short circuits are likely to be encountered. This family offers fixed current-limit thresholds for applications requiring 1.5-A or 2-A loading, with options between high or low enable polarization in different packages. The TPS20xxE family limits the output current to a safe level by operating in a constant-current mode when the output load exceeds the current limit threshold. This provides a predictable fault current under all conditions. The fast overload response time eases the burden on the 2.7-V – 5.5-V supply to provide regulated power when the output is shorted. The power-switch rise and fall times are controlled to minimize current surges during turn-on and turn-off. Device Information PART NUMBER(1) PACKAGE(2) PACKAGE SIZE(3) TPS20xxE DBV (SOT-23, 5) 2.90 mm × 1.60 mm DGN (HVSSOP, 8) PowerPAD™ 3.00 mm × 3.00 mm DGK (VSSOP, 8) 3.00 mm × 3.00 mm (1) See the Device Comparison Table. (2) For all available packages, see the orderable addendum at the end of the data sheet. (3) The package size (length × width) is a nominal value and includes pins, where applicable. IN GNDFLT Control Signal VIN 0.1uF 120 uF Fault Signal VOUT EN or OUT 10k TPS20xxE Pad* EN * DGN only USB requirement only USB requirement that downstream facing ports are bypassed with at least 120uF per hub Typical Application Diagram TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10.2 Receiving Notification of Documentation Updates..19

11 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (May 2023) to Revision A (July 2023) Page TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 www.ti.com

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5 Device Comparison Table

DISCHARGE ENABLE BASE PART NUMBER PACKAGED DEVICE AND MARKING(1) DBV (SOT-23, 5) DGN (HVSSOP, 8)PowerPAD™ DGK (VSSOP, 8)(2)

1.5 Y Low TPS2068E 2068E 2068E -

1.5 Y High TPS2069E 2069E 2069E -

2 Y Low TPS2000E 2000E 2000E 000E

2 Y High TPS2001E 2001E 2001E 001E

(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) "–" indicates the device is not available in this package. www.ti.com TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS2000E TPS2001E TPS2068E TPS2069E

6 Pin Configuration and Functions

Figure 6-1. DGN Package 8-Pin MSOP-PowerPAD™ Top View 1GND 8 OUT 2IN 7 OUT 3IN 6 OUT 4EN/EN 5 FL T Figure 6-2. DGK Package 8-Pin VSSOP Top View Table 6-1. Pin Functions - 8 Pins PIN I/O DESCRIPTION NAME NO. EN/ EN 4 I Enable input, logic high turns on power switch FLT 5 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions GND 1 — Ground connection IN 2, 3 PWR Input voltage and power-switch drain; connect a 0.1-µF or greater ceramic capacitor from IN to GND close to the IC OUT 6, 7, 8 PWR Power-switch output, connect to load PowerPAD (DGN Only) PowerPAD — Connect PAD to GND plane as a heatsink for the best thermal performance. PAD may be left floating if desired. 1OUT 2GND 3FL T 4 EN/EN 5 IN Figure 6-3. DBV Package 5-Pin SOT-23 Top View Table 6-2. Pin Functions - 5 Pins PIN I/O DESCRIPTION NAME NO. EN/ EN 4 I Enable input, logic high turns on power switch FLT 3 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions GND 2 — Ground connection IN 5 PWR Input voltage and power-switch drain; connect a 0.1-µF or greater ceramic capacitor from IN to GND close to the IC OUT 1 PWR Power-switch output, connect to load. TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 www.ti.com

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VIN Input voltage –0.3 6 V VOUT Output voltage –0.3 6 V VEN Input voltage –0.3 6 V VFLT Voltage range –0.3 6 V IOUT Continuous output current Internal Limited TJ Junction temperature –40 125 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JS-002, all pins(2) ±500 V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge, OUT pin(3) ±8000 V V(ESD) Electrostatic discharge IEC 61000-4-2 air-gap discharge, OUT pin(3) ±15000 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. (3) VOUT was surged on a PCB with input and output bypassing per the Typical Application Diagram on the first page with no device failures.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage 2.7 5.5 V VEN Input voltage, EN or EN 0 5.5 V VIH High-level input voltage, EN or EN 1.8 V VIL Low-level input voltage, EN or EN 0.8 V IOUT Continuous output current - TPS2068E, TPS2069E 1.5 A IOUT Continuous output current - TPS2000E, TPS2001E 2 A TJ Junction temperature –40 125 °C IFLT Sink current into FLT 0 10 mA www.ti.com TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS2000E TPS2001E TPS2068E TPS2069E

7.4 Thermal Information

THERMAL METRIC(1) TPS20xxE UNITDBV (SOT-23)

5 PINS

RθJA Junction-to-ambient thermal resistance 184.6 ℃/W RθJC(top) Junction-to-case (top) thermal resistance 92.6 RθJB Junction-to-board thermal resistance 59.9 ΨJT Junction-to-top characterization parameter 30.7 ΨJB Junction-to-board characterization parameter 59.6 RθJC(bot) Junction-to-case (bottom) thermal resistance - (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Unless otherwise noted: VIN = 5.5 V, VEN = VIN, IOUT = 0 A, –40°C ≤ TJ ≤ 125°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SWITCH (TPS2068E, TPS2069E) RDS(ON) (DBV) Static drain-source on-state resistance, 5V or 3.3V operation VIN = 5 V or 3.3 V, IO = 1.5 A, -40°C ≤ TJ ≤ 125°C 70 105 mΩ Static drain-source on-state resistance, 2.7V operation VIN = 2.7 V, IO = 1.5 A, –40°C ≤ TJ ≤ 125°C 70 110 mΩ POWER SWITCH (TPS2000E, TPS2001E) RDS(ON) (DBV) Static drain-source on-state resistance, 5V or 3.3V operation VIN = 5 V or 3.3 V, IO = 2.0 A, -40°C ≤ TJ ≤ 125°C 70 105 mΩ Static drain-source on-state resistance, 2.7V operation VIN = 2.7 V, IO = 2.0 A, –40°C ≤ TJ ≤ 125°C 70 110 mΩ Trise and Tfall tr Rise time, output VIN = 5.5 V, CL = 1 uF, RL = 10 Ω, TJ = 25°C 0.6 1.5 ms VIN = 2.7 V, CL = 1 uF, RL = 10 Ω, TJ = 25°C 0.4 1 ms tf Fall time, output VIN = 5.5 V, CL = 1 uF, RL = 10 Ω, TJ = 25°C 0.05 0.5 ms VIN = 2.7 V, CL = 1 uF, RL = 10 Ω, TJ = 25°C 0.05 0.5 ms ENABLE INPUT EN VIH Enable High-level input voltage 2.7 V ≤ VIN ≤ 5.5 V 1.8 V VIL Enable Low-level input voltage 2.7 V ≤ VIN ≤ 5.5 V 0.8 V IEN EN pin leakage current VEN=5.5V –0.5 0.5 uA ton Turnon time CL = 100 µF, RL = 10 Ω 3 ms toff Turnoff time CL = 100 µF, RL = 10 Ω 3 ms DISCHARGE RDCHG Discharge resistance VIN = VOUT = 5V, disabled 400 500 810 Ω CURRENT LIMIT (TPS2068E and TPS2069E) IOS Short circuit output current VIN = 5 V, OUT connect to GND, device enable into short circuit, TJ = 25°C 1.71 2.13 2.55 A VIN = 5 V, OUT connect to GND, device enable into short circuit, –40°C ≤ TJ ≤ 125°C 1.6 2.13 2.66 A tios response time to short circuit VIN = 5.0 V, RL = 50mΩ. See Figure 7-5. 1.5 us TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 www.ti.com

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7.5 Electrical Characteristics (continued)

Unless otherwise noted: VIN = 5.5 V, VEN = VIN, IOUT = 0 A, –40°C ≤ TJ ≤ 125°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT LIMIT (TPS2000E and TPS2001E) IOS Short circuit output current VIN = 5 V, OUT connect to GND, device enable into short circuit, TJ = 25°C 2.24 2.8 3.36 A VIN = 5 V, OUT connect to GND, device enable into short circuit, –40°C ≤ TJ ≤ 125°C 2.1 2.8 3.5 A tios response time to short circuit VIN = 5.0 V, RL = 50mΩ. See Figure 7-5. 1.5 us SUPPLY CURRENT ISD Supply current, switch disable No load on OUT, VEN = 0 V, TJ = 25°C 0.5 1 uA No load on OUT, VEN = 0 V, –40°C ≤ TJ ≤ 125°C 0.5 5 uA ISE Supply current, switch enable No load on OUT, VEN = 5.5 V, TJ = 25°C 93 118 uA No load on OUT, VEN = 5.5 V, –40°C ≤ TJ ≤ 125°C 93 118 uA ILKG Leakage current OUT connected to ground, VEN = 0 V, – 40°C ≤ TJ ≤ 125°C 1 uA IREV Reverse leakage current VOUT = 5.5 V, IN = ground, TJ = 25°C 0 uA UNDERVOLTAGE LOCKOUT VUVLO undervoltage lockout threshold, IN VIN rising 2 2.6 V Hysteresis, IN TJ = 25°C 75 mV OVERCURRENT FLAG VOL(/OC) Output low voltage IO(/OC) = 5 mA 180 mV IOFF_Leaka ge Off-state leakage V/OC = 5.5 V 1 uA TOC_DEG /OC Flag deglitch /OC assertion or de-assertion 6 8 12 ms THERMAL SHUTDOWN TOTSD_R Thermal shutdown threshold rising threshold 155 175 195 °C Hysteresis 10 °C THERMAL SHUTDOWN in Current Limit TOTSD_CL Thermal shutdown rising threshold in current limit 135 155 175 °C Hysteresis 10 °C OUT RL CL Figure 7-1. Output Rise and Fall Test Load tR tF 10% 90% VOUT Figure 7-2. Power-On and Power-Off Timing www.ti.com TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS2000E TPS2001E TPS2068E TPS2069E

50% tON tOFF 50% 90% 10% Figure 7-3. Enable Timing, Active High Enable V/EN VOUT tON tOFF 50% 90% 10% 50% Figure 7-4. Enable Timing, Active Low Enable IOUT 120% x IOS IOS tIOS 0 A Figure 7-5. Output Short-Circuit Parameters VOUT IOUT IOS Decreasing Load Resistance VIN 0 A 0 V Slope = -RDS(ON) Figure 7-6. Output Characteristic Showing Current Limit TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 www.ti.com

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7.6 Typical Characteristics

TJ - Junction Temperature - °C t/FLT_DEG - /FAULT deglitch time - ms -40 -20 0 20 40 60 80 100 120 140 7.5 8.5 Figure 7-7. Deglitch Period (TFLT) vs Temperature TJ - Junction Temperature - °C RDCHG - Discharge Resistance -  -40 -20 0 20 40 60 80 100 120 140 500 550 600 650 700 Figure 7-8. Output Discharge Resistance vs Temperature TJ - Junction Temperature - °C IOS - Short Circuit Output Current - A -40 -20 0 20 40 60 80 100 120 140 1.8 1.9 2.1 2.2 2.3 VIN = 2.7 V VIN = 3.3 V VIN = 5 V Figure 7-9. TPS2068E, TPS2069E Short Circuit Current (IOS) vs Temperature TJ - Junction Temperature - °C IOS - Short Circuit Output Current - A -40 -20 0 20 40 60 80 100 120 140 2.5 2.6 2.7 2.8 2.9 VIN = 2.7 V VIN = 3.3 V VIN = 5 V Figure 7-10. TPS2000E, TPS2001E Short Circuit Current (IOS) vs Temperature TJ - Junction Temperature - °C IREV - Reverse Leakage Current - uA -40 -20 0 20 40 60 80 100 120 140 -0.01 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 VIN = 5 V VIN = 5.5 V Figure 7-11. Reverse Leakage Current (IREV) vs Temperature TJ - Junction Temperature - °C ISD - Supply Current, Output Disabled - uA -40 -20 0 20 40 60 80 100 120 140 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 VIN = 5 V VIN = 5.5 V Figure 7-12. Disabled Supply Current (ISD) vs Temperature www.ti.com TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS2000E TPS2001E TPS2068E TPS2069E

7.6 Typical Characteristics (continued)

TJ - Junction Temperature - °C ISE - Supply Current, Output Enabled - uA -40 -20 0 20 40 60 80 100 120 140 100 VIN = 5 V VIN = 5.5 V Figure 7-13. Enabled Supply Current (ISE) vs Temperature TJ - Junction Temperature - °C tf - Output Fall Time - ms -40 -20 0 20 40 60 80 100 120 140 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12 0.13 0.14 0.15 COUT = 1 uF, R LOAD = 10  VIN = 2.7 V VIN = 5.5 V Figure 7-14. Output Fall Time (TF) vs Temperature TJ - Junction Temperature - °C tr - Output Rise Time - ms -40 -20 0 20 40 60 80 100 120 140 0.4 0.5 0.6 0.7 0.8 COUT = 1 uF, R LOAD = 10  VIN = 2.7 V VIN = 5.5 V Figure 7-15. Output Rise Time (TR) vs Temperature TJ - Junction Temperature - °C RDS(ON) - Static Drain-Source On-State Resistance - m  -40 -20 0 20 40 60 80 100 120 140 100 VIN = 2.7 V VIN = 3.3 V VIN = 5 V Figure 7-16. Input-Output Resistance (RDS(ON)) vs Temperature TJ - Junction Temperature - °C VUVLO - Undervoltage Lockout - V -40 -20 0 20 40 60 80 100 120 140 2.2 2.3 2.4 2.5 2.6 Rising Falling Figure 7-17. Undervoltage Lockout vs Temperature Peak Current (A) Current Limit Response - us 2 4 6 8 10 12 14 15 1.5 2.5 3.5 VIN = 5 V Figure 7-18. Current Limit Response (tIOS) vs Peak Current TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 www.ti.com

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8 Detailed Description

8.1 Overview

The TPS20xxE are current-limited, power-distribution switches providing a range from 1.5 A and 2 A of continuous load current in 3.3V and 5V power rail circuits. These parts use N-channel MOSFETs for low resistance, maintaining voltage regulation to the load. They are designed for applications where short circuits or heavy capacitive loads are encountered. Device features include enable, reverse blocking when disabled, output discharge pulldown, overcurrent protection, overtemperature protection, and deglitched fault reporting.

8.2 Functional Block Diagram

+ UVLO Figure 8-1. TPS20xxE Block Diagram

8.3 Feature Description

8.3.1 Undervoltage Lockout

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turnon threshold. Built-in hysteresis prevents unwanted ON/OFF cycling due to input voltage drop from large current surges. FLT is high impedance when the TPS20xxE are in UVLO.

8.3.2 Enable

The logic enable input (EN, or EN), controls the power switch, bias for the charge pump, driver, and other circuits. The supply current is reduced to less than 1 µA when the TPS20xxE are disabled. Disabling the TPS20xxE immediately clears an active FLT indication. The enable input is compatible with both TTL and CMOS logic levels. The turnon and turnoff times (t ON, tOFF) are composed of a delay and a rise or fall time (t R, tF). The delay times are internally controlled. The rise time is controlled by both the TPS20xxE and the external loading (especially capacitance). TPS20xxE fall time is controlled by the loading (R and C), and the output discharge (R DCHG). An output load consisting of only a resistor experiences a fall time set by the TPS20xxE. An output load with parallel R and C elements experiences a fall time determined by the (R × C) time constant if it is longer than the t F TPS20xxE. The enable must not be left open, and may be tied to VIN or GND depending on the device.

8.3.3 Internal Charge Pump

The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump supplies power to the gate driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The driver incorporates circuitry that controls the rise and fall times of the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start functionality. The MOSFET power switch blocks current from OUT to IN when turned off by the UVLO or disabled. www.ti.com TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS2000E TPS2001E TPS2068E TPS2069E

8.3.4 Current Limit

The TPS20xxE responds to overloads by limiting output current to the static I OS levels shown in Section 7.5. When an overload condition is present, the device maintains a constant output current, with the output voltage determined by (I OS × R LOAD). Two possible overload conditions can occur. The first overload condition occurs when either: 1. input voltage is first applied, enable is true, and a short circuit is present (load which draws IOUT > IOS) 2. input voltage is present and the TPS20xxE are enabled into a short circuit. The output voltage is held near zero potential with respect to ground and the TPS20xxE ramps the output current to I OS. The TPS20xxE limits the current to I OS until the overload condition is removed or the device begins to thermal cycle. This is demonstrated in Figure 9-4 where the device was enabled into a short, and subsequently cycles current OFF and ON as the thermal protection engages. The second condition is when an overload occurs while the device is enabled and fully turned on. The device responds to the overload condition within t IOS (Figure 7-5 and Figure 7-6 ) when the specified overload (see Section 7.5) is applied. The response speed and shape varies with the overload level, input circuit, and rate of application. The current limit response vary between simply settling to I OS, or turnoff and controlled return to I OS. Similar to the previous case, the TPS20xxE limits the current to IOS until the overload condition is removed or the device begins to thermal cycle. The TPS20xxE thermal cycles if an overload condition is present long enough to activate thermal limiting in any of the above cases. This is due to the relatively large power dissipation [(V IN – VOUT) × IOS] driving the junction temperature up. The device turns off when the junction temperature exceeds 135°C (minimum) while in current limit. The device remains off until the junction temperature cools 10°C and then restarts. There are two kinds of current limit profiles typically available in TI switch products that are similar to the TPS20xxE. Many older designs have an output I vs V characteristic similar to the plot labeled Current Limit with Peaking in Figure 8-2. This type of limiting can be characterized by two parameters, the current limit corner (IOC), and the short circuit current (IOS). IOC is often specified as a maximum value. The TPS20xxE family of parts does not present noticeable peaking in the current limit, corresponding to the characteristic labeled Flat Current Limit in Figure 8-2. This is why the IOC parameter is not present in Section 7.5. V OUT IOUT IOS Decreasing Load Resistance VIN 0 A 0 V Slope = -RDS(ON) V OUT IOUT IOS Decreasing Load Resistance VIN 0 A 0 V Slope = -RDS(ON) IOC Current Limit with Peaking Flat Current Limit Figure 8-2. Current Limit Profiles

8.3.5 FLT

The FLT open-drain output is asserted (active low) during an overload or overtemperature condition. A 8-ms deglitch on both the rising and falling edges avoids false reporting at start-up and during transients. A current limit condition shorter than the deglitch period clears the internal timer upon termination. The deglitch timer does not integrate multiple short overloads and declare a fault. This is also true for exiting from a faulted state. An input voltage with excessive ripple and large output capacitance may interfere with operation of FLT around IOS as the ripple drives the TPS20xxE in and out of current limit. TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 www.ti.com

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If the TPS20xxE are in current limit and the overtemperature circuit goes active, FLT goes true immediately; however, the exiting this condition is deglitched. FLT is tripped just as the knee of the constant-current limiting is entered. Disabling the TPS20xxE clears an active FLT as soon as the switch turns off. FLT is high impedance when the TPS20xxE are disabled or in undervoltage lockout (UVLO).

8.3.6 Output Discharge

A 500-Ω (typical) output discharge dissipates stored charge and leakage current on OUT when the TPS20xxE is in UVLO or disabled. The pulldown circuit loses bias gradually as V IN decreases, causing a rise in the discharge resistance as VIN falls towards 0 V.

8.4 Device Functional Modes

8.4.1 Shutdown Mode

The logic enable input (EN or EN) pin provides electrical ON and OFF control for the TPS20xxE. When VEN/EN is below 0.8 V or V IN is below 2 V, the device is in shutdown mode in which the power switch is turned off and the supply current is reduced to less than 1 μA. Refer to Enable and Undervoltage Lockout sections for the detailed description of the Enable and Undervoltage Lockout functionality.

8.4.2 Active Mode

The TPS20xxE enters active mode when V EN/EN is above 1.8 V, and the supply voltage on the IN pin is above 2.6 V. At the onset of active mode, the power switch is turned on and the full features are enabled. www.ti.com TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS2000E TPS2001E TPS2068E TPS2069E

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TPS20xxE current-limited power switch uses N-channel MOSFETs in applications requiring continuous load current. The device enters constant-current mode when the load exceeds the current limit threshold.

9.2 Typical Application

2.7 V - 5.5 V 0.1uF COUT Fault Signal VOUT EN or OUT RFAULT TPS20xxE Pad* EN * DGN only USB requirement only USB requirement that downstream facing ports are bypassed with at least 120uF per hub Figure 9-1. Typical Application Schematic

9.2.1 Design Requirements

For this design example, use the following input parameters: 1. The TPS2001EDBV operates from a 5-V to ±0.5-V input rail. 2. What is the normal operation current, for example, the maximum allowable current drawn by portable equipment for BC1.2 is 1500 mA, so the normal operation current is 1500 mA, and the minimum current limit of power switch must exceed 1500 mA to avoid false trigger during normal operation. For the TPS2001E device, target 2-A continuous output current application. 3. What is the maximum allowable current provided by up-stream power, the maximum current limit of power switch that must lower it to ensure power switch can protect the up-stream power when overload is encountered at the output of power switch. For the TPS2001E device, the maximum IOS is 3.5 A.

9.2.2 Detailed Design Procedure

To begin the design process a few parameters must be decided upon. The designer must know the following: 1. Normal input operation voltage 2. Output continuous current 3. Maximum up-stream power supply output current

9.2.2.1 Input and Output Capacitance

Input and output capacitance improves the performance of the device; the actual capacitance must be optimized for the particular application. For all applications, TI recommends placing a 0.1-µF or greater ceramic bypass capacitor between IN and GND, as close to the device as possible for local noise decoupling. TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 www.ti.com

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Product Folder Links: TPS2000E TPS2001E TPS2068E TPS2069E

All protection circuits such as the TPS20xxE has the potential for input voltage overshoots and output voltage undershoots. Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high impedance (before turnon). Theoretically, the peak voltage is 2× the applied. The second cause is due to the abrupt reduction of output short-circuit current when the TPS20xxE turns off and energy stored in the input inductance drives the input voltage high. Input voltage droops may also occur with large load steps and as the TPS20xxE output is shorted. Applications with large input inductance (for example, connecting the evaluation board to the bench power-supply through long cables) may require large input capacitance reduce the voltage overshoot from exceeding the absolute maximum voltage of the device. The fast current limit speed of the TPS20xxE to hard output short circuits isolates the input bus from faults. However, ceramic input capacitance in the range of 1 µF to 22 µF adjacent to the TPS20xxE input aids in both speeding the response time and limiting the transient seen on the input power bus. Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred and the TPS20xxE has abruptly reduced OUT current. Energy stored in the inductance drives the OUT voltage down and potentially negative as it discharges. Applications with large output inductance (such as from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. When implementing USB standard applications, a 120-µF minimum output capacitance is required. Typically a 150-µF electrolytic capacitor is used, which is sufficient to control voltage undershoots. However, if the application does not require 120 µF of capacitance, and there is potential to drive the output negative, then TI recommends a minimum of 10-µF ceramic capacitance on the output. The voltage undershoot must be controlled to less than 1.5 V for 10 µs. www.ti.com TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS2000E TPS2001E TPS2068E TPS2069E

9.2.3 Application Curves

VIN = 5 V VEN = 4 V RLoad = 2.5 Ω Figure 9-2. Turnon Delay and Rise Time VIN = 5 V VEN = 4 V RLoad = 2.5 Ω Figure 9-3. Turnoff Delay and Fall Time VIN = 5 V VEN = 4 V OUT short to GND Figure 9-4. TPS2001E Enable into Output Short VIN = 5 V Figure 9-5. TPS2001E Full Load to Output Short VIN = 5 V Figure 9-6. TPS2001E Output Short to Full Load VIN = 5 V Figure 9-7. TPS2001E No Load to Output Short TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 www.ti.com

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Product Folder Links: TPS2000E TPS2001E TPS2068E TPS2069E

VIN = 5 V Figure 9-8. TPS2001E Output Short to No Load

9.3 Power Supply Recommendations

Design of the devices is for operation from an input voltage supply range of 2.7 V to 5.5 V. The current capability of the power supply should exceed the maximum current limit of the power switch.

9.4 Layout

9.4.1 Layout Guidelines

  1. Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a low inductance trace. 2. Place at least 10-µF low ESR ceramic capacitor near the OUT and GND pins, and make the connections using a low inductance trace. 3. The PowerPAD must be directly connected to PCB ground plane using wide and short copper trace.

9.4.2 Layout Example

/FLT GND VOUT GND EN/EN Figure 9-9. Recommended Layout - DBV www.ti.com TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS2000E TPS2001E TPS2068E TPS2069E

Via to Bo om Layer Signal Ground Plane 4 5 Via to Bo om Layer Signal VIN /FLTEN/EN VOUT GND GND Figure 9-10. Recommended Layout - DGN and DGK TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 www.ti.com

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Product Folder Links: TPS2000E TPS2001E TPS2068E TPS2069E

10 Device and Documentation Support

10.1 Documentation Support

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

PowerPAD™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TPS2000E, TPS2001E, TPS2068E, TPS2069E SLVSGZ7A – MAY 2023 – REVISED JULY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS2000E TPS2001E TPS2068E TPS2069E

www.ti.com 29-Aug-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTPS2001EDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 Samples PTPS2001EDGKR ACTIVE VSSOP DGK 8 2500 TBD Call TI Call TI -40 to 125 Samples PTPS2001EDGNR ACTIVE HVSSOP DGN 8 2500 TBD Call TI Call TI -40 to 125 Samples PTPS2068EDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 Samples PTPS2068EDGNR ACTIVE HVSSOP DGN 8 2500 TBD Call TI Call TI -40 to 125 Samples PTPS2069EDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 Samples PTPS2069EDGNR ACTIVE HVSSOP DGN 8 2500 TBD Call TI Call TI -40 to 125 Samples TPS2000EDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green Call TI Level-1-260C-UNLIM -40 to 125 2000E Samples TPS2001EDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM -40 to 125 2001E Samples TPS2068EDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green Call TI Level-1-260C-UNLIM -40 to 125 2068E Samples TPS2069EDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM -40 to 125 2069E Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

www.ti.com 29-Aug-2023 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2000EDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS2001EDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS2001EDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS2068EDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS2069EDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS2069EDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. PowerPAD VSSOP - 1.1 mm max heightDGN 8 SMALL OUTLINE PACKAGE3 x 3, 0.65 mm pitch 4225482/A

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 (0.1) (0.15) A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/G 03/2023 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/G 03/2023 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/G 03/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

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