PTPS1H200AQDGNRQ1 | DigiCamel IC Datasheet

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ADVANCE□INFORMATION DIAG_EN IN CL FAULT DELAY 3.5 ± 40 V Supply Voltage VS Up to 40 V Up to 40 V LED Strings Bulbs Relays, Solenoids Submodule Cameras, Sensors General Resistive Capacitive, Inductive Loads OUT Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPS1H200-Q1 SLVSEE0 –FEBRUARY 2018 TPS1H200-Q140-V200-mΩSingle-ChannelSmartHigh-SideSwitch

1 Features

1• Qualified for Automotive Applications

AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C4B
Single-Channel 200-mΩ Smart High-Side Switch
Wide Operating Voltage: 3.4 V to 40 V
Ultra-low Standby Current, < 500 nA
Adjustable Current Limit With External Resistor – ±15% When ≥ 500 mA – ±10% When ≥ 1.5 A
Configurable Behavior After Current Limit – Holding Mode – Latch-Off Mode With Adjustable Delay Time – Auto-Retry Mode
Supports Stand-Alone Operation Without an MCU
Protection: – Short-to-GND and Overload Protection – Thermal Shutdown and Thermal Swing – Negative Voltage Clamp for Inductive Loads – Loss of GND and Loss of Battery Protection
Diagnostics: – Overload and Short-to-GND Detection – Open-Load and Short-to-Battery Detection in ON or OFF State – Thermal Shutdown and Thermal Swing

2 Applications

Body Lighting
Infotainment System
Advanced Driver Assistance Systems (ADAS)
Single-Channel High-Side Switch for Submodules
General Resistive, Inductive, and Capacitive Loads

3 Description

The TPS1H200-Q1 device is a fully protected single- channel high-side power switch with an integrated 200-mΩ NMOS power FET. An adjustable current limit improves system reliability by limiting the inrush or overload current. The high accuracy of the current limit improves overload protection, simplifying the front-stage power design. Configurable features besides current limit provide design flexibility in functionality, cost, and thermal dissipation. The device supports full diagnostics with the digital status output. Open-load detection is available in ON and OFF states. The device supports operation with or without an MCU. Stand-alone mode allows isolated systems to use the device. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS1H200-Q1 HVSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Block Diagram Current Limit Protection in Auto-Retry Mode

11.2 Receiving Notification of Documentation Updates 27

12 Mechanical, Packaging, and Orderable

4 Revision History

February 2018 * Initial release.

ADVANCE□INFORMATION 1IN 8 VS 2DIAG_EN 7 OUT 3FAULT 6 GND 4CL 5 DELAY Not to scale Thermal Pad TPS1H200-Q1 www.ti.com SLVSEE0 –FEBRUARY 2018 Product Folder Links: TPS1H200-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

5 Pin Configuration and Functions

DGN PowerPAD™ Package 8-Pin HVSSOP With Exposed Thermal Pad Top View Pin Functions PIN I/O DESCRIPTION NAME NO. CL 4 O Adjustable current limit. Connect to device GND if external current limit is not used. DELAY 5 I/O Function configuration when current limit; internal pullup DIAG_EN 2 I Enable the diagnostic function FAULT 3 O Open-drain diagnostic status output. Leave floating if not used. GND 6 — Ground IN 1 I Input control for output activation; internal pulldown OUT 7 O Output, source of the high-side switch, connected to the load VS 8 I Power supply, drain for the high-side switch Thermal pad — — Thermal pad. Connect to device GND or leave floating.

ADVANCE□INFORMATION TPS1H200-Q1 SLVSEE0 –FEBRUARY 2018 www.ti.com Product Folder Links: TPS1H200-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to ground. (3) Reverse polarity condition: VIN = 0 V, reverse current < IR(2), GND pin 1-kΩ resistor in parallel with diode. (4) Test condition: VVS = 13.5 V, L = 8 mH, TJ = 150°C. FR4 2s2p board, 2 × 70-μm Cu, 2 × 35-μm Cu. 600 mm2 thermal pad copper area.

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT Supply voltage VS pin t < 400 ms — 42 V Reverse polarity voltage (3) t < 1 minute –36 — V Current on GND t < 2 minutes –100 250 mA Voltage on IN and DIAG_EN pins –0.3 VS V Current on IN and DIAG_EN pins –10 — mA Voltage on DELAY pin –0.3 7 V Current on DELAY pin –60 — mA Voltage on FAULT pin –0.3 7 V Current on FAULT pin –30 10 mA Voltage on CL pin –0.3 7 V Current on CL pin — 6 mA Voltage on OUT pin — 42 V Inductive load switch-off energy dissipation single pulse(4) — 40 mJ Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) AEC-Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specifications.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) All pins except VS, OUT, and GND ±2000 VPins VS, OUT, and GND ±3000 Charged-device model (CDM), per AEC Q100-011 ±750

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted) MIN MAX UNIT VS Operating voltage 4 40 V Voltage on IN and DIAG_EN pins 0 40 V Voltage on FAULT pin 0 5 V Io,nom Nominal DC load current 0 2.5 A TJ Operating junction temperature –40 150 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TPS1H200-Q1 UNITDGN (HVSSOP)

8 PINS

RθJA Junction-to-ambient thermal resistance 47.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 49.2 °C/W RθJB Junction-to-board thermal resistance 18.3 °C/W ψJT Junction-to-top characterization parameter 0.8 °C/W ψJB Junction-to-board characterization parameter 18.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 5.6 °C/W

ADVANCE□INFORMATION TPS1H200-Q1 SLVSEE0 –FEBRUARY 2018 www.ti.com Product Folder Links: TPS1H200-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Value specified by design, not subject to production test.

6.5 Electrical Characteristics

over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING VOLTAGE VVS(nom) Nominal operating voltage 4 40 V VVS(uvr) Undervoltage restart VVS rising 3.5 3.7 4 V VVS(uvf) Undervoltage shutdown VVS falling 3 3.2 3.4 V V(uv,hys) Undervoltage shutdown, hysteresis 0.5 V OPERATING CURRENT I(op) Nominal operating current VVS = 13.5 V, VIN = 5 V VDIAG_EN = 0 V, IOUT = 0.5 A ICL = 2 A 5 mA I(off) Standby current VVS = 13.5 V VIN = VDIAG_EN = VCL = VOUT = 0 V TJ = 25°C 0.5 µA VVS = 13.5 V VIN = VDIAG_EN = VCL = VOUT = 0 V TJ = 125°C I(off,diag) Standby current with diagnostics enabled VVS = 13.5 V VIN = 0 V, VDIAG_EN = 5 V 3 mA t(off,deg) Standby-mode deglitch time(1) IN from high to low if deglitch time ≥ t(off,deg), then the device enters into standby mode. 12.5 ms Ilkg(out) Output leakage current in OFF state VVS = 13.5 V VIN = VDIAG_EN = VOUT = 0 V 3 µA POWER STAGE rDS(on) ON state resistance VVS ≥ 3.5 V, TJ = 25°C 200 mΩ VVS ≥ 3.5 V, TJ = 150°C 400 ICL(int) Internal current limit CL pin connected to GND 3.5 4.8 6 A ICL(TSD) Current-limit value percentage during thermal shutdown 60% VDS(clamp) Drain−to−source voltage internally clamped 45 65 V OUTPUT DIODE CHARACTERISTICS VF Drain−to-source diode voltage IN = 0, IOUT = −0.15 A 0.3 0.7 1 V IR(1) Continuous reverse current from source to drain during a short-to-battery condition(1) t < 60 s, VIN= 0 V, TJ = 25°C. 2 A IR(2) Continuous reverse current from source to drain during a reverse-polarity condition(1) t < 60 s, VIN= 0 V, TJ = 25°C GND pin 1-kΩ resistor in parallel with diode. 2 A LOGIC INPUT (IN, DIAG_EN) VIH Logic high-level voltage 2 V VIL Logic low-level voltage 0.8 V Rpd,in Logic-pin pulldown resistor IN. VIN = 5 V 150 400 kΩ DIAG_EN. VVS = VDIAG_EN = 5 V 350 850 DIAGNOSTICS Ilkg(loss,GND) Loss of ground output leakage current 100 µA td(ol,on) Open-load deglitch time in ON state VIN = 5 V, VDIAG_EN = 5 V when IOUT < I(ol,on), duration longer than td(ol,on), open load is detected. 200 300 450 µs

ADVANCE□INFORMATION TPS1H200-Q1 www.ti.com SLVSEE0 –FEBRUARY 2018 Product Folder Links: TPS1H200-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(ol,on) Open-load detection threshold in ON state VIN = 5 V, VDIAG_EN = 5 V when IOUT < I(ol,on) duration longer than td(ol,on) open load is detected. 10 20 mA V(ol,off) Open-load detection threshold in OFF state VIN = 0 V, VDIAG_EN = 5 V when VVS – VOUT < V(ol,off) duration longer than td(ol,off) open load is detected. 1.4 2.6 V td(ol,off) Open-load deglitch time in OFF state VIN = 0 V, VDIAG_EN = 5 V when VVS – VOUT < V(ol,off) duration longer than td(ol,off) open load is detected. 200 300 450 µs I(ol,off) OFF state output sink current VIN = 0 V, VDIAG_EN = 5 V VVS = VOUT = 13.5 V –75 µA VFAULT FAULT low output voltage IFAULT = 2 mA 0.2 V tFAULT FAULT signal holding time(1) 8.5 ms T(SD) Thermal shutdown threshold(1) 175 °C T(SD,rst) Thermal shutdown status reset(1) 155 °C T(sw) Thermal swing shutdown threshold(1) 60 °C T(hys) Hysterisis for resetting the thermal shutdown and swing(1) 10 °C CURRENT LIMIT AND DELAY CONFIGURATION K(CL) Current-limit current ratio(1) 2500 VCL(th) Current-limit internal threshold voltage(1) 0.8 V dK(CL) / K(CL) External current limit accuracy (IOUT – ICL × K(CL) × 100 / (ICL × K(CL)) Ilimit ≥ 0.25 A, VVS – VOUT ≥ 2.5 V –20% 20% Ilimit ≥ 0.5 A, VVS – VOUT ≥ 2.5 V –15% 15% Ilimit ≥ 1.5 A, Ilimit < 5 A VVS – VOUT ≥ 2.5 V –10% 10% Idl(chg) Delay pin charging current in latch-off mode(1) 4.5 µA Vdl(th) Pulling up threshold in auto-retry mode 2.7 V Vdl(ref) Internal reference voltage in latch-off mode 1.45 V tdl1 Internal fixed delay time(1) 300 400 500 µs tdl2 Adjustable delay time by external capacitor on DELAY pin(1) Connect with 3.3 µF capacitor as the maximum value. 1000 ms tCL(deg) Deglitch time when current limit (1) IN low to high, VDIAG_EN = 5 V the deglitch time from IN rising edge to FAULT reporting out. 300 550 µs IN keeps high, VDIAG_EN = 5 V the deglitch time from CL start-point to FAULT reporting out. 80 200 thic(on) On-time when in auto-retry mode(1) 35 40 45 ms thic(off) Off-time when in auto-retry mode(1) 0.8 1 1.2 s

(1) Value specified by design, not subject to production test.

6.6 Switching Characteristics

Figure 1. Output Delay Characteristics Figure 2. Open-Load Blanking-Time Characteristic

ADVANCE□INFORMATION Gate Driver Diagnostics & Protection Short-to-GND and Overload Current Limit IN FAULT CL VDS Clamp GND Charge PumpInternal Reference ON/OFF State Open Load Detection Thermal Monitor DIAG_EN DELAY VS OUT GND Copyright © 2017, Texas Instruments Incorporated TPS1H200-Q1 www.ti.com SLVSEE0 –FEBRUARY 2018 Product Folder Links: TPS1H200-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TPS1H200-Q1 device is a smart high-side switch with an internal charge pump and single-channel integrated NMOS power FET. The adjustable current limit function improves the reliability of the whole system. Full diagnostic features enable intelligent control of the load. The external high-accuracy current limit sets the current limit value for the application. When overcurrent occurs, the device improves system reliability by clamping the inrush current effectively. The device saves system cost by reducing the size of PCB traces and connectors, and the capacity of the preceding power stage. The TPS1H200-Q1 device allows three modes when a current limit occurs. Users can set the output to consistently hold the current, to immediately latch off, or to automatically retry through the configuration on the DELAY pin. The configurable behaviors during a current limit provides design flexibility. This includes functionality, cost, and thermal dissipation. This device supports full diagnostics with the digital status output. High-accuracy and low-threshold open-load detection enables real-time ON state monitoring. The device supports operation without an MCU (stand-alone mode) which allows the system to locally implement full functionality. The TPS1H200-Q1 device is a smart high-side switch for a wide variety of resistive, inductive, and capacitive loads, including LEDs, bulbs, relays, solenoids, and submodules.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Current limit

set value, and a fault is reported. The device heats up because of high power dissipation on the power FET. The device has two current limit thresholds.

Internal current limit: The internal current limit is fixed at ICL(int). Tie the CL pin directly to the device GND for large-transient-current applications.
External adjustable current limit: An external resistor is used to set the current limit threshold. Use Equation 1 to calculate R(CL). The external adjustable current limit allows the flexibility to set the current limit value by application. where
VCL(th) is the internal band-gap voltage.
K(CL) is the ratio of the output current and the current limit set value.
K(CL) is constant across temperature and supply voltage. (1) NOTE When a GND network is used, that causes a level shift between the device GND and board GND, so the CL pin must be connected to the device GND. For better protection from a hard short-to-GND condition (when the IN pin is enabled, a short-to-GND occurs suddenly), the device will implement a fast-trip protection to turn off the output before the current limit closed loop is set up. Typically, the fast-trip response time is less than 1 µs. With a fast response like this, the device can achieve a better inrush current-suppression performance.

Figure 3. Current Limit

7.3.2 DELAY Pin Configuration

lists the current limit configurations and these outcomes behaviors. Table 1. Current Limit Configurations thermal shutdown mode when TJ > T(SD). the current limit is removed when IN is high. duration of time longer than tFAULT. on for thic(on) and turns off for thic(off). the current limit is removed for thic(on).

7.3.2.1 Holding Mode

output current holds at the setting current. The device then enters thermal shutdown mode when TJ > T(SD). Figure 4. Holding Mode Connection Figure 5. Holding Mode Example

7.3.2.2 Latch-Off Mode

limit is removed or not, the output remains latched off. The output only recovers when IN is toggling. tdl2 can be calculated by Equation 2.

CDELAY is the capacitor connected on the DELAY pin.
The Idl(chg) is the device that charges the current in latch-off mode.
tdl2 is the user-setting delay time.
Vdl(ref) is the internal reference voltage in latch-off mode. (2)

Figure 6. Latch-Off-Mode Connection Figure 7. Latch-Off-Mode Example

7.3.2.3 Auto-Retry Mode

for thic(on) and turns off for thic(off). Figure 8. Auto-Retry-Mode Connection Figure 9. Auto-Retry-Mode Example

3.4 V ± 40 V

7.3.3 Stand-alone Operation

directly. When in auto-retry mode, the DELAY pin is connected to the VS pin through a 100-kΩ resistor. Figure 10. Stand-Alone Operation in Latch-Off Mode Figure 11. Stand-Alone Operation in Auto-Retry Mode

(1) An external pullup is required for open-load detection.

7.3.4 Fault Truth Table

diagnostics of one device, and disables the diagnostics of the other devices by setting DIAG_EN low. Additionally, the device can keep power consumption to a minimum by setting DIAG_EN and IN low. Table 2 applies when the DIAG_EN pin is enabled, and Table 3 applies when the DIAG_EN pin is disabled. Table 2. Fault Truth Table Overload or short to GND H L current limit triggered L See Table 1. for a duration longer than tFAULT. for a duration longer than tFAULT. for a duration longer than tFAULT. Table 3. DIAG_EN Disabled Condition

7.3.5 Full Diagnostics

7.3.5.1 Short-to-GND and Overload Detection

the internal or external current limit threshold, the fault condition is reported as FAULT pin = low.

7.3.5.2 Open-Load Detection

7.3.5.2.1 Output On

l(ol,on). For open-load detection when output is on, no external circuitry is required.

7.3.5.2.2 Output Off

output voltage is close to the supply voltage (VVS – VOUT < V(ol,off)), and the device recognizes an open-load fault. when an open load is detected. The recommended pullup resistance is 15 kΩ. Figure 12. Open-Load Detection in Output OFF State

7.3.5.3 Short-to-Battery Detection

7.3.5.4 Thermal Fault Detection

Figure 13. Thermal Behavior Diagram

7.3.5.4.1 Thermal Shutdown

7.3.5.4.2 Thermal Swing

repetitively fast thermal variation.

7.3.5.4.3 Fault Report Holding

function allows the right behavior as shown in Figure 15. Figure 14. Without Fault-Report Holding Figure 15. With Fault-Report Holding

7.3.6 Full Protections

7.3.6.1 UVLO Protection

drops down to VVS(uvf), the device shuts down. When VVS rises up to VVS(uvr), the device turns on.

7.3.6.2 Inductive Load Switching Off Clamp

down, an internal clamp (VDS(clamp)) is implemented. Figure 16. Drain-to-Source Clamping Structure Figure 17. Inductive-Load Switching-Off Diagram

7.3.6.3 Loss-of-GND Protection

can protect against two ground-loss conditions, loss of device GND and loss of module GND.

7.3.6.4 Loss-of-Power-Supply Protection

TI recommends protection with an external free-wheeling diode. Figure 18. Protection for Loss of Power Supply

7.3.6.5 Reverse-Current Protection

Reverse current occurs in two conditions: short to supply and reverse polarity.

When a short to the supply occurs, there is only reverse current through the body diode. IR(1) specifies the limit of the reverse current.
In a reverse-polarity condition, there are reverse currents through the body diode and the device GND pin. IR(2) specifies the limit of the reverse current. To protect the device, TI recommends using two types of external circuitry.
Adding a blocking diode (method 1). The device and load are protected when in reverse polarity.
Adding a GND network (method 2). The reverse current through the device GND is blocked. The reverse current through the FET is limited by the load itself. TI recommends a resistor in parallel with the diode as a GND network. The recommended configuration is a 1-kΩ resistor in parallel with a diode that is less than 100 mA.

Figure 19. Reverse-Current External Protection Method 1 Figure 20. Reverse-Current External Protection Method 2

7.3.6.6 MCU I/O Protection

microcontroller and 10-kΩ for a 5-V microcontroller. Figure 21. MCU I/O External Protection

7.4 Device Functional Modes

7.4.1 Working Modes

diagnostics, as shown in Figure 22. Figure 22. Working Modes

7.4.1.1 Normal Mode

When IN is high, the device enters normal mode.

7.4.1.2 Standby Mode

When IN is high and DIAG_EN is high, the device enters standby mode with ultra-low power consumption.

7.4.1.3 Standby Mode With Diagnostics

open-load and short-to-battery detection even when IN is low.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

wide variety of resistive, inductive, and capacitive loads, including LEDs, relays, and submodules.

8.2 Typical Application

Figure 23 shows an example of how to design the external circuitry parameters. Figure 23. Typical Application Circuitry

8.2.1 Design Requirements

VVS range from 6 V to 18 V
Nominal current of 500 mA
Expected current limit value of 2 A
Thermal sensitive system. When current limit occurs, the output latches off after 0.2 seconds. The 0.2 seconds is to ensure the safe start-up for a capacitive load, clamping the inrush current but without latch-off during start-up.
Full diagnostics with 5-V MCU, including ON state open-load detection, short-to-GND, or overcurrent detection, and thermal shutdown detection

8.2.2 Detailed Design Procedure

TI recommends R(SER) = 10 kΩ for a 5-V MCU, and R(pullup) = 10 kΩ as the pullup resistor.

8.2.3 Application Curves

0.6 A. Figure 24 shows a waveform of the latch-off mode. Figure 25 shows a waveform of the auto-retry mode. Figure 24. Hard-Short Condition in Latch-Off Mode Figure 25. Hard-Short Condition in Auto-Retry Mode

9 Power Supply Recommendations

10 Layout

10.1 Layout Guidelines

essential for the long-term reliability of the device.

Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat- flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely important when no heat sinks are attached to the PCB on the other side of the board opposite the package.
Add as many thermal vias as possible directly under the package ground pad to optimize the thermal conductivity of the board.
All thermal vias should either be plated shut or plugged and capped on both sides of the board to prevent solder voids. To ensure reliability and performance, the solder coverage must be at least 85%.

10.2 Layout Example

Figure 26. Layout Example

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

Texas Instruments, TPS1H000-Q1 Evaluation Module (EVM) User's Guide

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper- right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 19-Mar-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTPS1H200AQDGNRQ1 ACTIVE MSOP- PowerPAD DGN 8 2500 TBD Call TI Call TI -40 to 125 TPS1H200AQDGNRQ1 PREVIEW MSOP- PowerPAD DGN 8 2500 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 19-Mar-2018 Addendum-Page 2

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Product Information

PTPS1H200AQDGNRQ1 specifications and overview.

Summary

40-V 200-m(ohm) Single-Channel Smart High-Side Switch

Description

40-V 200-m(ohm) Single-Channel Smart High-Side Switch

Source title PTPS1H200AQDGNRQ1 Datasheet(PDF) - Texas Instruments

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