TPS1641 TI | Alldatasheet
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Technical content
TPS1641x: 40-V, 1.8-A Power and Current Limiting eFuse with IN to OUT Short Detection
1 Features
- Operating voltage range (IN): – TPS16410, TPS16411 : 4.5 V to 40 V – TPS16412, TPS16413 : 2.7 V to 40 V
- Withstands negative voltages up to –1 V at output
- Ultra-low on-resistance: RON = 152 mΩ (typ.)
- 2-W to 64-W configurable power limiting
- IN to OUT short detection and indication on FLT pin
- FLT output for diagnostics and driving external PFET
- ±5% accurate power limit at 15 W (TPS16410, TPS16411)
- ±5% accurate current limit at 1.8 A (TPS16412, TPS16413)
- Configurable overvoltage protection
- Configurable overcurrent protection (IOCP)
- Configurable delay, blanking time for transient currents
- Overvoltage protection up to 60 V with external FET
- Adjustable output slew rate control (dVdt) for inrush current protection
- Enable and shutdown control
- Output load current monitoring on IOCP pin
- Overtemperature Protection (OTP) with thermal shutdown
- Small footprint: QFN 3 × 3 mm, 0.5-mm pitch
2 Applications
- Refrigerator and freezer
- Oven
- Dishwasher
- HVAC valve and actuator control
- Ventilators
- Anesthesia delivery systems
3 Description
The TPS1641x is an integrated eFuse with accurate power limit or current limit. The device provides robust protection with integrated overcurrent protection, overvoltage protection, IN to OUT short detection and overtemperature protection. TPS16410, TPS16411 devices provide ±5% power limiting at 15 W for loads and it also provides configurable blanking time for transient overload or overcurrent events. TPS16410 and TPS16411 can be used for low power circuits (LPCs) for 15-W power limiting as per IEC60335 and UL60730 standards. TPS1641x devices provide protection from adjacent pin short and pin short to GND faults. Applications such as backplane power protection in PLC and DCS modules configure the current limit with resistor on the ILIM pin. TPS16412, TPS16413 devices provide ±5% current limiting at 1.8 A for loads and these devices also provide output slew rate control with dVdT pin to charge large capacitive loads at power up. TPS1641x features IN to OUT short detection. The device indicates IN to OUT short on the FLT pin. The FLT pin can be either provided to MCU as Digital Input or it can be used to drive an external PFET. The devices are characterized for operation over a junction temperature range of –40°C to +125°C. Packaging Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) TPS16410 VSON (10) 3.00 mm × 3.00 mm TPS16411 TPS16412 TPS16413 (1) For all available packages, see the orderable addendum at the end of the data sheet. COUT TPS1641x 152 m IN OUT EN/SHDN PLIM/ILIM PDLY/IDLY VOUT RPLIM FLT GND CIN CDLY ROCP IOCP/IMON Vcc OVP dVdT Simplified Schematic IOUT POUT tPDLYt IOCP PLIM Configurable Blanking time and magnuitude for Transient Loads PDLY = Duration of Transient Load IOCP = Maximum magnitude of Transient Load IOUT = PLIM/VOUT Configurable Blanking Time for Transient Loads ADVANCE INFORMATION TPS1641 SLVSGF4 – JUNE 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.
9.2 Typical Application: 15-W Power Limiting for
10.1 Receiving Notification of Documentation Updates..27
11 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES June 2022 * Advance Information TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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5 Device Comparison Table
Part Number Power or Current Limit Fault Behavior TPS16410 Power limit Auto-retry TPS16411 Power limit Latch-off TPS16412 Current limit Auto-retry TPS16413 Current limit Latch-off www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS1641
6 Pin Configuration and Functions
Figure 6-1. TPS16410 and TPS16411 10-Pin DRC VSON Package TPS16412 TPS16413 Vcc IN FL T EN/SHDN OVP OUT IOCP ILIM IDL Y PowerP ADTM GND dVdT 101 Figure 6-2. TPS16412 and TPS16413 10-Pin DRC VSON Package Table 6-1. Pin Functions PIN I/O (1)
DESCRIPTION
NAME NO. IN 1 P Power input for internal FET Vcc 2 P Supply input for internal circuits of the device OVP 3 I Overvoltage protection input. This pin can be connected to GND for disabling OVP. FLT 4 O Active low fault output. See the FLT Pin Indication for Different Events section for different FLT pin indications. EN/SHDN 5 I Enable or shutdown input PDLY
6 I/O
TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to set PDLY blanking time. IDLY TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to set IDLY blanking time. dVdT 7 I/O Output slew control input. Connect a capacitor to set the output slew rate. If not used, this pin can be left open. PLIM
8 I/O
TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint. ILIM TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint. IOCP/IMON 9 I/O Overcurrent protection input and current monitoring output for output current. Output current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-point and for reading output current. OUT 10 P Power output from internal FET PowerPAD/GND — G GND connection for the device. PowerPAD™ must be connected to GND of input power supply. Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal performance. (1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Vcc, FLT Input Voltage –0.3 67 V OVP Input Voltage –0.3 62 V IN, IN-OUT, IOCP Input Voltage –0.3 42 V OUT Input Voltage –1 42 V EN/SHDN, PDLY/IDLY Input Voltage –0.3 5.5 V dVdT, PLIM/ILIM Input Voltage –0.3 5.5 V IIOCP,IPDLY,IPLIM, IdVdT, IILIM Source Current Internally Limited TJ Junction temperature –40 150 °C Transient Junction Temperature –40 TTSD °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±1500 V Charged device model (CDM), per JEDEC specification JS-002, all pins(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vcc Supply voltage VIN 60 V FLT Input Voltage 0 60 V IN Input Voltage (TPS16410, TPS16411) 4.5 40 V IN Input Voltage (TPS16412, TPS16413) 2.7 40 V OUT Input Voltage 0 40 V EN/SHDN, OVP Input Voltage 0 5.5 V PDLY/IDLY External capacitor 0.01 10 µF dVdT External capacitor 0.01 5 µF IOCP External resistor 6.34 80.6 kΩ PLIM External resistor 12.4 412 kΩ ILIM External resistor 5.1 348 kΩ TJ Junction temperature –40 125 °C www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS1641
7.4 Thermal Information
THERMAL METRIC(1) TPS1641 UNITDRC (VSON)
10 PINS
RθJA Junction-to-ambient thermal resistance 43.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.0 °C/W RθJB Junction-to-board thermal resistance 15.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.5 Electrical Characteristics
–40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF CdVdT = Open, PDLY = Open. , EN/SHDN = Open (All voltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING INPUT AND SUPPLY VOLTAGE Vcc Operating Supply voltage VIN 60 V VIN Operating Input voltage TPS16410, TPS16411 4.5 40 V VIN Operating Input voltage TPS16412, TPS16413 2.7 40 V IQ Operting Supply curent (Vcc) EN/SHDN = 2 V, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open 1.2 mA IQSD Shutdown Supply current (Vcc) EN/SHDN = GND, Vcc = 40 V, VIN = Open, RILIM or RPLIM = Open 25 µA IINLKG IN Leakage Current in ON State EN/SHDN = 2 V, VIN = Vcc = 40 V, Open, RILIM or RPLIM = Open 0.15 mA IINLKG-SD IN Leakage Current in Shutdown EN/SHDN = GND,VIN = Vcc = 40 V, RILIM or RPLIM = Open, RIOCP = Open 1.2 µA OVER-VOLTAGE PROTECTION (OVP) INPUT VOVPR OVP rising threshold 1.53 V VOVPF OVP falling threshold 1.39 V IOVP OVP leakage current 0 V ≤ VOVP ≤ 4 V –260 nA EN/SHDN INPUT VENR Enable rising threshold 1.2 V VENF Enable falling threshold 0.59 V IEN Enable leakage current 0 V ≤ VEN ≤ 4 V –1.7 µA VEN-Open Open circuit Enable Voltage IEN = 0.1 µA, VCC ≥ 6 V 5.05 V OUTPUT POWER LIMITING (PLIM) POUT Output Power Limit RPLIM = 26.7 kΩ 3.65 W POUT Output Power Limit RPLIM = 95.3 kΩ 13.65 W POUT Output Power Limit RPLIM = 255 kΩ 36.5 W OUTPUT CURRENT LIMITING (ILIM) IOUT Output Current Limit RILIM = 332 kΩ 0.030 A IOUT Output Current Limit RILIM = 10 kΩ 1.01 A IOUT Output Current Limit RILIM = 5.49 kΩ 1.84 A POWER OUTPUT (OUT) TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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7.5 Electrical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF CdVdT = Open, PDLY = Open. , EN/SHDN = Open (All voltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RON IN to OUT On resistance -40°C ≤ TJ ≤ 125°C 153 mΩ RON IN to OUT On resistance 0 °C ≤ TJ ≤ 85 °C 153 mΩ RON IN to OUT On resistance TJ = 25°C 153 mΩ ILKG-OUT Output Leakage current in OFF state VIN = 40 V, VOUT = 0 V, EN = Low –2.5 µA CURRENT MONITORING OUTPUT (IMON) GIMON Gain : IMON/IOUT IOUT = 0.05 A to 1.8 A 50 µA/A OSIMON IMON Offset current IOUT = 0 A 0.1 µA OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP) IOCP Over curret protection set-point RIOCP = 7.32 kΩ 2.18 A IOCP Over curret protection set-point RIOCP = 16.2 kΩ 0.96 A IFasttrip Fast Trip protection threshold 1.9 × IOCP A ISCP Short circuit protection threshold 7.4 A ILIM- Internal Internal Current Limit TPS16410, TPS16411 0.81 × IOCP A THERMAL PROTECTION and SHUTDOWN (TTSD) TTSD Thermal shutdown temperature 155 °C TTSD-hyst Thermal shutdown temperature hysteresis 12 °C Output slew rate control (dVdT) IdVdt dVdT charging current 2.04 µA GdVdt dVdT Gain 49.8 V/V FLT Output (FLT) (Open Drain Output) RFLT Fault pin pull down resistance 75 Ω IFLT-LKG Fault pin leakage current FLT is High, VFLT ≤ 28 V 0.01 µA IN to OUT Short Detection Rshort Resistance for IN to short detection 30 mΩ
7.6 Timing Requirements
–40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF CdVdT = Open, PDLY = Open. (All voltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Enable/SHDN and Vcc Input tON_dly Turn ON delay with Vcc VEN = VENR + 0.1 V , RLOAD = Open 495 µs tEN_ON_dly Enable ON Delay Fast turn-on with Enable when device is not in shutdown, VEN = VENR + 0.1 V , RLOAD = Open 290 µs tEN_OFF_dly Enable OFF Delay VEN < VENF to VOUT = 0.9 × VIN, , RLOAD = 100 Ω 1.2 µs tLow_SHDN Min Low Pulse for entering Shutdown RLOAD = 100 Ω 21.5 ms OVP Input www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS1641
7.6 Timing Requirements (continued)
–40°C ≤ TA = TJ ≤ +125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC = VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF CdVdT = Open, PDLY = Open. (All voltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tOVP_entry_dly OVP Entry Delay VOVP = VOVPR + 25 mV to FLT Low 0.75 µs tOVP_exit_dly OVP Exit Delay VOVP = VOVPF – 25 mV to to FLT High 0.6 µs Over Current Protection and Short-circuit protection tfasttrip_dly Fast Trip protection delay IFasttrip < IOUT < ISCP to FET OFF 5.65 µs tSCP_dly Short-Circuit protection delay IOUT = ISCP(min) + 500 mA to FET OFF 280 ns Power Limiting tPDLY Blanking time before power limiting IOUT < IOCP, POUT = 1.2 × PLIM, CDLY = 10 nF 5 ms tPLIM-RES Power Limit response time IOUT < IOCP, IOUT = 1.2 × ILIM, CDLY = Open 215 µs tPLIM-DUR PowerLimit Duration 2 × tPDLY s Current Limiting tIDLY Blanking time before current limiting IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = 10 nF 5 ms tILIM-RES Current Limit response time IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY = Open 280 µs tILIM-DUR Current Limit Duration 2 × tPDLY s Auto-Retry and Thermal Shutdown tretry Retry Delay after thermal shutdown 8 × tPDLY s Output Ramp Control (dVdT) tdVdt Output Ramp Time CdVdt = Open, VIN = VCC = 24 V 285 µs IN to OUT Short and FLT Output tIN_OUT_Short_Detect IN to OUT short detection time when FET is ON IN-OUT Short to FLT Low 200 ms tIN_OUT_Short_Detect IN to OUT short detection time when FET is OFF IN-OUT Short to FLT Low 20 ms TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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7.7 Typical Characteristics
T A ( C) IQ-ON (mA) -40 -20 0 20 40 60 80 100 120 140 0.9 0.95 1.05 1.1 1.15 1.2 1.25 1.3 1.35 (V CC = 4.5 V ) (V CC = 12 V ) (V CC = 24 V ) (V CC = 40 V ) Figure 7-1. IQ-ON vs Temperature T A ( C) IQSD (uA) 16 24 32 40 48 56 64 72 (V CC = 4.5 V ) (V CC = 12 V ) (V CC = 40 V ) (V CC = 24 V ) Figure 7-2. IQSD vs Temperature T A (C) ILKG-VIN (A) -40 -20 0 20 40 60 80 100 120 140 100 200 500 1000 2000 5000 (V IN = 4.5 V ) (V IN = 12 V ) (V IN = 24 V ) (V IN = 40 V ) Figure 7-3. ILKG-VIN vs Temperature Figure 7-4. ILKG-VIN-SD vs Temperature T A (C) R DS-ON (m ) -40 -20 0 20 40 60 80 100 120 140 100 120 140 160 180 200 220 240 (I OUT = 0.5 A) (I OUT = 1.7 A) Figure 7-5. RDS-ON vs Temperature T A (C) dVdT gain (V/V) -40 -20 0 20 40 60 80 100 120 140 49.7 49.71 49.72 49.73 49.74 49.75 49.76 49.77 49.78 49.79 49.8 49.81 Figure 7-6. GdVdT vs Temperature www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS1641
7.7 Typical Characteristics (continued)
T A (C) IdVdT (A) -40 -20 0 20 40 60 80 100 120 140 -2.0625 -2.06 -2.0575 -2.055 -2.0525 -2.05 -2.0475 -2.045 -2.0425 -2.04 -2.0375 Figure 7-7. IdVdT vs Temperature T A ( C) G IMON (A/A) -40 -20 0 20 40 60 80 100 120 140 49.8 49.9 50.1 50.2 50.3 50.4 50.5 50.6 50.7 50.8 50.9 (I OUT = 1 A ) (I OUT = 1.8 A ) Figure 7-8. GIMON vs Temperature T A ( C) IOCP (A) -60 -30 0 30 60 90 120 150 0.5 1.5 2.5 (R IOCP = 16.2 k ) (R IOCP = 7.32 k ) Figure 7-9. IOCP vs Temperature T A ( C) ILIM (A) -60 -30 0 30 60 90 120 150 0.6 1.2 1.8 2.4 ILIM (R ILIM = 332 k ) ILIM (R ILIM = 10 k ) ILIM (R ILIM = 5.49 k ) Figure 7-10. Output Current Limit vs Temperature for TPS16412 and TPS16413 T A ( C) P OUT (W) -40 -20 0 20 40 60 80 100 120 140 R PLIM = 26.7 k R PLIM = 95.3 k Figure 7-11. Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 12 V T A ( C) P OUT (W) -40 -20 0 20 40 60 80 100 120 140 R PLIM = 26.7 k R PLIM = 95.3 k R PLIM = 255 k Figure 7-12. Output Power Limit vs Temperature for TPS16410 and TPS16411 with VIN = 24 V TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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8 Detailed Description
8.1 Overview
The TPS1641x is an integrated eFuse with accurate power limit or current limit. The device integrates an NFET with RON of 152 m Ω. The TPS16410 and TPS16411 provides power limiting whereas the TPS16412 and TPS16413 provide current limiting. The TPS16410 and TPS16411 can provide 15-W accurate power limiting for low power circuit (LPCs) as per IEC60335 and UL60730 standards. TPS1641x devices also provide IN to OUT short detection and its indication on FLT output. IN to OUT short detection eliminates the need of additional eFuse or power limiting circuit in case of IN to OUT short test for IEC60335, UL60730, and similar standards. FLT can be used as input for MCU or it can be used to drive an external PFET. TPS1641x devices also provide protection from adjacent pin short and pin short to GND faults. The TPS1641x device also provide configurable blanking time (IDLY or PDLY) and overcurrent protection (IOCP) for transient loads. Load such as motors need higher current for start-up. Blanking time is useful for providing higher current for start-up of loads such as motors. TPS1641x devices have overvoltage protection (OVP), overtemperature protection, and adjustable output slew rate control (dvdt). Vcc and FLT are rated up to 60 V and can provide protection up to 60 V with an external PFET.
8.2 Functional Block Diagram
IOCP_REF Over-Voltage Protection TPS1641x IOCP/IMON PLIM/ILIM VINT Power or Current Limiting Short-Circuit ProtectionISCP Power or Current Limiting Delay PDLY/IDLY GdVdt Output Slew Rate Control (dVOUT/dt) VINT Internal Regulator Vcc V(OVPR) V(OVPF)OVP VINT FLT OVP TSD VINT Thermal Shutdown TSD IN to OUT Short Detection IOUT VOUT VIN IN-OUT Short V(ENR) V(ENF) VINT EN/SHDN Pulse Duration Detection ILIM/PLIM Timeout dVdt Ifast-trip IOUT IOUT POUT OR IOUT Isink VINT IdVdt www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS1641
8.3 Feature Description
8.3.1 Enable and Shutdown Input (EN/SHDN)
The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply. While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is not in shutdown. See the Electrical Characteristics for VENR and VENF thresholds and the Timing Requirements for tLow_SHDN, tEN_OFF_dly, and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the device for fast turn-on and turn-off of internal FET. Figure 8-1 illustrates the EN/SHDN input in the TPS1641x devices. Figure 8-2 shows the start-up of the device with enable input. TPS1641x EN/SHDN VENR VENF VINT EN/SHDN OFF ON Figure 8-1. EN/SHDN in TPS1641x Devices VIN = 12 V Figure 8-2. Turn-On with Enable
8.3.2 Overvoltage Protection (OVP)
The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above V OVPR, and as the OVP pin voltage falls below V OVPF, the internal FET is turned ON and FLT pin is de-asserted. See the Electrical Characteristics table for V OVPF and V OVPR and Timing Requirements for t OVP_entry_dly and t OVP_exit_dly TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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To disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the internal FET. Figure 8-6. Overvoltage Response with External PFET for IN Voltage from 12 V to 60 V Figure 8-7. Hot Plugin with External PFET for 60-V Input
8.3.3 Output Slew Rate and Inrush Current Control (dVdt)
During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is directly proportional to the load capacitance and rising slew rate. Equation 1 can be used to find the output slew rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT). SR = I I N RU SH C O U T (1) A capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using Equation 2. C dVdt = I d Vd t × G d Vd t SR (2) The fastest output slew rate is achieved by leaving the dVdt pin open. Figure 8-8 illustrates the output slew rate control in the TPS1641x devices. Figure 8-9 shows the output slew rate control response of the device. TPS1641x dvdt VINT Idvdt/Cdvdt Idvdt Gdvdt Cdvdt Output Slew Rate (SR) = [Gdvdt × Idvdt]/Cdvdt Figure 8-8. Output Slew Rate Control in the TPS1641x TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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Figure 8-9. Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF
8.3.4 Active Current Limiting (ILIM) with the TPS16412 and TPS16413
The TPS16412 and TPS16413 devices respond to output overcurrent or overload conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on the IDLY pin. During this blanking time, the device can provide a current up to I OCP value. After the end of this blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. R ILIM can be calculated by Equation 3. I L I M = 0.95 A R I LI M × 10 k Ω (3) If the output current exceeds I OCP, the device goes into current limiting. During current limiting, if the output current goes below ILIM (I OUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when I OUT > ILIM. Figure 8-10 illustrates the current limiting behavior for I OUT < I OCP and for I OCP ≤ IOUT < I fast-trip. During current limiting, if the output current goes below ILIM (I OUT < ILIM), the device resets the IDLY timer and restarts the IDLY timer when IOUT > ILIM. tIDLYt IOCP IOUT ILIM t t IOUT < IOCP IOCP IOUT < Ifast-trip IOCP IOUT tILIM-DUR or Thermal Shutdown (TJ > TTSD) tILIM-DUR or Thermal Shutdown (TJ > TTSD) ILIM Figure 8-10. Current Limit with Blanking Time (IDLY) in the TPS16412 and TPS16413 During the current limiting, the device dissipates a power of (V IN – V OUT) × I OUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (T TSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tILIM-DUR. After the internal FET is turned off, the TPS16412 auto-retries while the TPS16413 latches off. Table 8-1 summarizes the device behavior for different output currents. www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS1641
Table 8-1. Current Limiting and Overload Protection with TPS16412 and TPS16413 Output Current (IOUT) Device Response IOUT < ILIM The device provides current up to ILIM. ILIM ≤ IOUT < IOCP The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a maximum duration of tILIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to ILIM for a maximum duration of tILIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly.
8.3.5 Active Power Limiting (PLIM) with the TPS16410 and TPS16411
The TPS16410 and TPS16411 devices respond to output overcurrent or overload conditions by actively limiting the output power. The devices first provide a blanking time configured by capacitance on PDLY pin. During this blanking time, the device can provide a current up to I OCP value. After the end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor on the PLIM pin. During power limiting, if the output power goes below PLIM (P OUT < PLIM), the device resets the PDLY timer and restarts the PDLY timer when IOUT > PLIM. Use Equation 4 to calculate the value of resistor for power limiting. TI recommends to set PLIM < 0.9 × VOUT × IOCP. P L I M = 13.65 W 95.3 k Ω × R PL IM (4) Figure 8-11 illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT < Ifast-trip. tPDLYt IOCP POUT IOUT PLIM t t t tPOUT IOUT PLIM tPLIM-DUR or Thermal Shutdown (TJ > TTSD) tPLIM-DUR or Thermal Shutdown (TJ > TTSD) IOCP IOUT < IOCP IOCP IOUT < Ifast-trip Figure 8-11. Power Limit with Blanking Time in the TPS16410 and TPS16411 During power limiting, the device dissipates a power of (V IN – VOUT) × IOUT and the device gets heated up. If the junction temperature of device reaches thermal shutdown temperature (T TSD), the device turns off the internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of t ILIM-DUR. After the internal FET is turned off, the TPS16410 device auto-retries while the TPS16411 device latches off. Table 8-2 summarizes the device behavior for different output power and current. TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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Table 8-2. Power Limiting and Overload Response in TPS16410 and TPS16411 Devices Output Power (POUT) or Output Current (IOUT) Device Response POUT < PLIM The device provides power up to PLIM. PLIM ≤ POUT and IOUT < IOCP The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for a maximum duration of tPLIM-DUR. IOCP ≤ IOUT < Ifast-trip The device limits current to PLIM for a maximum duration of tPLIM-DUR. Ifast-trip ≤ IOUT < ISCP The device turns off the internal FET after a delay of tfast-trip. ISCP ≤ IOUT The device turns off the internal FET after a delay of tSCP_dly.
8.3.5.1 Internal Current Limit for the TPS16410 and TPS16411
In power limiting devices, there is an internal current limit. If during power up, the output current exceeds overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP. The TPS16410 and TPS16411 devices also limit the output current if PLIM is set to more than (VOUT × IOCP) and IOUT exceeds IOCP.
8.3.6 Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads
In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on I OCP pin. The resistor value for overcurrent can be calculated by Equation 5. I OC P = 2.18 A R I OCP × 7.32 k Ω (5) The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by Equation 6. Bl an k i ng T i me I D LY o r PDL Y = 5 ms 10 n F × C DL Y (6)
8.3.7 Fast-Trip and Short-Circuit Protection
During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected and output current reaches I SCP level, the device turns off the internal FET after a delay of tSCP_dly. In case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the output current exceeds I fast-trip for a duration of t fast-trip. Figure 8-12 shows the short-circuit response of the device. www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS1641
Figure 8-12. Short-Circuit Response with VIN = 12 V
8.3.8 Analog Load Current Monitor (IMON) on the IOCP Pin
The device allows the system to monitor the output load current accurately by providing an analog current on the IOCP pin, which is proportional to the current through the FET. The resistor on IOCP or IMON pin converts this current into voltage and this voltage can be used for monitoring the output current. Output current can be calculated from voltage at IOCP or IMON pins by using Equation 7. I OU T = V I OC P − OS I MON × R IOCP G I MO N × R IO C P (7)
8.3.9 IN to OUT Short Detection
The TPS1641x devices include short detection across IN and OUT pins. If the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See the Electrical Characteristics table for Rshort. See the Timing Requirements table for tIN_OUT_Short_Detect. At start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. Figure 8-13 illustrates the response of device for IN to OUT short. TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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Figure 8-13. IN to OUT Short Detection for VIN = 12 V
8.3.10 Thermal Shutdown and Overtemperature Protection
During power or current limiting, there is a power dissipation [(V IN – V OUT) × I OUT] in the internal FET of the device. Due to this power dissipation, the temperature (T J) of device increases. When the device temperature increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411 and TPS16413 remain latched. To reset the latch, toggle EN/ SHDN or recycle the Vcc supply. To reset the latch, keep EN/ SHDN pin low for duration more than tLow_SHDN. After thermal shutdown, the TPS16410 and TPS16412 devices wait for temperature to go below [T TSD – TTSD-hyst] and then the device restarts after a delay of tretry.
8.3.11 Fault Response and Indication (FLT)
FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, and current and power limit events. Table 8-3 summarizes the state of FLT pin under different events. To prevent excessive dissipation in device during adjacent pin short test ( FLT to EN/SHDN), pull up the FLT pin with a resistor (R FLT) such that sink current into FLT pin is less than 3 mA. Figure 8-14 shows the connection diagram for FLT pin with a pullup resistor. TPS1641x FLT INRFLT EN IFLT < 3 mA Figure 8-14. FLT Output in the TPS1641x www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS1641
Table 8-3. FLT Pin Indication for Different Events Event, Condition FLT Pin Device disabled or shutdown (EN Low) Low Overvoltage protection (VOVP > VOVPR) Low IN to short detection Low Thermal shutdown (TJ > TTSD) Low After current or power limiting timeout Low At power up for a duration of TON_dly Low
8.4 Device Functional Modes
The device can be brought into low power shutdown mode by bringing the EN/ SHDN pin low. In low power shutdown mode, the internal blocks of devices are shut down and it takes I QSD from VCC supply. See the Enable and Shutdown Input (EN/SHDN) section for details. TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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9 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
9.1 Application Information
TPS1641x devices include power limiting or current limiting for a low power circuit (as per IEC60335 and UL60730 standards) in appliances, HVAC actuators, and medical equipment. TPS1641x devices also have IN to OUT short detection for internal FET for IN-OUT short testing during IEC60335 or UL60730 certifications. The TPS16410 and TPS16411 have an accurate power limiting feature while the TPS16412 and TPS16413 have an accurate current limiting feature. For transient current required for start-up of motors or actuators, TPS1641x devices have a configurable overcurrent protection threshold (IOCP) and configurable blanking time (IDLY/PDLY). For start-up with big capacitance (< 1 mF) on output, the TPS1641x include dVdT feature to control the output slew rate and limiting the inrush current during power up. The output current can be monitored from IOCP or IMON pin, by sensing the voltage on this pin.
9.2 Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs)
The TPS16410 and TPS16411 can be used for 15-W power limiting for low-power circuits in IEC60335 and UL60730 standards. The output power limit can be configured by a resistor on the PLIM pin. Figure 9-1 provides a typical application circuit for 15-W power limiting. COUT TPS16410 TPS16411 IN OUT EN/SHDN PLIM PDLY FLT GND CIN IOCP/IMON Vcc OVP dVdT 95.3 k 16.2 k 1 M 47 k 100 nF 470 µF VIN = 18 to 32V VOUT R2 R3 CDLY 10 nF CdVdt 150 nF Figure 9-1. 15-W Power Limiting for Low-Power Circuits www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS1641
9.2.1 Design Requirements
Table 9-1. Design Parameters Parameter Value VIN 18 V to 32 V POUT ≤ 15 W Overcurrent protection 1 A Output capacitance (COUT) 470 μF IINRUSH ≤ 350 mA Blanking time for transients (PDLY) 5 ms
9.2.2 Detailed Design Procedure
9.2.2.1 Setting Overvoltage Setpoints
Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin. The value of resistors can be calculated using Equation 8 and Equation 9. To set the OVP rising setpoint to 32 V, R1 = 1 MΩ and R2 = 47 kΩ are selected. OVP R i sing Set point = V O VPR × R 1 + R 2 R 2 (8) OVP Fal ling Se t point = V OVPF × R 1 + R 2 R 2 (9)
9.2.2.2 Setting the Output Overcurrent Setpoint (IOCP)
To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this resistor (R4), use Equation 5. For IOCP = 1 A, R4 is selected as 16.2 kΩ.
9.2.2.3 Setting the Output Power Limit
For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power limit, useEquation 4. To keep output power limit ≤ 15 W, R3 was selected as 95.3 kΩ.
9.2.2.4 Monitoring the Output Current
The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current can be calculated using Equation 7.
9.2.2.5 Limiting the Inrush Current and Setting the Output Slew Rate
For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt pin. The value of inrush current can be estimated by Equation 10. To keep the inrush current below 350 mA, CdVdt is selected as 150 nF. I I NRU S H = I dV dt × G dV dt × C OU T C d Vd t (10) TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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9.2.3 Application Curves
Figure 9-2. Overvoltage Protection up to 40 V Figure 9-3. Inrush Current Control for Hot Plugin at Input Figure 9-4. Output Short-Circuit Protection Figure 9-5. 15-W Power Limiting Figure 9-6. IN to OUT Short Detection with VIN = 24 V www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPS1641
9.3 Best Design Practices
- Use CIN ≥ 10 nF for decoupling Vcc and IN pins.
- Do not leave the OVP, PLIM or ILIM, and IOCP or IMON pins open or floating.
- Connect the PowerPAD of the device to GND on the PCB.
- Do not connect the EN/SHDN pin to voltage more than 5 V.
- Do not connect dVdt, PLIM or ILIM, and IOCP or IMON pins to GND.
9.3.1 Applications Limitations
The following are limitations in present samples of the TPS1641x devices (PTPS1641x). These limitations will be corrected in production release of the device.
- With a CDLY capacitor on IDLY or PDLY pin, the device provides shorter tILIM-DUR or tILIM-DUR (< 2 × tIDLY or < 2 × tPDLY ) and tretry (< 8 × tIDLY or 8 × tPDLY) timings. In case of overload or overcurrent events (with IOUT > ILIM), the device ends current limiting and retries within a short duration. Without the CDLY capacitor, the device provides tILIM-DUR or tILIM-DUR of 155 ms and tretry of 620 ms. Figure 9-7 illustrates tILIM-DUR and tretry timings.
- The TPS16412 device latches off for an overcurrent event with IOUT close to ILIM and IOUT < IOCP. The TPS16412 device keeps the internal FET off after IDLY blanking duration for an overcurrent event with IOUT close to ILIM and IOUT < IOCP. Toggle the EN/SHDN pin or recycle VIN supply to restart.
- Devices can sustain ESD(HBM) voltage up to ±500 V. Use proper ESD safe work surfaces and ESD safe packaging process with the present samples of the device. Figure 9-7. Shorter tILIM-DUR and tretry Timings with CDLY = 10 nF
9.4 Power Supply Recommendations
- Use 4.5 V ≤ VIN ≤ 40 V for the TPS16410 and TPS16411.
- Use 2.7 V ≤ VIN ≤ 40 V for the TPS16412 and TPS16413.
- Use VIN ≤ VCC ≤ 60 V.
- Pull up FLT with voltage ≤ 60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA.
9.4.1 Transient Protection
In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. Figure 9-8 illustrates the transient protection circuit. Typical methods for addressing transients include:
- Minimize lead length and inductance into and out of the device.
- Use a large PCB GND plane.
- Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an absolute maximum rating of –1 V for negative transient spikes on output.
- Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device.
- Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with Equation 11. V I N − S PI KE = V I N + I LO AD × L I N C I N (11)
- Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient voltage below the absolute maximum rating of the device. TPS1641x IN OUT EN/SHDN PLIM/ILIM PDLY/IDLY VOUT RPLIM FLT GND CIN CDLY ROCP IOCP/IMON Vcc OVP dVdT COUTD2* D1* TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output. Figure 9-8. Transient Protection with TPS1641x
9.5 Layout
9.5.1 Layout Guidelines
- High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current.
- The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection.
- The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND pin of the IC.
- Locate the following support components close to their connection pins: – RILM or RPLM – RIOCP – CDLY – CdVdT – Resistors for OVP www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPS1641
- Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for these components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval, and soft-start timing.
- Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals.
- Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the GND pin of the IC.
9.5.2 Layout Example
Figure 9-9. Layout Example TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPS1641
11.1 Tape and Reel Information
Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PTPS16410DRCR VSON DRC 10 250 210.0 185.0 35.0 PTPS16411DRCR VSON DRC 10 250 210.0 185.0 35.0 PTPS16412DRCR VSON DRC 10 250 210.0 185.0 35.0 PTPS16413DRCR VSON DRC 10 250 210.0 185.0 35.0 www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TPS1641
www.ti.com PACKAGE OUTLINE C 10X 0.30 0.18 2.4 0.1 1.65 0.1 8X 0.5 1.0 0.8 10X 0.5 0.3 0.05 0.00 A 3.1 2.9 B 3.1 2.9 (0.2) TYP 4X (0.25) 2X (0.5) VSON - 1 mm max heightDRC0010J PLASTIC SMALL OUTLINE - NO LEAD 4218878/B 07/2018 PIN 1 INDEX AREA SEATING PLANE 0.08 C 5 6 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED SYMM SYMM11 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. SCALE 4.000 TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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www.ti.com EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND0.07 MAX ALL AROUND 10X (0.24) (2.4) (2.8) 8X (0.5) (1.65) ( 0.2) VIA TYP (0.575) (0.95) 10X (0.6) (R0.05) TYP (3.4) (0.25) (0.5) VSON - 1 mm max heightDRC0010J PLASTIC SMALL OUTLINE - NO LEAD 4218878/B 07/2018 SYMM 5 6 EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE:20X SYMM NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) EXPOSED METAL www.ti.com TPS1641 SLVSGF4 – JUNE 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TPS1641
www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 10X (0.24) 10X (0.6) 2X (1.5) (1.06) (2.8) (0.63) 8X (0.5) (0.5) 4X (0.34) 4X (0.25) (1.53) VSON - 1 mm max heightDRC0010J PLASTIC SMALL OUTLINE - NO LEAD 4218878/B 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 5 6 EXPOSED METAL TYP11 SYMM TPS1641 SLVSGF4 – JUNE 2022 www.ti.com ADVANCE INFORMATION
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www.ti.com 1-Jul-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTPS16410DRCR ACTIVE VSON DRC 10 3000 TBD Call TI Call TI -40 to 125 Samples PTPS16411DRCR ACTIVE VSON DRC 10 3000 TBD Call TI Call TI -40 to 125 Samples PTPS16412DRCR ACTIVE VSON DRC 10 3000 TBD Call TI Call TI -40 to 125 Samples PTPS16413DRCR ACTIVE VSON DRC 10 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1
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www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VSON - 1 mm max heightDRC 10 PLASTIC SMALL OUTLINE - NO LEAD3 x 3, 0.5 mm pitch 4226193/A
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