Driver IC

PTPS12000QDGXRQ1

Texas Instruments

TPS1200-Q1 45-V, Automotive Low IQ Smart High Side Driver with Short-Circuit Protection and Diagnostics DECEMBER 2023

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TPS1200-Q1 45-V, Automotive Low IQ Smart High Side Driver with Short-Circuit Protection and Diagnostics

1 Features

AEC-Q100 automotive qualified for automotive

applications

– Device temperature grade 1: –40°C to +125°C ambient operating temperature range

Functional Safety-Capable – Documentation available to aid functional safety system design
3.5V to 40V input range (45V absolute maximum)
Reverse input protection down to –40V
Integrated 11V charge pump
Low quiescent current, 43µA in operation
Low 1.5µA shutdown current (EN/UVLO = Low)
Strong gate driver (2A source and sink)
Adjustable short circuit protection (ISCP) using external Rsense or MOSFET VDS sensing with adjustable delay (TMR)
High or low-side current sense configuration (CS_SEL)
Fault indication (FLT) during short-circuit fault, input under voltage and short-circuit comparator diagnosis (SCP_TEST)
Fault indication (FLT_GD) for Gate drive UVLO
Adjustable input undervoltage lockout (UVLO) and overvoltage protection (OV)

2 Applications

Automotive 12V BMS
DC/DC converter
Power tools

3 Description

The TPS12000-Q1 is a 45V low IQ smart high side driver with protection and diagnostics. With wide operating voltage range of 3.5V–40V, the device is suitable for 12V system designs. The device can withstand and protect the loads from negative supply voltages down to –40V. It has a strong (2A) gate drive that enables power switching using parallel MOSFETs in high current system designs. The device provides adjustable short circuit protection. Auto-retry and latch-off fault behavior can be configured. By using CS+ and CS– pins, current sensing can be done either by an external sense resistor or by MOSFET VDS sensing. High side or low side current sense resistor configuration is possible by using CS_SEL pin input. The device also features diagnosis of the internal short circuit comparator using external control on SCP_TEST input. Low quiescent current 43µA (typical) in operation enables always ON system designs. Quiescent current reduces to 1.5μA (typical) with EN/UVLO low. The TPS12000-Q1 is available in a 19-pin VSSOP package.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TPS12000-Q1 DGX (VSSOP, 19) 5.1mm × 3.0mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. TPS12000-Q1 BSTSRC VS VBATT EN/UVLO CS+ CTMR TMR GND VOUT CBST OV PU PD INPON OFF SCP_TEST FLT VCC FLT_GD VCC Test Mode CS- RSNS ISCP RISCP Smart High Side Driver for DC-DC TPS12000-Q1 CBST BSTPU SRC INPONOFF PD RSNS CS-CS+ RISCP CTMR TMR GNDSCP_TESTISCP CS_SEL VCC CBULK Motor BridgeCSPCSM CSP CSM TPS12000-Q1 CBST BSTPU SRC VBATT INPONOFF PD CS-CS+ RISCP CTMR TMR GNDSCP_TESTISCP CS_SEL VOUT FLT VCC FLT_GD VCC VS EN/UVLO OV VBATT VS EN/UVLO OV VCC FLT_GD VCC FLT Circuits With High Side MOSFET VDS Sensing and Low Side Current Sensing ADVANCE INFORMATION TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

8.2 Typical Application: Driving Power at all Times

11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

N.C EN/UVLO 20 SRC PD CS- BST PU OV INP FLT_GD N.C CS_SEL SCP_TEST FLT GND TMR VS CS+ ISCP Figure 4-1. DGX Package, 19-Pin VSSOP (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. EN/UVLO 1 I EN/UVLO input. A voltage on this pin above 1.24V enables normal operation. Forcing this pin below 0.3V shuts down the device reducing quiescent current to approximately 1.5µA (typical). Optionally connect to the input supply through a resistive divider to set the undervoltage lockout. When EN/UVLO is left floating an internal pull down of 100nA pulls EN/UVLO low and keeps the device in shutdown state. OV 2 I Adjustable overvoltage threshold input. Connect a resistor ladder from input supply, OV to GND. When the voltage at OVP exceeds the overvoltage cut-off threshold then the PD is pulled down to SRC turning OFF the external FET. When the voltage at OV goes below OV falling threshold then PU gets pulled up to BST, turning ON the external FET. OV must be connected to GND when not used. When OV is left floating an internal pull down of 100nA pulls OV low and keeps PU pulled up to BST. INP 3 I Input signal for external discharge FET control. CMOS compatible input reference to GND that sets the state of PD and PU pins. INP has an internal weak pull down of 100nA to GND to keep PD pulled to SRC when INP is left floating. FLT_GD 4 O Open drain fault output for gate drive UVLO. This pin asserts low when gate drive across PU to SRC is above 7.5V. FLT 5 O Open drain fault output. This pin asserts low during short circuit fault, input UVLO and during SCP comparator diagnosis. If FLT feature is not desired then connect it to GND. GND 6 G Connect GND to system ground. www.ti.com TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS1200-Q1

Table 4-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. CS_SEL 7 I Current sense select input. Connect this pin to ground to activate high side current sense. Drive this pin to > 2V to activate low side current sensing. CS_SEL has an internal weak pull down of 100nA to GND. ISCP 8 I Short-circuit detection setting. A resistor across ISCP to GND sets the short circuit current comparator threshold. If short-circuit protection feature is not desired then connect CS+, CS–, and VS pins together and connect ISCP and TMR pins to GND. TMR 9 I Fault timer input. A capacitor across TMR pin to GND sets the delay time for short-circuit fault turn-off. Leave it open for fastest setting. If short-circuit protection feature is not desired then connect CS+, CS–, and VS pins together and connect ISCP and TMR pins to GND. SCP_TEST 10 I Internal short circuit comparator (SCP) diagnosis input. When SCP_TEST is driven low to high with INP pulled high, the internal SCP comparator operation is checked. FLT goes low and PD gets pulled to SRC if SCP comparator is functional. Connect SCP_TEST pin to GND if this feature is not desired. SCP_TEST has an internal weak pull down of 100nA to GND. NC 11 — No connect. BST 12 O High side bootstrapped supply. An external capacitor with a minimum value of > Qg(tot) of the external FET must be connected between this pin and SRC. SRC 13 O Source connection of the external FET PD 14 O High current gate driver pull-down. This pin pulls down to SRC. For the fastest turn-off, tie this pin directly to the gate of the external high side MOSFET. PU 15 O High current gate driver pull-up. This pin pulls up to BST. Connect this pin to PD for maximum gate drive transition speed. A resistor can be connected between this pin and the gate of the external MOSFET to control the in-rush current during turn-on. CS– 17 I Current sense negative input. CS+ 18 I Current sense positive input. NC 19 — No connect. VS 20 Power Supply pin of the controller. (1) I = input, O = output, I/O = input and output, P = power, G = ground TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 www.ti.com ADVANCE INFORMATION

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input pins VS, CS+, CS– to GND –40 45 V SRC to GND –40 45 PU, PD, BST to SRC –0.3 19 ISCP, TMR, SCP_TEST to GND –0.3 5.5 EN/UVLO, OV, INP, CS_SEL to GND, V(VS) > 0 V –1 45 EN/UVLO, OV, INP, CS_SEL to GND, V(VS) ≤ 0 V V(VS) (45 + V(VS)) CS+ to CS– –1 45 FLT , FLT_GD to GND –1 20 Sink current I(FLT), I(FLT_GD) 10 mA I(CS+) to I(CS–), 1 msec –100 100 mA Output pins PU, PD, BST to GND –40 60 V Operating junction temperature, Tj (2) –40 150 Storage temperature, Tstg –40 150 (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 VCharged device model (CDM), per AEC Q100-011 Corner pins (EN/UVLO, VS, SCP_TEST) ±750 Other pins ±500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1) MIN NOM MAX UNIT Input pins VS to GND 3.5 40 VEN/UVLO, INP, CS_SEL to GND 0 40 Output pins FLT , FLT_GD to GND 0 15 External capacitor VS, SRC to GND 22 nF BST to SRC 0.1 µF Tj Operating Junction temperature(2) –40 150 °C (1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test conditions, see Electrical Characteristics. (2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C. www.ti.com TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS1200-Q1

5.4 Thermal Information

THERMAL METRIC(1) TPS1200-Q1 UNITDGX

19 PINS

RθJA Junction-to-ambient thermal resistance 92.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.6 °C/W RθJB Junction-to-board thermal resistance 47.5 °C/W ΨJT Junction-to-top characterization parameter 0.6 °C/W ΨJB Junction-to-board characterization parameter 47.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Electrical Characteristics

TJ = –40 ℃ to +125℃. V(VS) = 12 V, V(BST – SRC) = 11 V, V(SRC) = 0 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE V(VS) Operating input voltage 3.5 40 V Total System Quiescent current, I(GND) V(EN/UVLO) = 2 V 43 µA I(SHDN) SHDN current, I(GND) V(EN/UVLO) = 0 V, V(SRC) = 0 V 1.5 µA ENABLE, UNDERVOLTAGE LOCKOUT (EN/UVLO), SHORT CIRCUIT COMPARATOR TEST (SCP_TEST) INPUT V(UVLOR) UVLO threshold voltage, rising 1.24 V V(UVLOF) UVLO threshold voltage, falling 1.14 V V(ENR) Enable threshold voltage for low Iq shutdown, rising 1.02 V V(ENF) Enable threshold voltage for low Iq shutdown, falling 0.3 V V(SCP_TESTR) SCP test mode rising threshold 1.02 V V(SCP_TESTF) SCP test mode rising threshold 0.3 V I(EN/UVLO) Enable input leakage current V(EN/UVLO) = 12 V 180 nA OVER VOLTAGE PROTECTION (OV) INPUT V(OVR) Overvoltage threshold input, risIng 1.24 V V(OVF) Overvoltage threshold input, falling 1.14 V CHARGE PUMP (BST–SRC) V(BST – SRC_ON) Charge Pump turn on voltage V(EN/UVLO) = 2 V 10 V V(BST – SRC_OFF) Charge Pump turn off voltage V(EN/UVLO) = 2 V 11.8 V V(BST_UVLOR) V(BST – SRC) UVLO voltage threshold, rising V(EN/UVLO) = 2 V 9.5 V V(BST_UVLOF) V(BST – SRC) UVLO voltage threshold, falling V(EN/UVLO) = 2 V 7.2 V I(SRC) SRC pin leakage current V(EN/UVLO) = 2 V, V(INP) = 0 V 1 µA GATE DRIVER OUTPUTS (PU, PD) I(PU) Peak source current 1.69 A I(PD) Peak sink current 2 A V(G_GOOD) VGS good threshold 7.5 V SHORT CIRCUIT PROTECTION (ISCP) V(SCP) SCP threshold RISCP = 32.5 kΩ 60 75 90 mV V(SCP) SCP threshold RISCP = 15 kΩ 40 mV DELAY TIMER (TMR) TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 www.ti.com ADVANCE INFORMATION

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5.5 Electrical Characteristics (continued)

TJ = –40 ℃ to +125℃. V(VS) = 12 V, V(BST – SRC) = 11 V, V(SRC) = 0 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(TMR_SRC_CB) TMR source current 80 µA I(TMR_SRC_FLT) TMR source current 2.2 µA I(TMR_SNK) TMR sink current 2.5 µA V(TMR_SC) 1.1 V V(TMR_LOW) 0.2 V N(A-R Count) 32 INPUT CONTROLS (INP), CURRENT SENSE SELECT (CS_SEL) , FAULT FLAGS (FLT, FLT_GD) R(FLT), R(FLT_GD) Pull-down resistance 70 Ω V(INP_H) 2 V V(INP_L) 0.8 V V(CS_SEL_H) CS_SEL threshold for low side sensing 2 V V(CS_SEL_L) CS_SEL threshold for high side sensing 0.8 V

5.6 Switching Characteristics

TJ = –40 ℃ to +125℃. V(VS) = 12 V, V(BST – SRC) = 11 V, V(SRC) = 0 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPU(INP_H) INP turn on propogation delay INP ↑ to PU ↑, CL = 47 nF 1 µs tPD(INP_L) INP turn off propogation delay INP ↓ to PD ↓, CL = 47 nF 5 µs tPD(UVLO_OFF) UVLO turn off propogation delay UVLO ↓ to PD ↓, CL = 47 nF 7.5 µs tPD(OV_OFF) OV turn off progopation delay OV ↑ to PD ↓, CL = 47 nF 7.5 µs tSC Hard short-circuit protection propogation delay V(CS+–CS-)↑ V(SCP) to PD ↓, CL = 47 nF, CTMR = Open 4 µs tSC_PUS Short-circuit protection propogation delay during power up with output short circuit CTMR = Open 10 µs www.ti.com TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS1200-Q1

6 Parameter Measurement Information

V(INP)V(PU) - V(SRC) 0 V tPU(INP_H) V(PU) tSC 0 V V(PD) V(PD) - V(SRC) V(SNS_SCP) + 0.02 V V(CS+) - V(CS-) 0 V V(INP_H) 0 V V(INP)V(PD) - V(SRC) 0 V tPD(INP_L) V(PD) V(INP_L) 1 V 1 V 5 V Figure 6-1. Timing Waveforms TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 www.ti.com ADVANCE INFORMATION

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7 Detailed Description

7.1 Overview

The TPS12000-Q1 is a 45V low IQ smart high side driver with protection and diagnostics. With wide operating voltage range of 3.5V–40V, the device is suitable for 12V system designs. The device can withstand and protect the loads from negative supply voltages down to –40V. It has strong 1.69A and 2A peak source and sink gate driver enabling power switching using parallel FETs in high current system designs. The device provides configurable short circuit protection using ISCP and TMR pins for adjusting the threshold and response time respectively. Auto-retry and latch-off fault behavior can be configured. With TPS12000-Q1, current sensing can be done either by an external sense resistor or by MOSFET VDS sensing. High or low side current sense resistor configuration is possible by using CS_SEL pin input. Diagnosis of the integrated short circuit comparator can be done using external control on SCP_TEST input. The device has adjustable undervoltage and overvoltage protection. The device indicates fault ( FLT) on open drain output during during short circuit and input under voltage conditions. It also have a dedicate fault indication (FLT_GD) to indicate the gate drive UVLO condition. Low Quiescent Current 43µA operation enables always ON system designs. Quiescent current reduces to 1.5 μA (typical) with EN/UVLO low.

7.2 Functional Block Diagram

FLT_GD CBST RSNS ISCP CS+ CS- PU PD SRC RISCP Gate Driver control logic CTMR OV EN/UVLO Charge pump enable logic SRC BST EN CP (11 V) 345 µA VS TMR VS Internal Regulators VINT EN POR 2.7 V 2.4 V GATE_ON/OFF GATE_ON/OFF VINT 80 µA/2.2 µA GND FLT FLT_GD 1.24 V 1.14 V 1 V 0.3 V 2 V 0.8 V 1.24 V 1.14 V EN UVLO 70 Ω VOUTQ1 2 A1.69 A TPS12000-Q1 BST VINT 2 V 0.8 V SCP_TEST VDS, VGS Fault logic 2 V 0.8 V CS_SEL PD SRC LSHS VDS Comparator HS, LS select VGS Comparator Reverse Protection LogicSRC VS FLT FLT 70 Ω FLT_GD www.ti.com TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS1200-Q1

7.3 Feature Description

7.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)

Figure 7-1 shows a simplified diagram of the charge pump and gate driver circuit implementation. The device houses a strong 1.69-A/2-A peak source/sink gate driver (PU, PD) for driving power FET. The strong gate drivers enable paralleling of FETs in high power system designs ensuring minimum transition time in saturation region. A 11-V, 345-µA charge pump is derived from VS terminal and charges the external boot-strap capacitor, C BST that is placed across the gate driver (BST and SRC). VS is the supply pin to the controller. With VS applied and EN/UVLO pulled high, the charge pump turns ON and charges the CBST capacitor. After the voltage across C BST crosses V(BST_UVLOR), the GATE driver section is activated. The device has a 1-V (typical) UVLO hysteresis to ensure chattering less performance during initial GATE turn ON. Choose C BST based on the external FET Q G and allowed dip during FET turn-ON. The charge pump remains enabled until the BST to SRC voltage reaches 11.8 V, typically, at which point the charge pump is disabled decreasing the current draw on the VS pin. The charge pump remains disabled until the BST to SRC voltage discharges to 10 V typically at which point the charge pump is enabled. The voltage between BST and SRC continue to charge and discharge between 11.8 V and 10 V as shown in the Figure 7-2. R LOAD BST SRC 12 V 345 µA PU PD Charge pump (11 V) Level ShifterINP C BST CS- CS+ To VDS current sensing TPS12000-Q1 VS 11.8 V 10 V V (BST – SRC) SRC Figure 7-1. Gate Driver TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 www.ti.com ADVANCE INFORMATION

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V (VS) V (BST-SRC) V (EN/UVLO) INTERNAL GATE DRIVER ENABLE T ON T OFF V (BST_UVLOR) T DRV_EN V (BST-SRC_ON) V (BST-SRC_OFF) Figure 7-2. Charge Pump Operation Use the following equation to calculate the initial gate driver enable delay: T D RV _ EN = C B ST × V BST _ UVL O R 345 µ A (1) Where, CBST is the charge pump capacitance connected across BST and SRC pins. V(BST_UVLOR) = 9.5 V (max). If T DRV_EN must be reduced then pre-bias BST terminal externally using an external V AUX supply through a low leakage diode D 1 as shown in Figure 7-3. With this connection, T DRV_EN reduces to 400 µs. TPS12000-Q1 application circuit with external supply to BST is shown in Figure 7-3. www.ti.com TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS1200-Q1

*D 1 V AUX R SNS TPS12000-Q1 C BST BSTPU SRC VBATT INPON OFF PDCS-CS+ R ISCP C TMR TMR GNDSCP_TEST ISCP CS_SEL VOUT FLT R 4 V CC FLT_GD R 5 V CC VS EN/UVLO OV R 1 R 2 R 3 Figure 7-3. TPS12000-Q1 Application Circuit With External Supply to BST Note VAUX can be supplied by external regulated supply ranging between 8 V and 18 V.

7.3.2 Capacitive Load Driving Using FET Gate (PU, PD) Slew Rate Control

Certain end equipments like automotive power distribution unit power different loads including other ECUs. These ECUs can have large input capacitances. If power to the ECUs is switched on in uncontrolled way, large inrush currents can occur potentially damaging the power FETs. To limit the inrush current during capacitive load switching, the following system design technique can be used with TPS12000-Q1. For limiting inrush current during turn ON of the FET with capacitive loads, use R 1, R2, C1 as shown in Figure 7-4. The R1 and C1 components slow down the voltage ramp rate at the gate of the FET. The FET source follows the gate voltage resulting in a controlled voltage ramp across the output capacitors. BST SRC PU PD Level ShifterINP CBST TPS12000-Q1 CLOAD Figure 7-4. Inrush Current limiting Use the Equation 2 to calculate the inrush current during turn-ON of the FET. I INRUSH = C LOAD × V B ATT T c ha r ge (2) TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 www.ti.com ADVANCE INFORMATION

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C 1 = 0.63 × V B ST − SRC × C LOAD R 1 × I INRUSH (3) Where, CLOAD is the load capacitance, VBATT is the input voltage and Tcharge is the charge time, V(BST-SRC) is the charge pump voltage (11 V), Use a damping resistor R2 (~ 10 Ω) in series with C1. Equation 3 can be used to compute required C1 value for a target inrush current. A 100 kΩ resistor for R1 can be a good starting point for calculations. Connecting PD pin of TPS12000-Q1 directly to the gate of the external FET ensures fast turn OFF without any impact of R1 and C1 components. C1 results in an additional loading on C BST to charge during turn-ON. Use below equation to calculate the required CBST value: C B ST = Q g t ot a l ∆ V BST + 10 × C 1 (4) Where, Qg(total) is the total gate charge of the FET. ΔVBST (1 V typical) is the ripple voltage across BST to SRC pins.

7.3.3 Short-Circuit Protection

The TPS12000-Q1 feature adjustable short circuit protection. The threshold and response time can be adjusted using RISCP resistor and CTMR capacitor respectively. The device senses the voltage across CS+ and CS– pins. These pins can be connected across an external high and low side current sense resistor (R SNS) as or across the FET drain and source terminals for FET R DSON sensing shown in Figure 7-5 , Figure 7-6 , Figure 7-7 and Figure 7-8 respectively. RSNS TPS12000-Q1 CBST BSTPU SRC VBATT INPON OFF PDCS-CS+ RISCP CTMR TMR GNDSCP_TEST ISCP CS_SEL VOUT FLT VCC FLT_GD VCC VS EN/UVLO OV Figure 7-5. TPS12000-Q1 Application Circuit With External Sense Resistor RSNS Based High Side Current Sensing TPS12000-Q1 CBST BSTPU SRC VBATT INPON OFF PD CS-CS+ RISCP CTMR TMR GNDSCP_TEST ISCP CS_SEL VOUT FLT VCC FLT_GD VCC VS EN/UVLO OV Figure 7-6. TPS12000-Q1 Application Circuit With MOSFET RDSON Based Current Sensing www.ti.com TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS1200-Q1

SCP_TEST RSNS ISCP CS_SEL CS- CS+ VCC 12 V FLT_GD VCC OV Figure 7-7. TPS12000-Q1 Application Circuit With External Sense Resistor RSNS Based Low Side Current Sensing on Battery Side CSM TPS12000-Q1 CBST BSTPU SRC INPON OFF PD RSNS CS-CS+ RISCP CTMR TMR GNDSCP_TESTISCP CS_SEL VCC CBULK Motor BridgeCSP CSM CSP VBATT VS EN/UVLO OV VCC FLT_GD VCC FLT Figure 7-8. TPS12000-Q1 Application Circuit With External Sense Resistor RSNS on Based Low Side Current Sensing on Load Side Set the short-circuit detection threshold using an external R ISCP resistor across ISCP and GND pins. Use Equation 5 to calculate the required RISCP value: R ISCP Ω = I SC × R SNS − 10 mV 2 µ A (5) Refer to Equation 9 in Section 8.1.1 section for update in equation in final revision of IC. Where, RSNS is the high or low side current sense resistor value or the FET RDSON value. ISC is the desired short circuit current level. The short circuit protection response is fastest with no CTMR cap connected across TMR and GND pins. With device powered ON and EN/UVLO, INP pulled high, During Q 1 turn ON, first VGS of external FET is sensed by monitoring the voltage across PD to SRC. Once PD to SRC voltage raises above V (G_GOOD) (7.5 V typical) threshold which ensures that the external FET is enhanced, then the SCP comparator output is monitored. If the sensed voltage across CS+ and CS– exceeds the short-circuit set point (V SCP), PD pulls low to SRC and FLT asserts low. Subsequent events can be set either to be auto-retry or latch off as described in following sections. VGS of external FET (Q 1) is only monitored when CS_SEL is pulled low. VGS of external FET (Q 1) is not monitored for low side current sensing as shown Figure 7-7 and Figure 7-8.

7.3.3.1 Short-Circuit Protection With Auto-Retry

The CTMR programs the short-circuit protection delay (t SC) and auto-retry time (t RETRY). Once the voltage across CS+ and CS– exceeds the set point, the CTMR starts charging with 80-μA pull-up current. After C TMR charges to V (TMR_SC), PD pulls low to SRC and FLT asserts low providing warning on impending FET turn OFF. Post this event, the auto-retry behavior starts. The C TMR capacitor starts discharging with 2.5-uA pulldown current. After the voltage reaches V (TMR_LOW) level, the capacitor starts charging with 2.2-uA pullup. After 32 charging-discharging cycles of CTMR the FET turns ON back and FLT de-asserts. The device retry time (tRETRY) is based on CTMR for the first time as per Equation 7. Use Equation 6 to calculate the CTMR capacitor to be connected across TMR and GND. TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 www.ti.com ADVANCE INFORMATION

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C TM R = I TMR × t SC 1.1 (6) Where, ITMR is internal pull-up current of 80-μA. tSC is desired short-circuit response time. Leave TMR floating for fastest short-circuit response time. t RETRY = 22.7 × 10 6 × C T M R (7) If the short-circuit pulse duration is below tSC then the FET remains ON and CTMR gets discharged using internal pull down switch. ISC 0 A I_LOAD FET VGS 12 V FLT 0 V 0 V tSC = T CB Vcc TPULSE VTMR V(TMR_SC) 1st 2nd 32nd V(TMR_LOW) 80 µA /2.2 µA 2.5 µA TMR VINT TPS1200-Q1 Figure 7-9. Short-Circuit Protection With Auto-Retry

7.3.3.2 Short-Circuit Protection With Latch-Off

Connect an approximately 100-k Ω resistor across C TMR as shown in . With this resistor, during the charging cycle, the voltage across CTMR gets clamped to a level below V (TMR_SC) resulting in a latch-off behavior and FLT asserts low at same time. Use Equation 8 to calculate CTMR capacitor to be connected between TMR and GND for RTMR = 100-kΩ. C TM R = t S C R TMR × ln 1 1 − 1.1 R TM R × 80 µ A (8) Where, ITMR is internal pull-up current of 80-μA. tSC is desired short-circuit response time. www.ti.com TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS1200-Q1

Toggle INP or EN/UVLO (below V (ENF)) or power cycle VS below V (VS_PORF) to reset the latch. At low edge, the timer counter is reset and CTMR is discharged. PU pulls up to BST when INP is pulled high. ISC 0 A I_LOADFET VGS 12 V FLT 0 V 0 V tSC = TCB Vcc TPULSE VTMR V(TMR_SC) 1st V(TMR_LOW) INP The resistor across TMR to GND prevents the VTMR to charge to upper threshold and the counter does not see next counts, resulting in FET to stay latch OFF When INP is pulled low, the timer counter is reset and TMR cap is discharged Starts a fresh turn ON cycle 80 µA /2.2 µA 2.5 µA TMR VINT TPS1200-Q1 100 kΩ Figure 7-10. Short-Circuit Protection With Latch-Off

7.3.4 Overvoltage (OV) and Undervoltage Protection (UVLO)

TPS12000-Q1 has an accurate undervoltage protection (< ±2%) using EN/UVLO pin and an accurate overvoltage protection (< ±2 %), providing robust load protection. Connect a resistor ladder as shown in Figure 7-11 for undervoltage and overvoltage protection threshold programming. TPS12000-Q1 R 2 R 1 R 3 EN/UVLO OV VIN UVLOb OVP 1.24 V 1.24 V 1.14 V 1.14 V Figure 7-11. Programming Overvoltage and Undervoltage Protection Threshold

7.3.5 Reverse Polarity Protection

The TPS12000-Q1 devices features integrated reverse polarity protection to protect the device from failing during input and output reverse polarity faults. Reverse polarity faults can occur during jump start, installation and maintenance of the end equipment’s. The device is tolerant to reverse polarity voltages down to -40 V both on input and output. TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 www.ti.com ADVANCE INFORMATION

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Product Folder Links: TPS1200-Q1

On the output side, the device can see transient negative voltages during regular operation due to output cable harness inductance kickbacks when the switches are turned OFF. In such systems, the output negative voltage level is limited by the output side TVS or a diode.

7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)

In the safety critical designs, short-circuit protection (SCP) feature and its diagnosis is important. The TPS12000-Q1 features the diagnosis of the internal short circuit protection. When SCP_TEST is driven low to high then, a voltage is applied internally across the SCP comparator inputs to simulate a short circuit event. The comparator output controls the gate drive (PU/PD) and also the FLT. If the gate drive goes low (with initially being high) and FLT alos goes low then it indicates that the SCP is good otherwise it is to be treated as SCP feature is not functional. If the SCP_TEST feature is not used, then connect SCP_TEST pin to GND.

7.3.7 TPS12000-Q1 as a Simple Gate Driver

Figure 7-12 shows application schematics of TPS12000-Q1 as a simple gate driver in load disconnect switch as well as back-to-back FETs driving topologies. The short-circuit protection feature is disabled. G TPS12000-Q1 C BST BSTPU SRC VBATT INPON OFF PDCS+ GND TMRSCP_TEST ISCP CS_SEL VOUT FLT FLT_GD R 5 V CC VS EN/UVLO OV R 1 R 2 R 3 CS- TPS12000-Q1 C BST BSTPU SRC VBATT INPON OFF PDCS+ GND TMRSCP_TEST ISCP CS_SEL VOUT FLT FLT_GD R 5 V CC VS EN/UVLO OV R 1 R 2 R 3 CS- G Figure 7-12. TPS12000-Q1 Application Circuit for Simple Gate Driver Design

7.4 Device Functional Modes

The TPS12000-Q1 has two modes of operation. Active mode and low IQ shutdown mode. If the EN/UVLO pin voltage is greater than V (ENR) rising threshold, then the device is in active mode. In active state the internal charge pump is enabled, gate drivers, all the protection and diagnostic features are enabled. If the EN/UVLO voltage is pulled below V (ENF) falling threshold, the device enters into low IQ shutdown mode. In this mode, the charge pump, gate drivers and all the protection features are disabled. The gate drive and external FETs turn OFF. The TPS12000-Q1 consumes low IQ of 1.5 μA (typical) in this mode. www.ti.com TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS1200-Q1

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TPS12000-Q1 is a 45-V low IQ smart high side driver with protection and diagnostics. With wide operating voltage range of 3.5 V–40 V, the device is suitable for 12-V system designs. The device can withstand and protect the loads from negative supply voltages down to –40 V. It has strong 1.69-A/2-A peak source/sink gate driver enabling power switching using parallel FETs in high current system designs. The device provides configurable short circuit protection using ISCP and TMR pins for adjusting the threshold and response time respectively. Auto-retry and latch-off fault behavior can be configured. With TPS12000-Q1, current sensing can be done either by an external sense resistor or by MOSFET VDS sensing. High or low side current sense resistor configuration is possible by using CS_SEL pin input. Diagnosis of the integrated short circuit comparator can be done using external control on SCP_TEST input.The device indicates fault (FLT) on open drain output during during short circuit and input under voltage conditions. It also have a dedicate fault indication (FLT_GD) to indicate the gate drive UVLO condition. Low Quiescent Current 43-µA operation enables always ON system designs. Quiescent current reduces to 1.5 μA (typical) with EN/UVLO low.

8.1.1 Application Limitations

This section highlights some limitations in the application which were identified during bench evaluation of the existing TPS12000-Q1 silicon on the evaluation module (EVM).

8.1.1.1 Short-Circuit Protection Delay

In application designs with high side current sense configurations as shown in Figure 7-5 and Figure 7-6 with CTMR = Open, the short-circuit protection delay during power up with output short circuited does not match the specified maximum value of 10 μs. Testing has shown that the actual short-circuit protection delay during power up by EN/UVLO signal is < 13 μs. A design fix must be included in the final version of the IC.

8.1.1.2 Short-Circuit Protection Threshold

The minimum short-circuit protection threshold is limited to 30 mV. A design update is planned in the final revision of the IC to extend the minimum threshold down to 20 mV. Due to the design update there will be a change of RSCP resistor formula and the revised formula will be as per the Equation 9. R ISCP Ω = I SC × R SNS − 19 mV 2 µ A (9) Lowest SCP threshold setting will be limited to 20 mV. TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 www.ti.com ADVANCE INFORMATION

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8.2 Typical Application: Driving Power at all Times (PAAT) Loads

TMR GNDSCP_TEST ISCP CS_SEL VOUT FLT R 4 V CC FLT_GD R 5 V CC VS EN/UVLO OV R 1 R 2 R 3 Figure 8-1. TPS12000-Q1 Application Circuit for driving PAAT loads with VDS based Current Sensing

8.2.1 Design Requirements

Table 8-1. Design Parameters PARAMETER VALUE Input Voltage Range, VIN 8 to 16V Undervoltage lockout set point, VINUVLO 6.5V Overvoltage set point, VINOVP 36V Maximum load current, IOUT 30A Short-circuit protection threshold, ISC 100A Fault timer period, tSC 50μs Fault response Auto-Retry Current sensing MOSFET VDS www.ti.com TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS1200-Q1

8.2.2 Detailed Design Procedure

Selection of MOSFET, Q1 For selecting the MOSFET Q 1, important electrical parameters are the maximum continuous drain current I D, the maximum drain-to-source voltage VDS(MAX), the maximum drain-to-source voltage VGS(MAX), and the drain-to- source ON resistance RDSON. The maximum continuous drain current, ID, rating must exceed the maximum continuous load current. The maximum drain-to-source voltage, V DS(MAX), must be high enough to withstand the highest voltage seen in the application. Considering 35 V as the maximum application voltage due to load dump, MOSFETs with V DS voltage rating of 40 V is chosen for this application. The maximum V GS TPS12000-Q1 can drive is 11 V, so a MOSFET with 15-V minimum V GS rating must be selected. To reduce the MOSFET conduction losses, an appropriate RDS(ON) is preferred. Based on the design requirements, BUK7J1R4-40H is selected and its ratings are:

40-V VDS(MAX) and ±20-V VGS(MAX)
RDS(ON) is 1.06-mΩ typical at 10-V VGS
MOSFET Qg(total) is 73 nC typical TI recommends to make sure that the short-circuit conditions such max V IN and ISC are within SOA of selected FET (Q1) for at-least > tSC timing. Selection of Bootstrap Capacitor, CBST The internal charge pump charges the external bootstrap capacitor (connected between BST and SRC pins) with approximately 345 μA. Use the following equation to calculate the minimum required value of the bootstrap capacitor for driving BUK7J1R4-40H MOSFET C B ST = Q g t ot a l

1 V = 73 nF (10)

Choose closest available standard value: 100 nF, 10 %. Programming the Short-Circuit Protection Threshold – RISCP Selection The RISCP sets the short-circuit protection threshold, whose value can be calculated using below equation: R ISCP Ω = I SC × R DS _ ON − 10 mV 2 µA (11) Refer to Equation 9 in Section 8.1.1 section for update in equation in final revision of IC. To set 100 A as short-circuit protection threshold, RISCP value is calculated to be 45 kΩ. Choose the closest available standard value: 45.2 kΩ, 1%. In case where large di/dt is involved, the system and layout parasitic inductances can generate large differential signal voltages between CS+ and CS- pins. This action can trigger false short-circuit protection and nuisance trips in the system. To overcome such scenario, TI suggests to add placeholder for RC filter components across sense resistor (R SNS) and tweak the values during test in the real system. The RC filter components should not be used in current sense designs by MOSFET VDS sensing to avoid impact on the short-circuit protection response. TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 www.ti.com ADVANCE INFORMATION

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Product Folder Links: TPS1200-Q1

Programming the Fault timer Period – CTMR Selection For the design example under discussion, overcurrent transients are allowed for 50- μs duration. This blanking interval, tSC (or circuit breaker interval, TCB) can be set by selecting appropriate capacitor C TMR from TMR pin to ground. The value of CTMR to set 50 μs for tSC can be calculated using following equation: C TM R = 80 µA × t SC 1.1 (12) Choose closest available standard value: 3.3 nF, 10 %. Setting the Undervoltage Lockout and Overvoltage Set Point The undervoltage lockout (UVLO) and overvoltage set point are adjusted using an external voltage divider network of R 1, R 2 and R 3 connected between VS, EN/UVLO, OV and GND pins of the device. The values required for setting the undervoltage and overvoltage are calculated by solving Equation 13 and Equation 14. V(OVR) = R3 × VINOVP (R1 + R2 + R3) (13) V(UVLOR) = R2 + R3 × VINUVLO (R1 + R2 + R3) (14) For minimizing the input current drawn from the power supply, TI recommends to use higher values of resistance for R1, R2 and R3. However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, I(R 123) must be chosen to be 20 times greater than the leakage current of UVLO and OV pins. From the device electrical specifications, V (OVR) = 1.24 V and V (UVLOR) = 1.24 V. From the design requirements, VINOVP is 36 V and VIN UVLO is 6.5 V. To solve the equation, first choose the value of R 1 = 470 k Ω and use Equation 13 to solve for (R2 + R3) = 108.3 kΩ. Use Equation 14 and value of (R2 + R3) to solve for R3 = 19.6 kΩ and finally R2 = 88.7 kΩ. Choose the closest standard 1 % resistor values: R 1 = 470 kΩ, R2 = 88.7 kΩ, and R3 = 19.6 kΩ. www.ti.com TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS1200-Q1

8.2.3 Application Curves

Figure 8-2. Start-Up Profile of Bootstrap Voltage with INP = GND and CBST = 470 nF Figure 8-3. Start-Up Profile of Bootstrap Voltage with INP = HIGH and CBST = 470 nF Figure 8-4. Turn-ON Response of TPS12000-Q1 for INP -> LOW to HIGH and CBST = 470 nF Figure 8-5. Turn-OFF Response of TPS12000-Q1 for INP -> HIGH to LOW and CBST = 470 nF PU/PD Figure 8-6. Overcurrent Response of TPS12000-Q1 for a Load Step from 40 A to 55 A with 50-A Shortcircuit Protection Setting and tsc = 1 ms PU/PD Figure 8-7. Auto-Retry Response of TPS12000-Q1 for an Overcurrent Fault TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 www.ti.com ADVANCE INFORMATION

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Figure 8-8. Latch-Off Response of TPS12000-Q1 for an Overcurrent Fault PU/PD Figure 8-9. Output Short-Circuit Response of TPS12000-Q1 Device with 50-A Shortcircuit Protection Setting and TMR = OPEN Figure 8-10. Overvoltage Cutoff Response of TPS12000-Q1 at 36-V Level

8.3 Power Supply Recommendations

When the external MOSFETs turn-OFF during the conditions such as INP1 control, overcurrent protection causing an interruption of the current flow, the input parasitic line inductance generates a positive voltage spike on the input and output parasitic inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) depends on the value of inductance in series to the input or output of the device. These transients can exceed the Section 5.1 of the device if steps are not taken to address the issue. Typical methods for addressing transients include:

Use of a TVS diode and input capacitor filter combination across input to and GND to absorb the energy and dampen the positive transients.
Use of a diode or a TVS diode across the output and GND to absorb negative spikes. The TPS12000-Q1 gets powered from the VS pin. Voltage at this pin must be maintained above V(VS_PORR) level to ensure proper operation. If the input power supply source is noisy with transients, then TI recommends to place a RVS – CVS filter between the input supply line and VS pin to filter out the supply noise. TI recommends RVS value around 100 Ω. In case where large di/dt is involved, the system and layout parasitic inductances can generate large differential signal voltages between CS+ and CS– pins. This action can trigger false short-circuit protection and nuisance trips in the system. To overcome such scenario, TI suggests to add placeholder for RC filter components across sense resistor (R SNS) and tweak the values during test in the real system. The RC filter components must www.ti.com TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPS1200-Q1

not be used in current sense designs by MOSFET VDS sensing to avoid impact on the short-circuit protection response. The following figure shows the circuit implementation with optional protection components. GND PU TPS1200-Q1 CBST CS+ CS- BSTSRC VOUTVBATT PD VS RVS CVS Parasitic inductance Parasitic inductance D1 D2 Figure 8-11. Circuit Implementation With Optional Protection Components For TPS12000-Q1

8.4 Layout

8.4.1 Layout Guidelines

Place the sense resistor (RSNS) close to the TPS12000-Q1 and then connect RSNS using the Kelvin techniques. Refer to Choosing the Right Sense Resistor Layout for more information on the Kelvin techniques. For VDS based Current Sensing, follow the same kevlin techniques across the MOSFET.
Choose a 0.1 µF or higher value ceramic decoupling capacitor between VS terminal and GND for all the applications. Consider adding RC network at the supply pin (VS) of the controller to improve decoupling against the power line disturbances.
Make the high-current path from the board input to the load, and the return path, parallel and close to each other to minimize loop inductance.
Place the external MOSFETs close to the controller GATE drive pins (PU/PD) such that the GATE of the MOSFETs are close to the controller GATE drive pins and forms a shorter GATE loop. Consider adding a place holder for a resistor in series with the Gate of each external MOSFET to damp high frequency oscillations if need arises.
Place a TVS diode at the input to clamp the voltage transients during hot-plug and fast turn-off events.
Place the external boot-strap capacitor close to BST and SRC pins to form very short loop.
Connect the ground connections for the various components around the TPS12000-Q1 directly to each other, and to the TPS12000-Q1 GND, and then connected to the system ground at one point. Do not connect the various component grounds to each other through the high current ground line. TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 www.ti.com ADVANCE INFORMATION

Product Folder Links: TPS1200-Q1

8.4.2 Layout Example

FLT_GD CS_SEL SCP_TEST ISCP GND TMR VS NC D S S S G RVS CTMR RSCP CIN RG1 CVS BST VIN SRC / VOUT GND PGND TPS1200-Q1 PGND Schottky Diode * Top Layer Inner Layer GND plane Inner Layer PGND plane Via to GND plane Via to PGND plane * Optional Inner Layer GND plane Inner Layer PGND plane CBST R2R3 R1 Figure 8-12. Typical PCB Layout Example for TPS12000-Q1 With VDS based Current Sensing www.ti.com TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPS1200-Q1

9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES December 2023 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 www.ti.com ADVANCE INFORMATION

Product Folder Links: TPS1200-Q1

11.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant www.ti.com TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPS1200-Q1

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PTPS12000QDGXRQ1 VSSOP DGX 19 5000 853.0 449.0 35.0 TPS1200-Q1 SLUSEZ3 – DECEMBER 2023 www.ti.com ADVANCE INFORMATION

Product Folder Links: TPS1200-Q1

www.ti.com 10-Jan-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTPS12000QDGXRQ1 ACTIVE VSSOP DGX 19 5000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com PACKAGE OUTLINE C 18X 0.5 2X 4.5 20X 0.275 0.165 5.1

4.7 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -15 ) 4X (7 -15 )

1.1 MAX

B 3.1 2.9 A 5.2 5.0 NOTE 3 0.7 0.4 (0.15) TYP VSSOP - 1.1 mm max heightDGX0019A SMALL OUTLINE PACKAGE 4226944/A 07/2021 10 11

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. No JEDEC registration as of July 2021. 5. Features may differ or may not be present. SEATING PLANE PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

20X (1.45) 20X (0.3) 18X (0.5) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGX0019A SMALL OUTLINE PACKAGE 4226944/A 07/2021 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. LAND PATTERN EXAMPLE SCALE: 16X SYMM SYMM 10 11 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (18X 0.5) 20X (1.45) 20X (0.3) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGX0019A SMALL OUTLINE PACKAGE 4226944/A 07/2021 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 16X SYMM SYMM 10 11

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