Amplifier

PTPA3138D2PWPR

Texas Instruments

10-W, 3.5-V to 14.4-V, Inductor Less, Analog Input, Stereo, Class-D Audio Amplifier with Ultra Low EMI

Manufacturer: Texas Instruments

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ADVANCE□INFORMATION Audio Source And Control RIGHT LEFT TPA3138D2 PLIMIT MOD_SEL SD/FAULT Power Limit Modulation Schemes/UV Level Select PVCC/AVCC Power Supply 3.5V t 14.4V FB FB GAIN_SEL 20dB/26dB GAIN Select PBTL DETECT Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPA3138D2 SLOS993 –MARCH 2018 TPA3138D210-W,3.5-Vto14.4-V,InductorLess,AnalogInput,Stereo,Class-DAudio AmplifierwithUltraLowEMI

1 Features

1• Reduced Solution Size and Cost: – Inductor-Less operation: Low-cost ferrite beads substitute inductors – EN55013 and EN55022 EMC compliant when no inductors are used – No external heatsink required: PCB plane can be used as heatsink

Longer Battery Life for Portable Systems: – Low idle-current mode – >90% Class-D Efficiency
Audio Performance: – 2 × 10 W/ch into 6-Ω,1% THD+N, 12-V supply – THD+N : 0.07% @ 1W, 1kHz input, 6-Ω
Voltage Range: 3.5-V to 14.4-V in Low idle current mode
Flexible Audio Solution: – Single-Ended or Differential Analog Inputs – Selectable Gain: 20dB and 26dB – Pop and Click-Free Startup
Integrated self-protection: – Pin-to-pin, Pin-to-Ground, and Pin-to-Power short circuit protection – Power short circuit protection – Power Limiter and DC Speaker Protection
Pin-to-Pin compatible with TPA3110D2, TPA3110LD2, TPA3136D2 and TPA3136AD2

2 Applications

Televisions
Bluetooth and Wireless Speakers
Consumer Audio Equipment

3 Description

The TPA3138D2 is 10-W, up-to-90% efficient, stereo Class-D audio amplifier. It can drive stereo speaker with as low as 4-Ω. Advanced EMI Suppression with Spread Spectrum Control enables the use of inexpensive ferrite bead filters while meeting EMC requirements for system cost reduction. The TPA3138D2 is fully protected against shorts and overload; It also includes a power limiter and DC detection circuit for speaker protection. The short- circuit and thermal protections include an auto- recovery feature. Customers can leverage every TPA3138D2 feature in existing designs as it is fully pin-to-pin compatible to TI's TPA3110D2, TPA3110LD2,TPA3136D2 and TPA3136AD2. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPA3138D2 HTSSOP (28) 9.70 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic

12.4 Receiving Notification of Documentation Updates 28

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES March 2018 V 0.7 Initial release.

ADVANCE□INFORMATION 1NC 28 PVCCL 2SD/FAULT 27 PVCCL 3LINP 26 BSPL 4LINN 25 OUTPL 5GAIN_SEL 24 GND 6MODE_SEL 23 OUTNL 7AVCC 22 BSNL 8GND 21 BSNR 9GVDD 20 OUTNR 10PLIMIT 19 GND 11RINN 18 OUTPR 12RINP 17 BSPR 13NC 16 PVCCR 14AGND 15 PVCCR Not to scale Thermal Pad TPA3138D2 www.ti.com SLOS993 –MARCH 2018 Product Folder Links: TPA3138D2 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) I = Input, O = Output, IO = Input and Output, P = Power

5 Pin Configuration and Functions

(Top View) Pin Functions PIN I/O/P(1) DESCRIPTION NAME NO. NC 1 – No Connect Pin. Can be shorted to PVCC or shorted to GND or left open. SD/FAULT 2 IO TTL logic levels with compliance to AVCC. Shutdown logic input for audio amp (LOW , outputs Hi-Z; HIGH , outputs enabled). General fault reporting including Over-Temp, Over-Current, DC Detect. SD/FAULT= High, normal operation, SD/FAULT= Low, fault condition Device will auto-recovery once the OT/OC/DC Fault has been removed. LINP 3 I Positive audio input for left channel. Biased at 2.5 V. Connect to GND for PBTL mode. LINN 4 I Negative audio input for left channel. Biased at 2.5 V. Connect to GND for PBTL mode. GAIN_SEL 5 I Gain select least significant bit. TTL logic levels with compliance to AVDD. Low=20dB Gain, High=26dB Gain, Floating=26dB Gain. MODE_SEL 6 I Mode select least significant bit. TTL logic levels with compliance to AVDD. Low=BD Mode/UV Threshold=7.5V, High=Low Idle Current Mode/UV Threshold=3.4V, Floating=Low Idle Current Mode/UV threshold=3.4V AVCC 7 P Analog supply. GND 8 – Analog signal ground. GVDD 9 O FET gate drive supply. Nominal voltage is 5 V. PLIMIT 10 I Power Limiter Control pin RINN 11 I Negative audio input for right channel. Biased at 2.5 V. RINP 12 I Positive audio input for right channel. Biased at 2.5 V. NC 13 – No Connect Pin. Can be shorted to PVCC or shorted to GND or left open.

ADVANCE□INFORMATION TPA3138D2 SLOS993 –MARCH 2018 www.ti.com Product Folder Links: TPA3138D2 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Pin Functions (continued) PIN I/O/P(1) DESCRIPTION NAME NO. AGND 14 – Analog signal ground. Connect to the thermal pad. PVCCR 15, 16 P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connected internally. BSPR 17 I Bootstrap I/O for right channel, positive high-side FET. OUTPR 18 O Class-D H-bridge positive output for right channel. GND 19 – Power ground for the H-bridges. OUTNR 20 O Class-D H-bridge negative output for right channel. BSNR 21 I Bootstrap I/O for right channel, negative high-side FET. BSNL 22 I Bootstrap I/O for left channel, negative high-side FET. OUTNL 23 O Class-D H-bridge negative output for left channel. GND 24 – Power ground for the H-bridges. OUTPL 25 O Class-D H-bridge positive output for left channel. BSPL 26 I Bootstrap I/O for left channel, positive high-side FET. PVCCL 27, 28 P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connected internally. Thermal Pad – Connect to GND for best thermal and electrical performance

ADVANCE□INFORMATION TPA3138D2 www.ti.com SLOS993 –MARCH 2018 Product Folder Links: TPA3138D2 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100 kΩ resister in series with the pins. (3) The TPA3138D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage AVCC to GND, PVCC to GND –0.3 20 V GVDD to GND V GND to GND -0.3 0.3 V Input current To any pin except supply pins 10 mA Voltage SD/FAULT to GND(2) –0.3 AVCC + 0.3 V

10 V/ms

Voltage RINN, RINP, LINN, LINP –0.3 5.5 V Minimum load resistance, RL BTL, (10V<PVCC<14.4V) 4.8 Ω BTL, (3.5V<PVCC<10 V) 3.2 PBTL, (10V<PVCC<14.4V) 2.4 PBTL, (3.5V<PVCC<10 V) 1.6 Continuous total power dissipation See the Thermal Information Table Operating free-air temperature range, TA (3) –10 85 °C Operating Juncation Temperature range –25 150 °C Storage temperature range, Tstg –40 125 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 V Charged device model (CDM), per JEDEC specification JESD22-C101 (2) ±250

ADVANCE□INFORMATION TPA3138D2 SLOS993 –MARCH 2018 www.ti.com Product Folder Links: TPA3138D2 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Set GAIN_SEL and MODE_SEL to low level, make sure pull down resistor<10kΩ (2) The TPA3138D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VCC Supply voltage PVCC, AVCC 3.5 14.4 V VIH High-level input voltage SD/FAULT, GAIN_SEL, MODE_SEL 2 AVCC V VIL Low-level input voltage SD/FAULT(4.7kΩ<Pull up resistor<500kΩ), GAIN_SEL, MODE_SEL(1) 0.8 V VOL Low-level output voltage SD/FAULT, RPULL-UP=100 k, PVCC=14.4 V 0.8 V IIH High-level input current SD/FAULT, GAIN_SEL, MODE_SEL, VI = 2 V, AVCC = 12 V 50 µA IIL Low-level input current SD/FAULT, GAIN_SEL, MODE_SEL, VI = 0.8 V, AVCC = 12 V 5 µA TA Operating free-air temperature(2) –10 85 °C TJ Operating junction temperature(2) -10 150 °C (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1) TPA3138D2 UNITPWP (HTSSOP)

28 PINS

RθJA Junction-to-ambient thermal resistance 30.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 33.5 °C/W RθJB Junction-to-board thermal resistance 17.5 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 7.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W

6.5 Electrical Characteristics

TA = 25°C, AVCC = PVCC = 12 V, RL = 6 Ω (unless otherwise noted). Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS | VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 26 dB 1.5 15 mV ICC Quiescent supply current SD/FAULT = 2 V, no load, 10 µF + 680 nF Output Filter, 1SPW Mode, PVCC=12V 15.5 20 mA ICC Quiescent supply current SD/FAULT = 2 V, no load, 10 µF + 680 nF Output Filter, BD Mode, PVCC=12V SD/FAULT = 2 V, no load, 10 µF + 680 nF Output Filter, BD Mode, PVCC=12V 32 40 mA ICC(SD) Quiescent supply current in shutdown mode SD/FAULT = 0.8 V, no load 40 60 µA rDS(on) Drain-source on-state resistance IO = 500 mA, TJ = 25°C Excluding Metal and Bond Wire Resistance High Side 180 mΩLow side 180 G Gain GAIN_SEL=0.8V GAIN_SEL=0.8V 19 20 21 dB G Gain GAIN_SEL=3.5V 25 26 27 dB ton Turn-on time SD/FAULT = 2 V 50 ms tOFF Turn-off time SD/FAULT = 0.8 V 2.5 µs GVDD Gate drive supply IGVDD = 2 mA 4.8 5 5.2 V tDCDET DC detect time VRINP = 2.6 V and VRINN = 2.4 V, or VRINP = 2.4 V and VRINN = 2.6 V 800 ms

ADVANCE□INFORMATION TPA3138D2 www.ti.com SLOS993 –MARCH 2018 Product Folder Links: TPA3138D2 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) TA = 25°C, AVCC = PVCC = 12 V, RL = 6 Ω (unless otherwise noted). Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC CHARACTERISTICS PSRR Power supply ripple rejection 200-mVPP ripple at 1 kHz, Gain = 26 dB, Inputs ac-coupled to GND –65 dB PO Continuous output power THD+N = 1%, f = 1 kHz, PVCC = 12 V, RL = 6 Ω 10 W PO Continuous output power THD+N = 10%, f = 1 kHz, PVCC = 12 V, RL = 6 Ω 12.4 W PO Continuous output power THD+N = 1%, f = 1 kHz, PVCC = 12 V, RL = 8 Ω 8 W PO Continuous output power THD+N = 10%, f = 1 kHz, PVCC = 12 V, RL = 8 Ω 9.9 W PO Continuous output power, PBTL (mono) THD+N = 10%, f = 1 kHz, PVCC = 12 V, RL = 4 Ω 15 W IO Maximum output current f = 1 kHz, RL=3 Ω 3.5 A THD+N Total harmonic distortion + noise f = 1 kHz, PO = 5 W (half-power) 0.06% Vn Output integrated noise

20 Hz to 22 kHz, A-weighted filter, Gain = 26 dB

91 100 µV –81 dBV

20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB

74 80 µV -82.6 dBV Crosstalk VO = 1 Vrms, Gain = 26 dB, f = 1 kHz –75 dB SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 26 dB, A-weighted 102 dB OTE Thermal trip point 150 °C Thermal hysteresis 15 °C

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT fOSC, SS Oscillator frequency, Spread Spectrum ON 255 315 355 kHz

6.7 Typical Characteristics

were made with AES17 filter using the TPA3138D2 EVM, which is available at ti.com. Figure 1. Total Harmonic Distortion vs Frequency (BTL) Figure 2. Total Harmonic Distortion vs Frequency (BTL) Figure 3. Total Harmonic Distortion + Noise vs Output Figure 4. Total Harmonic Distortion + Noise vs Output Figure 5. Output Power vs Supply Voltage (BTL), Figure 6. Output Power vs Supply Voltage (BTL),

2 Channel Output Power - W

were made with AES17 filter using the TPA3138D2 EVM, which is available at ti.com. Figure 7. Gain/Phase vs Frequency (BTL) Figure 8. Efficiency vs Output Power (BTL) Figure 9. Efficiency vs Output Power (BTL) Figure 10. Crosstalk vs Frequency (BTL) Figure 11. Total Harmonic Distortion + Noise vs Frequency Figure 12. Total Harmonic Distortion + Noise vs Output

were made with AES17 filter using the TPA3138D2 EVM, which is available at ti.com. Figure 13. Output Power vs Supply Voltage (PBTL) Figure 14. Efficiency vs Output Power (PBTL)

7 Parameter Measurement Information

All parameters are measured according to the conditions described in the Specifications section. reduce the out of band noise remaining on the amplifier outputs.

8 Detailed Description

8.1 Overview

To facilitate system design, the TPA3138D2 must only a single power supply between 3.5 V and 14.4 V for operation. An internal voltage regulator provides suitable voltage levels for the gate driver, digital, and low- voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, as in the high-side gate drive, is accommodated by built-in bootstrap circuitry with integrated boot strap diodes requiring only an external capacitor for each half-bridge. The audio signal path, including the gate drive and output stage, is designed as identical, independent full- bridges. All decoupling capacitors should be placed as close to their associated pins as possible. In general, the physical loop with the power supply pins, decoupling capacitors and GND return path to the device pins must be kept as short as possible and with as little area as possible to minimize induction (see reference board documentation for additional information). For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BSXX) to the power-stage output pin (OUTXX). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range of 315 kHz, use ceramic capacitors with at least 220-nF capacitance, size 0603 or 0805, for the bootstrap supply. These capacitors ensure sufficient energy storage, even during clipped low frequency audio signals, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of its ON cycle. Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. For optimal electrical performance, EMI compliance, and system reliability, each PVCC pin should be decoupled with ceramic capacitors that are placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the reference design. For additional information on recommended power supply and required components, see the application diagrams in this data sheet. The PVCC power supply should have low output impedance and low noise. The power-supply ramp and SD/FAULT release sequence is not critical for device reliability as facilitated by the internal power-on-reset circuit, but it is recommended to release SD/FAULT after the power supply is settled for minimum turn on audible artifacts.

ADVANCE□INFORMATION PWM Logic Gate Drive Gate Drive PVCC PVCC GVDD PVCC PVCC BSPL GND OUTPL OUTNL GND GVDD BSNL PWM Logic Gate Drive Gate Drive PVCC PVCC GVDD PVCC PVCC BSNR GND OUTNR OUTPR GND GVDD BSPR LINN LINP RINP RINN UVLO/OVLO SC Detect DC Detect Thermal Detect Startup Protection Logic Biases and References SD/FAULT SD GAIN_SEL MOD_SEL AVCC TTL Buffer Ramp Generator AVDD GVDD GVDD LDO Regulator Gain Control PLIMIT Spread Spectrum Control Gain Control Modulation Scheme and PBTL Select Modulation Scheme and PBTL Select OUTNL FB OUTPL FB OUTPR FB OUTNR FB OUTPR FB OUTNR FB OUTNL FB OUTPL FB PLIMIT PLIMIT LIMITER Reference UVLO Select FAULT Gain Control Modulation scheme /UVLO Select Input Sense PBTL Select GND TPA3138D2 SLOS993 –MARCH 2018 www.ti.com Product Folder Links: TPA3138D2 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Analog Gain

8.3.2 SD/FAULT Operation

unconnected, because amplifier operation would be unpredictable.

8.3.3 PLIMIT

by voltage clipping. PLIMIT threshold is set by the PLIMIT pin voltage. Figure 15. PLIMIT Circuit Operation a given maximum input voltage and speaker impedance.

ADVANCE□INFORMATION L P L S OUT L R VR + 2 R P = for unclipped power2 R /c230 /c246/c230 /c246 /c180/c231 /c247/c231 /c247/c231 /c247 /c180/c232 /c248/c232 /c248 /c180 TPA3138D2 SLOS993 –MARCH 2018 www.ti.com Product Folder Links: TPA3138D2 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Feature Description (continued) where

POUT (10%THD) = 1.25 × POUT (unclipped)
RL is the load resistance.
RS is the total series resistance including RDS(on), and output filter resistance.
VP is the peak amplitude, which is limited by "virtual" voltage rail. (1)

8.3.4 Spread Spectrum and De-Phase Control

The TPA3138D2 device has built-in spread spectrum control of the oscillator frequency and de-phase of the PWM outputs to improve EMI performance. The spread spectrum schemes is internally fixed is always turned on. De-phase inverts the phase of the output PWM such that the idle output PWM waveforms of the two audio channels are inverted. De-phase does not affect the audio signal, or its polarity. De-phase only works with BD mode, it is auto-disabled in 1SPW mode

8.3.5 GVDD Supply

The GVDD Supply is used to power the gates of the output full bridge transistors. Add a 1-μF capacitor to ground at this pin.

8.3.6 DC Detect

The TPA3138D2 device has circuitry which will protect the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on the SD/FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi-Z. A DC Detect Fault is issued when the output DC voltage sustain for more than 800 msec at the same polarity. This feature protects the speaker from large DC currents or AC currents less than 1 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD/FAULT pin low at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults.

8.3.7 PBTL Select

The TPA3138D2 device offers the feature of parallel BTL operation with two outputs of each channel connected directly. Connect INPL and INNL directly to Ground (Without Capacitors), this sets the device in Mono Mode during power up. Connect the OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL together for the negative pin. Analog input signal is applied to INPR and INNR. For an example of the PBTL connection, see the schematic in the Typical Applications section.

8.3.8 Short-Circuit Protection and Automatic Recovery Feature

The TPA3138D2 device has protection from over current conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the SD/FAULT pin as a low state. The amplifier outputs are switched to a Hi-Z state when the short circuit protection latch is engaged . Device will recover automatically once the over current condition has been removed.

8.3.9 Thermal Protection

Thermal protection on the TPA3138D2 device prevents damage to the device when the internal die temperature exceeds 150°C. This trip point has a ±15°C tolerance from device to device. Once the die temperature exceeds the thermal trip point, the device enters into the shutdown state and the outputs are disabled. This is a latched fault. Thermal protection faults are reported on the SD/FAULT pin.

8.4 Device Functional Modes

8.4.1 MODE_SEL = LOW: BD-modulation

driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage. speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages. reduces any I2R losses in the load. Figure 16. BD Mode Modulation

8.4.2 MODE_SEL = HIGH: Low Idle Current-modulation

majority of the audio cycle. Efficiency is improved in this mode due to the reduction of switching losses. Figure 17. Low Idle Current Modulation

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

system power, see functional description of these features.

9.2 Typical Applications

Figure 18. Stereo Class-D Amplifier with BTL Output and Single-Ended Inputs with Spread Spectrum

Figure 19. Stereo Class-D Amplifier with PBTL Output and Single-Ended Input with Spread Spectrum

9.2.1 Design Requirements

9.2.1.1 PCB Material Recommendation

for thermal coupling to a bottom side copper GND plane for best thermal performance.

9.2.1.2 PVCC Capacitor Recommendation

9.2.1.3 Decoupling Capacitor Recommendations

In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this application. The voltage of the decoupling capacitors should be selected in accordance with good design practices. Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the selection of the ceramic capacitors that are placed on the power supply to each full-bridge. They must withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple current created by high power output. A minimum voltage rating of 16 V is required for use with a 12-V power supply.

9.2.2 Detailed Design Procedure

A rising-edge transition on SD/FAULT input allows the device to start switching. It is recommended to ramp the PVCC voltage to its desired value before releasing SD/FAULT for minimum audible artifacts. The device is non-inverting the audio signal from input to output. The GVDD pin is not recommended to be used as a voltage source for external circuitry.

9.2.2.1 Ferrite Bead Filter Considerations

Using the Advanced Emissions Suppression Technology in the TPA3138D2 amplifier it is possible to design a high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite bead used in the filter. One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to the operation of the Class-D amplifier. Many of the specifications regulating consumer electronics have emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30-MHz and above range from appearing on the speaker wires and the power supply lines which are good antennas for these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance, the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz. Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead's current handling capability by measuring the resonant frequency of the filter output at low power and at maximum power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of ferrite beads which have been tested and work well with the TPA3138D2 device include NFZ2MSM series from Murata. A high quality ceramic capacitor is also required for the ferrite bead filter. A low ESR capacitor with good temperature and voltage characteristics will work best. Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to ground. Suggested values for a simple RC series snubber network would be 68 Ω in series with a 100-pF capacitor although design of the snubber network is specific to every application and must be designed taking into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make sure the layout of the snubber network is tight and returns directly to the GND or the thermal pad beneath the chip.

33 H/c109

9.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme

resistive and reactive, whereas an LC filter is almost purely reactive. applications the filter is not required. frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.

9.2.2.3 When to Use an Output Filter for EMI Suppression

application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency. second order Butterworth filter similar to those shown in the figures below can be used. low frequency ferrite material can also be effective at preventing line conducted interference. Figure 20. Typical Ferrite Chip Bead Filter (Chip Bead Example: NFZ2MSM series from Murata) Figure 21. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω

2 Z f/c112 i c

2 Z C/c112 i i

15 H/c109

Figure 22. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 6 Ω

9.2.2.4 Input Resistance

9.2.2.5 Input Capacitor, Ci

pass filter with the corner frequency determined in Equation 2. the example where Zi is 20 kΩ (26dB Gain) and the specification calls for a flat bass response down to 20 Hz. Equation 2 is reconfigured as Equation 3. voltages and it is important to ensure that boards are cleaned properly.

9.2.2.6 BSN and BSP Capacitors

The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 0.22-μF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 0.22-μF capacitor must be connected from OUTPx to BSPx, and one 0.22-μF capacitor must be connected from OUTNx to BSNx. (See the application circuit diagram in Figure 18.) The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.

9.2.2.7 Differential Inputs

The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3138D2 device with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3138D2 with a single-ended source, ac ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance. For good transient performance, the impedance seen at each of the two differential inputs should be the same. The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to allow the input dc blocking capacitors to become completely charged during the 50-ms power-up time. If the input capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching which can result in pop if the input components are not well matched.

9.2.2.8 Using Low-ESR Capacitors

Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor.

9.2.3 Application Performance Curves

9.2.3.1 EN55013 Radiated Emissions Results

Figure 23. Radiated Emission - Horizontal Figure 24. Radiated Emission - Vertical

9.2.3.2 EN55022 Conducted Emissions Results

Figure 25. Conducted Emission - Line Figure 26. Conducted Emission - Neutral

10 Power Supply Recommendations

10.1 Power Supply Decoupling, CS

The TPA3138D2 device is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and copper trace inductances as well as lead frame capacitance, a good quality low equivalent-series-resistance (ESR) ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be placed as close to the device PVCC pins and system ground (either GND pins or thermal pad) as possible. For mid- frequency noise due to filter resonances or PWM switching transients as well as digital hash on the line, another good quality capacitor typically 0.1 μF to 1 µF placed as close as possible to the device PVCC leads works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 100 μF or greater placed near the audio power amplifier is recommended. The 100-μF capacitor also serves as a local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC pins provide the power to the output transistors, so a 100-µF or larger capacitor should be placed on each PVCC pin. A 1-µF capacitor on the AVCC pin is adequate. Also, a small decoupling resistor between AVCC and PVCC can be used to keep high frequency class-D noise from entering the linear input amplifiers.

11 Layout

11.1 Layout Guidelines

The TPA3138D2 device can be used with a small, inexpensive ferrite bead output filter for most applications. However, since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the printed circuit board. The following suggestions will help to meet EMC requirements.

Decoupling capacitors— The high-frequency decoupling capacitors should be placed as close to the PVCC and AVCC pins as possible. Large (100-µF or greater) bulk power supply decoupling capacitors should be placed near the TPA3138D2 device on the PVCC supplies. Local, high-frequency bypass capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1 μF and 1 μF also of good quality to the PVCC connections at each end of the chip.
Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.
Grounding— The AVCC (pin 7) decoupling capacitor should be connected to ground (GND). The PVCC decoupling capacitors should connect to GND. Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the TPA3138D2.
Output filter— The ferrite EMI filter (Figure 20) should be placed as close to the output pins as possible for the best EMI performance. The capacitors used in the ferrite should be grounded to power ground.
Thermal Pad— The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be 3.04 mm × 2.34 mm. Seven rows of solid vias (three vias per row, 0.3302 mm or 13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application Report SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB footprints, see figures at the end of this data sheet. For an example layout, see the TPA3138D2 Evaluation Module (TPA3138D2EVM) User Manual. Both the EVM user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com.

11.2 Layout Example

Figure 27. BTL Layout Example

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

PowerPAD™ Thermally Enhanced Package Application Report (SLMA002)

12.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now.

12.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.5 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.6 Trademarks

E2E is a trademark of Texas Instruments.

12.7 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.8 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 13-Mar-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTPA3138D2PWP PREVIEW HTSSOP PWP 28 50 TBD Call TI Call TI -40 to 85 PTPA3138D2PWPR ACTIVE HTSSOP PWP 28 2000 TBD Call TI Call TI -40 to 85 TPA3138D2PWPR PREVIEW HTSSOP PWP 28 2000 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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Product Information

PTPA3138D2PWPR specifications and overview.

Summary

10-W, 3.5-V to 14.4-V, Inductor Less, Analog Input, Stereo, Class-D Audio Amplifier with Ultra Low EMI

Description

10-W, 3.5-V to 14.4-V, Inductor Less, Analog Input, Stereo, Class-D Audio Amplifier with Ultra Low EMI

Source title PTPA3138D2PWPR Datasheet(PDF) - Texas Instruments

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