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Technical content
- General description PTN5150A is a small thin low power CC Logic chip supporting the USB Type-C connector application with Configuration Channel (CC) control logic detection and indication functions. The features of PTN5150A enable USB Type-C connector to be used in both host and device ends of the Type-C cable. It can support Type-C to USB legacy cables and adapters defined in USB Type-C Spec. PTN5150A can work autonomously, or can connect to a controller through I2C-bus interface. PTN5150A can be configured to dual role, host, or device mode through external configuration pin or through I2C interface. The CC control logic detection and indication block supports 3 current modes (default current 500 mA/900 mA, medium current 1.5 A and high current 3.0 A) in DFP advertisement's perspective. When in UFP advertisement's perspective, the control logic will detect if a DFP with different pull-up Rp current source is connected. In addition, it will detect if Ra is present on CC1/CC2 pins. Upon detection of plug orientation, pin ID will indicate if PTN5150A is working under either host role or device role, and other status will also be reflected in I2C registers. 2. Features and benefits Support type C connector with existing chipsets USB Type-C Rev 1.1 compliance Compatible with legacy OTG hardware and software Support plug, orientation, role and charging current detection. USB-ID pin for OTG application I2C-bus interface support for fast mode EXT_SEL to control USB data switch CC control logic detection and indication PORT input pin to configure in DRP (Hi-Z), UFP (low) or DFP (high) Current mode detection when PTN5150A is operating under UFP (device) role: default current mode (<0.5 A/0.9 A); medium current mode (<1.5 A); high current mode (<3.0 A) Integrated accurate Rp current sources to support default mode and high current mode under host mode: default current mode at 80 A; medium current mode at 180 A; high current mode at 330 A Integrate Rd resistor in UFP device mode Report detail port states and accessory modes in I2C registers Support VCONN1/2 power detected status through VCONN Status I2C register 0AH Current consumption: Standby in DRP mode: 15 A PTN5150A CC logic for USB Type-C applications Rev. 1 — 9 December 2016 Product data sheet
4.1 Ordering options
Table 1. Ordering information Table 2. Ordering options
10000 T amb = 40 C to +85 C
Product data sheet Rev. 1 — 9 December 2016 3 of 27 NXP Semiconductors PTN5150A CC logic for USB Type-C applications 5. Functional diagram 6. Pinning information
6.1 Pinning
Fig 1. Functional diagram aaa-019980 DEVICE CONTROL AND MANAGEMENT VBUS_DET ID ADR/CON_DET EXT_SEL ROLE (UFP/DFP/DRP) CONTROL CC LEVEL DETECTION AND INDICATION SDA/OUT1 SCL/OUT2 INTB/OUT3 PORT CC1 CC2 VDD VDD PTN5150A Rp Rp Rd Rd Fig 2. Pin configuration aaa-019981 PTN5150A Transparent top view VDD EXT_SEL GND ID PORT VBUS_DET ADR/CON_DET INTB/OUT3 SCL/OUT2 SDA/OUT1 CC1 CC2 terminal 1 index area
6.2 Pin description
Table 3. Pin description
1 CC1 I/O Configure Channels as defined in USB Type-C specification
2 CC2
3 PORT Input Trinary GPIO Input selection run from VDD
PORT= VDD: DFP mode (Rp = 80uA power default for non-I2C mode). If ADR = Mid (no- I2C mode). PORT input can be dynamically change.
5 ADR/CON_DET I/O Trinary GPIO Input ADR pin run from VDD
- ADR pull up to VDD with 10 k resistor (I2C Enabled with ADDR bit 6 equal to 1, I2C Address 0x7A)
- ADR pull down to GND with 10 k resistor. (I2C Enabled with ADDR bit 6 equal to 0, I2C Address 0x3A)
- ADR = Mid or floating (Pin 6/7/8) configured as OUT1/2/3 in non-I2C mode Output. This pin will automatically switch from input to CON_DET output in "non-I2C mode or set 09H bit[0] to 0" after TINPUTLATCH
- CON_DET = High (Connection Detected)
- CON_DET = Low (No Connection)
6 INTB/OUT3 O/D
- Low = Interrupt asserted
- Hi-Z = Interrupt de-asserted OUT3: (only valid in non- I2C mode)
- Low = Analog Audio Detected
- Hi-Z = No Detection
7 SDA/OUT1 O/D
8 SCL/OUT2 O/D
9 ID O/D
enable OTG mode, requires external pull up resistor.
7.1 CC detection and indication block
and manage the DFP/UFP connection between a host port and a device port. trinary input pins should be powered by VDD.
- When PTN5150A is operating under host role, different current modes (high/medium/default) can be configured through I2C register. During initial power up, default current mode is being selected. In order to indicate different current modes, three Rp current sources are being implemented. Internal comparators are constantly monitoring the voltage levels of CC1 and CC2 pins. PTN5150A reports if an UFP (device) or powered cable is connected externally on the CC pins. When no external connection is detected, cable connected bit in the I2C register will be cleared. Any changes in the attach/detach events or Rp current source changes will trigger INTB pin to go LOW.
10 GND Power Ground
11 EXT_SEL O/D
- Low = CC2 orientation
- High = CC1 orientation or no valid CC1/CC2 detection
12 VDD Power Power supply
Table 3. Pin description …continued Table 4. Current source implementation for each DFP advertisement
1.5 A at 5 V 180 A 8%
3.0 A at 5 V 330 A 8%
Table 5. RD implementation for each UFP advertisement Table 6. Voltage range detection for each DFP advertisement
Product data sheet Rev. 1 — 9 December 2016 6 of 27 NXP Semiconductors PTN5150A CC logic for USB Type-C applications
- When PTN5150A is operating under device role (UFP), it is able to detect different current modes indicated by external host's pull-up resistors. Internally there is a pull-down resistor (Rd) of 5.1 k on CC1 and CC2 pins. Status of current mode detected is reported in the I2C register. If pin 6/7/8 is configured as OUT1/2/3, OUT1/2 reports the detected Rp pull up current source value as well. The configuration channel (CC1 or CC2) is used to serve the following purposes in this block
- Detect connection of USB ports, e.g. a DFP (host) or a UFP (device), and establish host or device roles between two connected ports. When there is no power supplied to PTN5150A, device role (with internal pull-down resistor Rd active) will be the default configuration.
- Resolve cable orientation and twist connections to establish USB data bus routing.
- Discover optional accessory modes such as audio adapter accessory and debug accessory modes. Resistors (Ra, Rd, Rp, or Open) connected on CC1/CC2 will be reported in the I2C registers, and host controller can configure the external interface accordingly.
7.2 ADR/CON_DET output pin
Pin 5 is multiple purpose I/O pin. When device power up, pin 5 is input which latched the input voltage level to configure I2C address. The I2C register offset 09H has default value "1" to disable CON_DET output. After TINPUT_LATCH, pin 5 becomes CON_DET output. When USB Type-C cable attached or detached in either DFP or UFP mode, CON_DET will asserted a signal to notify the system the status. The same attached or detached status also stored in the I2C interrupt register. For ADR strapping resistor selection, 10 k pull up or pull down resistor is recommended.
7.3 VCONN1/VCONN2 pow er output control
When a USB Type-C system need to support VCONN power in DFP or UFP power accessories mode, the system need to know the orientation to provide VCONN power. PTN5150A provides two bits of VCONN status register 0AH and an interrupt signal to notify system whether VCONN power is detected on VCONN1 or VCONN2 and then turn on discrete PowerFET using via 2 x GPIO. Figure 3 shows the system level implementation of VCONN power with PTN5150A.
Product data sheet Rev. 1 — 9 December 2016 7 of 27 NXP Semiconductors PTN5150A CC logic for USB Type-C applications
7.4 Off state
When PTN5150A is not powered (i.e., VDD = 0 V), special steps should be done to prevent back-current issues on control pins such PORT or ADR pins when these pins' states are not low. These pins can be controlled through two different ways. 1. pull-up/pull-down resistors - make sure these pull-up resistors' VDD is the same power source as to power PTN5150A. When power to PTN5150A is off, power to these pull-up resistors will be off as well. 2. external processor's GPIO - if PTN5150A is turned off when the external processor's power stays on, processor should configure these GPIOs connected to these control pins as output low (< 0.4 V) or tri-state mode (configure GPIOs as input mode). This will make sure no current will be flowing into PTN5150A through these control pins.
7.5 I 2C-bus
PTN5150A can work with systems with or without I2C-bus. “I2C mode” is defined as ADR pin has external 10 k pull-up or pull-down resistor during power up, and “non-I2C mode” is defined as ADR pin is not connected to any external pull-up or pull-down resistor during power up. When operating in I2C mode, all features of PTN5150A can be configured and accessed through registers. OUT1, OUT2, OUT3 are not available in I2C mode. PORT input will be a one-time latched during power up. In non-I2C mode, a subset of features can be configured or accessed through these I/O pins:
- PORT input: In non I2C-bus mode, PORT input can be dynamically change.
- CON_DET output: attached/detached notification
- OUT1/OUT2 output: detected Rp current source value
- OUT3: Analog Audio Detect Fig 3. Schematic connections to turn on/off VCONN1/2 power aaa-019982 AP I2C
2.7 V to 5 V supply
7.6 I 2C-bus programmability
the settings by programming the internal registers through I2C. and reflects the status in the I2C status registers as default condition. Table 7. I2C registers and descriptions
11 Reserved
1: Mask Interrupts for register offset 03H bit[1:0].
VCONN detected status read out is always 00. 10H Reset register [7:1] 0000000 Reserved. 12H Reserved [7:0] 000000 Reserved.
7.7 I 2C-bus read and write operations
PTN5150A supports programming of the internal registers through the I2C-bus interface. defined in combination with ADR pin. Reading/writing the internal registers must be done according to the following protocol.
- Command phase
- Data phase The command phase is an I2C write to PTN5150A that contains a single data byte indicating the internal register address to read out. The data phase is an I2C read operation that contains one byte of data and STOP bit is asserted, starting from the least significant byte. 19H Read Only/Clear on Read Interrupt Register status [7] 0 Reserved [6] 0 Reserved [5] 0 Reserved [4] 0 Interrupt Status for Comparator Change 0: No interrupt 1: When attached as UFP, Change of Rp current advertisement detected. New advertisement is reflected on register offset 04H bit[6:5]. [3] 0 Interrupt status for role change 0: No interrupt 1: Role changed detected. New role is reflected on register offset 04H bit[4:2]. [2] 0 Interrupt status for orientation found 0: No interrupt 1: Orientation detected on attachment. New orientation is reflected on register offset 04H bit[1:0]. [1] 0 Interrupt status for debug accessories found 0: No interrupt 1: Debug Accessory attachment detected. Register offset 04H bit[4:2] should be updated to 3’b100. [0] 0 Interrupt status for audio accessories found 0: No interrupt 1: Audio Accessory attachment detected. Register offset 04H bit[4:2] should be updated to 3’b011.
Table 8. Read/write device slave address
Product data sheet Rev. 1 — 9 December 2016 12 of 27 NXP Semiconductors PTN5150A CC logic for USB Type-C applications The I2C write operation contains only the command phase, which contains 8-bit internal register address, followed by one byte of data to be written to the register, starting from the least significant byte. It is recommended to use single-byte write/read commands to PTN5150A. Incremental address read/write function is not supported. Figure 4 and Figure 5 illustrate the protocol used on the I2C-bus to write and read register inside the device. Fig 4. I 2C-bus write sequences 0 AS slave address START condition R/W acknowledge from slave aaa-019852 1/0 0 0 1/0 1/0 1/0 1/00 command byte A acknowledge from slave 12345678SCL 9 SDA DATA 0 A acknowledge from slave data to register 11110AD DR0 P STOP condition MSB LSB Fig 5. I 2C-bus read sequences 11110AD DR 0 AS0 START condition R/W acknowledge from slave aaa-019853 A acknowledge from slave SDA NA P no acknowledge from master data from register DATA (first byte) slave address STOP condition S (repeated) START condition (cont.) (cont.) 11110AD DR 1 A0 R/W acknowledge from slave slave address at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter MSB LSB 1/0 0 0 1/0 1/0 1/0 1/00 command byte
[1] All voltage values, except differential volt ages, are with respect to network ground terminal. Component level; Electrostatic Discharge Association, Rome, NY, USA. Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
- Recommended operating conditions
Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 10. Operating conditions Table 11. General characteristics
Table 12. PORT control input characteristics Table 13. ADR/CON_DET input/output characteristics Table 14. SCL and SDA input characteristics Table 15. Open-drain output buffer characteristics (EXT_SEL, OUT2, OUT1, INTB/OUT3, ID pins)
Product data sheet Rev. 1 — 9 December 2016 16 of 27 NXP Semiconductors PTN5150A CC logic for USB Type-C applications 11. Package outline Fig 6. Package outline X2QFN12 (SOT1355-1) 5HIHUHQFHV2XWOLQH YHUVLRQ (XURSHDQ SURMHFWLRQ ,VVXHGDWH ,(& -('(& -(,7$ 627 02 VRWBSR 8QLW PP PD[ QRP PLQ 'LPHQVLRQV PPDUHWKHRULJLQDOGLPHQVLRQV ;4)1 SODVWLFVXSHUWKLQTXDGIODWSDFNDJH QROHDGV WHUPLQDOV ERG\\[[PP627 EF '(HH H / Y PP VFDOH 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG GHWDLO; F \\&\\ WHUPLQDO LQGH[DUHD WHUPLQDO LQGH[DUHD E $&%Y H H H H H H
Product data sheet Rev. 1 — 9 December 2016 17 of 27 NXP Semiconductors PTN5150A CC logic for USB Type-C applications 12. Packing information
12.1 X2QFN12; Reel dry pack, SMD, 13"; Q2/T3 standard product
orientation; Orderable part number ending ,528 or MP; Ordering code (12NC) ending 528
12.1.1 Packing method
Fig 7. Reel dry pack for SMD DDD 5HODWLYHKXPLGLW\\ LQGLFDWRU %DUFRGHODEHO %DJ (6'SULQW 0RLVWXUHFDXWLRQ SULQW 'U\\DJHQW 'U\\SDFN,'VWLFNHU 6SDFHIRUDGGLWLRQDO ODEHO 3UHSULQWHG(6' ZDUQLQJ %DUFRGHODEHO %DUFRGHODEHO (6'HPERVVHG 5HHODVVHPEO\\ 3ULQWHGSODQRER[ *XDUGEDQG 7DSH &RYHUWDSH &LUFXODUVSURFNHWKROHVRSSRVLWHWKH ODEHOVLGHRIUHHO &DUULHUWDSH 4$VHDO 3ULQWHGSODQRER[
[1] d = reel diameter; w = tape width. [2] Packing quantity dependent on specific product type. View ordering and availability details at NXP order portal, or contact your local NXP representative.
12.1.2 Product orientation
12.1.3 Carrier tape dimensions
Table 16. Dimensions and quantities Table 17. Carrier tape dimensions In accordance with IEC 60286-3.
12.1.4 Reel dimensions
Table 18. Reel dimensions In accordance with IEC 60286-3.
12.1.5 Barcode label
- Soldering of SMD packages
13.1 Introduction to soldering
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
- Through-hole components
- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Fig 11. Example of typical box and reel information barcode label
Table 19. Barcode label dimensions
due to an increased probability of bridging. packages with solder balls, and leadless packages are all reflow solderable.
- Board specifications, including the board finish, solder masks and vias
- Package footprints, including solder thieves and orientation
- The moisture sensitivity level of the packages
- Package placement
- Inspection and repair
- Lead-free soldering versus SnPb soldering
13.3 Wave soldering
- Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
- Solder bath specifications, including temperature and impurities
13.4 Reflow soldering
- Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 12) than a SnPb process, thus reducing the process window
- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
- Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 20 and 21
Table 20. SnPb eutectic process (from J-STD-020D)
“Surface mount reflow soldering description”. Table 21. Lead-free process (from J-STD-020D)
Product data sheet Rev. 1 — 9 December 2016 23 of 27 NXP Semiconductors PTN5150A CC logic for USB Type-C applications 14. Soldering: PCB footprints Fig 13. PCB footprint for SOT1355-1 (X2QFN12); reflow soldering 627)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI;4)1SDFNDJH VRWBIU RFFXSLHGDUHD VROGHUSDVWH VROGHUUHVLVW VROGHUODQGV ,VVXHGDWH 'LPHQVLRQVLQPP î î î î
Table 22. Revision history
- Table 9 “Limiting values”: Added condition to control pins
- Added Section 12 “Packing information” PTN5150A v.1.1 20160316 Product data sheet - PTN5150A v.1 Modifications: • Section 2: Removed “Hibernation mode: 4.5 A”; device does not support hibernation mode. PTN5150A v.1 20160203 Product data sheet - -
Product data sheet Rev. 1 — 9 December 2016 25 of 27 NXP Semiconductors PTN5150A CC logic for USB Type-C applications 16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
Product data sheet Rev. 1 — 9 December 2016 26 of 27 NXP Semiconductors PTN5150A CC logic for USB Type-C applications Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PTN5150A CC logic for USB Type-C applications © NXP Semiconductors N.V. 2016. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 December 2016 Document identifier: PTN5150A Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents 7.5 I
12.1 X2QFN12; Reel dry pack, SMD, 13"; Q2/T3
standard product orientation; Orderable part number ending ,528 or MP; Ordering code