PTN38007 NXP | Alldatasheet
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 59
Technical content
Datasheet sections
- 1 General description
- 2 Features and benefits
- 3 Applications
- 4 Ordering information
- 4.1 Ordering options
- 5 Block diagram
- 6 Pinning information
- 6.1 Pinning
- 6.2 Pin description
- 7 Functional description
- 7.2 DisplayPort operation
- 7.2.1 AUX monitoring and configuration
- 7.3 Thunderbolt3/USB4 operation
- 7.3.1 SB snooping monitor
- 7.4 Signal detectors
- 7.5 Linear redriver controls
- 7.6 USB Type-C DFP application
- 7.7 USB Type-C UFP application
- 7.8 Control and programmability
- 7.8.1 Power-on operational mode
- 7.8.2 Auto Orientation Detection feature
- 7.8.3 Mode transitions
- 7.8.5 I2C configurability
- 7.8.6 I2C registers
- 7.8.7 I2C read/write operations
- 7.8.7.1 Single byte register reads/writes
- 7.8.7.2 Multi-byte register reads/writes
- 8 Limiting values
- 9 Recommended operating conditions
- 10 Characteristics
- 10.1 Device characteristics
- 10.2 Input AC/DC characteristics
- 10.3 Output AC/DC characteristics
- 10.4 AUX and SB snooping monitor
- 10.5 Control characteristics for AUTO_ORIENT_
- 10.6 Ternary control characteristics for LCTL[1,
- 10.7 Quaternary control characteristics for
- 10.8 I2C AC/DC characteristics
- 11 Package outline
- 12 Packing information
- 12.1 SOT1948-1; HWFLGA36; reel dry pack,
- 12.1.1 Dimensions and quantities
- 12.1.2 Product orientation
- 12.1.3 Carrier tape dimensions
- 13 Soldering
- 14 Abbreviations
- 15 References
- 16 Revision history
- 17 Legal information
Multi-protocol USB4 20 Gbps linear redriver Rev. 2.1 — 8 December 2021 Product data sheet
1 General description
PTN38007 is a high-performance USB Type-C USB3.2/DisplayPort/Thunderbolt3/USB4 multi-protocol linear redriver that is optimized for USB3.2, DisplayPort and Thunderbolt3/ USB4 applications on either the downstream facing port (DFP) or upstream facing port (UFP) application. PTN38007 addresses high-speed signal quality enhancement requirements for implementation of USB Type-C interface in a platform that supports the USB Type- C, VESA DisplayPort and Thunderbolt Alternate Mode Standards. This device also implements the snooping monitor of the sideband (SB) signals from DP mode (AUX) and Thunderbolt3/USB4 mode (SBTX/RX) to optimize the configuration, power saving mode and performance. The device provides programmable linear equalization, output swing linearity control by pin strapping or I2C control to improve signal integrity and enable channel extension by reducing inter-symbol interference (ISI). DisplayPort AUX snooping is performed to follow certain DisplayPort source-sink AUX transactions and configure the redriver to meet link requirements. Thunderbolt3/USB4 SB snooping is performed to optimized the power saving mode and configuration. For USB operation, PTN38007 has built-in advanced power management capability that enables significant power saving under USB3.2 low power modes (U2/U3). It detects LFPS (Low Frequency Periodic Signaling)/LBPM (LFPS Based PWM Message) signaling to configure the operation (USB3.2 Gen 1/Gen 2 & x1/x2) and link electrical conditions and it activates/deactivates internal circuitry and logic dynamically. The device performs these actions without host software intervention and conserves power. The host processor keeps PTN38007 in deep power saving or USB mode until alternate mode has been entered. The device is tailored to support USB3.2 and USB4 electrical idle, receiver detection and power saving modes. It maintains two separate input signal detectors – loss of high- speed signal (LOS) and USB LFPS detectors with built-in hysteresis. For DisplayPort (DP) operation, PTN38007 monitors the AUX transactions and adjusts the DisplayPort channel setting during DP Link initialization and training. For Thunderbolt3 (TBT3) and USB4, PTN38007 monitors SBTX and SBRX sideband traffic to optimize the performance. It decodes LT transaction to determine link and power status. PTN38007 is powered from a 1.8 V supply. It is available in a small high performance HWFLGA36 package.
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver
2 Features and benefits
- Flexible multi-protocol linear redriver supports five signaling combinations specified in USB Type-C and VESA specifications – Mode 0: Deep Power saving – Mode 1: USB3.2 Gen1x1/Gen1x2/Gen2x1/Gen2x2 – Mode 2: USB3.2 + DP 2-Lane + AUX snooping – Mode 3: DP 4-Lane + AUX snooping – Mode 4: Thunderbolt3 mode + SB snooping – Mode 5: USB4 mode + SB snooping
- Supports USB 3.2 Gen1x1, Gen 1x2, Gen2x1, Gen2x2 (5 Gbps and 10 Gbps) – I2C register based Flat gain control – Peaking gain of +12.1 dB at 5 GHz – Output swing linearity control: 500 mVppd to 950 mVppd Gbps (HBR3),10 Gbps (UHBR10), 13.5 Gbps (UHBR13.5), 20 Gbps (UHBR20) – DP AUX monitoring during DP link training to control DP channel – I2C register based Flat gain control – Peaking gain of +10.2 dB at 4.05 GHz, 20 dB at 10 GHz – Output swing linearity control: 500 mVppd to 950 mVppd
- Support Thunderbolt3/USB4 lane speed of 10/10.3125/20/20.6 Gbps – SBTX and SBRX snooping – I2C register based Flat gain control – Peaking gain of +20 dB at 10 GHz – Output swing linearity control: 500 mVppd to 950 mVppd
- Compliant to DisplayPort, Thunderbolt3 and USB4, USB3.2 standard and USB Type-C Alternate mode interoperability testing – Implements USB Type-C Safe state conditions on all connector facing pins
- Configurable via I2C interface with a configurable address pin
- Integrated termination resistors provide impedance matching on both transmit and receive sides
- Autonomous Orientation detection of USB-C connection and its configurable enable control
- Supports maximum voltage limit (Vvoltage_jump) to align to the latest USB3 specification and computing platform capabilities
- RX equalizers on all high-speed inputs to compensate for signal attenuation
- Automatic receiver termination detection in USB 3.2 and USB4 modes
- Good linearity over the frequency band (50 MHz to 10.3 GHz) and voltage dynamic range
- Excellent Differential return loss performance: < -16 dB up to 10.3 GHz
- Flow-through pin-out to ease PCB layout and minimize crosstalk effects – Very low crosstalk: DDNEXT < -50 dB up to 10.3 GHz Product data sheet Rev. 2.1 — 8 December 2021
- Low active current consumption for output swing linearity control of 950 mVppd – USB3.2 Gen2x2 or Gen1x2 (Mode 1) active power: 250 mA (typ) – USB3.2 Gen2x1 or Gen1x1 (Mode 1) active power: 125 mA (typ) – 1-lane DP HBR3/UHBR10/UHBR13.5/UHBR20 (Mode 2 or 3): 62 mA (typ) – 2-lane DP HBR3/UHBR10/UHBR13.5/UHBR20 (Mode 2 or 3): 125 mA (typ) – 4-lane DP only HBR3/UHBR10/UHBR13.5/UHBR20 (Mode 3): 250 mA (typ) – Thunderbolt3/USB4 dual-lanes (Modes 4 and 5): 250 mA (typ)
- Power–saving states: – USB3.2 (Mode 1) – 0.22 mA (typ) when 2 lanes are enabled in USB3 U2/U3 states – 0.11 mA (typ) when 1 lane is enabled in USB3 U2/U3 states – 0.11 mA (typ) only Rx detection is enabled on 1 lane when no connection detected (USB Rx detection enabled) – DisplayPort sleep D3 mode (Mode 3): 3.2 mA (typ) – Thunderbolt3/USB4 in CL1/CL2 state (Mode 4/5) – 0.65 mA when in low power state (2 lanes) – 10 μA (typ) when in deep power saving state
- Hot Plug capable: – Support USB Type-C plug connection through PD controller
- Power Supply 1.7 V to 1.9 V
- Small high performance HWFLGA36 package
- ESD HBM 1.5 kV, CDM 1 kV
- Operating temperature range -20 °C to +85 °C
3 Applications
- For USB Type-C host/source application – Smartphones and tablets – Notebooks, AIO and desktop computers – Hub or Dock Devices
- For USB Type-C device/sink application – Docking stations – Display units
4 Ordering information
Table 1. Ordering information
4.1 Ordering options
7000 Tamb = -20 °C to 85 °C
Table 2. Ordering options
5 Block diagram
Figure 1. Block diagram
6 Pinning information
6.1 Pinning
Figure 2. PTN38007 pinning (transparent top view)
6.2 Pin description
1 B_IOP
2 B_ION
Table 3. Pin description
3 VCCB
11 VCCC
21 VCCD
29 VCCA
4 LCTL3 Ternary Input Ternary Input for controlling Output Swing Linearity on the
12 LCTL1
5 LCTL2
6 A_INP
7 A_INN
8 SCL Open Drain
3.3 V) is required
9 C_INN
10 C_INP
13 AUTO_
- If the pin input is HIGH, Autonomous orientation detection is enabled
- If this pin is LOW, Autonomous orientation detection is disabled The pin can be either strapped in the application or connected to host processor. The pin is sampled at POR for initiating orientation detection process. This pin has a weak internal pulldown resistor (2 MΩ typ) to GND. The resistor value could change based on die area available and maximum leakage current on the pin.
14 D_ION
15 D_IOP
17 AUXN
18 AUXP
19 DRX1P
20 DRX1N
22 ADDR Quaternary
23 RCTL1
30 RCTL2
Table 3. Pin description...continued
24 DTX1P
25 DTX1N
26 SDA Binary open
27 DTX2N
28 DTX2P
31 TEST Reserved
32 DRX2N
33 DRX2P
34 SBTX
35 SBRX
36 RCTL3 Ternary input Ternary input for controlling Output Swing Linearity on the
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver
7 Functional description
7.1 USB3.2 operation PTN38007 supports USB3.2 Redriver operation at Gen1 (5 Gbps) and Gen2 (10 Gbps) data rates. The receive equalization – peaking gain and linearity level (-1 dB compression point) are configured either via I2C register settings or pin strapping. PTN38007 has implemented an advanced power management scheme that operates in tune with USB Bus electrical condition. Though the device does not decode USB power management commands (related to USB3 U1/U2/U3 transitions) exchanged between USB Host and Peripheral/Device, it relies on bus electrical conditions and control pins/ register settings to decide to be in one of the following states:
- Active state wherein device is fully operational. In this state, USB connection exists and the Receive Termination remains active.
- Power-saving state wherein some portions of the TX and RX channels are kept enabled. In this state, LOS detector, LFPS/LBPM detection and/or Receive termination detection circuitry are active. Based on USB connection, there are two possibilities: – No USB connection (also called Rx-detect state) – Receive Termination detection circuitry keeps polling periodically – RX and TX signal paths (including LOS detector) are not enabled – Receive Termination is not active – When USB connection exists and when the link is in USB U2/U3 mode, – Receive Termination detection circuitry keeps polling periodically – RX and TX signal paths are not enabled; LOS detector is disabled, and LFPS detector is enabled. – Receive Termination is active
7.2 DisplayPort operation
PTN38007 supports DisplayPort v1.4/2.0 operation seamlessly at 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, 8.1 Gbps, 10 Gbps, 13.5 Gbps, and 20 Gbps with receiver equalization and output swing linearity control. The DisplayPort mode is selected only when DP alternate mode has been entered by the host controller. The DisplayPort source can activate power down via AUX command. DP spec supports two modes – D0/active or D3/Low power mode. In D0 mode, the linear redriver data path is active depending on the state of the DP link. In D3 mode, the AUX snooping logic is active while high-speed path is disabled resulting in lower current consumption. The DisplayPort lane count is configured during DisplayPort link training phase based on AUX communication exchanges between source and sink. PTN38007 performs equalization control for DP signals, and can be configured by LCTL[3:1] and RCTL[3:1] settings through either I2C or pin strapping. PTN38007 uses lane count information for configuring the transmitters and receivers. It is possible that only a subset of lanes gets selected during DP Link training and remaining lanes are not active. Depending on the number of lanes selected, PTN38007 is configured to operate with the selected lane count thereby saving power consumption on unused lanes. Product data sheet Rev. 2.1 — 8 December 2021
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver
7.2.1 AUX monitoring and configuration
PTN38007 monitors DP AUX communication exchanges that occur between DP source and DP sink. It detects AUX communication involving DPCD register controls – Lane count, sleep, wake and configures its operation suitably. AUX monitor function is enabled when operating mode is set to Mode 2 (USB+DP 2-Lane) or 3 (DP 4-Lane), and is disabled in other mode settings. The list of DPCD registers (with only the relevant bit fields) supported are as follows:
- LANE_COUNT_SET
- SET POWER
- Other DPCD registers and I2C over AUX transactions are not decoded Input receive equalization is determined by LCTL[2:1] pins, and output linearity (-1 dB compression point) is controlled by LCTL3. All lanes of DP redriver can be configured separately on a per lane basis using I2C. When the Lane-Count is set via AUX, then the legal values are 1,2,4. If AUX tries to set it to 0, PTN38007 ignores it, and continues with the last known legal value. When the Lane-Count is set via I2C, then the legal values are 0,1,2,4. If I2C sets it to 0, PTN38007 disables all the lanes.
- Operational Mode = 0/1, DP Lane count = 0
- Operational Mode = 2, DP Lane count = 1 or 2
- Operational Mode = 3, DP lane count = 1, 2 or 4
7.3 Thunderbolt3/USB4 operation
PTN38007 supports the 3rd generation Thunderbolt and USB4. It is also backward compatible to the first and 2nd generation Thunderbolt systems that follow the USB Type- C Thunderbolt Specification r1p5 D0.8.
7.3.1 SB snooping monitor
Thunderbolt and USB4 systems use sideband interface (SBTX/SBRX) to communicate and exchange information between link partners and end systems. UART signaling is done over SBTX/SBRX at 1 Mbaud. The SBTX/SBRX are connected to SBU1/ SBU2 after negotiation to the Thunderbolt/USB4 mode of operation. SBTX is a serial transmit signal from Thunderbolt/USB4 Controller, and SBRX is a serial receive signal to Thunderbolt/USB4 Controller. This chip implements SB snooping monitor to optimize the power saving and performance. The monitoring is done only for Link Type Transactions (LT), and is enabled when operating mode is set to Mode 4 (TBT3) or Mode 5 (USB4), and is disabled in other mode settings.
7.4 Signal detectors
PTN38007 implements two types of signal detectors:
- LFPS detector: This is used in detect LFPS signaling on high speed data path. This is implemented only on lanes wherein USB and TBT3/USB4 data flows. While LFPS decoding is done in USB to determine certain USB sub-states, only detection of LFPS signaling is used to trigger exit from low power states of TBT3/USB4. Product data sheet Rev. 2.1 — 8 December 2021
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver
- Loss of (High-speed) Signal detector (LOS detector): This is meant for detecting both presence and absence of high-speed signal at the input pins over all protocols - USB, DP, TBT3 and USB4. The LOS detection is used to enter and exit from low power states. Based on LOS detector output, PTN38007 turns off certain portions of the internal circuitry and optimizes current consumption under various modes: USB (U2/U3), DP (D3 mode), TBT3/USB4 (CLx) and especially under electrical idle conditions.
7.5 Linear redriver controls
PTN38007 allows for programming of linear redriver functions – equalizer and linearity on a per channel basis. Since the USB3.2, DisplayPort and TBT3/USB4 input channels support different maximum data rates, the corresponding input equalization on those paths need to be tuned accordingly. Each linear redriver channel path has individual control of
- Flat gain can be controlled via I2C register for all the high speed data paths
- Peaking gain referenced to the maximum data rate (or Nyquist channel) in that channel
- Output Linear Swing is set up based on selected input source signal amplitude and pre- emphasis and considering channel attenuation Product data sheet Rev. 2.1 — 8 December 2021
7.6 USB Type-C DFP application
Figure 3. Connection illustration when PTN38007 in DFP application downstream side is connected to a USB4 retimer/router in the system application.
33 DRX2P A11 RX2+
32 DRX2N A10 RX2-
27 DTX2N B3 TX2-
28 DTX2P B2 TX2+
24 DTX1P A2 TX1+
25 DTX1N A3 TX1-
20 DRX1N B10 RX1-
19 DRX1P B11 RX1+
18 AUXP Input of SBU XBAR
17 AUXN Input of SBU XBAR
35 SBRX Input of SBU XBAR
34 SBTX Input of SBU XBAR
Table 4. Downstream pin connection in DFP application
14 D_ION SSRX1- SSRX2- SSRX- SSRX- ML0- ML3- ML0-
15 D_IOP SSRX1+ SSRX2+ SSRX+ SSRX+ ML0+ ML3+ ML0+
10 C_INP SSTX1+ SSTX2+ SSTX+ SSTX+ ML1+ ML2- ML1+
9 C_INN SSTX1- SSTX2- SSTX- SSTX- ML1- ML2+ ML1-
6 A_INP SSTX2+ SSTX1+ SSTX+ ML1+ SSTX+ ML1+ ML2+
7 A_INN SSTX2- SSTX1- SSTX- ML1- SSTX- ML1- ML2-
1 B_IOP SSRX2+ SSRX1+ SSRX+ ML0+ SSRX+ ML0+ ML3+
2 B_ION SSRX2- SSRX1- SSRX- ML0- SSRX- ML0- ML3-
Table 5. Upstream pin connection to host processor in DFP application
7.7 USB Type-C UFP application
Figure 4. Connection illustration when PTN38007 in UFP application upstream side is connected to a USB4/CIO retimer/router in the system application. the upstream pin connection facing the Type-C receptacle.
14 D_IOP B2 TX2+
15 D_ION B3 TX2-
9 C_INN A10 RX2-
10 C_INP A11 RX2+
6 A_INP B11 RX1+
7 A_INN B10 RX1-
1 B_IOP A2 TX1+
2 B_ION A3 TX1-
18 AUXP Output of SBU XBAR
17 AUXN Output of SBU XBAR
35 SBRX Output of SBU XBAR
34 SBTX Output of SBU XBAR
Table 6. Upstream pin connection in UFP application
20 DRX1N SSTX2- SSTX1- SSTX- ML0- SSTX- ML0- ML3-
19 DRX1P SSTX2+ SSTX1+ SSTX+ ML0+ SSTX+ ML0+ ML3+
24 DTX1P SSRX2+ SSRX1+ SSRX+ ML1+ SSRX+ ML1+ ML2+
25 DTX1N SSRX2- SSRX1- SSRX- ML1- SSRX- ML1- ML2-
28 DTX2P SSRX1+ SSRX2+ SSRX+ SSRX+ ML1+ ML2+ ML1+
27 DTX2N SSRX1- SSRX2- SSRX- SSRX- ML1- ML2- ML1-
33 DRX2P SSTX1+ SSTX2+ SSTX+ SSTX+ ML0+ ML3+ ML0+
32 DRX2N SSTX1- SSTX2- SSTX- SSTX- ML0- ML3- ML0-
Table 7. Downstream pin connection to device processor in UFP application
7.8 Control and programmability
7.8.1 Power-on operational mode
is HIGH, then the device goes into USB mode of operation.
0 Default to operate in deep
Figure 5. AUTO_ORIENT_EN control flow diagram
7.8.2 Auto Orientation Detection feature
for overall operating settings, and details are explained below. are used to configure USB upstream and downstream channel conditions. RCTLx values in register 0x10 through 0x13.
aborting the auto orientation detection process. Auto Orientation Detection Executed. Figure 6. Auto-orientation flowchart
7.8.3 Mode transitions
and connection specification, USB Power Delivery and Alternate Mode specifications. Figure 7 illustrates the various functional modes and deep power saving state transitions. before making the mode transition. The user can configure the device to transition between different modes at any time. requires a disconnect event which requires a return to USB Safe state.
Figure 7. Mode transition state diagram the ternary inputs sampled at power-up.
Figure 8. LCTL/RCTL signals to corresponding transmitter or receiver protocols - USB, DP, TBT/USB4.
100 MHz
Table 8. LCTL[2:1] and RCTL[2:1] Channel configurations: Flat gain setting of 0
Table 9. LCTL[2:1] and RCTL[2:1] Channel configurations: Flat gain setting of 1
1 OPEN OPEN 650 mVppd
2 LOW LOW 800 mVppd
3 HIGH HIGH 950 mVppd
Table 10. LCTL3/RCTL3 channel configuration
7.8.5 I2C configurability
Table 11. I2C slave address options
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver
7.8.6 I2C registers
The system integrator must program the registers of the device for proper operation. Further, it is expected that the system integrator performs I2C configuration after power- up and before data transport is initiated over the link. If such an operation is attempted during normal operation, the device may not behave as specified. Register offset Register name Bits POR default value
Description
Chip ID 7:0 b'00001001 Chip ID Number 7:4 b'1010 Chip base layer version0x01 Read Only Chip Revision 3:0 b'0001 Chip metal layer version 0x02 Reserved 7:0 b'0000 0000 Flat gain control setting for each high speed data path. The gain is specified at 100 MHz 7:6 b'00 Write '0' only. Read is don't care 5 b'0 Lane B Rx path (Figure 8) flat gain control 0 = flat gain of +0.7 dB, 1 = flat gain of -0.7 dB 4 b'0 Lane D Rx path flat gain control 0 = flat gain of +0.7 dB, 1 = flat gain of -0.7 dB 3 b'0 Lane B Tx path (Figure 8) flat gain control 0 = flat gain of +0.7 dB, 1 = flat gain of -0.7 dB 2 b'0 Lane A Tx path flat gain control 0 = flat gain of +0.7 dB, 1 = flat gain of -0.7 dB 1 b'0 Lane C Tx path flat gain control 0 = flat gain of +0.7 dB, 1 = flat gain of -0.7 dB 0x03 Read/Write Flat gain control 0 b'0 Lane D Tx path downstream flat gain control 0 = flat gain of +0.7 dB, 1 = flat gain of -0.7 dB
7 AUTO_
ORIENT_EN pin value Auto orientation enable bit is used to select Auto orientation option
- 1 = Enable
- 0 = Disable or abort an ongoing auto orientation detection process 6 b'0 Orientation done bit
- When 0, 'Plug orientation control' bit (bit 4) is not valid
- When 1, then it conveys 'Plug orientation control' bit (bit 4) is valid. This bit is cleared when Auto orientation enable (bit 7) is cleared by host, and it is not valid when bit 7 is '0'. Writes to this bit do not have any effect. 0x04 Read/Write Mode control 5 b'0 DFP or UFP configuration
- 0: DFP configuration
- 1: UFP configuration
Table 12. I2C registers and description
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver Register offset Register name Bits POR default value 4 b'0 Plug orientation control. This orientation condition applies to high-speed TX/RX configuration
- 0: normal plug orientation of Type-C connection
- 1: reverse plug orientation of Type-C connection This bit is to be written/read by the host or it can get updated automatically whenever ‘Auto orientation enable’ option is selected by setting bit 7 to ‘1'. If bit 7 is ‘1’, then the bit value is valid only when ‘Orientation done’ bit (bit 6) is ‘1’. The host shall not write this bit while bit[7] = 1. Overriding the orientation selection is possible only when bit 7 is cleared. 3 b'0 AUX snooping polarity control bit
- When 0, AUXP/AUXN signal polarities follow pin naming: – Pin 18 = AUXP – Pin 17 = AUXN
- When 1, AUXP/AUXN signal polarities are reverse of the pin naming: – Pin 17 = AUXP – Pin 18 = AUXN 2:0 b'000 Operational mode of the device. Refer to Section 7.8.3 for mode transition requirement
- 0: Deep power saving state
- 1: USB3.2
- 2: USB3.2 and 2-lane DP
- 3: 4-lane DP
- 4: Thunderbolt3
- 5: USB4
- 6-7 Reserved 7:6 b'00 • Write '0' only. Read is don't care0x05 Read/Write Device control 5 b'0 LT bypass enable control
- 0: LT control is decoded and applied during transition from CLD to CL0 state
- 1: LT control is bypassed and not applied during transition from CLD to CL0 state
Table 12. I2C registers and description...continued
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver Register offset Register name Bits POR default value 4:2 b'101 Disconnect Programmable values for TBT and USB4 Modes
- 111 - 5 ms
- 110 - 2 ms
- 101 - 1 ms
- 100 - 500 μs
- 011 - 250 μs
- 010 -100 μs
- 001 - 50 μs
- 000 - 25 μs This register shall be set before entering TBT or USB4 mode. 1 b'0 AUX/SB snooping pin muxing When 0, AUX and SB snooping are done through separate interface pairs.
- AUX snooping using AUXP/AUXN pins
- SB snooping using SBTX/SBRX pins When 1, AUX and SB snooping are done through the same AUXP/AUXN pins.
- AUXP/AUXN snooping using AUXP/AUXN pins
- SB snooping using AUXP/AUXN pins PTN38007 decodes the protocols based on the respective mode that is enabled. 0 b'0 Device Reset bit. This is a self-clearing bit, and reading this register will always return 0.
- Writing a ‘1’ to this register will soft reset the device including I2C register contents and internal digital logic states, while the chip continuing to operate under I2C mode.
- Writing a ‘0’ does not have any effect. 7:5 b'000 Write '0' only. Read is don't care 4 b'0 DisplayPort Power saving mode selection on all DP lanes.
- 0: Normal/Active mode
- 1: D3 Power saving mode This field may be modified thru I2C write or AUX monitor function. When corresponding DPCD register changes are detected via AUX monitor, this field will be updated. 0x06 Read/Write DP link control and status 3:2 b'00 DisplayPort operating lane count
- 0: 0 DP Lane
- 1: 1 DP Lane
- 2: 2 DP lanes
- 3: 4 DP lanes This field may be modified thru I2C write or AUX monitor function. When corresponding DPCD register changes are detected via AUX monitor, this field will be updated.
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver Register offset Register name Bits POR default value 1:0 b'00 DP Link rate
- 0: 1.62 Gbps (RBR)
- 1: 2.7 Gbps (HBR)
- 2: 5.4 Gbps (HBR2)
- 3: 8.1 Gbps (HBR3) The field may be modified through I2C write or AUX monitor function. When corresponding DPCD register changes are detected via AUX monitor, this field will be updated. 7:4 b'00 Write '0' only. Read is don't care0x07 Read/Write DP Lane 0 Control_1 Register 3:0 LCTL1, LCTL2 DP Lane 0 link Equalization gain. Refer to Table 8 and Table 9 in Section 7.8.4 for Peaking gain setting across various Nyquist frequencies of this interface. 7:2 b'0000 00 Write '0' only. Read is don't care0x08 Read/Write DP Lane 0 Control_2 Register 1:0 LCTL3 DP Lane 0 output signal swing linearity
- 0: 500 mVppd
- 1: 650 mVppd
- 2: 800 mVppd
- 3: 950 mVppd 7:4 b'0000 Write '0' only. Read is don't care0x09 Read/Write DP Lane 1 Control_1 Register 3:0 LCTL1, LCTL2 DP Lane 1 link Equalization gain. Refer to Table 8 and Table 9 in Section 7.8.4 for Peaking gain setting across various Nyquist frequencies of this interface. 7:2 b'0000 00 Write '0' only. Read is don't care0x0A Read/Write DP Lane 1 Control_2 Register 1:0 LCTL3 DP Lane 1 output signal swing linearity
- 0: 500 mVppd
- 1: 650 mVppd
- 2: 800 mVppd
- 3: 950 mVppd 7:4 b'0000 Write '0' only. Read is don't care0x0B Read/Write DP Lane 2 Control_1 Register 3:0 LCTL1, LCTL2 DP Lane 2 link Equalization gain. Refer to Table 8 and Table 9 in Section 7.8.4 for Peaking gain setting across various Nyquist frequencies of this interface. 7:2 b'0000 00 Write '0' only. Read is don't care0x0C Read/Write DP Lane 2 Control_2 Register 1:0 LCTL3 DP Lane 2 output signal swing linearity
- 0: 500 mVppd
- 1: 650 mVppd
- 2: 800 mVppd
- 3: 950 mVppd
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver Register offset Register name Bits POR default value 7:4 b'0000 Write '0' only. Read is don't care0x0D Read/Write DP Lane 3 Control_1 Register 3:0 LCTL1, LCTL2 DP Lane 3 link Equalization gain. Refer to Table 8 and Table 9 in Section 7.8.4 for Peaking gain setting across various Nyquist frequencies of this interface. 7:2 b'0000 00 Write '0' only. Read is don't care0x0E Read/Write DP Lane 3 Control_2 Register 1:0 LCTL3 DP Lane 3 output signal swing linearity
- 0: 500 mVppd
- 1: 650 mVppd
- 2: 800 mVppd
- 3: 950 mVppd 7 0 LFPS detection disable in U2/U3 state in USB3 operation. This bit can be set/changed only during Deep Power saving mode. 0: LFPS detector is used in U2/U3 state to transition back to U0 state 1: LFPS detector is not used to transition from U2/ U3 state to U0 state 6 0 LoS detector disable in USB3 operation. This bit can be set/changed only during Deep Power saving mode. 0: LOS detector is enabled 1: LOS detector is disabled 5:4 b’00 Chip upstream (B_IO, A_IN, C_IN, and D_IO) side LOS detector threshold setting
- 0: 45 mV (default/POR)
- 1: 60 mV
- 2: 70 mV
- 3: 80 mV
- Other values are reserved The setting is applicable for operational modes (USB3.2, DP, TBT and USB4). It is used as a signal threshold reference for low power state management 0x0F Read/Write LOS detector threshold 3:2 b’00 USB3 power saving mode (U2/U3) and compliance mode select. This function is only valid when bit 6 is set to 1. When entering USB mode, PTN38007 is in U0 state. System can write this bit to enter Power saving mode (U2/U3) or compliance mode. These bits are updated to 00 after PTN38007 exits power saving mode (U2/ U3) to active mode (U0), or compliance mode to active mode (U0). 00: Active state (U0) 01: Power saving state (U2/U3) 10: Compliance mode 11: Transition from power saving state (U2/U3) to active state (U0)
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver Register offset Register name Bits POR default value 1:0 b’00 Chip downstream (DRX1 and DRX2) side LOS detector threshold setting.
- 0: 45 mV (default/POR)
- 1: 60 mV
- 2: 70 mV
- 3: 80 mV
- Other values are reserved The setting is applicable for all operational modes (USB3.2, TBT and USB4). It is used as a signal threshold reference for low power state management 7:4 b'0000 Write '0' only. Read is don't care0x10 USB_Downstream_RX_ Control 3:0 RCTL1, RCTL2 USB3.2 Mode downstream (DRX2 and DRX1) side link Equalization gain. Refer to Table 8 and Table 9 in Section 7.8.4 for Peaking gain setting across various Nyquist frequencies of this interface. 7:2 b'0000 00 Write '0' only. Read is don't care0x11 Read/Write USB_Upstream_TX_ Control 1:0 RCTL3 USB3.2 Mode upstream (B_IO and D_IO) side link output signal swing linearity
- 0: 500 mVppd
- 1: 650 mVppd
- 2: 800 mVppd
- 3: 950 mVppd 7:4 b'0000 Write '0' only. Read is don't care0x12 Read/Write USB_Upstream_ RX_ Control 3:0 LCTL1, LCTL2 USB3.2 Mode upstream (A_IN and C_IO) side link Equalization gain. Refer to Table 8 and Table 9 in Section 7.8.4 for Peaking gain setting across various Nyquist frequencies of this interface. 7:2 b'0000 00 Write '0' only. Read is don't care0x13 Read/Write USB_Downstream_TX_ Control 1:0 LCTL3 USB3.2 Mode downstream (DTX2 and DTX1) side link output signal swing linearity
- 0: 500 mVppd
- 1: 650 mVppd
- 2: 800 mVppd
- 3: 950 mVppd 0x14 Read only TBT3/USB4 link status 7 b'0 Subordinate lane status 0 = low power state 1 = active state Based on LT packet information, this bit is set on LT Resume in USB4 mode, or LT_GEN_2 or LT_GEN_3 in TBT3 mode; and reset on LROFF/ DISCONNECT/LTFALL
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver Register offset Register name Bits POR default value 6 b'0 Primary lane status 0 = low power state 1 = active state Based on LT packet information, this bit is set on LT Resume in USB4 mode, or LT_GEN_2 or LT_GEN_3 in TBT3 mode; and reset on LROFF/ DISCONNECT/LTFALL 5 b'0 Write '0' only. Read is don't care 4 b'0 Channel B status
- 0: Channel is in low power state
- 1: Channel is in active state This status bit is updated based on LOS/LT packets 3 b'0 Channel A status
- 0: Channel is in low power state
- 1: Channel is in active state This status bit is updated based on LOS/LT packets 2 b'0 Channel C status
- 0: Channel is in low power state
- 1: Channel is in active state This status bit is updated based on LOS/LT packets 1 b'0 Channel D status
- 0: Channel is in low power state
- 1: Channel is in active state This status bit is updated based on LOS/LT packets 0 b'0 Thunderbolt lane speed
- 0: 10.3125 Gbps
- 1: 20.625 Gbps This field is read-only, and reflects the lane status. 7:6 b'00 Write '0' only. Read is don't care 5:4 b'01 LOS detection timeout for transition from Active to low power state for downstream side channels (DRX2 and DRX1)
- 00 = 10 ms (typ)
- 01 = 300 ms (typ)
- 10 = 750 ms (typ)
- 11 = 1000 ms (typ) 0x15 Read/Write TBT3/USB4_ Downstream_RX_Control 3:0 RCTL1, RCTL2 TBT3/USB4 downstream (DRX2 and DRX1) link Equalization gain. Refer to Table 8 and Table 9 in Section 7.8.4 for Peaking gain setting across various Nyquist frequencies of this interface.
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver Register offset Register name Bits POR default value 7:2 b'000000 Write '0' only. Read is don't care0x16 Read/Write TBT3/USB4_Upstream_ TX_Control 1:0 RCTL3 TBT3/USB4 Upstream (B_IO and D_IO) output signal swing linearity
- 0: 500 mVppd
- 1: 650 mVppd
- 2: 800 mVppd
- 3: 950 mVppd 7:6 b'00 Select low-power state entry through LoS detector result 00: Enable entry only into CL1/CL2 01: Enable entry into CL0s/CL1/CL2 10: Reserved 11: Disable entry into CL0s/CL1/CL2 (Stay in CL0 only ) 5:4 b'01 LOS detection timeout for transition from Active to low power state for upstream side channels (A_IN and C_IN)
- 00 = 10 ms (typ)
- 01 = 300 ms (typ)
- 10 = 750 ms (typ)
- 11 = 1000 ms (typ) 0x17 Read/Write TBT3/USB4_Upstream_ RX_Control 3:0 LCTL1, LCTL2 TBT3/USB4 Upstream (A_IN and C_IN) link Equalization gain. Refer to Table 8 and Table 9 in Section 7.8.4 for Peaking gain setting across various Nyquist frequencies of this interface. 7:2 b'000000 Write '0' only. Read is don't care0x18 Read/Write TBT3/USB4_ Downstream_TX_Control 1:0 LCTL3 TBT3/USB4 Downstream (DTX2 and DTX1) output signal swing linearity
- 0: 500 mVppd
- 1: 650 mVppd
- 2: 800 mVppd
- 3: 950 mVppd 0x19-0xFF Reserved Reserved for NXP Internal use only; Do not write to these registers
7.8.7 I2C read/write operations
writing the registers must be done according to the following sequences.
- Command phase
- Data phase Product data sheet Rev. 2.1 — 8 December 2021
7.8.7.1 Single byte register reads/writes
back from the device register address. Figure 9. I2C read sequence the device register address. Figure 10. I2C write sequence
7.8.7.2 Multi-byte register reads/writes
- Master asserts START condition or repeated-START condition
- Master addresses PTN38007's slave address with R/W bit set as "Write"
- Slave acknowledges the request by asserting ACK
- Master writes the desired starting register address
8 Limiting values
periods may affect device reliability. In accordance with the Absolute Maximum Rating System (IEC 60134).
1500 V LTC-VOL-PRIO1-008
1500 V LTC-VOL-PRIO1-009
1000 V LTC-VOL-PRIO1-010
1000 V LTC-VOL-PRIO1-011
Table 13. Limiting values [1] All voltage values, except differential voltages, are with respect to network ground terminal.
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver [2] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model – Component level; Electrostatic Discharge Association, Rome, NY, USA. [3] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device Model – Component level; Electrostatic Discharge Association, Rome, NY, USA Product data sheet Rev. 2.1 — 8 December 2021
9 Recommended operating conditions
specified for 1.8 V and 25 °C operating temperature. Table 14. Operating conditions
10 Characteristics
10.1 Device characteristics
10 MHz)
5 GHz)
Measured by power rail probe.
10 MHz to 1 GHz 30 dB DEV-DB-PRIO2-004
10 MHz to 200 MHz 41 dB DEV-DB-PRIO2-005
Table 15. Device characteristics
10 GHz (Table 9)
5.0 GHz (Table 9)
10 GHz, 5 GHz
4.05 GHz (Table 9)
100 MHz to 15 GHz; Peaking
10 GHz and OS 950 mVppd
Table 15. Device characteristics...continued
[2] When one lane is active. Only LFPS detector is enabled. [3] Only Rx detection is enabled. [4] High Speed activity detector is enabled at the input of redriver.
Figure 13. Noise test configuration
10.2 Input AC/DC characteristics
120 MHz is deemed to
400 MHz is deemed to
1.8 V INC-VOL-PRIO2-008
Table 16. Input AC/DC characteristics
Table 16. Input AC/DC characteristics...continued
10.3 Output AC/DC characteristics
1.2 V OUC-VOL-PRIO2-003
1.3 V OUC-VOL-PRIO2-004
1.4 V OUC-VOL-PRIO2-005
1.5 V OUC-VOL-PRIO2-006
Table 17. Output AC/DC characteristics
10.4 AUX and SB snooping monitor characteristics
1 MΩ AUX-RES-PRIO2-006
Table 18. AUX monitor characteristics Table 19. SB monitor characteristics reference and 50 Ω single-ended impedance reference.
10.5 Control characteristics for AUTO_ORIENT_EN pin
Table 20. Binary control input characteristics (external system voltage VSYS = 1.7 V to 3.6 V) Figure 14. Binary input buffer setting
10.6 Ternary control characteristics for LCTL[1, 2, 3] and RCTL[1, 2, 3]
Table 21. Ternary control input characteristics (external system voltage VSYS= 1.7 V to 3.6 V) Figure 15. Ternary input buffer setting
10.7 Quaternary control characteristics for ADDR pin
Table 22. Ternary control input characteristics Figure 16. Quaternary input buffer setting
10.8 I2C AC/DC characteristics
0.57 V SER-VOL-PRIO1-003
Table 23. I2C interface- AC/DC characteristics for SCL and SDA pins
Table 23. I2C interface- AC/DC characteristics for SCL and SDA pins...continued 3.3 V from another power supply. Figure 17. I2C-bus timing diagram
Figure 18. Package outline SOT1948-1
Figure 19. Package outline dt HWFLGA36 (SOT1948-1)
Figure 20. Package outline note HWFLGA36 (SOT1948-1)
12 Packing information
12.1 SOT1948-1; HWFLGA36; reel dry pack, SMD, 13" Q1 standard
12.1.1 Dimensions and quantities
Table 24. Dimensions and quantities [1] d = reel diameter; w = tape width. your local NXP representative.
12.1.2 Product orientation
Figure 21. Product orientation in carrier tape
12.1.3 Carrier tape dimensions
Figure 22. Carrier tape dimensions In accordance with IEC 60286-3/EIA-481. Table 25. Carrier tape dimensions
13 Soldering
Figure 23. Reflow soldering footprint for SOT1948-1
Figure 24. Reflow soldering footprint part2 for HWFLGA36 (SOT1948-1)
Figure 25. Reflow soldering footprint part3 for HWFLGA36 (SOT1948-1)
14 Abbreviations
Table 26. Abbreviations
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver
15 References
[1] USB3.2 Specification, Revision 1.0, Sep 22, 2017 [2] Thunderbolt Interconnect Specification - USB Type-C TBT Alternate mode Rev 1.5, Draft v0.8, Oct 2017 [3] USB4 Specification Version 1.0, June 2020 [4] VESA DisplayPort v1.4a, Apr 19, 2018 (with the addition of additional data rates - 10/13.5/20 Gbps from DisplayPort v2.0 specification) [5] UM10204, “I2C-bus specification and user manual”; NXP Semiconductors, Rev 6, April 4, 2014 Product data sheet Rev. 2.1 — 8 December 2021
- Updated with DP2.0 link rates PTN38007 v1.0 20210607 Product data sheet - -
Table 27. Revision history
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver
17 Legal information
17.1 Data sheet status
Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Product data sheet Rev. 2.1 — 8 December 2021
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.
17.4 Trademarks
Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. Product data sheet Rev. 2.1 — 8 December 2021
NXP Semiconductors PTN38007 Multi-protocol USB4 20 Gbps linear redriver Tables Tab. 4. Downstream pin connection in DFP Tab. 5. Upstream pin connection to host processor Tab. 6. Upstream pin connection in UFP Tab. 7. Downstream pin connection to device Tab. 8. LCTL[2:1] and RCTL[2:1] Channel Tab. 9. LCTL[2:1] and RCTL[2:1] Channel Tab. 20. Binary control input characteristics (external system voltage VSYS = 1.7 V to Tab. 21. Ternary control input characteristics (external system voltage VSYS = 1.7 V to Tab. 23. I2C interface- AC/DC characteristics for Figures Fig. 3. Connection illustration when PTN38007 in Fig. 4. Connection illustration when PTN38007 in Fig. 8. LCTL/RCTL signals to corresponding Fig. 19. Package outline dt HWFLGA36 Fig. 20. Package outline note HWFLGA36 Fig. 24. Reflow soldering footprint part2 for Fig. 25. Reflow soldering footprint part3 for Product data sheet Rev. 2.1 — 8 December 2021