PTN36502A

PTN36502 NXP | Alldatasheet

Document overview

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Technical content

Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Rev. 3 — 28 September 2018 Product data sheet

1 General description

PTN36502/PTN36502A is a Type-C USB 3.1 Gen 1/ DP1.2 combo redriver that is optimized for USB 3.1 Gen 1 and DisplayPort applications on either the Downstream Facing Port (DFP) or Upstream Facing Port (UFP) by following the four high-speed differential data flows to extend the signal reach. PTN36502/PTN36502A addresses high-speed signal quality enhancement requirements for implementation of a USB Type-C interface in a platform that supports the VESA DisplayPort Alt Mode Standard v1.0a, includes a DisplayPort Branch or Sink function. PTN36502/PTN36502A has three ternary (3-level) configuration pins (SCL/C1, SDA/ C2 and EN), and depending on the state of EN pin during Power-On Reset (POR), the device gets into GPIO mode or I2C mode. When EN is driven LOW during POR, PTN36502/PTN36502A operates under GPIO mode, and these three ternary pins are used to configure DFP/UFP configuration followed by mode setting (USB 3.1 Gen 1 and DisplayPort TX and RX function selection), as well as selecting receive equalization, transmit de-emphasis and output swing level. To support applications that require greater level of configurability, PTN36502/PTN36502A can operate in I2C mode when EN pin is left open (OPEN/NC) during POR. For DisplayPort (DP) operation, PTN36502/PTN36502A has a built-in internal crossbar function that can swap AUXP and AUXN signals for supporting plug orientation. PTN36502/PTN36502A monitors the AUX transactions and adjusts the DisplayPort transmitter’s output swing and emphasis setting during DP Link training accordingly. PTN36502/PTN36502A has built-in advanced power management capability that enables significant power saving under USB 3.1 Gen 1 Low power modes (U2/U3). It can detect LFPS signaling and link electrical conditions and can dynamically activate/deactivate internal circuitry and logic. The device performs these actions without host software intervention and conserves power. The host processor keeps PTN36502/PTN36502A in deep power saving or USB operation mode until DP Alt mode is entered. PTN36502/PTN36502A is powered from a 1.8 V supply and it is available in an extremely

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018

2 Features and benefits

• Flexible Type-C USB/DP combo redriver supports four signaling combinations specified in USB Type-C and VESA DisplayPort Alt Mode Standards through either I2C slave interface or ternary GPIO pins – Mode 1: One USB 3.1 Gen 1 port only – Mode 2: One USB 3.1 Gen 1 port + 2 lane DP + AUX channel – Mode 3: 4 lane DP + AUX channel
• Supports USB 3.1 Gen 1 data rate of 5 Gbps, and DisplayPort data rates at 1.62 Gbps, 2.7 Gbps and 5.4 Gbps (HBR2), AUX at 1 Mbps
• Compliant to SuperSpeed USB 3.1 Gen 1 standard
• Compliant to DisplayPort v1.2 standard for DFP applications
• Compliant to VESA DisplayPort Alt mode on USB Type-C standard
• Implements USB Type-C Safe state conditions on all connector facing pins
• Configurable via ternary GPIO or I2C interface (operating up to 1 MHz)
• PTN36502 7-bit I2C address = 001 1010
• PTN36502A 7-bit I2C address = 001 0010
• Integrated termination resistors provide impedance matching on both transmit and receive sides
• RX equalizers on all inputs to compensate for high speed signal attenuation in PCB and cable channels
• Active TX De-emphasis and Output swing on all outputs to assure high frequency boost
• Automatic Receiver Termination Detection in USB 3.1 Gen 1 mode
• Supports auto power saving modes during USB 3.1 Gen 1 operation
• DP AUX sideband crossbar switch for Type-C plug orientation
• DP AUX monitoring during DP link training to control DP TX output driver adjustment
• Flow-through pinout to ease PCB layout and minimize crosstalk effects – Low crosstalk: DDNEXT < -45 dB at 2.7 GHz
• Low active current consumption – USB 3.1 Gen 1 only (Mode 1) active power: 115 mA (typ) for VOS = 1Vpp and DE=-3.5 dB – 2-lane DP HBR2 level 0 (Mode 3): 75 mA (Level 0 : 400 mV with no Pre-emphasis) – 1-lane DP HBR2 level 0 (Mode 3): 38 mA (Level 0 : 400 mV with no Pre-emphasis) – 4-lane DP only HBR2 level 0 (Mode 3): 150 mA
• Power-saving states: – USB 3.1 Gen 1 mode (mode 1): – 1.16 mA (typ) when in USB 3.1 Gen 1 U2/U3 states – 0.77 mA (typ) when no connection detected (USB Rx detection enabled) (when a USB Type-C to USB Type-A adapter is connected to a USB Type-C port, but no USB Type-A device is attached to the adapter) – DP sleep D3 mode (Mode 2/3): 0.5 mA (typ) – 3 μA (typ) when in deep power-saving state
• Excellent Differential and Common return loss performance
• Hot Plug capable
• Single Power Supply 1.8 V
• Extremely thin HX2QFN24 package – 2.4 mm x 3.2 mm x 0.35 mm with 0.4 mm pitch

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018

• ESD HBM 8 kV CDM 1 kV on high speed pins and HBM 4 kV CDM 500 V on control pins
• Supports IEC61000-4-5 8/20 μs ±16 V Surge test performance with external 4.7 Ω series resistors on the DRX1P/N, DRX2P/N and DAUXP/N pins
• Operating temperature range -40 to +85 ℃

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018

3 Applications

• For USB Type-C Host/Source application – Smartphones and Tablets – Notebooks, AIO and Desktop Computers – Hub or Dock Devices
• For USB Type-C Device/Sink application – Docking Stations – Display units

4 Ordering information

Table 1. Ordering information

4.1 Ordering options

Table 2. Ordering options

3000 Tamb = -40 ℃ to 85 ℃

5 Functional diagram

Figure 1. Functional diagram

6 Pinning information

6.1 Pinning

Figure 2. PTN36502/PTN36502A pinning (transparent top view)

6.2 Pin description

Table 3. Pin description

1 SCL/C1 Ternary open drain input/

tolerant. Refer to Section 7.6 for more details.

2 SDA/C2 Ternary open drain input/

tolerant. Refer to Section 7.6 for more details.

3 C_INP

4 C_INN

5 A_INP

6 A_INN

7 UAUXP

8 UAUXN

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018 Symbol Pin Type Description

9 B_IOP

10 B_ION

Self-biasing differential input/ output Differential signal high speed input/output. B_IOP makes a differential pair with B_ION. The associated output/input pair is DRX2P and DRX2N. The I/O configuration is controlled by mode setting

11 DRX2P

12 DRX2N

Self-biasing differential input/ output Differential signal high speed input/output. DRX2P makes a differential pair with DRX2N. The associated output/input pair is B_ IOP and B_ION. The I/O configuration is controlled by mode setting

13 DAUXN

14 DAUXP

I/O Downstream AUX Channel I/O. When PTN36502/PTN36502A is placed in UFP application, these signals should be AC coupled as per DP spec

15 DTX2N

16 DTX2P

Differential signal of high speed TX path. DTX2P makes a differential pair with DTX2N. The associated RX input pair is A_IP and A_IN

17 DTX1P

18 DTX1N

Differential signal of high speed TX path. DTX1P makes a differential pair with DTX1N. The associated RX input pair is C_IP and C_IN 19 VDD18 1.8 V Supply 20 EN Ternary input 3 level mode configuration pin. When power is applied on VDD18 pin

• If EN = 0, PTN36502/PTN36502A is operating in GPIO mode
• If EN = OPEN, PTN36502/PTN36502A is operating in I2C mode

21 DRX1N

22 DRX1P

Self-biasing differential input/ output Differential signal high speed input/output. DRX1P makes a differential pair with DRX1N. The associated output/input pair is D_ IOP and D_ION. The I/O configuration is controlled by mode setting

23 D_ION

24 D_IOP

Self-biasing differential input/ output Differential signal high speed input/output. D_IOP makes a differential pair with D_ION. The associated output/input pair is DRX1P and DRX1N. The I/O configuration is controlled by mode setting Center pad GND The center pad must be connected to GND plane for both electrical grounding and thermal relief

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018

7 Functional description

7.1 USB 3.1 Gen 1 operation PTN36502/PTN36502A supports USB redriver operation at 5 Gbps. The receive equalization, transmit output swing and de-emphasis settings are configured via GPIO or I2C register settings. PTN36502/PTN36502A has implemented an advanced power management scheme that operates in tune with USB 3.1 Gen 1 Bus electrical condition. Though the device does not decode USB power management commands (related to USB 3.1 Gen 1 U1/ U2/U3 transitions) exchanged between USB Host and Peripheral/Device, it relies on bus electrical conditions and control pins/register settings to decide to be in one of the following states:

• Active state wherein device is fully operational. In this state, USB connection exists and the Receive Termination remains active.
• Power-saving state wherein some portions of the TX and RX channels are kept enabled. In this state, squelching, LFPS detection and/or Receive termination detection circuitry are active. Based on USB connection, there are two possibilities: – No USB connection (also called Rx-detect state) – Receive Termination detection circuitry keeps polling periodically – RX and TX signal paths (including squelch detector) are not enabled – Receive Termination is not active – DC Common mode voltage level is not maintained – When USB connection exists and when the link is in USB U2/U3 mode, – Receive Termination detection circuitry keeps polling periodically – RX and TX signal paths are not enabled; squelch detector is enabled – Receive Termination is active – DC Common mode voltage level is maintained 7.2 DisplayPort v1.2 operation PTN36502/PTN36502A supports DisplayPort redriver operation at 1.62 Gbps, 2.7 Gbps and 5.4 Gbps, with 2-tap pre-emphasis, pre-emphasis levels 0 to 3 and output swing levels 0 to 3. The DisplayPort mode is selected only when DP Alternate mode has been entered by the host controller. Until then, PTN36502/PTN36502A stays in deep power saving or USB 3.1 Gen 1 only mode. The DisplayPort source can activate power down via AUX command. The DisplayPort link rate, lane count, transmit output swing and pre-emphasis settings are configured autonomously during DisplayPort link training phase based on AUX communication exchanges between Source and Sink. In addition, the host can configure these settings via I2C interface. Table 4 illustrates the various combinations allowed and supported in DisplayPort modes. The host AP shall configure the settings only based on valid combinations listed in this table. Note PTN36502/PTN36502A does not check if combination is valid while being configured.

Table 4. Allowed output swing and pre-emphasis combinations in DisplayPort mode consumption on unused lanes.

7.2.1 AUX crossbar switch

is in Hi-Z state at power-on reset.

7.2.2 AUX monitoring and configuration

local biasing and AC coupling capacitance are implemented. DAUXN pins will be interpreted as AUXN and AUXP signals internally.

• LINK_BW_SET
• LANE_COUNT_SET
• TRAINING_LANEx_SET (x=0-3) (the DP source issues this command after sending the specific training pattern and so, the redriver must target very small delay)
• SET POWER
• Other DPCD registers and I2C over AUX transactions are not decoded The applied values are expected to be within the capabilities of PTN36502/PTN36502A. In case GPU sends out LANE_COUNT_SET =0 during AUX training, it is necessary to program I2C register 0x06 to value of 0x06 after entering DP modes (either mode 2 or 3).

PTN36502/PTN36502A programming guide.

7.3 USB Type-C DFP receptacle application

Figure 3. Connection illustration when PTN36502/PTN36502A in DFP receptacle application (1): 0.33μF capacitors are recommended on Type-C's receiver pins based on latest USB specification. (2): 0.22μF capacitors are recommended on Type-C's transmitter pins based on latest USB specification. and downstream (right) side is connected to Type-C receptacle.

Table 5. Downstream pin connection to Type-C receptacle in DFP application

22 DRX1P A11 RX2+

21 DRX1N A10 RX2-

18 DTX1N B3 TX2-

17 DTX1P B2 TX2+

16 DTX2P A2 TX1+

15 DTX2N A3 TX1-

12 DRX2N B10 RX1-

11 DRX2P B11 RX1+

14 DAUXP A8 SBU1

13 DAUXN B8 SBU2

mode according to the mode setting. Table 6. Upstream pin connection to application processor in DFP receptacle application

23 D_ION SSRX- ML0- SSRX- ML0- ML3-

24 D_IOP SSRX+ ML0+ SSRX+ ML0+ ML3+

3 C_INP SSTX+ ML1+ SSTX+ ML1+ ML2+

4 C_INN SSTX- ML1- SSTX- ML1- ML2-

5 A_INP SSTX+ SSTX+ ML1+ ML2+ ML1+

6 A_INN SSTX- SSTX- ML1- ML2- ML1-

9 B_IOP SSRX+ SSRX+ ML0+ ML3+ ML0+

10 B_ION SSRX- SSRX- ML0- ML3- ML0-

7 UAUXP AUX+ AUX+ AUX+ AUX+

8 UAUXN AUX- AUX- AUX- AUX-

7.4 USB Type-C UFP receptacle application

Figure 4. Connection illustration when PTN36502/PTN36502A in UFP receptacle application (1): 0.33μF capacitors are recommended on Type-C's receiver pins based on latest USB specification. (2): 0.22μF capacitors are recommended on Type-C's transmitter pins based on latest USB specification. crossbar switch function, and upstream (left) side is connected to Type-C receptacle.

Table 7. Upstream pin connection to Type-C receptacle in UFP application

23 D_ION A3 TX1-

24 D_IOP A2 TX1+

3 C_INP B11 RX1+

4 C_INN B10 RX1-

5 A_INP A11 RX2+

6 A_INN A10 RX2-

9 B_IOP B2 TX2+

10 B_ION B3 TX2-

7 UAUXP B8 SBU2

8 UAUXN A8 SBU1

1 and/or DisplayPort hubs, with specific functions assigned to each differential signal. DisplayPort mode according to the mode setting. Table 8. Downstream pin connection to USB 3.1 Gen 1/DisplayPort hubs in UFP receptacle application

22 DRX1P SSTX+ SSTX+ ML0+ ML3+ ML0+

21 DRX1N SSTX- SSTX- ML0- ML3- ML0-

18 DTX1N SSRX- SSRX- ML1- ML2- ML1-

17 DTX1P SSRX+ SSRX+ ML1+ ML2+ ML1+

16 DTX2P SSRX+ ML1+ SSRX+ ML1+ ML2+

15 DTX2N SSRX- ML1- SSRX- ML1- ML2-

12 DRX2N SSTX- ML0- SSTX- ML0- ML3-

11 DRX2P SSTX+ ML0+ SSTX+ ML0+ ML3+

14 DAUXP AUX+ AUX+ AUX+ AUX+

13 DAUXN AUX- AUX- AUX- AUX-

7.5 USB Type-C UFP_Dongle application

Figure 5. Connection illustration when PTN36502/PTN36502A in UFP_Dongle application (1): 0.33μF capacitors are recommended on Type-C's receiver pins based on latest USB specification. (2): 0.22μF capacitors are recommended on Type-C's transmitter pins based on latest USB specification. crossbar switch function, and upstream (left) side is connected to Type-C plug.

Table 9. Upstream pin connection to Type-C plug UFP_Dongle application

23 D_ION A10 RX2-

24 D_IOP A11 RX2+

3 C_INP B2 TX2+

4 C_INN B3 TX2-

5 A_INP A2 TX1+

6 A_INN A3 TX1-

9 B_IOP B11 RX1+

10 B_ION B10 RX1-

7 UAUXP A8 SBU1

8 UAUXN B8 SBU2

1 and/or DisplayPort hubs, with specific functions assigned to each differential signal. DisplayPort mode according to the mode setting. typical dongle use case, only one orientation is necessary. Table 10. Downstream pin connection to USB 3.1 Gen 1/DisplayPort hubs in UFP_Dongle application

22 DRX1P SSTX+ ML0+ SSTX+ ML0+ ML3+

21 DRX1N SSTX- ML0- SSTX- ML0- ML3-

18 DTX1N SSRX- ML1- SSRX- ML1- ML2-

17 DTX1P SSRX+ ML1+ SSRX+ ML1+ ML2+

16 DTX2P SSRX+ SSRX+ ML1+ ML2+ ML1+

15 DTX2N SSRX- SSRX- ML1- ML2- ML1-

12 DRX2N SSTX- SSTX- ML0- ML3- ML0-

11 DRX2P SSTX+ SSTX+ ML0+ ML3+ ML0+

7.6 Control and programmability

above. Hi-Z and OPEN/NC are used interchangeably in these figures.

1 Hi-Z I2C Mode

Figure 6. GPIO mode control flow chart Function DFP /UFP/UFP_Dongle configured. Figure 7. GPIO mode control sequence diagram illustration

7.6.1 Operating mode selection (I2C mode or GPIO mode)

Section 7.6.6 for I2C register details. are tri-stated, and mode configuration remains undetermined. Figure 8. EN control flow diagram Table 11. EN control for various mode setting during POR on the DRXn pins for higher level surge protection. 1 0 GPIO Mode – UFP Configuration. 0 0 GPIO Mode – UFP_Dongle Configuration.

1 X X Reserved Operation Mode

7.6.2 Mode configuration through GPIO mode

cleared, and the PTN36502/PTN36502A is placed in deep power saving mode.

• C1/SCL indicates the orientation, 0 = normal orientation, 1 = reversed orientation
• C2/SDA indicates different mode configurations – OPEN=USB 3.1 Gen 1 only, no AUX support – 0 = USB 3.1 Gen 1 + DP 2Lane + AUX – 1 = DP 4Lane + AUX Definitions of different lane TX and RX paths in the tables are illustrated in Figure 9. Lane D RX path Lane D TX path Lane C TX path Lane A TX path Lane B TX path Lane B RX path AUX path aaa-026918 B_ION B_IOP DRX2N DRX2P A_IN A_IP DTX2N DTX2P C_IN C_IP DTX1N DTX1P D_IOP D_ION DRX1P DRX1N UAUXN UAUXP DAUXN DAUXP

Figure 9. Different lane TX and RX paths definitions Table 12. PTN36502/PTN36502A DFP mode configuration

0 OPEN SSTX SSRX [1] [1] Normal

3.1 Gen

1 Only

Table 13. PTN36502/PTN36502A UFP mode configuration

0 OPEN [1] [1] SSRX SSTX Normal

1 OPEN SSRX SSTX [1] [1]

Table 14. PTN36502/PTN36502A UFP_Dongle mode configuration

0 OPEN SSRX SSTX [1] [1] Normal

1 OPEN [1] [1] SSRX SSTX

7.6.3 Mode transitions

functional modes and deep power saving state transitions. places DisplayPort operation in low power state. Figure 10. Mode transition state diagram

as long as EN is set to HIGH. interfacing pins with the host processor interface.

• When C1 = HIGH, the upstream (left) side of the redriver is optimized to drive long channel trace length
• When C1 = OPEN, the upstream (left) side of the redriver is optimized to drive medium channel trace length
• When C1 = LOW, the upstream (left) side of the redriver is optimized to drive short channel trace length

Table 15. Upstream channel configuration using C1 pin (as shown in Figure 3). These pins are the Type-C connector in a DFP system. Table 16. Downstream channel configuration using C2 pin

7.6.5 Channel settings for DisplayPort mode

by C1 value. C2 is not used.

Table 17. DisplayPort channel equalization settings these can also be configured via I2C-bus interface. swing and pre-emphasis will be adjusted; the RX equalization value is not modified.

7.6.6 I2C configurability

by programming the registers through I2C. operation is attempted during normal operation, the device may not behave as specified. settings that are applied to the DP channel training through AUX. Table 18. I2C registers and description

• 0: de-emphasis = 0 dB
• 1: de-emphasis = -3.1 dB
• 2: de-emphasis = -5.3 dB
• 3: Reserved

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018 Register offset Register name Bits POR default value Description 5:4 b\`00 USB mode upstream (left) side link output signal swing

• 0: output swing level = 900mVppd
• 1: output swing level = 1000mVppd
• 2: output swing level = 1100mVppd
• 3: reserved 3:0 b\`0010 USB mode upstream (left) side link Rx Equalization gain
• 0: 0 dB
• 1: 3 dB
• 2: 6 dB
• 3: 9 dB
• 4: 12 dB
• 5-15: reserved 7:6 b\`01 USB mode downstream (right) side link de-emphasis level
• 0: de-emphasis = 0 dB
• 1: de-emphasis = -3.1dB
• 2: de-emphasis = -5.1 dB
• 3: Reserved 5:4 b\`00 USB mode downstream (right) side link output signal swing
• 0: output swing level = 900mVppd
• 1: output swing level = 1000mVppd
• 2: output swing level = 1100mVppd
• 3: reserved 0x05 Read/Write USB_DS_TX/RX_ Control 3:0 b\`0010 USB mode downstream (right) side link Rx Equalization gain
• 0: 0 dB
• 1: 3 dB
• 2: 6 dB
• 3: 9 dB
• 4: 12 dB
• 5-15: reserved 7:5 b\000 Reserved 4 b\0 DisplayPort Power saving mode selection on all DP lanes.
• 0: Normal/Active mode
• 1: D3 Power saving mode 0x06 Read/Write DP link control 3:2 b\`00 DisplayPort operating lane count.
• 0: 0 DP Lane (i.e. USB 3.1 Gen 1 Only)
• 1: 1 DP Lane
• 2: 2 DP lanes
• 3: 4 DP lanes

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018 Register offset Register name Bits POR default value Description 1:0 b\`00 DP Link rate

• 0: 1.62 Gbps (RBR)
• 1: 2.7 Gbps (HBR)
• 2: 5.4 Gbps (HBR2)
• 3: Reserved. 7 b\0 Reserved 6:4 b\000 DP Lane 0 Rx equalization gain control
• 0: 0 dB
• 1: 1.5 dB
• 2: 3 dB
• 3: 4.5 dB
• 4: 6 dB
• 5: 9 dB
• 6: 12dB
• 7: Reserved 3:2 b\`00 DP Lane 0 TX output swing control (When AUX monitor bit in 0x0D byte is disabled)
• 0: 400 mVppd
• 1: 600 mVppd
• 2: 800 mVppd
• 3: 1100mVppd 0x07 Read/Write DP Lane 0 TX/RX Control Register 1:0 b\`00 DP Lane 0 pre-emphasis control (When AUX monitor bit in 0x0D byte is disabled)
• 0: 0 dB
• 1: 3.5 dB
• 2: 6 dB
• 3: 8.8 dB 7 b\0 Reserved 6:4 b\000 DP Lane 1 Rx equalization gain control
• 0: 0 dB
• 1: 1.5 dB
• 2: 3 dB
• 3: 4.5 dB
• 4: 6 dB
• 5: 9 dB
• 6: 12dB
• 7: Reserved 0x08 Read/Write DP Lane 1 TX/RX Control Register 3:2 b\`00 DP Lane 1 TX output swing control (When AUX monitor bit in 0x0D byte is disabled)
• 0: 400 mVppd
• 1: 600 mVppd
• 2: 800 mVppd
• 3: 1100 mVppd

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018 Register offset Register name Bits POR default value Description 1:0 b\`00 DP Lane 1 pre-emphasis control (When AUX monitor bit in 0x0D byte is disabled)

• 0: 0 dB
• 1: 3.5 dB
• 2: 6 dB
• 3: 8.8 dB 7 b\0 Reserved 6:4 b\000 DP Lane 2 Rx equalization gain control
• 0: 0 dB
• 1: 1.5 dB
• 2: 3 dB
• 3: 4.5 dB
• 4: 6 dB
• 5: 9 dB
• 6: 12dB
• 7: Reserved 3:2 b\`00 DP Lane 2 TX output swing control (When AUX monitor bit in 0x0D byte is disabled)
• 0: 400 mVppd
• 1: 600 mVppd
• 2: 800 mVppd
• 3: 1100 mVppd 0x09 Read/Write DP Lane 2 TX/RX Control Register 1:0 b\`00 DP Lane 2 pre-emphasis control (When AUX monitor bit in 0x0D byte is disabled)
• 0: 0 dB
• 1: 3.5 dB
• 2: 6 dB
• 3: 8.8 dB 7 b\0 Reserved0x0A Read/Write DP Lane 3 TX/RX Control Register 6:4 b\000 DP Lane 3 Rx equalization gain control
• 0: 0 dB
• 1: 1.5 dB
• 2: 3 dB
• 3: 4.5 dB
• 4: 6 dB
• 5: 9 dB
• 6: 12 dB
• 7: Reserved

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018 Register offset Register name Bits POR default value Description 3:2 b\`00 DP Lane 3 TX output swing control (When AUX monitor bit in 0x0D byte is disabled)

• 0: 400 mVppd
• 1: 600 mVppd
• 2: 800 mVppd
• 3: 1100 mVppd 1:0 b\`00 DP Lane 3 pre-emphasis control (When AUX monitor bit in 0x0D byte is disabled)
• 0: 0 dB
• 1: 3.5 dB
• 2: 6 dB
• 3: 8.8 dB 7:6 b\`00 DFP or /UFP application mode
• 0: DFP configuration, without external 4.7Ω resistors on the DRXn pins. This setting also applies to UFP_Dongle configuration.
• 1: DFP configuration, with external 4.7Ω resistors on the DRXn pins for higher level surge protection
• 2: UFP configuration.
• 3: Reserved (DFP/UFP application mode must be set once before taking PTN36502/PTN36502A out of deep power saving state. Changing these bits after the operational mode of the device is set to a mode other than deep power saving state is not allowed) 5 b\`0 Plug orientation control. This orientation condition applies to both high speed TX/RX configuration and AUX crossbar switch.
• 0: normal plug orientation of Type-C connection
• 1: reverse plug orientation of Type- C connection 4 b\`0 AUX monitor polarity control.
• 0: Polarity automatically controlled by plug orientation configuration
• 1: reverse polarity with respect to automatically controlled polarity. 0x0B Read/Write Mode control 1 3 b\`0 AUX crossbar switch control
• 0: AUX switch path disabled. (AUX switch is in high-Z state; but AUX monitor is still connected to DAUXP/N pins)
• 1: AUX switch path enabled in DP mode

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018 Register offset Register name Bits POR default value Description 2:0 b\`000 Operational mode of the device. Refer to 7.6.3 for mode transition requirement.

• 0: Deep power saving state
• 1: USB 3.1 Gen 1 only
• 2: USB 3.1 Gen 1 and 2-lane DP
• 3: 4-lane DP
• 4-7: Reserved 7:4 b’0001 Upstream side (left) squelch threshold setting
• 0: 75mVpp
• 1: 80mVpp
• 2: 90mVpp
• 3: 100mVpp
• Other values are reserved 0X0C Read/Write Squelch threshold 3:0 b’0001 Downstream side (right) squelch threshold setting
• 0: 75mVpp
• 1: 80mVpp
• 2: 90mVpp
• 3: 100mVpp
• Other values are reserved 7 b\`1 AUX monitoring function
• 0: Disabled. DisplayPort OS/DE settings are adjusted through GPIO/ I2C registers.
• 1: Enabled. DisplayPort OS/DE settings are adjusted autonomously by monitoring AUX channel traffic. 6:1 b\000000 Reserved 0x0D Read/Write Device control 0 b\0 Device Reset bit. This is a self- clearing bit, and reading this register will always return 0.
• Writing a ‘1’ to this register will soft reset the device including I2C register contents and internal digital logics, while the chip continuing to operating under I2C mode.
• Writing a ‘0’ does not have any effect. 0x0E-0x1F Reserved Reserved for NXP Internal use only; Do not write to these registers 0x20-0xFF Reserved Reserved for NXP Internal use only; Do not write to these registers

7.6.7 I2C read/write operations

PTN36502/PTN36502A has an I2C register interface that enables system integrator to program register settings suitable as per application needs. Table 18 describes possible

and 8-bit device slave address is defined in Table 19. Table 19. Read/write device slave address PTN36502/PTN36502A supports programming of the registers through the I2C interface. Reading/writing the registers must be done according to the following sequences.

• Command phase
• Data phase The command phase is an I2C write to PTN36502/PTN36502A that contains a single data byte. The LS bit indicates if the command that is being executed will read or write data from/to the device. The other 7 bits are the device slave address. The single data byte followed is the register offset that is used to indicate which register address is being accessed (read or written). The data phase is a second I2C transaction that starts with 7- bit slave address, with LS bit set to 1 indicating a read operation, followed by a 8-bit data read back from the device register address. bits 7:0 of the register data aaa-027399 STARTCommand phase 7 bits slave address ACK0 8-bit offset ACK STOP STOP driven by master driven by slave STARTData phase 7 bits slave address ACK1 NACK R/W(1)

Figure 11. I2C read sequence the device register address.

Figure 12. I2C write sequence

8 Limiting values

periods may affect device reliability. Table 20. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). [1] All voltage values, except differential voltages, are with respect to network ground terminal.

9 Recommended operating conditions

Table 21. Recommended operating conditions

10 Characteristics

10.1 Device characteristics

Table 22. Device characteristics receive detection is active. specified operating characteristics.

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018 Symbol Parameter Conditions Min Typ Max Unit Active state (Mode 1 USB 3.1 Gen 1 only) TX Output Swing 1000 mVppd TX De-emphasis is -3.5dB RX Equalization gain 6 dB 115 mA Active state (Mode 2, 2-lane DP and USB 3.1 Gen 1) DP TX Output Swing 600mV DP TX Pre-emphasis 3.5 dB USB TX Output Swing 1000 mVppd USB TX De-emphasis is -3.5 dB RX Equalization gain 6 dB 225 mA Active state (Mode 3, 4-lane DP) TX Output Swing 600 mVppd TX Pre-emphasis is 3.5 dB RX Equalization gain 6 dB 220 mA U2/U3 Power Saving states (USB mode) 1.16 1.70 mA No USB connection state (Rx termination detection active) 0.77 0.96 mA DP 4-lane @ HBR2 level 0 TX output Swing 400 mVppd TX Pre-emphasis is 0 dB RX Equalization is 6 dB AUX and I2C Idle 150 mA DP 2-lane @ HBR2 level 0 TX output Swing 400 mVppd TX Pre-emphasis is 0 dB RX Equalization is 6 dB AUX and I2C Idle 75 mA DP 1-lane @ HBR2 level 0 TX output Swing 400 mVppd TX Pre-emphasis is 0 dB RX Equalization is 6 dB AUX and I2C Idle 38 mA DP 4-lane D3 state, with AUX switch and AUX monitoring enabled 0.5 0.66 mA IDD Supply current Deep Power-saving state 3 µA DDNEXT1 Near end cross talk for adjacent high speed differential pins (between TX and RX signal pairs within the same USB 3.1 Gen 1 port ) @ 2.7 GHz between DTX1 and DRX1; Between DTX2 and DRX2; Between B_IO and A_IN; Between D_IO and C_IN -45 dB

drivers for far end crosstalk analysis. Table 23. USB 3.1 Gen 1 receiver dynamic characteristics

10 MHz to 1250 MHz 14 dB

1250 MHz to 2500 MHz 9 dB

2500 MHz to 3000 MHz 8 dB

3000 MHz to 5400MHz 6 dB

1250 MHz to 2500 MHz 11 dB

2500 MHz to 3000 MHz 11 dB

3000 MHz to 5400MHz 11 dB

10 MHz to 1250 MHz 15 dB

2500 MHz to 3000 MHz 10 dB

3000 MHz to 5400 MHz 7 dB

10 MHz to 1250 MHz 16 dB

1250 MHz to 2500 MHz 13 dB

2500 MHz to 3000 MHz 13 dB

3000 MHz to 5400MHz 12 dB

Table 24. USB 3.1 Gen 1 transmitter dynamic characteristics

3000 MHz to 5400 MHz 11 dB

3000 MHz to 5400 MHz 9 dB

10 MHz to 1250 MHz 17 dB

1250 MHz to 2500 MHz 14 dB

2500 MHz to 3000 MHz 14 dB

3000 MHz to 5400 MHz 14 dB

3000 MHz to 5400 MHz 10 dB

Figure 13. Propagation delay Figure 14. LFPS electrical idle transitions in U0/U1 Figure 15. U2/U3 exit behavior

10.4 USB jitter characteristics

Table 25. USB jitter characteristics

30 FR4 TraceAWG

Figure 16. Jitter measurement setup

10.5 DisplayPort receiver dynamic characteristics

Table 26. DisplayPort receiver dynamic characteristics

10 MHz-1250 MHz 14 dB

1250 MHz-2500 MHz 9 dB

2500 MHz-3000 MHz 8 dB

3000 MHz-5400MHz 6 dB

10 MHz-1250 MHz 15 dBRLCC11,RX Rx Common mode Return

2500 MHz-3000 MHz 10 dB

3000 MHz-5400 MHz 7 dB

10.6 DisplayPort transmitter dynamic characteristics

Table 27. DisplayPort transmitter dynamic characteristics output voltage in active state.

1250 MHz-2500 MHz 11 dB

2500 MHz-3000 MHz 11 dB

3000 MHz-5400 MHz 9 dB

10 MHz-1250 MHz 16 dB

1250 MHz-2500 MHz 14 dB

2500 MHz-3000 MHz 14 dB

3000 MHz-5400 MHz 10 dB

10.7 AUX switch and AUX monitor characteristics

Table 28. AUX switch and AUX monitor characteristics

[1] All S-parameter measurements are with respect to 100 Ω differential impedance reference and 50 Ω single-ended impedance reference.

10.8 Ternary control characteristics

Table 29. Ternary control characteristics

10.9 I2C dynamic characteristics

Table 30. I2C dynamic characteristics otherwise noted). Typical values are specified at 27 °C (unless otherwise noted).

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018 Symbol Parameter Conditions Min Typ Max Unit Vhys Hysteresis of Schmitt trigger inputs Vpullup < 3.6V 0.095 V VOL LOW-level output voltage at 3mA sink current Vpullup < 3.6V 0 0.4 V VOL =0.4V; Standard and Fast modes 3 mA VOL =0.4V; Fast mode plus 20 mA IOL LOW-level output current VOL =0.6V; Fast mode 6 mA IIL LOW-level input current Pin voltage = 0.1* Vpullup to 0.9*Vpullup, max -10 10 μA CI Capacitance of IO pin 10 pF tHD,STA Hold time (repeated) START condition Fast mode plus; After this period, the first clock pulse is generated 0.26 μs tLOW LOW period of I2C clock Fast mode plus 0.5 μs tHIGH HIGH period of I2C clock Fast mode plus 0.26 μs TSU,STA Setup time (repeated) START condition Fast mode plus 0.26 μs THD,DAT Data Hold time Fast mode plus 0 μs TSU,DAT Data Setup time Fast mode plus 50 ns Tr Rise time of I2C_SCL and I2C_SDA signals Fast mode plus - 120 ns Tf Fall time of I2C_SCL and I2C_SDA signals Fast mode plus - 120 ns TSU,STO Setup time for STOP condition Fast mode plus 0.26 μs tBUF Bus free time between STOP and START condition Fast mode plus 0.5 μs tVD,DAT Data valid time Fast mode plus 0.45 μs tVD,ACK Data valid acknowledge time Fast mode plus 0.45 μs tSP Pulse width of spikes that must be suppressed by input filter 0 50 ns Note: Vpullup is external pull up voltage on SCL and SDA pins. The voltage can be up to 3.6V from another power supply.

Figure 17. I2C-bus timing diagram

Table 31. Package summary

Figure 18. Package outline SOT1903-1

Figure 19. Package outline detail G of HX2QFN24 (SOT1903-1)

Figure 20. Package outline note HX2QFN24 (SOT1903-1)

13 Soldering

Figure 21. Reflow soldering footprint for SOT1903-1

Figure 22. Reflow soldering footprint part2 for HX2QFN24 (SOT1903-1)

Figure 23. Reflow soldering footprint part3 for HX2QFN24 (SOT1903-1)

14 Packing information

14.1 Dimensions and quantities

Table 32. Dimensions and quantities [1] d = reel diameter; w = tape width.

14.2 Product orientation

Figure 24. Product orientation in carrier tape

14.3 Carrier tape dimensions

Figure 25. Carrier tape dimensions Table 33. Carrier tape dimensions In accordance with IEC 60286-3.

15 Abbreviations

Table 34. Abbreviations

Table 35. Revision history

• Section 12 and Section 13: added min/max dimensions, no change to device
• Minor text edits
• Updated Figure 3, Figure 4, and Figure 5 PTN36502 v.1.0 20180316 Product data sheet - -

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018

17 Legal information

17.1 Data sheet status

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

17.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018 No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non- automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018 Tables Tab. 4. Allowed output swing and pre-emphasis Tab. 5. Downstream pin connection to Type-C Tab. 6. Upstream pin connection to application Tab. 7. Upstream pin connection to Type-C Tab. 8. Downstream pin connection to USB 3.1 Gen 1/DisplayPort hubs in UFP receptacle Tab. 9. Upstream pin connection to Type-C plug Tab. 10. Downstream pin connection to USB 3.1 Gen 1/DisplayPort hubs in UFP_Dongle Tab. 11. EN control for various mode setting during Tab. 12. PTN36502/PTN36502A DFP mode Tab. 13. PTN36502/PTN36502A UFP mode Tab. 14. PTN36502/PTN36502A UFP_Dongle mode Tab. 15. Upstream channel configuration using C1 Tab. 16. Downstream channel configuration using C2 Tab. 23. USB 3.1 Gen 1 receiver dynamic Tab. 24. USB 3.1 Gen 1 transmitter dynamic Tab. 26. DisplayPort receiver dynamic Tab. 27. DisplayPort transmitter dynamic

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Product data sheet Rev. 3 — 28 September 2018 Figures Fig. 2. PTN36502/PTN36502A pinning Fig. 3. Connection illustration when PTN36502/ Fig. 4. Connection illustration when PTN36502/ Fig. 5. Connection illustration when PTN36502/ Fig. 7. GPIO mode control sequence diagram Fig. 14. LFPS electrical idle transitions in U0/U1 Fig. 19. Package outline detail G of HX2QFN24 Fig. 20. Package outline note HX2QFN24 Fig. 22. Reflow soldering footprint part2 for Fig. 23. Reflow soldering footprint part3 for

NXP Semiconductors PTN36502/PTN36502A Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2018. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 September 2018 Document identifier: PTN36502_PTN36502A

Contents

7.6.1 Operating mode selection (I2C mode or

10.2 USB 3.1 Gen 1 receiver dynamic 10.3 USB 3.1 Gen 1 transmitter dynamic 10.5 DisplayPort receiver dynamic characteristics ...38

10.6 DisplayPort transmitter dynamic

10.7 AUX switch and AUX monitor characteristics ...40