PTN3355 NXP-Semiconductors | Alldatasheet
Document overview
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Technical content
- General description PTN3355 is a DisplayPort to VGA adapter with an integrated 1 : 2 VGA switch optimized primarily for motherboard applications, to convert a DisplayPort signal from the chip set to an analog video signal that directly connects to the VGA connector. PTN3355 integrates a DisplayPort receiver, a high-speed triple video digital-to-analog converter and 1 : 2 VGA switch that supports a wide range of display resolutions, for example, VGA to WUXGA (see Table 9). PTN3355 supports either one or two DisplayPort lanes operating at either 2.7 Gbit/s or 1.62 Gbit/s per lane. PTN3355 supports I2C-bus over AUX per DisplayPort standard (Ref. 1), and bridges the VESA DDC channel to the DisplayPort Interface. PTN3355 is powered from a 3.3 V power supply and consumes approximately 200 mW of power for video streaming in WUXGA resolution and 410 W of power in Low-power mode. The VGA output is powered down when there is no valid DisplayPort source data being transmitted. PTN3355 also aids in monitor detection by performing load sensing on RGB lines and reporting sink connection status to the source. 2. Features and benefits
2.1 VESA-compliant DisplayPort converter
Main Link: 1-lane and 2-lane modes supported HBR (High Bit Rate) at 2.7 Gbit/s per lane RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane BER (Bit Error Rate) better than 109 DisplayPort Link down-spreading supported 1 MHz AUX channel Supports native AUX CH syntax Supports I2C-bus over AUX CH syntax Active HIGH Hot Plug Detect (HPD) signal to the source
2.2 VESA-compliant eDP extensions
Supports Alternate Scrambler Seed Reset (ASSR) Supports Alternate Enhanced Framing mode - Enhanced Framing PTN3355 Low power DisplayPort to VGA adapter with integrated 1 : 2 VGA switch Rev. 3.1 — 4 November 2016 Product data sheet
Product data sheet Rev. 3.1 — 4 November 2016 2 of 37 NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch
2.3 DDC channel output
I2C-Over-AUX feature facilitates support of MCCS, DDC/CI, and DDC protocols (see Ref. 2)
2.4 Analog video output
VSIS 1.2 compliance (Ref. 3) for supported video output modes Analog RGB current-source outputs 3.3 V VSYNC and HSYNC outputs Pixel clock up to 240 MHz Triple 8-bit Digital-to-Analog Converter (DAC) Direct drive of double terminated 75 load with standard 700 mV (peak-to-peak) signals Integrated 1 : 2 VGA switch
2.5 General features
Supports firmware upgradability through ‘Flash-over-AUX’ scheme for Windows Supports firmware upgradability through I2C-bus interface Monitor presence detection through load detection scheme. Connection/disconnection reported via HPD IRQ and DPCD update. Wide set of display resolutions are supported1: 1920 1440, 60 Hz, 18 bpp, 234 MHz pixel clock rate 2048 1152, 60 Hz (reduced blanking), 24 bpp, 162 MHz pixel clock rate 2048 1536, 50 Hz (reduced blanking), 24 bpp, 167.2 MHz pixel clock rate WUXGA: 1920 1200, 60 Hz, 18 bpp, 193 MHz pixel clock rate WUXGA: 1920 1200, 60 Hz (reduced blanking), 24 bpp, 154 MHz pixel clock rate UXGA: 1600 1200, 60 Hz, 162 MHz pixel clock rate SXGA: 1280 1024, 60 Hz, 108 MHz pixel clock rate XGA: 1024 768, 60 Hz, 65 MHz pixel clock rate SVGA: 800 600, 60 Hz, 40 MHz pixel clock rate VGA: 640 480, 60 Hz, 25 MHz pixel clock rate Any resolution and refresh rates are supported from 25 MHz up to 180 MHz pixel clock rate at 24 bpp, or up to 240 MHz pixel clock rate at 18 bpp Bits per color (bpc) supported1 6, 8 bits supported 10, 12, 16 bits supported by truncation to 8 MSBs All VGA colorimetry formats (RGB) supported Power modes (when the application design is as per Figure 4) Active-mode power consumption: ~200 mW at WUXGA, 1920 1200, 60 Hz (18 bpc) 410 W at Low-power mode Supports slave I2C-bus interface for host debugging and configuration 1. Except for color depth beyond 8 bits, display resolutions and refresh rates are only limited to those which a standard 2-lane DisplayPort configuration is able to support over 2.7 Gbit/s per lane of DP Main Link.
[1] PTN3355BS uses latest firmware version. [2] PTN3355BS/FX uses specific firmware version (‘X’ = 1, 2, 3, etc., and changes according to firmware version).
4.1 Ordering options
[1] PTN3355BS uses latest firmware version. [2] PTN3355BS/FX uses specific firmware version (‘X’ = 1, 2, 3, etc., and changes according to firmware version). Table 1. Ordering information Table 2. Ordering options
4000 T amb =0 Ct o+ 8 5C
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data sheet Rev. 3.1 — 4 November 2016 4 of 37 NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch 5. Functional diagram Fig 1. Functional diagram 002aag883 DIFF RCV CDR, S2P RX PHY ANALOG SUBSYSTEM DIFF RCV CDR, S2P RCV PTN3355 DRV MANCHESTER CODEC RX DIGITAL SUBSYSTEM 10b/8b DE-SCRAM INTERFACE DE-SKEWING 10b/8b DE-SCRAM RX PHY DIGITAL AUX COMMAND LEVEL MODULE DPCD REGISTERS I2C-BUS MASTER NVM MCU CONTROL TIME CONV. ISOCHRONOUS LINK TIMING RECOVERY MAIN STREAM DAC DAC DAC R[7:0] G[7:0] B[7:0] VGA OUTPUT WITH 1 : 2 VGA SWITCH H, V sync VIDEO DAC SUBSYSTEM RED1 GRN1 BLU1 HSYNC1 VSYNC1 DDC1_SCL DDC1_SDA Vbias Vbias Vbias MONITOR PRESENCE DETECTML0_P, ML0_N ML1_P, ML1_N AUX_P, AUX_N channel 1 DOCK_IN, CFG3, CFG5, TESTMODE RED2 GRN2 BLU2 HSYNC2 VSYNC2 channel 2 DDC2_SCL DDC2_SDA HPD CFG1_SCL, CFG2_SDAOSC_OUT RST_NOSC_IN RSET
6.1 Pinning
6.2 Pin description
Table 3. Pin description
the PCB in the thermal pad region. Table 3. Pin description …continued
Product data sheet Rev. 3.1 — 4 November 2016 7 of 37 NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch 7. Functional description Referring to Figure 1 “Functional diagram”, the PTN3355 performs protocol conversion from VESA DisplayPort specification to VESA VGA output. At the physical layer, PTN3355 implements the advanced DisplayPort Front-end technology (Auto receive equalization, Clock Data Recovery) to support the objectives of delivering excellent Signal Integrity (SI) performance, and consuming very low power consumption. The PTN3355 integrates a DisplayPort receiver (according to VESA DisplayPort standard, Ref. 1) and a high-speed triple 8-bit video digital-to-analog converter that supports a wide range of video resolutions (see Table 9 “Display resolution and pixel clock rate[1]”), up to a pixel clock rate of 240 MHz. The PTN3355 supports one or two DisplayPort Main Link lanes operating at either in 2.7 Gbit/s or 1.62 Gbit/s per lane. PTN3355 also integrates a 1 : 2 VGA switch that enables driving VGA signals either to main board connector or docking connector. This feature helps realize BOM saving due to removal of discrete VGA switch component. PTN3355 comprises the following functional blocks:
- DP Main Link
- DP AUX CH (Auxiliary Channel)
- DPCD (DisplayPort Configuration Data)
- VGA monitor detection
- Video DAC
- 1 : 2 VGA switch The RGB video data with corresponding synchronization references are extracted from the main stream video data. Main stream video attribute information is also extracted. This information is inserted once per video frame during the vertical blanking period by the DP source. The attributes describe the main video stream format in terms of geometry, timing, and color format. The original video clock and video stream are derived from these main link data. The PTN3355 internal DPCD registers can be accessed by the DP source via the DP AUX channel. The monitor’s DDC control bus may also be controlled via the DP AUX channel. PTN3355 implements the standard DisplayPort I 2C-over-AUX protocol conversion to provide DP source access to the VGA plug DDC-I2C interface. The PTN3355 passes through sink-side status change (for example, hot-plug events) to the source side, through HPD interrupts and DPCD registers. PTN3355 integrates a 1 : 2 VGA switch that selects between the two channels, depending on DOCK_IN setting.
7.1 DisplayPort Main Link
The DisplayPort main link consists of two AC-coupled differential pairs. The 50 termination resistors are integrated inside PTN3355. The PTN3355 supports HBR at 2.7 Gbit/s and RBR at 1.62 Gbit/s per lane.
7.2 DisplayPort auxiliary channel (AUX CH)
The AUX CH is a half-duplex, bidirectional channel between DisplayPort source and sink. DisplayPort source AUX CH requester (or master). HIGH-to-LOW transition, in the middle of the bit time.
7.3 DPCD registers
Ref. 1. The following describes the specific implementation by PTN3355 only. controls are also made available to initialize and maintain the DisplayPort Link.
7.3.1 PTN3355 specific DPCD register settings
Table 4. PTN3355 specific DPCD registers 0000Dh eDP_CONFIGURATION_CAP. Bit 0 = ALTERNATE_SCRAMBLER_RESET_CAPABLE. source of ENHANCED_FRAME_EN. Bit 2 = reserved for eDP. Read 0. starting at address 00700h are enabled. Bits 7:4 = reserved for eDP. Read all zeros.
[1] Byte fields that are not explicit ly listed are by definition reserved (‘RES’) and their default value is 0h. [2] Example only. Firmware number changes as firmware updated. Remark: If necessary, the DDC bus speed control can be done via I2C-bus interface. For any requirement to change DDC bus speed, contact NXP . supported. Writes are ignored and reads would get zeros. 0010Ah Bit 0 = ALTERNATE_SCRAMBLER_RESET_ENABLE. Source sets to 1 to select the alternate scrambler reset. ALTERNATE_SCRAMBLER_RESET_CAPABLE = 0. Bits 6:2 = reserved. Read all zeros. Branch vendor 24-bit IEEE OUI. Table 4. PTN3355 specific DPCD registers …continued
Product data sheet Rev. 3.1 — 4 November 2016 10 of 37 NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch
7.4 VGA monitor detection
The PTN3355 implements a robust scheme for VGA monitor detection. It senses presence or absence of VGA monitor load termination (75 ) by pulsing the RGB lines. The load sensing operation is performed periodically to determine the latest VGA connectivity status. If the VGA monitor is disconnected, then the detection logic informs the host platform via IRQ_HPD signal.
7.5 EDID handling
Figure 3 shows a DisplayPort-to-analog video converter between the DisplayPort source and a VGA monitor. The PTN3355 implements a DP I2C-Over-AUX protocol, providing for DP source access to the monitor’s DDC bus. With this, the monitor’s EDID data is made available to DP source for access at any time. It is the responsibility of the source to choose only video modes which are declared in the EDID and to adjust the DisplayPort link capabilities (link rate and lane count) to provide the necessary video bandwidth. The PTN3355 does not cache or modify the EDID to match the capabilities of the DisplayPort link data. If the DisplayPort source drives display modes that are not specified in the EDID mode list, the PTN3355 does not detect such conditions, and it depends entirely on the VGA display on what is being displayed.
7.6 Triple 8-bit video DACs and VGA outputs
The triple 8-bit video DACs output a 700 mV (peak-to-peak) analog video output signal into 37.5 load, as is the case of a doubly terminated 75 cable. The DAC is capable of supporting the maximum pixel rate supported by a two-lane DP link (240 MHz).
7.6.1 DAC reference resistor
An external reference resistor must be connected between pin RSET and ground. This resistor sets the reference current which determines the analog output level, and is specified as 1.2 k with a 1 % tolerance. This value allows a 0.7 V (peak-to-peak) output into a 37.5 load (for example, double-terminated 75 coaxial cable). Fig 3. DisplayPort to VGA adapter IC sits between the DisplayPort source and a VGA monitor with EDID DP Tx 002aaf640 embedded DisplayPort source device DP Rx with DPCD VIDEO DAC DisplayPort to VGA adapter IC box-to-box legacy VGA DISPLAY WITH EDID sink device
debug or application purpose.
- The HPD signal is driven LOW, to indicate to the DisplayPort source that the PTN3355 is not ready for AUX channel communication. Once the device is initialized, the HPD level is produced based on CFG1_SCL/CFG2_SDA setting
- The RGB outputs are disabled
- The VSYNC and HSYNC outputs are maintained LOW as long as there is no active video streaming from the DisplayPort source. 9. Configurability and programmability The PTN3355 delivers flexibility for application usage by providing configurability via two options:
- Configuration pins CFG1_SCL, CFG2_SDA, CFG5, DOCK_IN and TESTMODE
- DP-AUX vendor-specific configuration registers The pins provide limited application board level configurability, whereas vendor-specific configuration registers deliver ultimate flexibility. The configuration pin changes (static, dynamic) are reflected in the IC behavior. The configuration pin definitions are as follows:
- CFG1_SCL, CFG2_SDA are used for either host I2C communication or as dedicated configuration pins with binary leveled I/O. PTN3355 is flexible to accept either. The use of these configuration pins is defined in Table 8.
- Configuration pin CFG5 selects OSC_IN clock frequency setting. Table 5 captures the pin definition. Table 6 captures DOCK_IN pin definition.
Table 5. CFG5 pin definition Table 6. DOCK_IN pin definitions
during I2C data transport and receives data properly. registers can be accessed by GPU/CPU software driver via DP AUX channel or I2C-bus.
- Application design-in information
design information, contact NXP team. Table 7. TESTMODE pin definition HIGH JTAG functionality is selected. Table 8. CFG1_SCL/CFG2_SDA pin definitions
00 Compliant HPD behavior
01 Most interoperable (non -compliant) HPD behavior
10 Most interoperable (non -compliant) HPD behavior
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 3.1 — 4 November 2016 13 of 37 NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch Parts shown with shading are extra components required in DC-to-DC converter mode to achieve low power performance. Fig 4. Application with DC-to-DC converter mode 002aah568 PTN3355 VDDE33_IO ML1_P ML1_N DDC_SDA1 VDDA15_DP DDC_SCL2 ML0_N VSYNC1 ML0_P HSYNC1 VDDE33_IO BLU1 AUX_N BLU2 AUX_P GRN1 DOCK_IN GRN2 VDDA33_DNW RSET RST_N DDC_SDA2 HPD CFG1_SCL CFG5 CFG3 CFG2_SDA VSYNC2 HSYNC2 DDC_SCL1 PGND SWOUT PVDD33 TESTMODE VDDD15 VDDA15_DAC OSC_OUT OSC_IN RED2 RED1 10 21 92 2 82 3 72 4 62 5 52 6 42 7 32 8 22 9 13 0 open: I2C address = C0h RED HPD DIE PAD ML1_P ML1_N ML0_N ML0_P AUX_N AUX_P 0.01 μF VBUCK_1V5 0.1 μF VDD_3V3 0.1 μF VDD_3V3 DDC_SCL 0.1 μF VDD_3V3 DDC_SDA VSYNC_VGA HSYNC_VGA BLU GRN 1.2 kΩ ± 1 % 0.1 μF
27 MHz
0.1 μF VDD_3V3 4.7 μH 4.7 μF VBUCK_1V5 1 μF (optional) 0.1 μF2.2 μF VDD_3V3+3.3 V FB CFG1, CFG2: 11, default 00, if MS bus is not used 10 kΩ 10 kΩ 10 kΩ 36 Ω 36 Ω 0.1 μF 0.1 μF ML0_N ML0_P 0.1 μF 0.1 μF ML1_N ML1_P 0.1 μF 0.1 μF AUX_N AUX_P 100 kΩ HPD CPU/GPU +3.3 VVDD_5V (optional)MS_SDA_CFG2 MS_SCL_CFG1 Assume SM_BUS has pull-up on system side. Resonator (with built-in capacitors) MS_SDA_CFG2 MS_SCL_CFG1 CFG5_XTAL CFG5 open: 27 MHz XTAL is used CFG3 CFG3 open: not used PESD5V0U2BT (optional) 10 pF 10 pF 2 kΩ 2 kΩ DDC1_PU BAT54 VDD_5V Option design: ESD protection circuitry RED_RTN NC1 RED GREEN_RTN SDA GREEN BLU_RTN HS BLUE +5V VS NC2 GND1 SCL GND2 GND3 GND4 VGA_CONN VDD_CONN_5V RED_VGA DDC_SDA GRN_VGA HSYNC_VGA BLU_VGA VSYNC_VGA DDC_SCL BAT54 VDD_5V PESD5V0U2BT (optional) PESD5V0U2BT (optional) 22 Ω; 300 mA 22 Ω; 300 mA 22 Ω; 300 mA PI filter design is customer specific RED_VGA DNL 3.3 pF GRN_VGA BLU_VGA 3.3 pF DNL 3.3 pF 3.3 pF DNL 3.3 pF 3.3 pF75 Ω 75 Ω 75 Ω RED GRN BLU Header 4 (no load) I2C BIRD PIN OUT Option design MS_I2C MS_SCL_CFG1 MS_SDA_CFG2 74LVC2T45GN VCCA GND VCCB DIR 0.1 μF HS_5V VS_5V 10 kΩ VDD_3V3 VDD_5VVDD_3V3 0.1 μF HSYNC_VGA VSYNC_VGA Option design: Install to support 5 V H/V for legacy projector and CRTs. Place 100 nF capacitor as close as possible to pin 38 and pin 40 without vias at same side as PTN3355. FB FB FB
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 3.1 — 4 November 2016 14 of 37 NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch Fig 5. Application with LDO mode aaa-010214 PTN3355 VDDE33_IO ML1_P ML1_N DDC_SDA1 VDDA15_DP DDC_SCL2 ML0_N VSYNC1 ML0_P HSYNC1 VDDE33_IO BLU1 AUX_N BLU2 AUX_P GRN1 DOCK_IN GRN2 VDDA33_DNW RSET RST_N DDC_SDA2 HPD CFG1_SCL CFG5 CFG3 CFG2_SDA VSYNC2 HSYNC2 DDC_SCL1 PGND SWOUT PVDD33 TESTMODE VDDD15 VDDA15_DAC OSC_OUT OSC_IN RED2 RED1 10 21 92 2 82 3 72 4 62 5 52 6 42 7 32 8 22 9 13 0 RED HPD DIE PAD ML1_P ML1_N ML0_N ML0_P 0.1 μF 0.1 μF VDD_3V3 0.1 μF VDD_3V3 DDC_SCL 0.1 μF VDD_3V3 DDC_SDA VSYNC_VGA HSYNC_VGA BLU GRN 1.2 kΩ ± 1 % 0.1 μF resonator (with built-in capacitors) 0.1 μFVDD_3V3 0.1 μF 0.1 μF ML0_N ML0_P 0.1 μF 0.1 μF ML1_N ML1_P 0.1 μF 0.1 μF AUX_N AUX_P HPD CPU/GPU VDD_3V3 CFG1, CFG2: 11, default 00, if MS bus is not used VDD_5V 36 Ω 36 Ω AUX_N AUX_P MS_SDA_CFG2 MS_SCL_CFG1 CFG5_XTAL CFG3 2.2 kΩ 2.2 kΩ VDD_5V C59 Assume SMBus has pull-up on system side. C21 C60 C61 C10 C11 MS_SCL_CFG1 MS_SDA_CFG2 CFG3 MS_SCL_CFG1 MS_SDA_CFG2 CFG5_XTAL TESTMODE DOCK_IN TESTMODE open: I2C address = C0h CFG5 open: 27 MHz XTAL is used CFG3 open: not used RED_RTN NC1 RED GREEN_RTN SDA GREEN BLU_RTN HS BLUE +5V VS NC2 GND1 SCL GND2 GND3 GND4 VGA_CONN VDD_5V RED DDC_SDA GRN HSYNC_VGA BLU VSYNC_VGA DDC_SCL RED GRN BLU 75 Ω 75 Ω 75 Ω PI filter design is customer specific VDDD15 VDD_3V3 2.2 μF 4.7 μF
10.1 Display resolution
Table 9 lists some example display resolutions and clock rates that PTN3355 supports. [1] Contact NXP team for other monitor timings not listed in this table.
- 240 MHz at 6 bpc
- 180 MHz at 8 bpc
Table 9. Display resolution and pixel clock rate [1]
Product data sheet Rev. 3.1 — 4 November 2016 16 of 37 NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch
10.2 Power supply filter
Sufficient decoupling capacitance to ground should be connected from each VDD pin directly to ground to filter supply noise.
10.3 DAC terminations
Typically, the VGA RGB outputs are (doubly) terminated. Figure 6 shows an example VGA application. A 75 termination is used to terminate inside the motherboard, and another 75 termination is typically used inside the RGB monitor. The load sensing mechanism assumes this double termination. Figure 7 is another example of VGA application with 50 PCB trace impedance with 150 terminations. In general, it is left to the system integrator to decide on their specific implementation. Fig 6. PTN3355 DAC termination example 1 Fig 7. PTN3355 DAC termination example 2 002aah582 DAC RED, GRN, BLU GND MOTHERBOARD PCB EMI filter 75 Ω 75 Ω cable MONITOR 75 Ω 37.5 Ω PCB traces 75 Ω PCB traces close to VGA connector aaa-010215 DAC RED, GRN, BLU GND MOTHERBOARD PCB EMI filter 150 Ω 75 Ω cable MONITOR 75 Ω 37.5 Ω PCB traces 50 Ω PCB traces 150 Ω 75 Ω PCB traces close to PTN3355 close to VGA connector
10.4 Timing reference
PTN3355 requires a crystal or ceramic resonator for a stable VGA clock timing reference. integrated capacitors and therefore a small PCB area and potentially lower cost. Table 10. Required crystal specifications (SMD components)
State Technology Association, Arlington, VA, USA. testing, Charged Device Model - Component level; JEDEC Solid State Technology Association, Arlington, VA, USA.
- Recommended operating conditions
Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 12. Operating conditions
13.1 Current consumption, power dissipation and thermal characteristics
(non-compliant) HPD mode (that is, CFG1_SCL/CFG2_SDA is ‘01’ or ‘10’). Table 13. Current consumption, power dissipation and thermal characteristics Over operating free-air temperature range, unless otherwise noted. Table 14. Device characteristics Over operating free-air temperature range, unless otherwise noted.
13.2 DisplayPort receiver main link
[1] Ref. 1 supersedes in case of any mismatch of specification items. [2] Up to 0.5 % down spread is supported. Modulation frequency range of 30 kHz to 33 kHz must be supported. [3] Informative; refer to Figure 8 for definition of differential voltage. [4] Common mode voltage is equal to V bias_RX voltage. [5] Total drive current of the input bias circuit when it is shorted to its ground. Table 15. DisplayPort receiver main link characteristics [1] Over operating free-air temperature range, unless otherwise noted.
13.3 DisplayPort receiver AUX CH
[1] Ref. 1 supersedes in case of any mismatch of specification items. [2] Results in the bit rate of 1 Mbit/s including the overhead of Manchester II coding. transmitting device is a source device for a request transaction and a sink device for a reply transaction. transmitting device is a source device for a request transaction and a sink device for a reply transaction. [5] V AUX_DIFFp-p = 2 VAUX+ VAUX. [6] Common-mode voltage is equal to V bias_TX (or Vbias_RX) voltage. [7] Steady-state common-mode voltage shift between transmit and receive modes of operation. [8] Total drive current of the transmitter when it is shorted to its ground. [9] The AUX CH AC coupling capacitor placed both on the DisplayPort source and sink devices. Table 16. DisplayPort receiver AUX CH characteristics [1] Over operating free-air temperature range, unless otherwise noted.
13.4 HPD characteristics
[1] Ref. 1 supersedes in case of any mismatch of specification items.
13.5 DDC/I 2C characteristics
[1] V CC is the pull-up voltage for DDC/I2C. [2] Table 18 applies to CFG1_SCL and CFG2_SDA pins as they operate as I2C-bus I/O. Table 17. HPD characteristics [1] Over operating free-air temperature range, unless otherwise noted. Table 18. DDC/I 2C characteristics VCC = 4.5 V to 5.5 V[1]. Over operating free-air temperature range, unless otherwise noted.
13.6 DAC
13.7 HSYNC, VSYNC characteristics
[1] The parameter values specified are simulated and absolute values.
13.8 Configuration pins CF G5, DOCK_IN, TESTMODE
Table 19. DAC characteristics Over operating free-air temperature range, unless otherwise noted. Table 20. HSYNC and VSYNC characteristics Over operating free-air temperature range, unless otherwise noted. Table 21. Configuration pins characteristics Over operating free-air temperature range, unless otherwise noted.
13.9 RST_N
Table 22. RST_N characteristics Over operating free-air temperature range, unless otherwise noted.
Product data sheet Rev. 3.1 — 4 November 2016 25 of 37 NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch 14. Package outline Fig 9. Package outline SOT618-1 (HVQFN40) ReferencesOutline version European projection Issue date IEC JEDEC JEITA SOT618-1 MO-220 sot618-1_po 02-10-22 13-11-05 Unit mm max nom min 0.4 A(1) Dimensions (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm SOT618-1 A1 b 0.30 cD (1) Dh E(1) Eh 4.10 ee 1 e2 Lvw 0.05 y 0.05 0.1 e e 1/2 e 1/2 e y terminal 1 index area A A1 c L Eh Dh b 11 20 40 31 2110 D E terminal 1 index area 0 2.5 5 mm scale A C C Bv w Cy1 C X detail X B A
15.1 Packing method
[1] d = reel diameter; w = tape width. Table 23. Dimensions and quantities
15.2 Product orientation
15.3 Carrier tape dimensions
Table 24. Carrier tape dimensions In accordance with IEC 60286-3.
15.4 Reel dimensions
Table 25. Reel dimensions In accordance with IEC 60286-3.
15.5 Barcode label
- Soldering of SMD packages
16.1 Introduction to soldering
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
- Through-hole components
- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Fig 14. Box and reel information barcode
Table 26. Barcode dimensions
due to an increased probability of bridging. packages with solder balls, and leadless packages are all reflow solderable.
- Board specifications, including the board finish, solder masks and vias
- Package footprints, including solder thieves and orientation
- The moisture sensitivity level of the packages
- Package placement
- Inspection and repair
- Lead-free soldering versus SnPb soldering
16.3 Wave soldering
- Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
- Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
- Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 15) than a SnPb process, thus reducing the process window
- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
- Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 27 and 28
Table 27. SnPb eutectic process (from J-STD-020D)
“Surface mount reflow soldering description”. Table 28. Lead-free process (from J-STD-020D)
Product data sheet Rev. 3.1 — 4 November 2016 32 of 37 NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch 17. Soldering: PCB footprints Fig 16. PCB footprint for SOT618-1 (HVQFN40); reflow soldering SOT618-1Footprint information for reflow soldering of HVQFN40 package sot618-1_fr occupied area solder paste solder resist solder lands Dimensions in mm Ay Bx D SLx SLy SPy totP 7.000 5.200 By 5.200 0.900 0.290 C 4.100 4.100 2.400 SPx tot 2.400 SPx 0.600 SPy 0.600 Gx 6.300 Gy 6.300 Hx 7.250 Hy 7.2500.500 Ax 7.000 nSPx nSPy Issue date 09-06-11 14-08-13 Ax Bx SLx Gx GyHy Hx AyBy SLy P 0.025 0.025D (0.105) SPx tot SPy tot nSPx nSPy SPx SPy C Generic footprint pattern Refer to the package outline drawing for actual layout
Table 29. Abbreviations
Table 29. Abbreviations …continued Table 30. Revision history
- Section 7: Deleted last sentence in last paragraph referencing programming document; there is no programming document. PTN3355 v.3 20140714 Product data sheet - PTN3355 v.2 Modifications: • Updated Figure 4 PTN3355 v.2 20140703 Product data sheet - PTN3355 v.1 PTN3355 v.1 20140310 Product data sheet - -
Product data sheet Rev. 3.1 — 4 November 2016 35 of 37 NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch 21. Legal information
21.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
Product data sheet Rev. 3.1 — 4 November 2016 36 of 37 NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 22. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch © NXP Semiconductors N.V. 2016. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 November 2016 Document identifier: PTN3355 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 23. Contents 7.6 Triple 8-bit video DACs and VGA outputs . . . 10