PTMUX9612RUMR

TMUX9612 TI | Alldatasheet

Document overview

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Technical content

TMUX9612 220V, Flat Ron, 1:1 (SPST), 4-Channel Switches with Latch-Up Immunity and 1.8V Logic

1 Features

High supply voltage capable: – Dual supply: ±10V to ±110V – Single supply: 10V to 140V – Asymmetric dual supply operation: between +90V / –130V and 140V / -80V
Consistent parametric across supply voltages
Latch-up immune
High continuous current: 200mA
Low input leakage: 80pA at 25°C
Low charge injection: –20pC
Low off isolation & crosstalk: < –100dB
Low On-Resistance flatness: 0.435Ω
Low On-Resistance: 14Ω
Low off-capacitance: 5pF
Removes need for additional logic rail (VL)
1.8-V Logic capable
Fail-safe logic: up to 48 V independent of supply
Integrated Pull-Down resistor on logic pins
Bidirectional signal path
Wide operating temperature TA: –40°C to 125°C
Industry-standard, small WQFN package

2 Applications

High voltage bidirectional switching
Analog and digital signal switching
Semiconductor test equipment
LCD test equipment
Battery test equipment
Data acquisition systems (DAQ)
Digital multi-meter (DMM)
Factory automation and control
Programmable logic controllers (PLC)
Analog input modules

3 Description

The TMUX9612 is a modern high voltage capable analog switch with Latch-Up immunity. Each device has four independently controllable 1:1, single-pole single-throw (SPST) switch channels. The device works well with dual supplies, a single supply, or asymmetric supplies up to a maximum supply voltage of 220V. The TMUX9612 device provides consistent analog parametric performance across the entire supply voltage range. The device also supports bidirectional analog and digital signals on the source (Sx) and drain (Dx) pins. All logic inputs support logic levels of 1.8V, 3.3V, and 5V and can be connected as high as 48V, allowing for system flexibility with control signal voltage. Fail-safe logic circuitry allows voltages on the logic pins to be applied before the supply pin, protecting the device from potential damage. The device provides Latch-Up immunity, preventing undesirable high current events between parasitic structures within the device. A Latch-Up condition typically continues until the power supply rails are turned off and can lead to device failure. The Latch- Up immunity feature allows this family of multiplexers to be used in harsh environments.

Package Information

PART NUMBER(2) PACKAGE(1) BODY SIZE (NOM) TMUX9612 RUM (WQFN, 16) 4.00mm × 4.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) See the Device Comparison Table. TMUX9612 SEL1 SEL2 SEL3 SEL4 ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT Functional Block Diagram ADVANCE INFORMATION TMUX9612 SCDS473 – JULY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

6.3 Recommended Operating Conditions:

6.6 Electrical Characteristics (Global): TMUX961x

10.2 Receiving Notification of Documentation Updates..25

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4 Device Comparison Table

TMUX9612 High Voltage, 4-channel, 1:1 (SPST) switches, (Logic High) www.ti.com TMUX9612 SCDS473 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 ADVANCE INFORMATION

5 Pin Configuration and Functions

Figure 5-1. RUM Package, 16-Pin WQFN (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME WQFN D1 16 I/O Drain pin 1. Can be an input or output. D2 13 I/O Drain pin 2. Can be an input or output. D3 8 I/O Drain pin 3. Can be an input or output. D4 5 I/O Drain pin 4. Can be an input or output. GND 3 P Ground (0 V) reference S1 15 I/O Source pin 1. Can be an input or output. S2 14 I/O Source pin 2. Can be an input or output. S3 7 I/O Source pin 3. Can be an input or output. S4 6 I/O Source pin 4. Can be an input or output. SEL1 2 I Logic control input 1. SEL2 12 I Logic control input 2. SEL3 11 I Logic control input 3. SEL4 4 I Logic control input 4. VOUT 10 P Internally generated voltage output rail. For reliable operation, connect a decoupling capacitor ranging from 0.01µF to 0.1µF between VOUT and GND on pin 10 or on the thermal pad. Having the decoupling capacitor as close to the thermal pad as possible yeilds the best performance. VDD 9 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 1µF to 10µF between VDD and GND. VSS 1 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 1µF to 10µF between VSS and GND. Thermal Pad (VOUT) P The thermal pad is internally connected to VOUT (same node as pin 10). VOUT is an internally generated voltage output rail. For reliable operation, connect a decoupling capacitor ranging from 0.01µF to 0.1µF between VOUT and GND on pin 10 or on the thermal pad. Having the decoupling capacitor as close to the thermal pad as possible yeilds the best performance. (1) I = input, O = output, I/O = input and output, P = power TMUX9612 SCDS473 – JULY 2025 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings: TMUX961x Devices

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD–VSS Supply voltage 240 V VDD –0.5 240 V VSS –135 0.5 V VSELx Logic control input pin voltage (SELx) –0.5 50 V ISELx Logic control input pin current (SELx) –30 30 mA VS or VD Source or drain voltage (Sx, Dx) VSS–2 VDD+2 V IDC Source or drain continuous current (Sx, Dx) –200 200 mA IIK (2) Diode clamp current at 85°C –100 100 mA Diode clamp current at 125°C –15 15 mA Tstg Storage temperature –65 150 °C TA Ambient temperature –55 150 °C TJ Junction temperature 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Signal path pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) ±500 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions: TMUX961x Devices

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD – VSS Power supply voltage differential 10 220 V VDD Positive power supply voltage 10 140 V VSS Negative power supply voltage -130 0 V VS or VD Signal path input/output voltage (source or drain pin) VSS VDD (1) V VSEL Logic input pin voltage 0 48 V TA Ambient temperature –40 125 °C IS or ID (CONT) Source or drain continuous current (Sx, D) IDC (2) mA (1) RON and RON_FLAT will increase when operating VS or VD greater than VDD - 5V. Other Electrical Characterisitics specifications may be violated as well. (2) Refer to Source or Drain Continuous Current table for IDC specifications. www.ti.com TMUX9612 SCDS473 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 ADVANCE INFORMATION

6.4 Source and Drain Continuous Current

over operating free-air temperature range (unless otherwise noted) PACKAGE MIN NOM MAX UNIT IDC 1 ch(1) RUM (WQFN) Continuous current through switch for 1 channel TA = 25°C 200 mATA = 85°C 200 TA = 125°C 110 IDC All ch(2) RUM (WQFN) Continuous current through switch on all channels at the same time TA = 25°C 150 mATA = 85°C 100 TA = 125°C 55 (1) Max continuous current shown for a single channel at a time. (2) Max continuous current shown for all channels at a time. Refer to max power dissipation (Ptot) to ensure package limitations are not violated.

6.5 Source and Drain Pulse Current

over operating free-air temperature range (unless otherwise noted) PACKAGE MIN NOM MAX UNIT IDC All ch(1) RUM (WQFN) Pulse (2) current through switch on all channels at the same time TA = 25°C 250 mATA = 85°C 200 TA = 125°C 150 (1) Max pulse current shown for all channels at a time. Refer to max power dissipation (Ptot) to ensure package limitations are not violated. (2) Pulsed at 10ms, 10% duty cycle

6.6 Electrical Characteristics (Global): TMUX961x Devices

over operating free-air temperature range (unless otherwise noted) typical at VDD = +110V, VSS = –110V, GND = 0V and TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT LOGIC INPUTS VIH Logic voltage high –40°C to +125°C 1.3 48 V VIL Logic voltage low –40°C to +125°C 0 0.8 V IIH Input leakage current Logic inputs = 0V, 5V, or 48V –40°C to +125°C 0.4 3.8 µA IIL Input leakage current Logic inputs = 0V, 5V, or 48V –40°C to +125°C –0.2 –0.005 µA CIN Logic input capacitance –40°C to +125°C 3 pF POWER SUPPLY IDD VDD supply current Logic inputs = 0V, 5V, or 48V 25°C 130 175 µA –40°C to +85°C 190 µA –40°C to +125°C 210 µA ISS VSS supply current Logic inputs = 0V, 5V, or 48V 25°C 100 135 µA –40°C to +85°C 150 µA –40°C to +125°C 160 µA TMUX9612 SCDS473 – JULY 2025 www.ti.com

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6.7 Electrical Characteristics (±110V Dual Supply)

VDD = +110V, VSS = –110V, GND = 0V (unless otherwise noted) Typical at TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = –105V to +105V ID = –10mA 25°C 14 19.6 Ω –40°C to +50°C 21 –40°C to +125°C 28 ΔRON On-resistance mismatch between channels VS = –105V to +105V ID = –10mA 25°C 0.28 0.84 Ω –40°C to +50°C 1 RON FLAT On-resistance flatness VS = –105V to +105V ID = –10mA 25°C 0.435 Ω RON DRIFT On-resistance drift VS = 0V, IS = –10mA –40°C to +125°C 0.08 Ω/°C IS(OFF) Source off leakage current(1) VDD = 110V, VSS = –110V Switch state is off VS = +105V / –105V VD = –105V / +105V 25°C 80 TBD pA –40°C to +50°C TBD 315 TBD –40°C to +85°C TBD TBD –40°C to +125°C TBD TBD ID(OFF) Drain off leakage current(1) VDD = 110V, VSS = –110V Switch state is off VS = +105V / –105V VD = –105V / +105V 25°C 80 TBD pA –40°C to +50°C TBD 315 TBD –40°C to +85°C TBD TBD –40°C to +125°C TBD TBD IS(ON) ID(ON) Channel on leakage current(2) VDD = 110V, VSS = –110V Switch state is on VS = VD = ±105V 25°C -50 TBD pA –40°C to +50°C TBD 120 TBD –40°C to +85°C TBD TBD –40°C to +125°C TBD TBD (1) When VS is positive,VD is negative. And when VS is negative, VD is positive. (2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating. www.ti.com TMUX9612 SCDS473 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 ADVANCE INFORMATION

6.8 Electrical Characteristics (±50V Dual Supply)

VDD = +50V, VSS = –50V, GND = 0V (unless otherwise noted) Typical at TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = –45V to 45V ID = –10mA 25°C 14 19.6 Ω –40°C to +50°C 21 –40°C to +125°C 28 ΔRON On-resistance mismatch between channels VS = –45V to 45V ID = –10mA 25°C 0.28 0.84 Ω –40°C to +50°C 1 RON FLAT On-resistance flatness VS = –45V to 45V ID = –10mA 25°C 0.4 Ω RON DRIFT On-resistance drift VS = 0V, IS = –10mA –40°C to +125°C 0.08 Ω/°C IS(OFF) Source off leakage current(1) VDD = 50V, VSS = –50V Switch state is off VS = +45V / –45V VD = –45V / +45V 25°C 30 TBD pA –40°C to +50°C TBD 130 TBD –40°C to +85°C TBD TBD –40°C to +125°C TBD TBD ID(OFF) Drain off leakage current(1) VDD = 50V, VSS = –50V Switch state is off VS = +45V / –45V VD = –45V / +45V 25°C 30 TBD pA –40°C to +50°C TBD 130 TBD –40°C to +85°C TBD TBD –40°C to +125°C TBD TBD IS(ON) ID(ON) Channel on leakage current(2) VDD = 50V, VSS = –50V Switch state is on VS = VD = ±45V 25°C -35 TBD pA –40°C to +50°C TBD 25 TBD –40°C to +85°C TBD TBD –40°C to +125°C TBD TBD (1) When VS is positive, VD is negative. And when VS is negative, VD is positive. (2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating. TMUX9612 SCDS473 – JULY 2025 www.ti.com

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6.9 Electrical Characteristics (100V Single Supply)

VDD = +100V, VSS = 0V, GND = 0V (unless otherwise noted) Typical at TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = 0V to +95V ID = –10mA 25°C 14 19.6 Ω –40°C to +50°C 21 –40°C to +125°C 28 ΔRON On-resistance mismatch between channels VS = 0V to +95V ID = –10mA 25°C 0.28 0.84 Ω –40°C to +50°C 1 RON FLAT On-resistance flatness VS = 0V to +95V ID = –10mA 25°C 0.36 Ω RON DRIFT On-resistance drift VS = 50V, IS = –10mA –40°C to +125°C 0.08 Ω/°C IS(OFF) Source off leakage current(1) VDD = 100V, VSS = 0V Switch state is off VS = +95V / 0V VD = 0V / +95V 25°C 30 TBD pA –40°C to +50°C TBD 130 TBD –40°C to +85°C TBD TBD –40°C to +125°C TBD TBD ID(OFF) Drain off leakage current(1) VDD = 100V, VSS = 0V Switch state is off VS = +95V / 0V VD = 0V / +95V 25°C 30 TBD pA –40°C to +50°C TBD 130 TBD –40°C to +85°C TBD TBD –40°C to +125°C TBD TBD IS(ON) ID(ON) Channel on leakage current(2) VDD = 100V, VSS = 0V Switch state is on VS = VD = 0V / +95V 25°C -35 TBD pA –40°C to +50°C TBD 30 TBD –40°C to +85°C TBD TBD –40°C to +125°C TBD TBD (1) When VS is positive, VD is negative. And when VS is negative, VD is positive. (2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating. www.ti.com TMUX9612 SCDS473 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 ADVANCE INFORMATION

6.10 Switching Characteristics: TMUX961x Devices

over operating free-air temperature range (unless otherwise noted) typical at VDD = +110V, VSS = –110V, GND = 0V and TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT tON (EN) Turn-on time from enable VS = 10V RL = 300Ω, CL = 35pF 25°C 40 µs–40°C to +85°C 75 –40°C to +125°C 75 tOFF (EN) Turn-off time from enable VS = 10V RL = 300Ω, CL = 35pF 25°C 18 µs–40°C to +85°C 35 –40°C to +125°C 35 tON (VDD) Device turn on time (VDD to output) VDD ramp rate = 20V/µs, VS = 10V RL = 300Ω, CL = 35pF 25°C 45 µs tPD Propagation delay RL = 50Ω , CL = 5pF 25°C 410 ps QINJ Charge injection VS = (VDD + VSS) / 2, CL = 1nF 25°C -20 pC OISO Off isolation RL = 50Ω , CL = 5pF VS = (VDD + VSS) / 2, f = 100kHz 25°C –104 dB XTALK Inter-channel crosstalk RL = 50Ω , CL = 5pF VS = (VDD + VSS) / 2, f = 100kHz 25°C –110 dB BW –3dB bandwidth RL = 50Ω , CL = 5pF VS = (VDD + VSS) / 2 25°C 530 MHz IL Insertion loss RL = 50Ω , CL = 5pF VS = (VDD + VSS) / 2, f = 1MHz 25°C -1.13 dB ACPSRR AC power supply rejection ratio VPP = 0.62V on VDD and VSS RS = 5Ω, 0.01µF decoupling cap on VOUT CL = 50pF f = 1MHz 25°C –70 dB THD+N Total harmonic distortion + Noise VPP = (VDD - VSS)/2V (20V cap), VS = (VDD + VSS) / 2 RL = 1kΩ , CL = 5pF, f = 20Hz to 20kHz 25°C 0.0015 % CS(OFF) Source off capacitance VS = (VDD + VSS) / 2V, f = 1MHz 25°C 5 pF CD(OFF) Drain off capacitance VS = (VDD + VSS) / 2V, f = 1MHz 25°C 5 pF CS(ON), CD(ON) On capacitance VS = (VDD + VSS) / 2V, f = 1MHz 25°C 15 pF TMUX9612 SCDS473 – JULY 2025 www.ti.com

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6.11 Typical Characteristics

at TA = 25°C, VDD = +110V, and VSS = –110V (unless otherwise noted) V S o r V D - S o u r c e o r D r a i n V o l t a g e ( V ) On Resistance () - 1 1 0 - 9 0 - 7 0 - 5 0 - 3 0 - 1 0 1 0 3 0 5 0 7 0 9 0 1 1 0 1 2 1 6 2 0 2 4 2 8 3 2 T A = - 4 0  C T A = 2 5  C T A = 5 0  C T A = 8 5  C T A = 1 2 5  C VDD = +110V, VSS = –110V Flattest Ron Region Figure 6-1. On-Resistance vs Source or Drain Voltage V S o r V D - S o u r c e o r D r a i n V o l t a g e ( V ) On Resistance () - 1 3 0 - 1 1 0 - 9 0 - 7 0 - 5 0 - 3 0 - 1 0 1 0 3 0 5 0 7 0 9 0 1 2 1 6 2 0 2 4 2 8 3 2 T A = - 4 0  C T A = 2 5  C T A = 5 0  C T A = 8 5  C T A = 1 2 5  C VDD = +90V, VSS = –130V Flattest Ron Region Figure 6-2. On-Resistance vs Source or Drain Voltage V S o r V D - S o u r c e o r D r a i n V o l t a g e ( V ) On Resistance () - 1 1 0 - 9 0 - 7 0 - 5 0 - 3 0 - 1 0 1 0 3 0 5 0 7 0 9 0 1 1 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 T A = - 4 0  C T A = 2 5  C T A = 5 0  C T A = 8 5  C T A = 1 2 5  C VDD = +110V, VSS = –110V Figure 6-3. On-Resistance vs Source or Drain Voltage V S o r V D - S o u r c e o r D r a i n V o l t a g e ( V ) On Resistance () - 1 3 0 - 1 1 0 - 9 0 - 7 0 - 5 0 - 3 0 - 1 0 1 0 3 0 5 0 7 0 9 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 T A = - 4 0  C T A = 2 5  C T A = 5 0  C T A = 8 5  C T A = 1 2 5  C VDD = +90V, VSS = –130V Figure 6-4. On-Resistance vs Source or Drain Voltage V S o r V D - S o u r c e o r D r a i n V o l t a g e ( V ) On Resistance () - 1 3 0 - 1 0 5 - 8 0 - 5 5 - 3 0 - 5 2 0 4 5 7 0 9 5 1 2 0 3 0 6 0 9 0 1 2 0 1 5 0 V D D = + 5 0 V , V S S = - 5 0 V V D D = + 1 1 0 V , V S S = 0 V V D D = + 1 1 0 V , V S S = - 1 1 0 V V D D = + 9 0 V , V S S = - 1 3 0 V Figure 6-5. On-Resistance vs Source or Drain Voltage V S o r V D - S o u r c e o r D r a i n V o l t a g e ( V ) Leakage Current (pA) - 1 2 5 - 1 0 0 - 7 5 - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 - 5 0 - 2 5 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 7 5 2 0 0 2 2 5 2 5 0 2 7 5 3 0 0 3 2 5 3 5 0 I S ( O F F ) a n d I D ( O F F ) V D D = + 1 1 0 V , V S S = - 1 1 0 V T A = 2 5 ° C T A = 5 0 ° C Figure 6-6. Off-Leakage Current vs Source or Drain Voltage www.ti.com TMUX9612 SCDS473 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 ADVANCE INFORMATION

6.11 Typical Characteristics (continued)

at TA = 25°C, VDD = +110V, and VSS = –110V (unless otherwise noted) V S o r V D - S o u r c e o r D r a i n V o l t a g e ( V ) Leakage Current (pA) - 1 2 5 - 1 0 0 - 7 5 - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 - 6 0 - 4 0 - 2 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 I S ( O N ) V D D = + 1 1 0 V , V S S = - 1 1 0 V T A = 2 5 ° C T A = 5 0 ° C Figure 6-7. On-Leakage Current vs Source or Drain Voltage TMUX9612 SCDS473 – JULY 2025 www.ti.com

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7 Parameter Measurement Information

7.1 On-Resistance

The On-Resistance of the TMUX9612 is the ohmic resistance across the source (Sx) and drain (Dx) pins of the device. The On-Resistance varies with input voltage and supply voltage. The symbol R ON is used to denote On-Resistance. Figure 7-1 shows the measurement setup used to measure R ON. ΔRON represents the difference between the R ON of any two channels, while R ON_FLAT denotes the flatness that is defined as the difference between the maximum and minimum value of On-Resistance measured over the specified analog signal range. VDD VDD VSS VSS GND Sx Dx SW V IS 410 = 8 VS Figure 7-1. On-Resistance Measurement Setup

7.2 Off-Leakage Current

There are two types of leakage currents associated with a switch during the off state: 1. Source Off-Leakage current IS(OFF): the leakage current flowing into or out of the source pin when the switch is off. 2. Drain Off-Leakage current ID(OFF): the leakage current flowing into or out of the drain pin when the switch is off. Figure 7-2 shows the setup used to measure both Off-Leakage currents. Is (OFF) SWS1 VDD VSS GND A GND ... GND VDVS IS(OFF) Is (OFF) SWS4 GND A GND VDVS SWS1 VDD VSS GND GND GND VDVS ID(OFF) SWS4 GND GND VDVS ID (OFF) A D4 ... ID (OFF) A D4 ... ... ... ... Figure 7-2. Off-Leakage Measurement Setup www.ti.com TMUX9612 SCDS473 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 ADVANCE INFORMATION

7.3 On-Leakage Current

Source On-Leakage current (I S(ON)) and drain On-Leakage current (I D(ON)) denote the channel leakage currents when the switch is in the on state. I S(ON) is measured with the drain floating, while I D(ON) is measured with the source floating. Figure 7-3 shows the circuit used for measuring the On-Leakage currents. Is (OFF) VDD VSS GND A GND ...VS IS(ON) Is (OFF) GND A VS D4 ... ... N.C. N.C. SW SW ID (OFF) VDD VSS GND A GND ... VS ID(ON) ID (OFF) GND A VS D4 ... ... SW SW N.C. N.C. Figure 7-3. On-Leakage Measurement Setup

7.4 Device Turn-On and Turn-Off Time

Turn-On time (tON) is defined as the time taken by the output of the TMUX9612 to rise to a 90% final value after the SELx signal has risen (for NC switches) or fallen (for NO switches) to a 50% final value. Turn-Off time (t OFF) is defined as the time taken by the output of the TMUX9612 to fall to a 10% initial value after the SELx signal has fallen (for NC switches) or risen (for NO switches) to a 50% initial value. Figure 7-4 shows the setup used to measure tON and tOFF. 3 V VSEL 0 V 50% 50% tON tOFF 0.1 0.9 Output tr < 20 ns tf < 20 ns GND RL VSEL GND CL GND VDD VSS VDD VSS GND 0.1 µF GND 0.1 µF SWSx GND GND VS Dx SELx Output Figure 7-4. Enable Delay Measurement Setup TMUX9612 SCDS473 – JULY 2025 www.ti.com

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7.5 Charge Injection

Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching, and is denoted by the symbol QINJ. Figure 7-5 shows the setup used to measure charge injection from the source to drain. VOUT Output VS 0 V 3 V VSELx QINJ = CL × VOUT tr < 20 ns tf < 20 ns GND ... S4 D4 ... SW SW GND VS GND VS GND CL GND CL Output Output VDD VSS VDD VSS GND 0.1 µF GND 0.1 µF SELx VSELx Figure 7-5. Charge-Injection Measurement Setup

7.6 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the source pin (Sx) of an off-channel. The characteristic impedance, ZO, for the measurement is 50Ω. Figure 7-6 and Equation 1 shows the setup used to measure off isolation. SELx GND VSELx SX Dx VS VOUTRS SW Network Analyzer VDD VSS VDD VSS GND 0.1 µF GND 0.1 µF Other Sx/ Dx pins Figure 7-6. Off Isolation Measurement Setup O f f I s ol at i on = 20 × L og V OU T V S (1) www.ti.com TMUX9612 SCDS473 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 ADVANCE INFORMATION

7.7 Crosstalk

Crosstalk (XTALK) is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is applied at the source pin (Sx) of an on-channel. The characteristic impedance, Z O, for the measurement is 50 Ω, as shown in Figure 7-7 and Equation 2. INx GNDVINx SX VS VOUT RS Network Analyzer VDD VSS VDD VSS GND 0.1 µF GND 0.1 µF Other Sx/ Dx pins SW SW DX SY DY Figure 7-7. Inter-channel Crosstalk Measurement Setup I n ter − c ℎ an n el C ro s s tal k = 20 × Lo g V OU T V S (2)

7.8 Bandwidth

Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3dB when the input is applied to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx). Figure 7-8 and Equation 3 shows the setup used to measure bandwidth of the switch. SELx GND VSELx SX Dx VS VOUTRS Network Analyzer VDD VSS VDD VSS GND 0.1 µF GND 0.1 µF SW Other Sx/ Dx pins Figure 7-8. Bandwidth Measurement Setup Ban d wi d t ℎ = 20 × L og V OU T V S (3) TMUX9612 SCDS473 – JULY 2025 www.ti.com

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7.9 THD + Noise

The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the multiplexer output. The On-Resistance of the device varies with the amplitude of the input signal and results in distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as THD+N. Figure 7-9 shows the setup used to measure THD+N of the devices. SELx GNDVSELX SX Dx VS Audio Precision VOUT RS RL SW VDD VSS VDD VSS GND 0.1 µF GND 0.1 µF 50 Other Sx/ Dx pins Figure 7-9. THD+N Measurement Setup www.ti.com TMUX9612 SCDS473 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 ADVANCE INFORMATION

8 Detailed Description

8.1 Overview

The TMUX9612 is a modern complementary metal-oxide semiconductor (CMOS) analog switches in quad single-pole single-throw configuration. The device works well with dual supplies, a single supply, or asymmetric supplies.

8.2 Functional Block Diagram

ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT

8.3 Feature Description

8.3.1 Bidirectional Operation

The devices conduct equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each signal path has similar characteristics in both directions.

8.3.2 Flat On-Resistance

The TMUX9612 devices are designed with a special switch architecture to produce ultra-flat On-Resistance (RON) across most of the switch input operating region. The flat R ON response allows the device to be used in precision sensor applications since the R ON is controlled regardless of the signals sampled. The architecture is implemented without a charge pump so no unwanted noise is produced from the device to affect sampling accuracy. The flattest On-Resistance region extends from V SS to roughly 5V below V DD. Once the signal is within 5V of VDD the On-Resistance will exponentially increase and may impact desired signal transmission.

8.3.3 Protection Features

These devices offer a number of protection features to enable robust system implementations.

8.3.3.1 Fail-Safe Logic

Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting the device from potential damage. Additionally the fail safe logic feature allows the logic inputs of the mux to be interfaced with high voltages, allowing for simplified interfacing if only high voltage control signals are present. The logic inputs are protected against positive faults of up to +48V in powered-off condition, but do not offer protection against negative over-voltage condition. Fail-safe logic also allows the devices to interface with a voltage greater than V DD on the control pins during normal operation to add maximum flexibility in system design. For example, with a V DD = 15V, the logic control pins could be connected to +24V for a logic high signal which allows different types of signals, such as analog feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the logic inputs can be interfaced as high as 48V.

8.3.3.2 ESD Protection

All pins support HBM ESD protection level up to ±2kV, which helps protect the devices from ESD events during the manufacturing process. TMUX9612 SCDS473 – JULY 2025 www.ti.com

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8.3.3.3 Latch-Up Immunity

Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This condition is caused by a trigger (current injection or over-voltage), but once activated the low impedance path remains even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic damage due to excessive current levels. The Latch-Up condition typically requires a power cycle to eliminate the low impedance path. In the TMUX9612 devices, an insulating oxide layer is placed on top of the silicon substrate to prevent any parasitic junctions from forming. As a result, the devices are Latch-Up immune under all circumstances by device construction. The TMUX9612 devices are constructed on silicon on insulator (SOI) based process where an oxide layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events due to over-voltage or current injections. The Latch-Up immunity feature allows the TMUX9612 to be used in harsh environments. For more information on Latch-Up immunity, refer to Using Latch Up Immune Multiplexers to Help Improve System Reliability. 8.3.4 1.8V Logic Compatible Inputs The TMUX9612 devices have 1.8V logic compatible control for all logic control inputs. 1.8V logic level inputs allows the TMUX9612 to interface with processors that have lower logic I/O rails and eliminates the need for an external translator, which saves both space and BOM cost. For more information on 1.8V logic implementations, refer to Simplifying Design with 1.8 V logic Muxes and Switches.

8.3.5 Integrated Pull-Down Resistor on Logic Pins

The TMUX9612 has internal weak Pull-Down resistors to GND to ensure the logic pins are not left floating. The value of this Pull-Down resistor is approximately 4M Ω, but is clamped to 1µA at higher voltages. This feature integrates up to four external components and reduces system size and cost. www.ti.com TMUX9612 SCDS473 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 ADVANCE INFORMATION

8.4 Device Functional Modes

8.4.1 Normal Mode

In Normal Mode operation, signals of up to V DD and V SS can be passed through the switch from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). The select (SELx) pins determine which switch path to turn on, according to the Truth Table. The following conditions must be satisfied for the switch to stay in the ON condition:

The difference between the primary supplies (VDD – VSS) must be greater than or equal to 10V. With a minimum VDD of 10V.
The input signals on the source (Sx) or the drain (Dx) must be between VDD and VSS.
The logic control (SELx) must have selected the switch.

8.4.2 Truth Tables

TMUX9612 Truth Table shows the truth tables for the TMUX9612. Table 8-1. TMUX9612 Truth Table SEL #(1) CHANNEL #

0 Channel # OFF

1 Channel # ON

(1) "#"designates the channel number controlled by SEL pin: "1, 2, 3, or 4" If unused, then the SELx pins must be tied to GND or Logic High so that the devices do not consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs . Unused signal path inputs (Sx or Dx) should be connected to GND for best performance. TMUX9612 SCDS473 – JULY 2025 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TMUX9612 is a high voltage switch capable of supporting analog and digital signals. The high voltage capability of these multiplexers allow them to be used in systems with high voltage signal swings, or in systems with high common mode voltages. Additionally, the TMUX9612 provides consistent analog parametric performance across the entire supply voltage range allowing the devices to be powered by the most convenient supply rails in the system while still providing excellent performance.

9.2 Typical Application

A common feature of many PMUs (precision measurement units) is the ability to change current ranges. This allows for a system defined current clamp when testing devices and reduces possible damage to the PMU and DUT (device under test). In high voltage PMUs, large relays are often used to enable this switching, but this comes with the trade-off of size. To reduce system size, a multi-channel high voltage switch can be added to facilitate this switching with minimal impact to system size and performance. The TMUX9612 allows for switching between multiple current ranges, and has the added flexibility to use multiple channels in parallel for high current applications. VDD VSS DAC + VDD VSS Gain / Filter Network 10k DUT High Voltage Offset TMUX9612 VDD VSS DAC + VDD VSS Gain / Filter Network 10k DUT High Voltage Offset TMUX9612 Figure 9-1. TMUX9612 Application Schematic www.ti.com TMUX9612 SCDS473 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 ADVANCE INFORMATION

9.2.1 Design Requirements

Table 9-1. Design Parameters PARAMETERS VALUES Positive supply (VDD) mux and Op Amps 110V Positive supply (VSS) mux and Op Amps -110V Maximum input or output signals with common mode shift -110V to 110V Control logic thresholds 1.8V compatible, up to 48V Temperature range -40°C to +125°C

9.2.2 Detailed Design Procedure

Multiplexing PMU systems enables a small, flexible solution that can be used over a wide range of current ranges. TI’s high voltage multiplexers offer a size advantage over typical relay solutions while still achieving an extremely low level of distortion, noise, and leakage. This high voltage multiplexer can be use in tandem with high voltage operational amplifiers and DACs to create an accurate PMU with excellent signal-to-noise ratio. In this example application, the TMUX9612 is paired with a high voltage amplifier and a DAC. The DAC generates an arbitrary voltage signal that feeds into the amplifier. An additional high voltage offset is also fed into the amplifier to add any needed common mode shift. This arbitrary signal is then passed through a current limiting resistor before reaching the DUT. To change the current range of the system, different current limiting resistors are added in series with each channel of the multiplexer. In this example, the first channel of the multiplexer uses a 10kΩ resistor for the low current clamp. The maximum output current of the PMU in this range is 5mA because of this design. During the system operation, the PMU is set to this lower current range in the beginning of the test routine. After the DUT is initially checked in this range and is operating normally with no unexpected shorts, the current range can be switched to high current. This way the PMU and DUT will not be unnecessarily damaged from excess current due to a short. In this example, the remaining three channels of the TMUX9612 are connected in parallel, increasing the maximum current through the device and reducing the low On-Resistance. Because of the flexibility of the TMUX9612, this could easily be modified to fit any system need. For example, if less maximum current is needed, then two channels could be connected in parallel instead of three, and the additional single channel could be used to add a third current range option. The additional input channels make this multiplexed application increasingly valuable by greatly reducing solution size. The TMUX9612 switches have exceptionally flat On-Resistance and low leakage currents across the signal voltage range. The ultra-flat On-Resistance keeps the current clamp constant across the signal voltage range, and the low leakage current reduces the potential noise/offset when measuring on the lowest current range. Additionally, excellent crosstalk and off-isolation performance allows the TMUX9612 device to perform well in multi-channel switching applications without having an unselected channel impact the measurement on selected channels. TMUX9612 SCDS473 – JULY 2025 www.ti.com

9.2.3 Application Curves

The example application utilizes the excellent leakage and On-Resistance flatness performance of the TMUX9612 device. Figure 9-2 shows the leakage current for a channel that is ON across a varying source voltage. Figure 9-3 shows the extremely flat On-Resistance across source voltage while operating within the flattest R ON range of the TMUX9612 device. These features make the device an option for applications that require excellent linearity and low distortion. V S o r V D - S o u r c e o r D r a i n V o l t a g e ( V ) Leakage Current (pA) - 1 2 5 - 1 0 0 - 7 5 - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 - 6 0 - 4 0 - 2 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 I S ( O N ) V D D = + 1 1 0 V , V S S = - 1 1 0 V T A = 2 5 ° C T A = 5 0 ° C Figure 9-2. On-Leakage V S o r V D - S o u r c e o r D r a i n V o l t a g e ( V ) On Resistance () - 1 1 0 - 9 0 - 7 0 - 5 0 - 3 0 - 1 0 1 0 3 0 5 0 7 0 9 0 1 1 0 1 2 1 6 2 0 2 4 2 8 3 2 T A = - 4 0  C T A = 2 5  C T A = 5 0  C T A = 8 5  C T A = 1 2 5  C Figure 9-3. RON Flatness

9.3 Power Supply Recommendations

The TMUX9612 device operates across a wide supply range of ±10V to ±110V (10V to 140V in single-supply mode). It also performs well with asymmetrical supplies such as V DD = 140V and V SS= –80V or V DD = 90V and VSS= –130V. For improved supply noise immunity, use a supply decoupling capacitor ranging from 1µF to 10µF at both the V DD and V SS pins to ground. An additional 0.1µF capacitor placed closest to the supply pins will provide the best supply decoupling solution. Always ensure the ground (GND) connection is established before supplies are ramped. VOUT is an internally generated voltage output rail. For reliable operation, connect a decoupling capacitor ranging from 0.01μF to 0.1μF between VOUT and GND on pin 10 or on the thermal pad. Having the decoupling capacitor as close to the thermal pad as possible yeilds the best performance.

9.4 Layout

9.4.1 Layout Guidelines

The image below illustrates an example of a PCB layout with the TMUX9612 device. Some key considerations are:

For reliable operation, connect at least one decoupling capacitor ranging from 0.1µF to 10µF between VDD and VSS to GND. We recommend a 0.1µF and 1µF capacitor, placing the lowest value capacitor as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
For reliable operation, connect at least one decoupling capacitor ranging from 0.01µF to 0.1µF between VOUT to GND. We recommend a capacitor with sufficient voltage rating, that can keep its capacitance value to at least 0.01µF at 100V.
Keep the input lines as short as possible.
Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary. www.ti.com TMUX9612 SCDS473 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 ADVANCE INFORMATION

9.4.2 Layout Example

C D1D4 VSS SEL2 S1S4 SEL1 SEL3 S2S3 GND VOUT D2D3 SEL4 VDD C C C Wide (low inductance) trace for power Wide (low inductance) trace for power Via to ground plane C Via to VOUT pour/plane Figure 9-4. TMUX9612 Layout Example TMUX9612 SCDS473 – JULY 2025 www.ti.com

10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation, see the following:

Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
Texas Instruments, Multiplexers and Signal Switches Glossary application report
Texas Instruments, Using Latch-Up Immune Multiplexers to Help Improve System Reliability application report

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. DATE REVISION NOTES July 2025 * Initial APL Release

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TMUX9612 SCDS473 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 ADVANCE INFORMATION

www.ti.com 2-Aug-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PTMUX9612RUMR Active Preproduction WQFN (RUM) | 16 3000 | LARGE T&R - Call TI Call TI - (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightRUM 16 PLASTIC QUAD FLATPACK - NO LEAD4 x 4, 0.65 mm pitch 4224843/A

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Summary

TMUX9612 220V, Flat Ron, 1:1 (SPST), 4-Channel Switches with Latch-Up Immunity and 1.8V Logic JULY 2025

Description