TMUX7436F_V02 TI | Alldatasheet
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TMUX7436F ±60 V Fault-Protected, Dual 2:1 Multiplexer With Latch-Up Immunity and 1.8 V Logic
1 Features
- Wide supply voltage range: – Single supply: 8 V to 44 V – Dual supply: ±5 V to ±22 V
- Integrated fault protection: – Overvoltage protection, source to supplies or source to drain: ±85 V – Overvoltage protection: ±60 V – Powered-off protection: ±60 V – Interrupt flags to indicate fault status – Output open circuited during fault
- Latch-up immunity by device construction
- 6 kV human body model (HBM) ESD rating
- Low On-Resistance: 8.6 Ω typical
- Flat On-Resistance: 10 mΩ typical
- 1.8-V Logic capable
- Failsafe logic: up to 44 V independent of supply
- Industry-standard TSSOP and smaller WQFN packages
2 Applications
- Factory automation and control
- Programmable logic controllers (PLC)
- Analog input modules
- Semiconductor test equipment
- Battery test equipment
- Servo drive control module
- Data acquisition systems (DAQ) S1A S1B VDD VSS TMUX7436F Fault Detection/ Switch Driver/ Logic Decoder SEL1 SEL2 EN DR FF SF S2A S2B Functional Block Diagram
3 Description
The TMUX7436F is a complementary metal-oxide semiconductor (CMOS) analog multiplexer with latch- up immunity in a dual channel, 2:1 configuration. The device works well with dual supplies (±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as V DD = 12 V, V SS = –5 V). The overvoltage protection is available in powered and powered-off conditions, making the TMUX7436F device suitable for applications where power supply sequencing cannot be precisely controlled. The device blocks fault voltages up to +60 V or −60 V relative to ground in powered and powered-off conditions. When no power supplies are present, the switch channels remain in the OFF state regardless of switch input conditions, and any control signal present on the logic pins is ignored. If the signal path input voltage on any Sx pin exceeds the supply voltage (VDD or V SS) by a threshold voltage (V T), then the channel turns OFF and the Sx pin becomes high impedance. The drain pin (Dx) is either pulled to the fault supply voltage that was exceeded or left floating depending on the DR control logic. The TMUX7436F device provides two active-low interrupt flags (FF and SF) to provide details of the fault and help system diagnostics. The FF flag indicates if any of the source inputs are experiencing a fault condition, while the SF flag is used to decode which specific inputs are experiencing a fault condition. Package Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TMUX7436F PW (TSSOP, 16) 5.00 mm × 4.40 mm RRP (WQFN, 16)(2) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Preview package TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
7.4 Input and Output Leakage Current Under
12.2 Receiving Notification of Documentation Updates..43
13 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Revision * (October 2022) to Revision A (November 2022) Page TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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5 Pin Configuration and Functions
Figure 5-1. PW Package, 16-Pin TSSOP (Top View)
16 S1A5DR
15 SEL16SEL2
14 SF7N.C. 3VSS 10 S2B
13 FF8S2A
Figure 5-2. RRP (Preview) Package, 16-Pin WQFN (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME TSSOP WQFN(2) D1 3 1 I/O Drain pin 1. Can be an input or output. The drain pin is not overvoltage protected. D2 11 9 I/O Drain pin 2. Can be an input or output. The drain pin is not overvoltage protected. DR 8 5 I Drain Response (DR) input. Tying the DR pin to GND enables the drain to be pulled to VDD or VSS through a 40 kΩ resistor during an overvoltage fault event. The drain pin becomes open circuit when the DR pin is a logic high or left floating. EN 14 12 I Active high logic enable (EN) pin, has internal 4 MΩ pull-down resistor. The device is disabled and all switches become high impedance when the pin is low. As provided in Table 8-1, when the pin is high, the SELx logic inputs determine individual switch states. FF 15 13 O General fault flag. This pin is an open drain output and is asserted low when overvoltage condition is detected on any of the source (Sxy) input pins. Connect this pin to an external supply (1.8 V to 5.5 V) through a 1 kΩ pull-up resistor. GND 6 4 P Ground (0 V) reference N.C. 7 7 — No internal connection. This pin can be shorted to GND or left floating. S1A 2 16 I/O Overvoltage protected source pin 1A. Can be an input or output. S1B 4 2 I/O Overvoltage protected source pin 1B. Can be an input or output. S2A 10 8 I/O Overvoltage protected source pin 2A. Can be an input or output. S2B 12 10 I/O Overvoltage protected source pin 2B. Can be an input or output. SEL1 1 15 I Logic control input 1. SEL2 9 6 I Logic control input 2. SF 16 14 O Specific fault flag. This pin is an open drain output and is asserted low when an overvoltage condition is detected on a specific (Sxy) input pin, depending on the state of the SELx pins, as provided in Table 8-1. Connect this pin to an external supply (1.8 V to 5.5 V) through a 1 kΩ pull-up resistor. VDD 13 11 P Positive power supply. This pin is the most positive power-supply potential. Connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND for reliable operation. VSS 5 3 P Negative power supply. This pin is the most negative power-supply potential. This pin can be connected to ground in single-supply applications. Connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND for reliable operation. Thermal Pad — The thermal pad is not connected internally. It is recommended to tie the pad to GND or VSS for best performance. (1) I = input, O = output, I/O = input and output, P = power. (2) Preview package. www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TMUX7436F
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD to VSS Supply voltage 48 V VDD to GND –0.3 48 V VSS to GND –48 0.3 V VS to GND Source input pin (Sx) voltage to GND –65 65 V VS to VDD Source input pin (Sx) voltage to VDD –90 V VS to VSS Source input pin (Sx) voltage to VSS 90 V VD Drain pin (Dx) voltage VSS–0.7 VDD+0.7 V VLOGIC Logic control input pin voltage (EN, SELx, DR)(2) GND –0.7 48 V VxF Logic output pin voltage (FF, SF)(2) GND –0.7 6 V ILOGIC Logic control input pin current (EN, SELx, DR)(2) –30 30 mA IxF Logic output pin current (FF, SF)(2) –10 10 mA IS or ID (CONT) Source or drain continuous current (Sx or Dx) IDC ± 10 %(3) IDC ± 10 %(3) mA Tstg Storage temperature –65 150 °C TA Ambient temperature –55 150 °C TJ Junction temperature 150 °C Ptot (4) Total power dissipation (TSSOP) 650 mW (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Stresses have to be kept at or below both voltage and current ratings at all time. (3) Refer to Recommended Operating Conditions for IDC ratings. (4) For TSSOP package: Ptot derates linearly above TA = 70°C by 10.1 mW/°C.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±4000 VCharged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) ±750 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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6.3 Thermal Information
THERMAL METRIC(1) TMUX7436F UNITPW (TSSOP) RRP (WQFN)
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 100.4 TBD °C/W RθJC(top) Junction-to-case (top) thermal resistance 31.3 TBD °C/W RθJB Junction-to-board thermal resistance 46.4 TBD °C/W ΨJT Junction-to-top characterization parameter 1.7 TBD °C/W ΨJB Junction-to-board characterization parameter 45.8 TBD °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A TBD °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD – VSS (1) Power supply voltage differential 8 44 V VDD Positive power supply voltage 5 44 VS Source pin (Sx) voltage (non-fault condition) VSS VDD V VS to GND Source pin (Sx) voltage to GND (fault condition) –60 60 VS to VDD (2) Source pin (Sx) voltage to VDD or VD (fault condition) –85 VS to VSS (2) Source pin (Sx) voltage to VSS or VD (fault condition) 85 VD Drain pin (Dx) voltage VSS VDD VLOGIC Logic control input pin voltage (EN, SELx, DR) GND 44 V VxF (3) Logic output pin voltage (FF, SF) GND 5.5 TA Ambient temperature –40 125 °C IDC Continuous current through switch operating 1 channel, TSSOP package TA = 25°C 115 mA TA = 85°C 115 mA TA = 125°C 85 mA IDC Continuous current through switch operating max number of channels at the same time, TSSOP package TA = 25°C 115 mA TA = 85°C 115 mA TA = 125°C 60 mA (1) VDD and VSS can be any value as long as 8 V ≤ (VDD – VSS) ≤ 44 V, and the minimum VDD is met. (2) Source pin voltage (Sx) under a fault condition may not exceed 85 V from supply pins (VDD and VSS.) or drain pins (D, Dx). (3) Logic output pin (FF) is an open drain output and should be pulled up to a voltage within the maximum ratings. www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TMUX7436F
6.5 Electrical Characteristics: Global
at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG SWITCH VT Threshold voltage for fault detector 25°C 0.7 V LOGIC INPUT/ OUTPUT VIH High-level input voltage EN, SELx, DR pins –40°C to +125°C 1.3 44 V VIL Low-level input voltage EN, SELx, DR pins –40°C to +125°C 0 0.8 V VOL(FLAG) Low-level output voltage FF and SF pins, IO = 5 mA –40°C to +125°C 0.35 V POWER SUPPLY VUVLO Undervoltage lockout (UVLO) threshold voltage (VDD – VSS) Rising edge, single supply –40°C to +125°C 5.1 5.8 6.6 V Falling edge, single supply –40°C to +125°C 5 5.7 6.4 V VHYS VDD Undervoltage lockout (UVLO) hysteresis Single supply –40°C to +125°C 0.2 V RD(OVP) Drain resistance to supply rail during overvoltage event on selected source pin Drain resistance to supply rail during overvoltage event on selected source pin 25°C 40 kΩ TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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6.6 ±15 V Dual Supply: Electrical Characteristics VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = –10 V to +10 V ID = –10 mA 25°C 8.6 11 Ω–40°C to +85°C 14 –40°C to +125°C 16.5 ΔRON On-resistance mismatch between channels VS = –10 V to +10 V ID = –10 mA 25°C 0.06 0.45 Ω–40°C to +85°C 0.5 RFLAT On-resistance flatness VS = –10 V to +10 V ID = –10 mA 25°C 0.01 0.4 Ω–40°C to +85°C 0.4 RON_DRIFT On-resistance drift VS = 0 V, IS = –10 mA –40°C to +125°C 0.04 Ω/°C IS(OFF) Input leakage current(1) VDD = 16.5 V, VSS = –16.5 V Switch state is off VS = +10 V / –10 V VD = –10 V / + 10 V 25°C –0.7 0.03 0.7 nA–40°C to +85°C –2 2 –40°C to +125°C –11 11 ID(OFF) Output off leakage current(1) VDD = 16.5 V, VSS = –16.5 V Switch state is off VS = +10 V / –10 V VD = –10 V / + 10 V 25°C –1.4 0.06 1.4 nA–40°C to +85°C –4 4 –40°C to +125°C –24 24 IS(ON) ID(ON) Output on leakage current(2) VDD = 16.5 V, VSS = –16.5 V Switch state is on VS = VD = ±10 V 25°C –1.4 0.08 1.4 nA–40°C to +85°C –4 4 –40°C to +125°C –27 27 FAULT CONDITION IS(FA) Input leakage current durring overvoltage VS = ± 60 V, GND = 0 V, VDD = 16.5 V, VSS = –16.5 V –40°C to +125°C ±100 µA IS(FA) Grounded Input leakage current during overvoltage with grounded supply voltages VS = ± 60 V, GND = 0 V VDD = VSS = 0 V –40°C to +125°C ±125 µA IS(FA) Floating Input leakage current during overvoltage with floating supply voltages VS = ± 60 V, GND = 0 V, VDD = VSS = floating –40°C to +125°C ±125 µA ID(FA) Output leakage current during overvoltage VS = ± 60 V, GND = 0 V, VDD = 16.5 V, VSS = –16.5 V 25°C –20 ±0.1 20 nA–40°C to +85°C –30 30 –40°C to +125°C –60 60 ID(FA) Grounded Output leakage current during overvoltage with grounded supply voltages VS = ± 60 V, GND = 0 V, VDD = VSS = 0 V 25°C –30 ±0.01 30 nA–40°C to +85°C –50 50 –40°C to +125°C –90 90 ID(FA) Floating Output leakage current during overvoltage with floating supply voltages VS = ± 60 V, GND = 0 V, VDD = VSS = floating 25°C ±4 µA–40°C to +85°C ±6 –40°C to +125°C ±8 IIH High-level input current VEN = VSELx = VDR = VDD 25°C ±1.6 µA –40°C to +125°C ±2 IIL Low-level input current VEN = VSELx = VDR = 0 25°C ±1 µA www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TMUX7436F
6.6 ±15 V Dual Supply: Electrical Characteristics (continued) VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT SWITCHING CHARACTERISTICS tON (EN) Enable turn-on time VS = 10 V, RL = 300 Ω, CL= 12 pF 25°C 435 515 ns–40°C to +85°C 530 –40°C to +125°C 550 tOFF (EN) Enable turn-off time VS = 10 V, RL = 300 Ω, CL= 12 pF 25°C 50 130 ns–40°C to +85°C 140 –40°C to +125°C 150 tTRAN Transition time VS = 10 V, RL = 300 Ω, CL= 12 pF 25°C 417 540 ns–40°C to +85°C 555 –40°C to +125°C 570 tRESPONSE Fault response time RL = 300 Ω, CL= 12 pF 25°C 110 505 ns–40°C to +85°C 515 –40°C to +125°C 520 tRECOVERY Fault recovery time RL = 300 Ω, CL= 12 pF 25°C 1600 4500 ns–40°C to +85°C 4800 –40°C to +125°C 4800 tRESPONSE(FLAG) Fault flag response time RL = 300 Ω, CL= 12 pF, RPU = 1 kΩ, CL_xF = 12 pF 25°C 120 ns tRECOVERY(FLAG) Fault flag recovery time RL = 300 Ω, CL= 12 pF, RPU = 1 kΩ, CL_xF = 12 pF 25°C 1 µs tBBM Break-before-make time delay VS = 10 V, RL = 300 Ω, CL= 12 pF –40°C to +125°C 200 380 ns QINJ Charge injection VS = 0 V, CL = 1 nF 25°C –300 pC OISO Off-isolation RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz 25°C –60 dB XTALK Intra-channel crosstalk RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz 25°C –62 dB Inter-channel crosstalk RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz 25°C –88 BW –3 dB bandwidth RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 0 V 25°C 220 MHz ILOSS Insertion loss RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz 25°C –0.7 dB THD+N Total harmonic distortion plus noise RS = 50 Ω, RL = 10 kΩ, VS = 15 VPP, VBIAS = 0 V, f = 20 Hz to 20 kHz 25°C 0.0007 % CS(OFF) Input off-capacitance f = 1 MHz, VS = 0 V 25°C 13 pF CD(OFF) Output off-capacitance f = 1 MHz, VS = 0 V 25°C 25 pF CS(ON) CD(ON) Input/Output on-capacitance f = 1 MHz, VS = 0 V 25°C 28 pF POWER SUPPLY IDD VDD supply current VDD = 16.5 V, VSS = –16.5 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.32 0.5 mA–40°C to +85°C 0.5 ISS VSS supply current VDD = 16.5 V, VSS = –16.5 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.26 0.4 mA–40°C to +85°C 0.4 IGND GND current VDD = 16.5 V, VSS = –16.5 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.06 mA IDD(FA) VDD supply current under fault VS = ± 60 V, VDD = 16.5 V, VSS = –16.5 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.27 0.7 mA–40°C to +85°C 0.8 TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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6.6 ±15 V Dual Supply: Electrical Characteristics (continued) VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ISS(FA) VSS supply current under fault VS = ± 60 V, VDD = 16.5 V, VSS = –16.5 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.2 0.6 mA–40°C to +85°C 0.8 IGND(FA) GND current under fault VS = ± 60 V, VDD = 16.5 V, VSS = –16.5 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.15 mA IDD(DISABLE) VDD supply current (disable mode) VDD = 16.5 V, VSS = –16.5 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 0 V 25°C 0.15 0.5 mA–40°C to +85°C 0.5 ISS(DISABLE) VSS supply current (disable mode) VDD = 16.5 V, VSS = –16.5 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 0 V 25°C 0.1 0.4 mA–40°C to +85°C 0.4 (1) When VS is positive,VD is negative. And when VS is negative, VD is positive. (2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating. www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TMUX7436F
6.7 ±20 V Dual Supply: Electrical Characteristics VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = –15 V to +15 V ID = –10 mA 25°C 8.6 11 Ω–40°C to +85°C 14 –40°C to +125°C 17 ΔRON On-resistance mismatch between channels VS = –15 V to +15 V ID = –10 mA 25°C 0.06 0.35 Ω–40°C to +85°C 0.5 RFLAT On-resistance flatness VS = –15 V to +15 V ID = –10 mA 25°C 0.015 0.4 Ω–40°C to +85°C 0.5 RON_DRIFT On-resistance drift VS = 0 V, IS = –10 mA –40°C to +125°C 0.04 Ω/°C IS(OFF) Input leakage current(1) VDD = 22 V, VSS = –22 V Switch state is off VS = +15 V / –15 V VD = –15 V / + 15 V 25°C –0.7 0.03 0.7 nA–40°C to +85°C –2 2 –40°C to +125°C –11 11 ID(OFF) Output off leakage current(1) VDD = 22 V, VSS = –22 V Switch state is off VS = +15 V / –15 V VD = –15 V / + 15 V 25°C –1.4 0.06 1.4 nA–40°C to +85°C –4 4 –40°C to +125°C –24 24 IS(ON) ID(ON) Output on leakage current(2) VDD = 22 V, VSS = –22 V Switch state is on VS = VD = ±15 V 25°C –1.4 0.08 1.4 nA–40°C to +85°C –4 4 –40°C to +125°C –27 27 FAULT CONDITION IS(FA) Input leakage current durring overvoltage VS = ± 60 V, GND = 0 V, VDD = 22 V, VSS = –22 V –40°C to +125°C ±85 µA IS(FA) Grounded Input leakage current during overvoltage with grounded supply voltages VS = ± 60 V, GND = 0 V, VDD = VSS = 0 V –40°C to +125°C ±125 µA IS(FA) Floating Input leakage current during overvoltage with floating supply voltages VS = ± 60 V, GND = 0 V, VDD = VSS = floating –40°C to +125°C ±125 µA ID(FA) Output leakage current during overvoltage VS = ± 60 V, GND = 0 V, VDD = 22 V, VSS = –22 V, 25°C –50 ±5 50 nA–40°C to +85°C –70 70 –40°C to +125°C –90 90 ID(FA) Grounded Output leakage current during overvoltage with grounded supply voltages VS = ± 60 V, GND = 0 V, VDD = VSS = 0 V 25°C –30 ±10 30 nA–40°C to +85°C –50 50 –40°C to +125°C –90 90 ID(FA) Floating Output leakage current during overvoltage with floating supply voltages VS = ± 60 V, GND = 0 V, VDD = VSS = floating 25°C ±4 µA–40°C to +85°C ±6 –40°C to +125°C ±8 IIH High-level input current VEN = VSELx = VDR = VDD 25°C ±1.8 µA IIL Low-level input current VEN = VSELx = VDR = 0 25°C ±1 µA TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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6.7 ±20 V Dual Supply: Electrical Characteristics (continued) VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT SWITCHING CHARACTERISTICS tON (EN) Enable turn-on time VS = 10 V, RL = 300 Ω, CL= 12 pF 25°C 430 535 ns–40°C to +85°C 560 –40°C to +125°C 585 tOFF (EN) Enable turn-off time VS = 10 V, RL = 300 Ω, CL= 12 pF 25°C 50 120 ns–40°C to +85°C 130 –40°C to +125°C 150 tTRAN Transition time VS = 10 V, RL = 300 Ω, CL= 12 pF 25°C 433 555 ns–40°C to +85°C 571 –40°C to +125°C 580 tRESPONSE Fault response time RL = 300 Ω, CL= 12 pF 25°C 110 505 ns–40°C to +85°C 515 –40°C to +125°C 520 tRECOVERY Fault recovery time RL = 300 Ω, CL= 12 pF 25°C 1600 4500 ns–40°C to +85°C 4900 –40°C to +125°C 4900 tRESPONSE(FLAG) Fault flag response time RL = 300 Ω, CL= 12 pF, RPU = 1 kΩ, CL_xF = 12 pF 25°C 140 ns tRECOVERY(FLAG) Fault flag recovery time RL = 300 Ω, CL= 12 pF, RPU = 1 kΩ, CL_xF = 12 pF 25°C 1 µs tBBM Break-before-make time delay VS = 10 V, RL = 300 Ω, CL= 12 pF –40°C to +125°C 210 400 ns QINJ Charge injection VS = 0 V, CL = 1 nF 25°C –330 pC OISO Off-isolation RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz 25°C –60 dB XTALK Intra-channel crosstalk RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz 25°C –64 dB Inter-channel crosstalk RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz 25°C –81 BW –3 dB bandwidth RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 0 V 25°C 230 MHz ILOSS Insertion loss RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz 25°C –0.7 dB THD+N Total harmonic distortion plus noise RS = 50 Ω, RL = 10 kΩ, VS = 20 VPP, VBIAS = 0 V, f = 20 Hz to 20 kHz 25°C 0.0008 % CS(OFF) Input off-capacitance f = 1 MHz, VS = 0 V 25°C 12 pF CD(OFF) Output off-capacitance f = 1 MHz, VS = 0 V 25°C 24 pF CS(ON) CD(ON) Input/Output on-capacitance f = 1 MHz, VS = 0 V 25°C 27 pF POWER SUPPLY IDD VDD supply current VDD = 22 V, VSS = –22 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.32 0.5 mA–40°C to +85°C 0.5 ISS VSS supply current VDD = 22 V, VSS = –22 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.26 0.4 mA–40°C to +85°C 0.4 IGND GND current VDD = 22 V, VSS = –22 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.06 mA IDD(FA) VDD supply current under fault VS = ± 60 V, VDD = 22 V, VSS = –22 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.27 0.8 mA–40°C to +85°C 1 –40°C to +125°C 1 www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TMUX7436F
6.7 ±20 V Dual Supply: Electrical Characteristics (continued) VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ISS(FA) VSS supply current under fault VS = ± 60 V, VDD = 22 V, VSS = –22 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.2 0.7 mA–40°C to +85°C 1 –40°C to +125°C 1 IGND(FA) GND current under fault VS = ± 60 V, VDD = 22 V, VSS = –22 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.15 mA IDD(DISABLE) VDD supply current (disable mode) VDD = 22 V, VSS = –22 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 0 V 25°C 0.15 0.5 mA–40°C to +85°C 0.5 ISS(DISABLE) VSS supply current (disable mode) VDD = 22 V, VSS = –22 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 0 V 25°C 0.1 0.4 mA–40°C to +85°C 0.4 (1) When VS is positive,VD is negative. And when VS is negative, VD is positive. (2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating. TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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6.8 12 V Single Supply: Electrical Characteristics VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = 0 V to 7.8 V, IS = –10 mA 25°C 8.6 11 Ω–40°C to +85°C 15 –40°C to +125°C 18 ΔRON On-resistance mismatch between channels VS = 0 V to 7.8 V, IS = –10 mA 25°C 0.06 0.5 Ω–40°C to +85°C 0.6 RFLAT On-resistance flatness VS = 0 V to 7.8 V, IS = –10 mA 25°C 0.06 0.4 Ω–40°C to +85°C 0.5 RON_DRIFT On-resistance drift VS = 6 V, IS = –10 mA –40°C to +125°C 0.04 Ω/°C IS(OFF) Input leakage current(1) VDD = 13.2 V, VSS = 0 V Switch state is off VS = 10 V / 1 V VD = 1 V / 10 V 25°C –0.7 0.03 0.7 nA–40°C to +85°C –2 2 –40°C to +125°C –11 11 ID(OFF) Output off leakage current(1) VDD = 13.2 V, VSS = 0 V Switch state is off VS = 10 V / 1 V VD = 1 V / 10 V 25°C –1.4 0.06 1.4 nA–40°C to +85°C –4 4 –40°C to +125°C –24 24 IS(ON) ID(ON) Output on leakage current(2) VDD = 13.2 V, VSS = 0 V Switch state is on VS = VD = 10 V or 1 V 25°C –1.4 0.08 1.4 nA–40°C to +85°C –4 4 –40°C to +125°C –26 26 FAULT CONDITION IS(FA) Input leakage current durring overvoltage VS = ± 60 V, GND = 0 V, VDD = 13.2 V, VSS = 0 V –40°C to +125°C ±130 µA IS(FA) Grounded Input leakage current during overvoltage with grounded supply voltages VS = ± 60 V, GND = 0 V, VDD = VSS = 0 V –40°C to +125°C ±125 µA IS(FA) Floating Input leakage current during overvoltage with floating supply voltages VS = ± 60 V, GND = 0 V, VDD = VSS = floating –40°C to +125°C ±125 µA ID(FA) Output leakage current during overvoltage VS = ± 60 V, GND = 0 V, VDD = 13.2 V, VSS = 0 V 25°C –20 ±2 20 nA–40°C to +85°C –30 30 –40°C to +125°C –50 50 ID(FA) Grounded Output leakage current during overvoltage with grounded supply voltages VS = ± 60 V, GND = 0 V, VDD = VSS = 0 V 25°C –30 ±10 30 nA–40°C to +85°C –50 50 –40°C to +125°C –90 90 ID(FA) Floating Output leakage current during overvoltage with floating supply voltages VS = ± 60 V, GND = 0 V, VDD = VSS = floating 25°C ±4 µA–40°C to +85°C ±6 –40°C to +125°C ±8 IIH High-level input current VEN = VSELx = VDR = VDD 25°C ±1.6 µA –40°C to +125°C ±2 IIL Low-level input current VEN = VSELx = VDR = 0 25°C ±1 µA www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TMUX7436F
6.8 12 V Single Supply: Electrical Characteristics (continued) VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT SWITCHING CHARACTERISTICS tON (EN) Enable turn-on time VS = 8 V, RL = 300 Ω, CL= 12 pF 25°C 350 515 ns–40°C to +85°C 530 –40°C to +125°C 550 tOFF (EN) Enable turn-off time VS = 8 V, RL = 300 Ω, CL= 12 pF 25°C 85 200 ns–40°C to +85°C 210 –40°C to +125°C 210 tTRAN Transition time VS = 8 V, RL = 300 Ω, CL= 12 pF 25°C 360 520 ns–40°C to +85°C 540 –40°C to +125°C 560 tRESPONSE Fault response time RL = 300 Ω, CL= 12 pF 25°C 180 765 ns–40°C to +85°C 765 –40°C to +125°C 765 tRECOVERY Fault recovery time RL = 300 Ω, CL= 12 pF 25°C 950 2400 ns–40°C to +85°C 2900 –40°C to +125°C 2900 tRESPONSE(FLAG) Fault flag response time RL = 300 Ω, CL= 12 pF, RPU = 1 kΩ, CL_xF = 12 pF 25°C 160 ns tRECOVERY(FLAG) Fault flag recovery time RL = 300 Ω, CL= 12 pF, RPU = 1 kΩ, CL_xF = 12 pF 25°C 0.7 µs tBBM Break-before-make time delay VS = 8 V, RL = 300 Ω, CL= 12 pF 25°C 155 250 ns QINJ Charge injection VS = 6 V, CL = 1 nF 25°C –203 pC OISO Off-isolation RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz 25°C –56 dB XTALK Intra-channel crosstalk RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz 25°C –58 dB Inter-channel crosstalk RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz 25°C –81 BW –3 dB bandwidth RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 0 V 25°C 213 MHz ILOSS Insertion loss RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz 25°C –0.7 dB THD+N Total harmonic distortion plus noise RS = 50 Ω, RL = 10k Ω, VS = 6 VPP, VBIAS = 6 V, f = 20 Hz to 20 kHz 25°C 0.0009 % CS(OFF) Input off-capacitance f = 1 MHz, VS = 6 V 25°C 13 pF CD(OFF) Output off-capacitance f = 1 MHz, VS = 6 V 25°C 28 pF CS(ON) CD(ON) Input/Output on-capacitance f = 1 MHz, VS = 6 V 25°C 31 pF POWER SUPPLY IDD VDD supply current VDD = 13.2 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.3 0.5 mA –40°C to +85°C 0.5 –40°C to +125°C 0.6 mA ISS VSS supply current VDD = 13.2 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.14 0.4 mA–40°C to +85°C 0.4 IGND GND current VDD = 13.2 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.06 mA IDD(FA) VDD supply current under fault VS = ± 60 V, VDD = 13.2 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.25 0.6 mA–40°C to +85°C 0.7 TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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6.8 12 V Single Supply: Electrical Characteristics (continued) VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ISS(FA) VSS supply current under fault VS = ± 60 V, VDD = 13.2 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.15 0.5 mA–40°C to +85°C 0.5 IGND(FA) GND current under fault VS = ± 60 V, VDD = 13.2 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.15 mA IDD(DISABLE) VDD supply current (disable mode) VDD = 13.2 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 0 V 25°C 0.15 0.5 mA–40°C to +85°C 0.5 ISS(DISABLE) VSS supply current (disable mode) VDD = 13.2 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 0 V 25°C 0.1 0.4 mA–40°C to +85°C 0.4 (1) When VS is 10 V, VD is 1 V. Or when VS is 1 V, VD is 10 V. (2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating. www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TMUX7436F
6.9 36 V Single Supply: Electrical Characteristics VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = 0 V to 30 V, IS = –10 mA 25°C 8.6 11 Ω–40°C to +85°C 14 –40°C to +125°C 17 ΔRON On-resistance mismatch between channels VS = 0 V to 30 V, IS = –10 mA 25°C 0.06 0.5 Ω–40°C to +85°C 0.6 RFLAT On-resistance flatness VS = 0 V to 30 V, IS = –10 mA 25°C 0.07 0.4 Ω–40°C to +85°C 0.5 RON_DRIFT On-resistance drift VS = 18 V, IS = –1 mA –40°C to +125°C 0.04 Ω/°C IS(OFF) Input leakage current(1) VDD = 39.6 V, VSS = 0 V Switch state is off VS = 30 V / 1 V VD = 1 V / 30 V 25°C –0.7 0.05 0.7 nA–40°C to +85°C –2 2 –40°C to +125°C –11 11 ID(OFF) Output off leakage current(1) VDD = 39.6 V, VSS = 0 V Switch state is off VS = 30 V / 1 V VD = 1 V / 30 V 25°C –1.4 0.1 1.4 nA–40°C to +85°C –4 4 –40°C to +125°C –24 24 IS(ON) ID(ON) Output on leakage current(2) VDD = 39.6 V, VSS = 0 V Switch state is on VS = VD = 30 V or 1 V 25°C –1.4 0.15 1.4 nA–40°C to +85°C –4 4 –40°C to +125°C –27 27 FAULT CONDITION IS(FA) Input leakage current durring overvoltage VS = 60 / –40 V, VDD = 39.6 V, VSS = 0 V, GND = 0 V –40°C to +125°C ±90 µA IS(FA) Grounded Input leakage current during overvoltage with grounded supply voltages VS = ± 60 V, VDD = VSS = 0 V, GND = 0 V –40°C to +125°C ±125 µA IS(FA) Floating Input leakage current during overvoltage with floating supply voltages VS = ± 60 V, VDD = VSS = floating, GND = 0 V, –40°C to +125°C ±125 µA ID(FA) Output leakage current during overvoltage VS = 60 / –40 V, VDD = 39.6 V, VSS = 0, GND = 0V 25°C –20 ±2 20 nA–40°C to +85°C –30 30 –40°C to +125°C –60 60 ID(FA) Grounded Output leakage current during overvoltage with grounded supply voltages VS = ± 60 V, GND = 0 V, VDD = VSS = 0 V 25°C –30 ±10 30 nA–40°C to +85°C –50 50 –40°C to +125°C –90 90 ID(FA) Floating Output leakage current during overvoltage with floating supply voltages VS = ± 60 V, GND = 0 V, VDD = VSS = floating 25°C ±4 µA–40°C to +85°C ±6 –40°C to +125°C ±8 IIH High-level input current VEN = VSELx = VDR = VDD 25°C ±2.7 µA IIL Low-level input current VEN = VSELx = VDR = 0 25°C ±1 µA TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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6.9 36 V Single Supply: Electrical Characteristics (continued) VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT SWITCHING CHARACTERISTICS tON (EN) Enable turn-on time VS = 18 V, RL = 300 Ω, CL= 12 pF 25°C 370 520 ns–40°C to +85°C 550 –40°C to +125°C 560 tOFF (EN) Enable turn-off time VS = 18 V, RL = 300 Ω, CL= 12 pF 25°C 100 210 ns–40°C to +85°C 230 –40°C to +125°C 230 tTRAN Transition time VS = 18 V, RL = 300 Ω, CL= 12 pF 25°C 365 540 ns–40°C to +85°C 560 –40°C to +125°C 570 tRESPONSE Fault response time RL = 300 Ω, CL= 12 pF 25°C 120 340 ns–40°C to +85°C 360 –40°C to +125°C 385 tRECOVERY Fault recovery time RL = 300 Ω, CL= 12 pF 25°C 1250 2350 ns–40°C to +85°C 2850 –40°C to +125°C 2850 tRESPONSE(FLAG) Fault flag response time RL = 300 Ω, CL= 12 pF, RPU = 1 kΩ, CL_xF = 12 pF 25°C 100 ns tRECOVERY(FLAG) Fault flag recovery time RL = 300 Ω, CL= 12 pF, RPU = 1 kΩ, CL_xF = 12 pF 25°C 1 µs tBBM Break-before-make time delay VS = 18 V, RL = 300 Ω, CL= 12 pF 25°C 160 270 ns QINJ Charge injection VS = 18 V, CL = 1 nF 25°C –300 pC OISO Off-isolation RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz 25°C –56 dB XTALK Intra-channel crosstalk RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz 25°C –59 dB Inter-channel crosstalk RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz 25°C –80 BW –3 dB bandwidth RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 6 V 25°C 215 MHz ILOSS Insertion loss RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz 25°C –0.7 dB THD+N Total harmonic distortion plus noise RS = 50 Ω, RL = 10 kΩ, VS = 18 VPP, VBIAS = 18 V, f = 20 Hz to 20 kHz 25°C 0.0008 % CS(OFF) Input off-capacitance f = 1 MHz, VS = 18 V 25°C 14 pF CD(OFF) Output off-capacitance f = 1 MHz, VS = 18 V 25°C 28 pF CS(ON) CD(ON) Input/Output on-capacitance f = 1 MHz, VS = 18 V 25°C 31 pF POWER SUPPLY IDD VDD supply current VDD = 39.6 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.3 0.5 mA–40°C to +85°C 0.5 ISS VSS supply current VDD = 39.6 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.14 0.4 mA–40°C to +85°C 0.4 IGND GND current VDD = 39.6 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.06 mA IDD(FA) VDD supply current under fault VS = 60 / –40 V, VDD = 39.6 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.25 1.2 mA–40°C to +85°C 1.6 www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TMUX7436F
6.9 36 V Single Supply: Electrical Characteristics (continued) VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ISS(FA) VSS supply current under fault VS = 60 / –40 V, VDD = 39.6 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.15 0.5 mA–40°C to +85°C 0.5 IGND(FA) GND current under fault VS = 60 / –40 V, VDD = 39.6 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 5 V or VDD 25°C 0.1 mA IDD(DISABLE) VDD supply current (disable mode) VDD = 39.6 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 0 V 25°C 0.15 0.5 mA–40°C to +85°C 0.5 ISS(DISABLE) VSS supply current (disable mode) VDD = 39.6 V, VSS = 0 V, VSELx = VDR = 0 V, 5 V, or VDD, VEN = 0 V 25°C 0.1 0.4 mA–40°C to +85°C 0.4 (1) When VS is 30 V, VD is 1 V. Or when VS is 1 V, VD is 30 V. (2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating. TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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6.10 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted) V S or V D - Source or Drain Voltage (V) On Resistance ( ) -22 -18 -14 -10 -6 -2 2 6 10 14 18 22 100 120 140 160 V DD = 13.5 V, V SS = -13.5 V V DD = 15 V, V SS = -15 V V DD = 16.5 V, V SS = -16.5 V V DD = 18 V, V SS = -18 V V DD = 20 V, V SS = -20 V V DD = 22 V, V SS = -22 V Dual Supply Voltages Figure 6-1. On-Resistance vs Source or Drain Voltage V S or V D - Source or Drain Voltage (V) On Resistance ( ) -22 -18 -14 -10 -6 -2 2 6 10 14 18 22 7.5 8.5 9.5 10.5 11.5 V DD = 13.5 V, V SS = -13.5 V V DD = 15 V, V SS = -15 V V DD = 16.5 V, V SS = -16.5 V V DD = 18 V, V SS = -18 V V DD = 20 V, V SS = -20 V V DD = 22 V, V SS = -22 V Dual Supply Flat Ron Region Figure 6-2. On-Resistance vs Source or Drain Voltage V S or V D - Source or Drain Voltage (V) On Resistance ( ) -10 -8 -6 -4 -2 0 2 4 6 8 10 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9.1 9.2 9.3 V DD = 13.5 V, V SS = -13.5 V V DD = 15 V, V SS = -15 V V DD = 16.5 V, V SS = -16.5 V V DD = 18 V, V SS = -18 V V DD = 20 V, V SS = -20 V V DD = 22 V, V SS = -22 V Flatest RON region for all supply voltages shown Figure 6-3. On-Resistance vs Source or Drain Voltage V S or V D - Source or Drain Voltage (V) On Resistance ( ) -15 -12 -9 -6 -3 0 3 6 9 12 T A = − 40 C T A = 25 C T A = 85 C T A = 125 C 15 V Supply Flatest Ron Region Figure 6-4. On-Resistance vs Source or Drain Voltage V S or V D - Source or Drain Voltage (V) On Resistance ( ) -20 -16 -12 -8 -4 0 4 8 12 16 18 T A = − 40 CT A = 25 C T A = 85 C T A = 125 C 20 V Supply Flatest Ron Region Figure 6-5. On-Resistance vs Source or Drain Voltage V S or V D - Source or Drain Voltage (V) On Resistance ( ) 0 2 4 6 8 10 12 14 100 120 140 160 NOTE_U_L NOTE_U_L Single Supply Voltages V DD = 8 V, V SS = 0 V V DD = 8.8 V, V SS = 0 V V DD = 10.8 V, V SS = 0 V V DD = 12 V, V SS = 0 V V DD = 13.2 V, V SS = 0 V Figure 6-6. On-Resistance vs Source or Drain Voltage www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TMUX7436F
6.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted) V S or V D - Source or Drain Voltage (V) On Resistance ( ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9.1 9.2 Single Supply Flat Ron Region V DD = 8 V, V SS = 0 V V DD = 8.8 V, V SS = 0 V V DD = 10.8 V, V SS = 0 V V DD = 12 V, V SS = 0 V V DD = 13.2 V, V SS = 0 V Figure 6-7. On-Resistance vs Source or Drain Voltage V S or V D - Source or Drain Voltage (V) On Resistance ( ) 0 1 2 3 4 5 6 7 8 9 10 T A = 25 C T A = 85 C T A = 125 C T A = − 40 C
12 V DD Flatest Ron Region
Figure 6-8. On-Resistance vs Source or Drain Voltage V S or V D - Source or Drain Voltage (V) On Resistance ( ) 0 4 8 12 16 20 24 28 32 36 40 44 100 120 140 160 NOTE_U_L NOTE_U_L Single Supply Voltages V DD = 32.4 V, V SS = 0 V V DD = 36 V, V SS = 0 V V DD = 39.6 V, V SS = 0 V V DD = 44 V, V SS = 0 V Figure 6-9. On-Resistance vs Source or Drain Voltage V S or V D - Source or Drain Voltage (V) On Resistance ( ) 0 4 8 12 16 20 24 28 32 36 40 44 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9.1 9.2 9.3 NOTE_U_L NOTE_U_L Single Supply Flat Ron Region V DD = 32.4 V, V SS = 0 V V DD = 36 V, V SS = 0 V V DD = 39.6 V, V SS = 0 V V DD = 44 V, V SS = 0 V Figure 6-10. On-Resistance vs Source or Drain Voltage V S or V D - Source or Drain Voltage (V) On Resistance ( ) 0 4 8 12 16 20 24 28 32 34 T A = 25 C T A = 85 C T A = 125 C T A = − 40 C
36 V DD Flatest Ron Region
Figure 6-11. On-Resistance vs Source or Drain Voltage V S or V D - Source or Drain Voltage (V) On Resistance ( ) 0 4 8 12 16 20 24 28 32 36 40 42 T A = 25 C T A = 85 C T A = 125 C T A = − 40 C
44 V DD Flatest Ron Region
Figure 6-12. On-Resistance vs Source or Drain Voltage TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted) Temperature ( C) Leakage Current (nA) 0 20 40 60 80 100 120 V DD = 12 V, V SS = 0 V I ON V S = 1 V, V D = 1 V I DOFF V S = 1 V, V D = 10 V I SOFF V S = 1 V, V D = 10 V I DOFF V S = 10 V, V D = 1 V I SOFF V S = 10 V, V D = 1 V I ON V S = 10 V, V D = 10 V Figure 6-13. Leakage Current vs Temperature Temperature ( C) Leakage Current (nA) 0 20 40 60 80 100 120 V DD = 15 V, V SS = − 15 V I ON V S = − 10 V, V D = − 10 V I DOFF V S = − 10 V, V D = 10 V I SOFF V S = − 10 V, V D = 10 V I DOFF V S = 10 V, V D = − 10 V I SOFF V S = 10 V, V D = − 10 V I ON V S = 10 V, V D = 10 V Figure 6-14. Leakage Current vs Temperature Temperature ( C) Leakage Current (nA) 0 20 40 60 80 100 120 V DD = 36 V, V SS = 0 V I ON V S = 1 V, V D = 1 V I DOFF V S = 1 V, V D = 30 V I SOFF V S = 1 V, V D = 30 V I DOFF V S = 30 V, V D = 1 V I SOFF V S = 30 V, V D = 1 V I ON V S = 30 V, V D = 30 V Figure 6-15. Leakage Current vs Temperature Temperature ( C) Leakage Current (nA) 0 20 40 60 80 100 120 V DD = 20 V, V SS = − 20 V I ON V S = − 15 V, V D = − 15 V I DOFF V S = − 15 V, V D = 15 V I SOFF V S = − 15 V, V D = 15 V I DOFF V S = 15 V, V D = − 15 V I SOFF V S = 15 V, V D = − 15 V I ON V S = 15 V, V D = 15 V Figure 6-16. Leakage Current vs Temperature Temperature ( C) Leakage Current (nA) 0 20 40 60 80 100 120 15 V Dual Supply V S = -60 V, V D = 15 V V S = -30 V, V D = 15 V V S = 30 V, V D = -14 V V S = 60 V, V D = -14 V Figure 6-17. ID(FA) Overvoltage Leakage Current vs Temperature Temperature ( C) Leakage Current (nA) 0 20 40 60 80 100 120 20 V Dual Supply V S = -60 V, V D = 20 V V S = -30 V, V D = 20 V V S = 30 V, V D = -19 V V S = 60 V, V D = -19 V Figure 6-18. ID(FA) Overvoltage Leakage Current vs Temperature www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TMUX7436F
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted) Temperature ( C) Leakage Current (nA) 0 20 40 60 80 100 120 -2.5 2.5 7.5 12.5 17.5 22.5 V DD = 12 V Single Supply V S = -60 V, V D = 12 V V S = -30 V, V D = 12 V V S = 30 V, V D = 1 V V S = 60 V, V D = 1 V Figure 6-19. ID(FA) Overvoltage Leakage Current vs Temperature Temperature ( C) Leakage Current (nA) 0 20 40 60 80 100 120 V DD = 36 V Single Supply V S = -40 V, V D = 36 V V S = -30 V, V D = 36 V V S = 30 V, V D = 1 V V S = 60 V, V D = 1 V Figure 6-20. ID(FA) Overvoltage Leakage Current vs Temperature Temperature ( C) Leakage Current ( A) 0 20 40 60 80 100 120 -220 -180 -140 -100 -60 -20 100 15 V Dual Supply V S = -60 V V S = -30 V V S = 30 V V S = 60 V Figure 6-21. IS(FA) Overvoltage Leakage Current vs Temperature Frequency (Hz) THD+N (%) 0.0001 0.0002 0.0003 0.0005 0.001 0.002 0.003 0.005 0.01 0.02 0.03 0.05 0.1 0 4k 8k 12k 16k 20k V DD = 12 V, V SS = 0 V V DD = 15 V, V SS = -15 V V DD = 20 V, V SS = -20 V V DD = 36 V, V SS = 0 V Figure 6-22. THD+N vs Frequency V S - Source Voltage (V) Charge Injection (pC) -20 -16 -12 -8 -4 0 4 8 12 16 20 -500 -450 -400 -350 -300 -250 -200 -150 -100 -50 V DD = 15 V, V SS = -15 V V DD = 20 V, V SS = -20 V Figure 6-23. Charge Injection vs Source Voltage – Dual Supply V S - Source Voltage (V) Charge Injection (pC) 0 4 8 12 16 20 24 28 32 36 40 44 -450 -400 -350 -300 -250 -200 -150 -100 -50 V DD = 8 V, V SS = 0 V V DD = 12 V, V SS = 0 V V DD = 36 V, V SS = 0 V V DD = 44 V, V SS = 0 V Figure 6-24. Charge Injection vs Source Voltage – Single Supply TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted) Figure 6-25. Transition Times vs Temperature Temperature ( C) Time (ns) -40 -15 10 35 60 85 110 125 100 150 200 250 300 350 400 V DD : 8 V, V SS : 0 V, Falling Edge V DD : 8 V, V SS : 0 V, Rising Edge V DD : 12 V, V SS : 0 V, Falling Edge V DD : 12 V, V SS : 0 V, Rising Edge VDD = 36V, VSS = 0 V, Falling Edge VDD = 36V, VSS = 0 V, Rising Edge Figure 6-26. Transition Times vs Temperature Temperature ( C) Time (ns) -40 -15 10 35 60 85 110 125 100 150 200 250 300 350 400 450 500 T OFF 15V T ON 15V T OFF 20V T ON 20V Figure 6-27. Turn-On and Turn-Off Times vs Temperature Temperature ( C) Time (ns) -40 -15 10 35 60 85 110 125 100 150 200 250 300 350 400 450 T OFF +8V T ON +8V T OFF +12V T ON +12V T OFF +36V T ON +36V Figure 6-28. Turn-On and Turn-Off Times vs Temperature Frequency(Hz) Gain (dB) -130 -110 -90 -70 -50 -30 -10 1M 10M 100M 1G100k10k CrossTalk: Adjacent Channel CrossTalk: Nonadjacent Channel Off-Isolation Figure 6-29. Crosstalk and Off Isolation vs Frequency Frequency (Hz) Gain (dB) 100k 1M 10M 100M Figure 6-30. Insertion Loss vs Frequency www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TMUX7436F
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted) Temperature ( C) Threshold Voltage (V) -40 -15 10 35 60 85 110 125 0.4 0.5 0.6 0.7 0.8 0.9 V T Falling V T Rising Figure 6-31. Threshold Voltage vs Temperature Time ( s) Volts (V) -40 -20 0 20 40 60 80 100 120 DRAIN FF/SF SOURCE V DD Figure 6-32. Fault Response and Recovery Time ( s) Volts (V) -10 SOURCE 40V/ s Fault Ramp DRAIN V DD FF/SF Figure 6-33. Drain Output Response – Positive Overvoltage Time ( s) Volts (V) -2 -1 0 1 2 3 4 5 6 7 8 -35 -30 -25 -20 -15 -10 SOURCE 30V/ s Fault Ramp DRAIN V SS FF/SF Figure 6-34. Drain Output Response – Negative Overvoltage Time( s) Volts(V) -2 -1 0 1 2 3 4 5 SOURCE DRAIN V DD 40V/ s fault ramp Figure 6-35. Drain Output Recovery – Positive Overvoltage Time( s) Volts(V) 0.5 1 1.5 2 2.5 3 3.5 4 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 SOURCE DRAIN V SS 400V/ s fault ramp Figure 6-36. Drain Output Recovery – Negative Overvoltage TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of the TMUX7436F is the ohmic resistance across the source (Sx) and drain (Dx) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol R ON is used to denote on-resistance. Figure 7-1 shows the measurement setup used to measure R ON. ΔRON represents the difference between the R ON of any two channels, while R ON_FLAT denotes the flatness that is defined as the difference between the maximum and minimum value of on-resistance measured over the specified analog signal range. VDD VDD VSS VSS GND Sx Dx SW V IS 410 = 8 VS Figure 7-1. On-Resistance Measurement Setup
7.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state: 1. Source off-leakage current IS(OFF): the leakage current flowing into or out of the source pin when the switch is off. 2. Drain off-leakage current ID(OFF): the leakage current flowing into or out of the drain pin when the switch is off. Figure 7-2 shows the setup used to measure both off-leakage currents. S1A GND VS VD A Is (OFF) S1B VDD VSS IS(OFF) S1A GND VS VD S1B VDD VSS ID(OFF) ID (OFF) A S2A VS S2B ID (OFF) A VD S2A VS VD A Is (OFF) S2B VD Figure 7-2. Off-Leakage Measurement Setup www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TMUX7436F
7.3 On-Leakage Current
Source on-leakage current (I S(ON)) and drain on-leakage current (I D(ON)) denote the channel leakage currents when the switch is in the on state. I S(ON) is measured with the drain floating, while I D(ON) is measured with the source floating. Figure 7-3 shows the circuit used for measuring the on-leakage currents. S1A GND VS D1A Is (ON) S1B VDD VSS IS(ON) S1A GND VD S1B VDD VSS ID(ON) ID (ON) AN.C. N.C. N.C. S2A VS D2A Is (ON) S2B N.C. N.C. N.C. S2A VD S2B A N.C. N.C. Figure 7-3. On-Leakage Measurement Setup
7.4 Input and Output Leakage Current Under Overvoltage Fault
If any of the source pin voltage goes above the supplies (V DD or V SS) by one threshold voltage (V T), then the overvoltage protection feature of the TMUX7436F is triggered to turn off the switch under fault, keeping the fault channel in a high-impedance state. I S(FA) and I D(FA) denotes the input and output leakage current under overvoltage fault conditions, respectively. When the overvoltage fault occurs, the supply (or supplies) can either be in normal operating condition ( Figure 7-4 ) or abnormal operating condition ( Figure 7-5 ). During abnormal operating condition, the supply (or supplies) can either be unpowered (V DD= VSS = 0 V) or floating (V DD= VSS = no connection), and remains within the leakage performance specifications. S1A GND VS VD A IS (FA) S1B VDD VSS S2A VS VD A IS (FA) S2B A ID (FA) A ID (FA) N.C. N.C. IS(FA) / ID(FA) ( |VS| > |VDD + VT| or |VSS - VT| ) Figure 7-4. Measurement Setup for Input and Output Leakage Current under Overvoltage Fault With Normal Supplies TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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IS (FA) S1B S2A VS D2A IS (FA) S2B A ID (FA) A ID (FA) N.C. N.C. S1A GND VS D1A IS (FA) S1B S2A VS D2A IS (FA) S2B A ID (FA) A ID (FA) N.C. N.C. VDD VSS GND VDD VSS N.C. Unpowered (VDD = VSS = GND = 0 V) Floating (VDD = VSS = N.C.) Figure 7-5. Measurement Setup for Input and Output Leakage Current under Overvoltage Fault With Unpowered or Floating Supplies
7.5 Enable Delay Time
tON(EN) is defined as the time taken by the output of the TMUX7436F to rise to a 90% final value after the EN signal has past the 50% threshold. t OFF(EN) is defined as the time taken by the output of the TMUX7436F to fall to a 10% initial value after the EN signal has past the 50% threshold. Figure 7-6 shows the setup used to measure tON and tOFF. VDD VSS VDD VSS 0.1 µF 0.1 µF GNDVEN RL S1A D1 OutputVS S1B CL RL S2A D2 OutputVS S2B CL EN 3 V VEN 0 V 50% 50% tON(EN) tOFF(EN) 0.1 VS 0.9 VS Output VS tr < 20 ns tf < 20 ns Figure 7-6. Enable Delay Measurement Setup
7.6 Break-Before-Make Delay
The break-before-make delay is a safety feature of the TMUX7436F switch. The ON switches of the TMUX7436F first break the connection before the OFF switches make connection. The time delay between the break and the make is known as break-before-make delay. Figure 7-7 shows the setup used to measure break-before-make delay, denoted by the symbol tBBM. www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TMUX7436F
0.1 µF 0.1 µF S1A GND SELx VSEL VS S1B 3 V 0 V tBBM 1 0.8 VS Output 0 V tBBM = min ( tBBM 1, tBBM 2) tBBM 2 VSEL tr < 20 ns tf < 20 ns RL Output CL S2A S2B RL Output CL VS VS Figure 7-7. Break-Before-Make Delay Measurement Setup
7.7 Transition Time
Transition time is defined as the time taken by the output of the device to rise (to 90% of the transition) or fall (to 10% of the transition) after the select signal (SELx) has fallen or risen to 50% of the transition. Figure 7-8 shows the setup used to measure transition time, denoted by the symbol tTRAN. 3 V VSEL 0 V 50% 50% tTRAN 1 tTRAN 2 0.1 VS 0.9 VS Output tr < 20 ns tf < 20 ns RL VDD VSS VDD VSS 0.1 µF 0.1 µF S1A GND SELx Output 0 V VSEL VS S1B CL RL S2A D2 OutputVS S2B CL VS tTRAN = max ( tTRAN 1, tTRAN 2) Figure 7-8. Transition Time Measurement Setup
7.8 Fault Response Time
Fault response time (t RESPONSE) measures the delay between the source voltage exceeding the supply voltage (VDD or VSS) by 0.5 V and the drain voltage failing to 50% of the maximum output voltage. Figure 7-9 shows the setup used to measure tRESPONSE. TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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tRESPONSE (VDD) Output VDD + 0.5 V 0 V Output × 50% VDD VS 0 V tRESPONSE (VSS) Output VSS - 0.5 V 0 V Output × 50% VSS tRESPONSE = max ( tRESPONSE(VDD), tRESPONSE(VSS)) Max positive fault Max negative fault 60V/µs ramp
60 V/µs
0.1 µF 0.1 µF S1A GND D1 Output S1B CL RL S2A D2 Output S2B CL VS VS Figure 7-9. Fault Response Time Measurement Setup
7.9 Fault Recovery Time
Fault recovery time (t RECOVERY) measures the delay between the source voltage falling from overvoltage condition to below supply voltage (V DD or V SS) plus 0.5 V and the drain voltage rising from 0 V to 50% of the final output voltage. Figure 7-10 shows the setup used to measure tRECOVERY. RL VDD VSS VDD VSS 0.1 µF 0.1 µF S1A GND D1 Output S1B CL RL S2A D2 Output S2B CL VS VS VS tRECOVERY (VDD) Output VDD + 0.5 V 0 V Output × 50% Output 0 V tRECOVERY = max ( tRECOVERY(VDD), tRECOVERY(VSS)) 0 V VSS - 0.5 V 0 V Output x 50% tRECOVERY (VSS) VS Figure 7-10. Fault Recovery Time Measurement Setup
7.10 Fault Flag Response Time
Fault flag response time (t RESPONSE(FLAG)) measures the delay between the source voltage exceeding the fault supply voltage (V DD or V SS) by 0.5 V and the general fault flag (FF) pin to go below 10% of its original value. Figure 7-11 shows the setup used to measure tRESPONSE(FLAG). www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TMUX7436F
tRESPONSE(FLAG)_VDD VFF VDD + 0.5 V 0 V 0.5 V VS 0 V tRESPONSE(FLAG)_VSS VFN - 0.5 V tRESPONSE(FLAG) = max ( tRESPONSE(FLAG)_VDD, tRESPONSE(FLAG)_VSS) 5 V VFF 0.5 V 5 V 0 V CL_xF GND RPU 5 V RL VDD VSS VDD VSS 0.1 µF 0.1 µF S1A GND D1 Output S1B CL RL S2A D2 Output S2B CL VS VS SF/FF Figure 7-11. Fault Flag Response Time Measurement Setup
7.11 Fault Flag Recovery Time
Fault flag recovery time (t RECOVERY(FLAG)) measures the delay between the source voltage falling from overvoltage condition to below fault supply voltage (V DD or V SS) plus 0.5 V and the general fault flag (FF) pin to rise above 3 V with 5 V external pull-up. Figure 7-12 shows the setup used to measure tRECOVERY(FLAG). CL_xF GND RPU 5 V RL VDD VSS VDD VSS 0.1 µF 0.1 µF S1A GND D1 Output S1B CL RL S2A D2 Output S2B CL VS VS SF/FF tRECOVERY(FLAG)_VDD VFF 0 V 3 V tRECOVERY(FLAG)_VSS tRECOVERY(FLAG) = max ( tRECOVERY(FLAG)_VDD, tRECOVERY(FLAG)_VSS) 5 V 0 V 3 V 5 V VDD + 0.5 V 0 V VDD - 0.5 V 0 V VSVS VFF Figure 7-12. Fault Flag Recovery Time Measurement Setup TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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7.12 Charge Injection
Charge injection is a measure of the glitch impulse transferred from the logic input to the signal path during logic pin switching, and is denoted by the symbol QINJ. Figure 7-13 shows the setup used to measure charge injection from the source to drain. VDD VSS VDD VSS 0.1 µF 0.1 µF GNDVEN VOUT Output VD 0 V 3 V VEN QINJ = CL × VOUT tr < 20 ns tf < 20 ns S1A D1 Output S1B CL VS S2A D2 Output S2B CL VS EN Figure 7-13. Charge-Injection Measurement Setup
7.13 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the source pin (Sx) of an off-channel. Figure 7-14 shows the setup used to measure off isolation. GND S D VSIG VOUT50 Network Analyzer VDD VSS VDD VSS 0.1 µF 0.1 µF SxA / SxB / Dx VS Figure 7-14. Off Isolation Measurement Setup www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TMUX7436F
7.14 Crosstalk
The following are two types of crosstalk that can be defined for the devices: 1. Intra-channel crosstalk (XTALK(INTRA)): the voltage at the source pin (Sx) of an off-switch input, when a 1-VRMS signal is applied at the source pin of an on-switch input in the same channel, as shown in Figure 7-15. 2. Inter-channel crosstalk (XTALK(INTER)): the voltage at the source pin (Sx) of an on-switch input, when a 1-VRMS signal is applied at the source pin of an on-switch input in a different channel, as shown in Figure 7-16. GND S1A S1B VSIG VOUT50 Network Analyzer VDD VSS VDD VSS 0.1 µF 0.1 µF VS S2A S2B 50 Figure 7-15. Intra-Channel Crosstalk Measurement Setup GND S1A S1B VSIG VOUT50 Network Analyzer VDD VSS VDD VSS 0.1 µF 0.1 µF VS S2A S2B 50 Figure 7-16. Inter-Channel Crosstalk Measurement Setup TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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7.15 Bandwidth
Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. Figure 7-17 shows the setup used to measure bandwidth of the switch. GND S D VSIG VOUT50 Network Analyzer VDD VSS VDD VSS 0.1 µF 0.1 µF SxA / SxB / Dx VS Figure 7-17. Bandwidth Measurement Setup
7.16 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the switch output. The on-resistance of the device varies with the amplitude of the input signal and results in distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as THD+N. Figure 7-18 shows the setup used to measure THD+N of the devices. GND S D Audio Precision VOUT RL VDD VSS VDD VSS 0.1 µF 0.1 µF VS SxA / SxB / Dx Figure 7-18. THD+N Measurement Setup www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TMUX7436F
8 Detailed Description
8.1 Overview
The TMUX7436F device is a 44-V fault protected multiplexer with latch-up immunity in a 2:1, 2 channel configuration. The device works well with dual supplies (±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as VDD = 15 V, VSS = –5 V). The overvoltage protection feature on the source pins works under powered and powered-off conditions, allowing for use in harsh industrial environments. The powered-off condition includes floating power supplies, grounded power supplies, or power supplies at any level that are below the undervoltage (UV) threshold.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Flat ON-Resistance
The TMUX7436F is designed with a special switch architecture to produce ultra-flat on-resistance (R ON) across most of the switch input operation region. The flat RON response allows the device to be used in precision sensor applications since the R ON is controlled regardless of the signals sampled. The architecture is implemented without a charge pump so no unwanted noise is produced from the device to affect sampling accuracy.
8.3.2 Protection Features
The TMUX7436F offers a number of protection features to enable robust system implementations.
8.3.2.1 Input Voltage Tolerance
The maximum voltage that can be applied to any source input pin is +60 V or –60 V, regardless of supply voltage. This allows the device to handle typical voltage fault condition in industrial applications. Caution: the device is rated to handle a maximum stress of 85 V across different pins, such as the following: 1. Between source pins and supply rails: 85 V For example, if the device is powered by VDD supply of 25 V, then the maximum negative signal level on any source pin is –60 V to maintain the 60 V maximum rating on any source pin. If the device is powered by VDD supply of 40 V, then the maximum negative signal level on any source pin is reduced to –45 V to maintain the 85 V maximum rating across the source pin and the supply. 2. Between source pins and the drain pin: 85 V For example, if channel S1A is ON and the voltage on S1A pin is 40 V, then the drain voltage D1 is also 40 V. In this case, the maximum negative voltage allowed on S1B is –45 V to maintain the 85 V maximum rating across the source pin and the drain pin. TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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8.3.2.2 Powered-Off Protection
When the supplies of TMUX7436F are removed (V DD/ VSS = 0 V or floating), the source (Sx) pins of the device remain in high impedance (Hi-Z) state, and the source (Sx) and drain (Dx) pins of the device remain within the leakage performance mentioned in the Electrical Characteristics. Powered-off protection minimizes system complexity by removing the need to control power supply sequencing of the system. The feature prevents errant voltages on the input source pins from reaching the rest of the system and maintains isolation when the system is powering up. Without powered-off protection, signals on the input source pins can back-power the supply rails through internal ESD diodes and cause potential damage to the system. For more information on powered-off protection, refer to the Eliminate Power Sequencing with Powered-Off Protection Signal Switches application brief. A GND reference must always be present to ensure proper operation. Source and drain voltage levels of up to ±60 V are blocked in the powered-off condition.
8.3.2.3 Fail-Safe Logic
Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting the device from potential damage. The switch is specified to be in the OFF state, regardless of the state of the logic signals. The logic inputs are protected against positive faults of up to +44 V in powered-off condition, but do not offer protection against negative overvoltage condition. Fail-safe logic also allows the TMUX7436F device to interface with a voltage greater than V DD during normal operation to add maximum flexibility in system design. For example, with a V DD of = 15 V, the logic control pins could be connected to +24 V for a logic high signal which allows different types of signals, such as analog feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the logic inputs can be interfaced as high as 44 V.
8.3.2.4 Overvoltage Protection and Detection
The TMUX7436F detects overvoltage inputs by comparing the voltage on a source pin (Sx) with the supplies (VDD and VSS). A signal is considered overvoltage if it exceeds the supply voltages by the threshold voltage (VT). The switch automatically turns OFF regardless of the logic controls when an overvoltage is detected. The source pin becomes high impedance and ensures only small leakage current flows through the switch. The drain pin (Dx) behavior can be adjusted by controlling the drain response (DR) pin in the following ways: 1. DR pin floating or driven above VIH: If the DR pin is driven above VIH level of the pin, then the drain pin becomes high impedance (Hi-Z) upon overvoltage fault. 2. DR driven below VIL: If the DR pin is driven below VIL level of the pin, and the channel expeirencing the overvoltage fault condition is currently being selected by the logic controls (EN, SELx), then the drain pin (Dx) is pulled to the supply that was exceeded through a 40 kΩ resistor. For example, if the source voltage exceeds VDD, then the drain output is pulled to VDD. If the source voltage exceeds VSS, then the drain output is pulled to VSS. The pull-up/pull-down impedance is approximately 40 kΩ, and as a result, the drain current is limited during a shorted load (to GND) condition. Figure 8-1 shows a detailed view of the how the DR pin, SELx pin, and EN pin controls the output state of the drain pin under a fault scenario. www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TMUX7436F
Logic & Fault Detection 40 k 40 k SELx EN DR Figure 8-1. Detailed Functional Diagram
8.3.2.5 Adjacent Channel Operation During Fault
When the logic pins are set to a channel under a fault, the overvoltage detection will trigger, the switch will open, and the drain pin will operate as described in Section 8.3.2.4. During such an event, all other channels not under a fault can continue to operate as normal. For example, if S1A voltage exceeds V DD, and the logic pins are set to S1A, and the DR pin is set to logic low, then the drain output is pulled to V DD. Afterwards if the logic pins are changed to set S1B, which is not in overvoltage or undervoltage, then the drain will disconnect from the pullup to VDD and the S1B switch will be enabled and connected to the drain, operating as normal, although there is still an overvoltage condition present on S1A. If the logic pins are switched back to S1A, then the S1B switch will be disabled, the drain pin will be pulled up to V DD again, and the switch from S1A to drain will be disabled until the overvoltage fault is removed.
8.3.2.6 ESD Protection
All pins on the TMUX7436F support HBM ESD protection level up to ±6 kV, which helps prevent the device from being damaged by ESD events during the manufacturing process. The drain pins (Dx) have internal ESD protection diodes to the supplies V DD and V SS; therefore the voltage at the drain pins must not exceed the supply voltages to prevent excessive diode current. The source pins have specialized ESD protection that allows the signal voltage to reach ±60 V regardless of supply voltage level. Exceeding ±60 V on any source input may damage the ESD protection circuitry on the device and cause the device to malfunction if the damage is excessive.
8.3.2.7 Latch-Up Immunity
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the low impedance path. The TMUX7436F device is constructed on silicon on insulator (SOI) based process where an oxide layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events due to overvoltage or current injections. The latch-up immunity feature allows the TMUX7436F to be used in harsh environments. For more information on latch-up immunity, refer to Using Latch Up Immune Multiplexers to Help Improve System Reliability. TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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8.3.2.8 EMC Protection
The TMUX7436F is not intended for standalone electromagnetic compatibility (EMC) protection in industrial applications. There are three common high voltage transient specifications that govern industrial high voltage transient specification: IEC61000-4-2 (ESD), IEC61000-4-4 (EFT), and IEC61000-4-5 (surge immunity). A transient voltage suppressor (TVS), along with some low-value series current limiting resistor, are required to prevent source input voltages from going above the rated ±60 V limits. When selecting a TVS protection device, it is critical to ensure that the maximum working voltage is greater than both the normal operating range of the input source pins to be protected and any known system common-mode overvoltage that may be present due to miswiring, loss of power, or short circuit. Figure 8-2 shows an example of the proper design window when selecting a TVS device. Region 1 denotes normal operation region of TMUX7436F, where the input source voltages stay below the supplies VDD and VSS. Region 2 represents the range of possible persistent DC (or long duration AC overvoltage fault) presented on the source input pins. Region 3 represents the margin between any known DC overvoltage level and the absolute maximum rating of the TMUX7436F. The TVS breakdown voltage must be selected to be less than the absolute maximum rating of the TMUX7436F, but greater than any known possible persistent DC or long duration AC overvoltage fault to avoid triggering the TVS inadvertently. Region 4 represents the margin system designers must impose when selecting the TVS protection device to prevent accidental triggering of ESD cells of the TMUX7436F device. Normal Operation Positive Supply VDD System Overvoltage Overvoltage Protection Window Device Absolute Max Rating Internal ESD Trigger Voltage TVS Breakdown Voltage Negative Supply VSS 0 V Overvoltage Protection Window TVS Breakdown Voltage System Overvoltage Device Absolute Max Rating Internal ESD Trigger Voltage Figure 8-2. System Operation Regions and Proper Region of Selecting a TVS Protection Device
8.3.3 Overvoltage Fault Flags
The voltages on the source input pins of the TMUX7436F are continuously monitored, and the status of whether an overvoltage condition occurs is indicated by an active low general fault flag (FF). The voltage on the FF pin indicates if any of the source input pins are experiencing an overvoltage condition. If any source pin voltage exceeds the fault supply voltages by a VT, then the FF output is pulled-down to below VOL. The specific fault (SF) output pins, on the other hand, can be used to decode which inputs are experiencing an overvoltage condition. As provided in the Table 8-1, the SF pin is pulled-down to below VOL when an overvoltage condition is detected on a specific source input pin, depending on the state of the SEL1, SEL2, and EN logic pins. www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TMUX7436F
Both the FF pin and the SF pin are an open-drain output and an external pull-up resistor of 1 k Ω is recommended. The pull-up voltage can be in the range of 1.8 V to 5.5 V, depending on the controller voltage the device interfaces with.
8.3.4 Bidirectional Operation
The TMUX7436F conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). However, it is noted that the overvoltage protection is implemented only on the source (Sx) side. The voltage on the drain is only allowed to swing between V DD and VSS and no overvotlage protection is available on the drain side. The flatest on-resistance region extends from VSS to roughly 3 V below VDD. Once the signal is within 3 V of VDD the on-resistance will expoentially increase and may impact desired signal transmission. 8.3.5 1.8 V Logic Compatible Inputs The TMUX7436F device has 1.8 V logic compatible control for all logic control inputs. 1.8 V logic level inputs allows the TMUX7436F to interface with processors that have lower logic I/O rails and eliminates the need for an external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations, refer to Simplifying Design with 1.8 V logic Muxes and Switches.
8.3.6 Integrated Pull-Down Resistor on Logic Pins
The TMUX7436F has internal weak pull-down resistors to GND to ensure the logic pins are not left floating. The value of this pull-down resistor is approximately 4 M Ω, but is clamped to about 1 µA at higher voltages. This feature integrates up to four external components and reduces system size and cost.
8.4 Device Functional Modes
The TMUX7436F offers two modes of operation (normal mode and fault mode) depending on whether any of the input pins experience an overvoltage condition.
8.4.1 Normal Mode
In Normal mode operation, signals of up to V DD and VSS can be passed through the switch from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). As provided in Table 8-1, the select pins (SELx) and enable pin (EN) determines which switch path to turn on. The following conditions must be satisfied for the switch to stay in the ON condition:
- The difference between the supples (VDD – VSS) must be greater than or equal to 8 V, with a minimum VDD of 5 V.
- The input signals on the source (Sx) or the drain (Dx) must be be between VDD+ VT and VSS – VT.
- The logic control (SELx and EN) must have selected the switch.
8.4.2 Fault Mode
The TMUX7436F enters into Fault mode when any of the input signals on the source (Sx) pins exceed V DD or V SS by a threshold voltage V T. Under the overvoltage condition, the switch input experiencing the fault automatically turns off regardless of the logic status, and the source pin becomes high impedance with negligible amount of leakage current flowing through the switch. For more information about how the drain pain (Dx) behavior under the Fault mode can be programmed, see Section 8.3.2.4. In the Fault mode, the general fault flag (FF) is asserted low. Table 8-1 provides how the specific flag (SF) is asserted low depending on the status of the logic control pins SELx and EN. The overvoltage protection is provided only for the source (Sx) input pins. The drain (Dx) pin, if used as signal input, must stay in between VDD and VSS at all times since no overvoltage protection is implemented on the drain pin. TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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8.4.3 Truth Tables
Table 8-1 and Table 8-2 provides the truth tables for the TMUX7436F under normal and fault conditions. Table 8-1. TMUX7436F Truth Table EN SEL2 SEL1 Normal Condition Fault Condition State of Specific Flag (SF) when fault occurs on On Switch S1A S1B S2A S2B 0 0 0 None 0 1 1 1 0 0 1 None 1 0 1 1 0 1 0 None 1 1 1 0 0 1 1 None 1 1 0 1 1 0 0 S1B, S2B 0 1 1 1 1 0 1 S1A, S2B 1 0 1 1 1 1 0 S1B, S2A 1 1 1 0 1 1 1 S1A, S2A 1 1 0 1 Take note, more than one source pin can be in fault at a given time. As Table 8-1 provides, the SF pin will assert low even when multiple source pins are under fault. Table 8-2. TMUX7436F DR Truth Table DR PIN STATE Dx State During Fault Condition
0 Pulled up to VDD or VSS
1 Open (HI-Z)
If unused, then SELx pins must be tied to GND to ensure the device does not consume additional current (for more information, refer to Implications of Slow or Floating CMOS Inputs . Unused signal path inputs (Sx or Dx) should be connected to GND. www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TMUX7436F
9 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
9.1 Application Information
The TMUX7436F is a part of the fault protected switches and multiplexers family of devices. The abilty to protect downstream components from overvoltage events up to ±60 V and latch-up immunity features makes these switches and multiplexers suitable for harsh environments.
9.2 Typical Application
The need to monitor remote sensors is common among factory automation control systems. For example, an analog input module or mixed module (AI, AO, DI, and DO) of a programmable logic controller (PLC) will interface to a field transmitter to monitor various process sensors at remote locations around the factory. A switch or multiplexer is often used to connect multiple inputs from the system and reduce the number of downstream channels. There are a number of fault cases that may occur that can be damaging to many of the integrated circuits. Such fault conditions may include, but are not limited to, human error from wiring the connections incorrectly, component failure, wire shorts, electromagnetic interference (EMI), transient distrubances, and more. Power Module Local Control Side GND Supply Fault Protected Mux Inputs TMUX7436F VDD VSS +15V -15V +15V -15V Logic Select Pins 1.8V Logic SignalsSEL1 SEL2 Di eren al Output Di eren al Output Field Side Control & ProcessingADC DAC Sensors Sensors Sensors Sensors RG ADC +60V +24V S2A S2B S1A S1B Figure 9-1. Typical Application TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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9.2.1 Design Requirements
Table 9-1. Design Parameters PARAMETER VALUE Positive supply (VDD) mux +15 V Negative supply (VSS) mux −15 V Power board supply voltage 24 V Input or output signal range non-faulted −15 V to 15 V Overvoltage protection levels −60 V to 60 V Control logic thresholds 1.8 V compatible, up to 44 V Temperature range −40°C to +125°C
9.2.2 Detailed Design Procedure
The normal operation of the application is to take multiple differential inputs and use a 2:1 multiplexer to pass the signal to the downstream instrumentation amplifier. A fault protected switch can add extra robustness to the sytem against fault conditions while also reducing the number of components required to interface with the systems physical input channels. The Figure 9-1 shows the case where a human wired the condition incorrectly and one of the input connectors shorted to the power board supply voltage. If the board supply voltage is higher than the power supply of the multiplexer, then the TMUX7436F device will disconnect the source input from passing the signal to protect the downstream components. The drain pin of the channels can either be pulled up to the supply voltage (V DD and VSS) through a 40 k Ω resistor or be left floating depending on the state of the DR pin. This can be configured to match the system requirements on how to handle a fault condition.
9.2.3 Application Curves
The previous example shows how the fault protection of the TMUX7436F is utilized to protect downstream components from damage due to wiring the connections incorrectly from the power module. Figure 9-2 shows an example of positive overvoltage fault response with a fast fault ramp rate of 40 V/µs. Figure 9-3 shows the extremely flat on-resistance across source voltage while operating within a common signal range of ±10 V. These features make the TMUX7436F an ideal solution for factory automation applications that can face various fault conditions but also require excellent linearity and low distortion. Time ( s) Volts (V) -10 SOURCE 40V/ s Fault Ramp DRAIN V DD FF/SF Figure 9-2. Positive Overvoltage Response V S or V D - Source or Drain Voltage (V) On Resistance ( ) -10 -8 -6 -4 -2 0 2 4 6 8 10 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9.1 9.2 9.3 V DD = 13.5 V, V SS = -13.5 V V DD = 15 V, V SS = -15 V V DD = 16.5 V, V SS = -16.5 V V DD = 18 V, V SS = -18 V V DD = 20 V, V SS = -20 V V DD = 22 V, V SS = -22 V Figure 9-3. RON Flatness in Non-Fault Region www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TMUX7436F
10 Power Supply Recommendations
The TMUX7436F operates across a wide supply range of ±5 V to ±22 V (8 V to 44 V in single-supply mode). It also performs well with asymmetrical supplies such as V DD = 12 V and V SS = –5 V. Use a supply decoupling capacitor ranging from 1 µF to 10 µF at the V DD and V SS pins to ground for improved supply noise immunity. Always ensure the ground (GND) connection is established before supplies are ramped.
11 Layout
11.1 Layout Guidelines
Figure 11-1 and Figure 11-2 shows an example of a PCB layout with the TMUX7436F. The following are some key considerations:
- Decouple the VDD and VSS pins with a 1-µF capacitor, placed as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
- Multiple decoupling capacitors can be used if their is a lot of noise in the system. For example, a 0.1-µF and 1-µF can be placed on the supply pins. If multiple capacitors are used, placing the lowest value capacitor closest to the supply pin is recommended.
- Keep the input lines as short as possible.
- Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
- Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
C SEL2DR C Via to power plane Figure 11-1. TSSOP Layout Example C S1ADR D1 EN SEL1SEL2 S1B VDD SFN.C. VSS S2B FFS2A C Via to ground plane C C Wide (low inductance) trace for power Wide (low inductance) trace for power GND 1kΩ 1kΩ Wide (low inductance) trace for power Figure 11-2. WQFN Layout Example TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 www.ti.com
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
- Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
- Texas Instruments, Improving Analog Input Modules Reliability Using Fault Protected Multiplexers application report
- Texas Instruments, Multiplexers and Signal Switches Glossary application report
- Texas Instruments, Protection Against Overvoltage Events, Miswiring, and Common Mode Voltages application report
- Texas Instruments, Using Latch-Up Immune Multiplexers to Help Improve System Reliability application report
- Texas Instruments, Using Latch Up Immune Multiplexers to Help Improve System Reliability
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TMUX7436F SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: TMUX7436F
www.ti.com 7-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTMUX7436FPWR ACTIVE TSSOP PW 16 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 28-Nov-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 28-Nov-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMUX7436FPWR TSSOP PW 16 3000 356.0 356.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.19 TYP6.6 6.2
1.2 MAX
0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 5.1 4.9 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017
0.1 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9
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