PTMUX7219RQXR

TMUX7219_V02 TI | Alldatasheet

Document overview

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Technical content

TMUX7219 44-V, Latch-Up Immune, 2:1 (SPDT) Precision Switch with 1.8-V Logic

1 Features

• Latch-up immune
• Dual supply range: ±4.5 V to ±22 V
• Single supply range: 4.5 V to 44 V
• Low on-resistance: 2.1 Ω
• Low charge injection: −10 pC
• High current support: 330 mA (maximum) (VSSOP)
• High current support: 440 mA (maximum) (WSON)
• –40°C to +125°C operating temperature
• 1.8 V logic compatible
• Fail-safe logic
• Rail-to-rail operation
• Bidirectional signal path
• Break-before-make switching

2 Applications

• Factory automation and industrial controls
• Programmable logic controllers (PLC)
• Analog input modules
• Semiconductor test
• AC charging (Pile) station
• Ultrasound scanners
• Patient monitoring and diagnostics
• Optical networking
• Optical test equipment
• Remote radio units
• Wired networking
• Data acquisition systems
• Gas meters
• Flow transmitters

3 Description

The TMUX7219 is a complementary metal-oxide semiconductor (CMOS) switch with latch-up immunity in a single channel, 2:1 (SPDT) configuration. The device works with a single supply (4.5 V to 44 V), dual supplies (±4.5 V to ±22 V) , or asymmetric supplies (such as V DD = 12 V, V SS = –5 V). The TMUX7219 supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from V SS to VDD. The TMUX7219 can be enabled or disabled by controlling the EN pin. When disabled, both signal path switches are off. When enabled, the SEL pin can be used to turn on signal path 1 (S1 to D) or signal path 2 (S2 to D). All logic control inputs support logic levels from 1.8 V to V DD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage. The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TMUX7219 VSSOP (8) DGK 3.00 mm × 3.00 mm WSON (8) RQX 3.00 mm × 2.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. EN D VDD VSS Decoder SEL Block Diagram TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

12.2 Receiving Notification of Documentation Updates..36

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (March 2022) to Revision E (August 2022) Page Changes from Revision C (December 2020) to Revision D (March 2022) Page Changes from Revision B (December 2020) to Revision C (December 2020) Page TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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5 Pin Configuration and Functions

Figure 5-1. DGK Package, 8-Pin VSSOP (Top View)

8 S21D

7 VSS2S1

6 SEL3GND

5 EN4VDD

Figure 5-2. RQX Package, 8-Pin WSON (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION(2) NAME RQX DGK D 1 1 I/O Drain pin. Can be an input or output. S1 2 2 I/O Source pin 1. Can be an input or output. GND 3 3 P Ground (0 V) reference VDD 4 4 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. EN 5 5 I Active high logic enable, has internal pull-up resistor. When this pin is low, all switches are turned off. When this pin is high, the SEL logic input determine which switch is turned on. SEL 6 6 I Logic control input, has internal pull-down resistor. Controls the switch connection as shown in Section 8.5. VSS 7 7 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. S2 8 8 I/O Source pin 2. Can be an input or output. Thermal Pad — — The thermal pad is not connected internally. There is no requirement to electrically connect this pad. If connected, it is recommended that the pad be left floating or tied to GND. (1) I = input, O = output, I/O = input and output, P = power. (2) Refer to Section 8.4 for what to do with unused pins. www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TMUX7219

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT VDD – VSS Supply voltage 48 V VDD –0.5 48 V VSS –48 0.5 V VSEL or VEN Logic control input pin voltage (SEL, EN)(3) –0.5 48 V ISEL or IEN Logic control input pin current (SEL, EN)(3) –30 30 mA VS or VD Source or drain voltage (Sx, D)(3) VSS–0.5 VDD+0.5 V IIK Diode clamp current(3) –30 30 mA IS or ID (CONT) Source or drain continuous current (Sx, D) IDC + 10 %(4) mA TA Ambient temperature –55 150 °C Tstg Storage temperature –65 150 °C TJ Junction temperature 150 °C Ptot Total power dissipation(5) 460 mW (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltages are with respect to ground, unless otherwise specified. (3) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings. (4) Refer to Source or Drain Continuous Current table for IDC specifications. (5) For DGK package: Ptot derates linearily above TA = 70°C by 6.7mW/°C.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), ANSI/ESDA/ JEDEC JS-002, all pins (2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Thermal Information

THERMAL METRIC(1) TMUX7219 TMUX7219 UNITDGK (VSSOP) RQX (WSON)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 152.1 62.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.4 54.0 °C/W RθJB Junction-to-board thermal resistance 73.2 31.0 °C/W ΨJT Junction-to-top characterization parameter 4.1 0.8 °C/W ΨJB Junction-to-board characterization parameter 71.8 30.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 23.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD – VSS (1) Power supply voltage differential 4.5 44 V VDD Positive power supply voltage 4.5 44 V VS or VD Signal path input/output voltage (source or drain pin) (Sx, D) VSS VDD V VSEL or VEN Address or enable pin voltage 0 44 V IS or ID (CONT) Source or drain continuous current (Sx, D) IDC (2) mA TA Ambient temperature –40 125 °C (1) VDD and VSS can be any value as long as 4.5 V ≤ (VDD – VSS) ≤ 44 V, and the minimum VDD is met. (2) Refer to Source or Drain Continuous Current table for IDC specifications.

6.5 Source or Drain Continuous Current

at supply voltage of VDD ± 10%, VSS ± 10 % (unless otherwise noted) CONTINUOUS CURRENT PER CHANNEL (IDC) TA = 25°C TA = 85°C TA = 125°C UNIT PACKAGE TEST CONDITIONS RQX (WSON) +44 V Single Supply(1) 440 270 130 mA ±15 V Dual Supply 440 270 130 mA +12 V Single Supply 330 200 105 mA ±5 V Dual Supply 330 200 105 mA +5 V Single Supply 230 140 90 mA DGK (VSSOP) +44 V Single Supply(1) 330 210 120 mA ±15 V Dual Supply 330 210 120 mA +12 V Single Supply 240 160 100 mA ±5 V Dual Supply 240 160 100 mA +5 V Single Supply 180 120 80 mA (1) Specified for nominal supply voltage only. www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TMUX7219

6.6 ±15 V Dual Supply: Electrical Characteristics VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = –10 V to +10 V ID = –10 mA Refer to On-Resistance 25°C 2.1 2.9 Ω –40°C to +85°C 3.8 Ω –40°C to +125°C 4.5 Ω ΔRON On-resistance mismatch between channels VS = –10 V to +10 V ID = –10 mA Refer to On-Resistance 25°C 0.05 0.25 Ω –40°C to +85°C 0.3 Ω –40°C to +125°C 0.35 Ω RON FLAT On-resistance flatness VS = –10 V to +10 V IS = –10 mA Refer to On-Resistance 25°C 0.5 0.6 Ω –40°C to +85°C 0.7 Ω –40°C to +125°C 0.85 Ω RON DRIFT On-resistance drift VS = 0 V, IS = –10 mA Refer to On-Resistance –40°C to +125°C 0.01 Ω/°C IS(OFF) Source off leakage current(1) VDD = 16.5 V, VSS = –16.5 V Switch state is off VS = +10 V / –10 V VD = –10 V / + 10 V Refer to Off-Leakage Current 25°C –0.15 0.05 0.15 nA –40°C to +125°C –15 15 nA ID(OFF) Drain off leakage current(1) VDD = 16.5 V, VSS = –16.5 V Switch state is off VS = +10 V / –10 V VD = –10 V / + 10 V Refer to Off-Leakage Current 25°C –1 0.05 1 nA –40°C to +85°C –3 3 nA –40°C to +125°C –26 26 nA IS(ON) ID(ON) Channel on leakage current(2) VDD = 16.5 V, VSS = –16.5 V Switch state is on VS = VD = ±10 V Refer to On-Leakage Current 25°C –1 0.04 1 nA –40°C to +125°C –18 18 nA LOGIC INPUTS (SEL / EN pins) VIH Logic voltage high –40°C to +125°C 1.3 44 V VIL Logic voltage low –40°C to +125°C 0 0.8 V IIH Input leakage current –40°C to +125°C 0.005 1 µA IIL Input leakage current –40°C to +125°C –1 –0.005 µA CIN Logic input capacitance –40°C to +125°C 3 pF POWER SUPPLY IDD VDD supply current VDD = 16.5 V, VSS = –16.5 V Logic inputs = 0 V, 5 V, or VDD 25°C 30 40 µA –40°C to +85°C 48 µA –40°C to +125°C 62 µA ISS VSS supply current VDD = 16.5 V, VSS = –16.5 V Logic inputs = 0 V, 5 V, or VDD 25°C 3 10 µA –40°C to +85°C 15 µA –40°C to +125°C 25 µA (1) When VS is positive, VD is negative, or when VS is negative, VD is positive. (2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating. TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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6.7 ±15 V Dual Supply: Switching Characteristics VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT tTRAN Transition time from control input VS = 10 V RL = 300 Ω, CL = 35 pF Refer to Transition Time 25°C 120 175 ns –40°C to +85°C 190 ns –40°C to +125°C 210 ns tON (EN) Turn-on time from enable VS = 10 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time 25°C 100 170 ns –40°C to +85°C 185 ns –40°C to +125°C 200 ns tOFF (EN) Turn-off time from enable VS = 10 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time 25°C 100 180 ns –40°C to +85°C 195 ns –40°C to +125°C 210 ns tBBM Break-before-make time delay VS = 10 V, RL = 300 Ω, CL = 35 pF Refer to Break-Before-Make 25°C 50 ns –40°C to +85°C 1 ns –40°C to +125°C 1 ns TON (VDD) Device turn on time (VDD to output) VDD rise time = 100 ns RL = 300 Ω, CL = 35 pF Refer to Turn-on (VDD) Time 25°C 0.19 ms –40°C to +85°C 0.2 ms –40°C to +125°C 0.2 ms tPD Propagation delay RL = 50 Ω , CL = 5 pF Refer to Propagation Delay 25°C 700 ps QINJ Charge injection VD = 0 V, CL = 1 nF Refer to Charge Injection 25°C –10 pC OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 0 V, f = 100 kHz Refer to Off Isolation 25°C –75 dB OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 0 V, f = 1 MHz Refer to Off Isolation 25°C –55 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 0 V, f = 100 kHz Refer to Crosstalk 25°C –117 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 0 V, f = 1 MHz Refer to Crosstalk 25°C –106 dB BW –3dB Bandwidth RL = 50 Ω , CL = 5 pF VS = 0 V Refer to Bandwidth 25°C 40 MHz IL Insertion loss RL = 50 Ω , CL = 5 pF VS = 0 V, f = 1 MHz 25°C –0.18 dB ACPSRR AC Power Supply Rejection Ratio VPP = 0.62 V on VDD and VSS RL = 50 Ω , CL = 5 pF, f = 1 MHz Refer to ACPSRR 25°C –64 dB THD+N Total Harmonic Distortion + Noise VPP = 15 V, VBIAS = 0 V RL = 10 kΩ , CL = 5 pF, f = 20 Hz to 20 kHz Refer to THD + Noise 25°C 0.0005 % CS(OFF) Source off capacitance VS = 0 V, f = 1 MHz 25°C 33 pF CD(OFF) Drain off capacitance VS = 0 V, f = 1 MHz 25°C 48 pF CS(ON), CD(ON) On capacitance VS = 0 V, f = 1 MHz 25°C 148 pF www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TMUX7219

6.8 ±20 V Dual Supply: Electrical Characteristics VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = –15 V to +15 V ID = –10 mA Refer to On-Resistance 25°C 1.9 2.7 Ω –40°C to +85°C 3.5 Ω –40°C to +125°C 4.2 Ω ΔRON On-resistance mismatch between channels VS = –15 V to +15 V ID = –10 mA Refer to On-Resistance 25°C 0.04 0.22 Ω –40°C to +85°C 0.28 Ω –40°C to +125°C 0.3 Ω RON FLAT On-resistance flatness VS = –15 V to +15 V IS = –10 mA Refer to On-Resistance 25°C 0.3 0.75 Ω –40°C to +85°C 0.9 Ω –40°C to +125°C 1.2 Ω RON DRIFT On-resistance drift VS = 0 V, IS = –10 mA Refer to On-Resistance –40°C to +125°C 0.009 Ω/°C IS(OFF) Source off leakage current(1) VDD = 22 V, VSS = –22 V Switch state is off VS = +15 V / –15 V VD = –15 V / + 15 V Refer to Off-Leakage Current 25°C –1.5 0.05 1.5 nA –40°C to +85°C –4 4 nA –40°C to +125°C –24 24 nA ID(OFF) Drain off leakage current(1) VDD = 22 V, VSS = –22 V Switch state is off VS = +15 V / –15 V VD = –15 V / + 15 V Refer to Off-Leakage Current 25°C –2 0.1 2 nA –40°C to +85°C –8 8 nA –40°C to +125°C –44 44 nA IS(ON) ID(ON) Channel on leakage current(2) VDD = 22 V, VSS = –22 V Switch state is on VS = VD = ±15 V Refer to On-Leakage Current 25°C –2 0.1 2 nA –40°C to +85°C –5 5 nA –40°C to +125°C –29 29 nA LOGIC INPUTS (SEL / EN pins) VIH Logic voltage high –40°C to +125°C 1.3 44 V VIL Logic voltage low –40°C to +125°C 0 0.8 V IIH Input leakage current –40°C to +125°C 0.005 1 µA IIL Input leakage current –40°C to +125°C –1 –0.005 µA CIN Logic input capacitance –40°C to +125°C 3 pF POWER SUPPLY IDD VDD supply current VDD = 22 V, VSS = –22 V Logic inputs = 0 V, 5 V, or VDD 25°C 34 44 µA –40°C to +85°C 50 µA –40°C to +125°C 65 µA ISS VSS supply current VDD = 22 V, VSS = –22 V Logic inputs = 0 V, 5 V, or VDD 25°C 4 9 µA –40°C to +85°C 12 µA –40°C to +125°C 25 µA (1) When VS is positive, VD is negative, or when VS is negative, VD is positive. (2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating. TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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6.9 ±20 V Dual Supply: Switching Characteristics VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT tTRAN Transition time from control input VS = 10 V RL = 300 Ω, CL = 35 pF Refer to Transition Time 25°C 110 175 ns –40°C to +85°C 190 ns –40°C to +125°C 205 ns tON (EN) Turn-on time from enable VS = 10 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time 25°C 110 170 ns –40°C to +85°C 185 ns –40°C to +125°C 200 ns tOFF (EN) Turn-off time from enable VS = 10 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time 25°C 90 180 ns –40°C to +85°C 190 ns –40°C to +125°C 200 ns tBBM Break-before-make time delay VS = 10 V, RL = 300 Ω, CL = 35 pF Refer to Break-Before-Make 25°C 55 ns –40°C to +85°C 1 ns –40°C to +125°C 1 ns TON (VDD) Device turn on time (VDD to output) VDD rise time = 100 ns RL = 300 Ω, CL = 35 pF Refer to Turn-on (VDD) Time 25°C 0.18 ms –40°C to +85°C 0.2 ms –40°C to +125°C 0.2 ms tPD Propagation delay RL = 50 Ω , CL = 5 pF Refer to Propagation Delay 25°C 715 ps QINJ Charge injection VD = 0 V, CL = 1 nF Refer to Charge Injection 25°C –15 pC OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 0 V, f = 100 kHz Refer to Off Isolation 25°C –75 dB OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 0 V, f = 1 MHz Refer to Off Isolation 25°C –55 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 0 V, f = 100 kHz Refer to Crosstalk 25°C –117 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 0 V, f = 1 MHz Refer to Crosstalk 25°C –106 dB BW –3 dB Bandwidth RL = 50 Ω , CL = 5 pF VS = 0 V, Refer to Bandwidth 25°C 38 MHz IL Insertion loss RL = 50 Ω , CL = 5 pF VS = 0 V, f = 1 MHz 25°C –0.16 dB ACPSRR AC Power Supply Rejection Ratio VPP = 0.62 V on VDD and VSS RL = 50 Ω , CL = 5 pF, f = 1 MHz Refer to ACPSRR 25°C –63 dB THD+N Total Harmonic Distortion + Noise VPP = 20 V, VBIAS = 0 V RL = 10 kΩ , CL = 5 pF, f = 20 Hz to 20 kHz Refer to THD + Noise 25°C 0.0005 % CS(OFF) Source off capacitance VS = 0 V, f = 1 MHz 25°C 32 pF CD(OFF) Drain off capacitance VS = 0 V, f = 1 MHz 25°C 45 pF CS(ON), CD(ON) On capacitance VS = 0 V, f = 1 MHz 25°C 146 pF www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TMUX7219

6.10 44 V Single Supply: Electrical Characteristics VDD = +44 V, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +44 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = 0 V to 40 V ID = –10 mA Refer to On-Resistance 25°C 2.2 2.8 Ω –40°C to +85°C 3.6 Ω –40°C to +125°C 4.2 Ω ΔRON On-resistance mismatch between channels VS = 0 V to 40 V ID = –10 mA Refer to On-Resistance 25°C 0.1 0.2 Ω –40°C to +85°C 0.3 Ω –40°C to +125°C 0.35 Ω RON FLAT On-resistance flatness VS = 0 V to 40 V ID = –10 mA Refer to On-Resistance 25°C 0.2 1 Ω –40°C to +85°C 1.3 Ω –40°C to +125°C 1.5 Ω RON DRIFT On-resistance drift VS = 22 V, IS = –10 mA Refer to On-Resistance –40°C to +125°C 0.008 Ω/°C IS(OFF) Source off leakage current(1) VDD = 44 V, VSS = 0 V Switch state is off VS = 40 V / 1 V VD = 1 V / 40 V Refer to Off-Leakage Current 25°C –5 0.05 5 nA –40°C to +85°C –10 10 nA –40°C to +125°C –35 35 nA ID(OFF) Drain off leakage current(1) VDD = 44 V, VSS = 0 V Switch state is off VS = 40 V / 1 V VD = 1 V / 40 V Refer to Off-Leakage Current 25°C –8 0.05 8 nA –40°C to +85°C –12 12 nA –40°C to +125°C –70 70 nA IS(ON) ID(ON) Channel on leakage current(2) VDD = 44 V, VSS = 0 V Switch state is on VS = VD = 40 V or 1 V Refer to On-Leakage Current 25°C –8 0.05 8 nA –40°C to +85°C –10 10 nA –40°C to +125°C –45 45 nA LOGIC INPUTS (SEL / EN pins) VIH Logic voltage high –40°C to +125°C 1.3 44 V VIL Logic voltage low –40°C to +125°C 0 0.8 V IIH Input leakage current –40°C to +125°C 0.005 1 µA IIL Input leakage current –40°C to +125°C –1 –0.005 µA CIN Logic input capacitance –40°C to +125°C 3 pF POWER SUPPLY IDD VDD supply current VDD = 44 V, VSS = 0 V Logic inputs = 0 V, 5 V, or VDD 25°C 17 50 µA –40°C to +85°C 60 µA –40°C to +125°C 75 µA (1) When VS is 40 V, VD is 1 V, or when VS is 1 V, VD is 40 V. (2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating. TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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6.11 44 V Single Supply: Switching Characteristics VDD = +44 V, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +44 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT tTRAN Transition time from control input VS = 18 V RL = 300 Ω, CL = 35 pF Refer to Transition Time 25°C 120 175 ns –40°C to +85°C 190 ns –40°C to +125°C 205 ns tON (EN) Turn-on time from enable VS = 18 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time 25°C 120 168 ns –40°C to +85°C 185 ns –40°C to +125°C 195 ns tOFF (EN) Turn-off time from enable VS = 18 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time 25°C 120 180 ns –40°C to +85°C 200 ns –40°C to +125°C 205 ns tBBM Break-before-make time delay VS = 18 V, RL = 300 Ω, CL = 35 pF Refer to Break-Before-Make 25°C 45 ns –40°C to +85°C 1 ns –40°C to +125°C 1 ns TON (VDD) Device turn on time (VDD to output) VDD rise time = 1 µs RL = 300 Ω, CL = 35 pF Refer to Turn-on (VDD) Time 25°C 0.15 ms –40°C to +85°C 0.17 ms –40°C to +125°C 0.17 ms tPD Propagation delay RL = 50 Ω , CL = 5 pF Refer to Propagation Delay 25°C 930 ps QINJ Charge injection VD = 22 V, CL = 1 nF Refer to Charge Injection 25°C –16 pC OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 6 V, f = 100 kHz Refer to Off Isolation 25°C –75 dB OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 6 V, f = 1 MHz Refer to Off Isolation 25°C –55 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 6 V, f = 100 kHz Refer to Crosstalk 25°C –117 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 6 V, f = 1 MHz Refer to Crosstalk 25°C –106 dB BW –3dB Bandwidth RL = 50 Ω , CL = 5 pF VS = 6 V Refer to Bandwidth 25°C 37 MHz IL Insertion loss RL = 50 Ω , CL = 5 pF VS = 6 V, f = 1 MHz 25°C –0.18 dB ACPSRR AC Power Supply Rejection Ratio VPP = 0.62 V on VDD and VSS RL = 50 Ω , CL = 5 pF, f = 1 MHz Refer to ACPSRR 25°C –60 dB THD+N Total Harmonic Distortion + Noise VPP = 22 V, VBIAS = 22 V RL = 10 kΩ , CL = 5 pF, f = 20 Hz to 20 kHz Refer to THD + Noise 25°C 0.0004 % CS(OFF) Source off capacitance VS = 6 V, f = 1 MHz 25°C 34 pF CD(OFF) Drain off capacitance VS = 6 V, f = 1 MHz 25°C 48 pF CS(ON), CD(ON) On capacitance VS = 6 V, f = 1 MHz 25°C 146 pF www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TMUX7219

6.12 12 V Single Supply: Electrical Characteristics VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = 0 V to 10 V ID = –10 mA Refer to On-Resistance 25°C 4.6 6 Ω –40°C to +85°C 7.5 Ω –40°C to +125°C 8.4 Ω ΔRON On-resistance mismatch between channels VS = 0 V to 10 V ID = –10 mA Refer to On-Resistance 25°C 0.08 0.2 Ω –40°C to +85°C 0.32 Ω –40°C to +125°C 0.35 Ω RON FLAT On-resistance flatness VS = 0 V to 10 V IS = –10 mA Refer to On-Resistance 25°C 1.2 2 Ω –40°C to +85°C 2.2 Ω –40°C to +125°C 2.4 Ω RON DRIFT On-resistance drift VS = 6 V, IS = –10 mA Refer to On-Resistance –40°C to +125°C 0.017 Ω/°C IS(OFF) Source off leakage current(1) VDD = 13.2 V, VSS = 0 V Switch state is off VS = 10 V / 1 V VD = 1 V / 10 V Refer to Off-Leakage Current 25°C –0.5 0.05 0.5 nA –40°C to +85°C –2 2 nA –40°C to +125°C –12 12 nA ID(OFF) Drain off leakage current(1) VDD = 13.2 V, VSS = 0 V Switch state is off VS = 10 V / 1 V VD = 1 V / 10 V Refer to Off-Leakage Current 25°C –0.5 0.05 0.5 nA –40°C to +85°C –3 3 nA –40°C to +125°C –23 23 nA IS(ON) ID(ON) Channel on leakage current(2) VDD = 13.2 V, VSS = 0 V Switch state is on VS = VD = 10 V or 1 V Refer to On-Leakage Current 25°C –1.5 0.05 1.5 nA –40°C to +85°C –3 3 nA –40°C to +125°C –15 15 nA LOGIC INPUTS (SEL / EN pins) VIH Logic voltage high –40°C to +125°C 1.3 44 V VIL Logic voltage low –40°C to +125°C 0 0.8 V IIH Input leakage current –40°C to +125°C 0.005 1 µA IIL Input leakage current –40°C to +125°C –1 –0.005 µA CIN Logic input capacitance –40°C to +125°C 3 pF POWER SUPPLY IDD VDD supply current VDD = 13.2 V, VSS = 0 V Logic inputs = 0 V, 5 V, or VDD 25°C 10 35 µA –40°C to +85°C 45 µA –40°C to +125°C 55 µA (1) When VS is 10 V, VD is 1 V, or when VS is 1 V, VD is 10 V. (2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating. TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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6.13 12 V Single Supply: Switching Characteristics VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT tTRAN Transition time from control input VS = 8 V RL = 300 Ω, CL = 35 pF Refer to Transition Time 25°C 180 185 ns –40°C to +85°C 215 ns –40°C to +125°C 235 ns tON (EN) Turn-on time from enable VS = 8 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time 25°C 120 180 ns –40°C to +85°C 210 ns –40°C to +125°C 230 ns tOFF (EN) Turn-off time from enable VS = 8 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time 25°C 130 210 ns –40°C to +85°C 235 ns –40°C to +125°C 250 ns tBBM Break-before-make time delay VS = 8 V, RL = 300 Ω, CL = 35 pF Refer to Break-Before-Make 25°C 40 ns –40°C to +85°C 1 ns –40°C to +125°C 1 ns TON (VDD) Device turn on time (VDD to output) VDD rise time = 100 ns RL = 300 Ω, CL = 35 pF Refer to Turn-on (VDD) Time 25°C 0.19 ms –40°C to +85°C 0.2 ms –40°C to +125°C 0.2 ms tPD Propagation delay RL = 50 Ω , CL = 5 pF Refer to Propagation Delay 25°C 740 ps QINJ Charge injection VD = 6 V, CL = 1 nF Refer to Charge Injection 25°C –6 pC OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 6 V, f = 100 kHz Refer to Off Isolation 25°C –75 dB OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 6 V, f = 1 MHz Refer to Off Isolation 25°C –55 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 6 V, f = 100 kHz Refer to Crosstalk 25°C –117 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 6 V, f = 1 MHz Refer to Crosstalk 25°C –106 dB BW –3 dB Bandwidth RL = 50 Ω , CL = 5 pF VS = 6 V Refer to Bandwidth 25°C 42 MHz IL Insertion loss RL = 50 Ω , CL = 5 pF VS = 6 V, f = 1 MHz 25°C –0.3 dB ACPSRR AC Power Supply Rejection Ratio VPP = 0.62 V on VDD and VSS RL = 50 Ω , CL = 5 pF, f = 1 MHz Refer to ACPSRR 25°C –65 dB THD+N Total Harmonic Distortion + Noise VPP = 6 V, VBIAS = 6 V RL = 10 kΩ , CL = 5 pF, f = 20 Hz to 20 kHz Refer to THD + Noise 25°C 0.0009 % CS(OFF) Source off capacitance VS = 6 V, f = 1 MHz 25°C 38 pF CD(OFF) Drain off capacitance VS = 6 V, f = 1 MHz 25°C 56 pF CS(ON), CD(ON) On capacitance VS = 6 V, f = 1 MHz 25°C 150 pF www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TMUX7219

6.14 Typical Characteristics

at TA = 25°C Figure 6-1. On-Resistance vs Source or Drain Voltage – Dual Supply Figure 6-2. On-Resistance vs Source or Drain Voltage – Dual Supply Figure 6-3. On-Resistance vs Source or Drain Voltage – Single Supply Figure 6-4. On-Resistance vs Source or Drain Voltage – Single Supply VDD = 15 V, VSS = −15 V Figure 6-5. On-Resistance vs Temperature VDD = 20 V, VSS = −20 V Figure 6-6. On-Resistance vs Temperature TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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6.14 Typical Characteristics (continued)

at TA = 25°C VDD = 5 V, VSS = −5 V Figure 6-7. On-Resistance vs Temperature VDD = 12 V, VSS = 0 V Figure 6-8. On-Resistance vs Temperature VDD = 36 V, VSS = 0 V Figure 6-9. On-Resistance vs Temperature Temperature ( C) Leakage Current (nA) -40 -25 -10 5 20 35 50 65 80 95 110 125 -35 -30 -25 -20 -15 -10 ID (OFF) V S /V D = − 15 V/15 V ID (OFF) V S /V D = 15 V/ − 15 V I(ON) − 15 V I(ON) 15 V IS (OFF) V S /V D = − 15 V/15 V IS (OFF) V S /V D = 15 V/ − 15 V VDD = 20 V, VSS = −20 V Figure 6-10. Leakage Current vs Temperature VDD = 15 V, VSS = −15 V Figure 6-11. Leakage Current vs Temperature VDD = 36 V, VSS = 0 V Figure 6-12. Leakage Current vs Temperature www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TMUX7219

at TA = 25°C VDD = 12 V, VSS = 0 V Figure 6-13. Leakage Current vs Temperature Figure 6-14. Supply Current vs Logic Voltage Source Voltage (V) Charge Injection (pC) -20 -15 -10 -5 0 5 10 15 20 -60 -40 -20 100 V DD = 20 V, V SS = − 20 V V DD = 15 V, V SS = − 15 V V DD = 5 V, V SS = − 5 V Figure 6-15. Charge Injection vs Source Voltage – Dual Supply Figure 6-16. Charge Injection vs Drain Voltage – Dual Supply Figure 6-17. Charge Injection vs Source Voltage – Single Supply Figure 6-18. Charge Injection vs Drian Voltage – Single Supply TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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at TA = 25°C VDD = 15 V, VSS = −15 V Figure 6-19. TTRANSITION vs Temperature VDD = 44 V, VSS = 0 V Figure 6-20. TTRANSITION vs Temperature VDD = 15 V, VSS = −15 V Figure 6-21. TON and TOFF vs Temperature VDD = 44 V, VSS = 0 V Figure 6-22. TON and TOFF vs Temperature Figure 6-23. Off-Isolation vs Frequency Switch ON (EN = 1) Figure 6-24. Crosstalk vs Frequency www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TMUX7219

at TA = 25°C Switch OFF (EN = 0) Figure 6-25. Crosstalk vs Frequency Figure 6-26. THD+N vs Frequency (Dual Supply) Figure 6-27. THD+N vs Frequency (Single Supply) VDD = 15 V, VSS = −15 V Figure 6-28. On Response vs Frequency VDD = +15 V, VSS = −15 V Figure 6-29. ACPSRR vs Frequency VDD = +15 V, VSS = −15 V Figure 6-30. Capacitance vs Source Voltage or Drain Voltage TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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at TA = 25°C VDD = 12 V, VSS = 0 V Figure 6-31. Capacitance vs Source Voltage or Drain Voltage www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TMUX7219

7 Parameter Measurement Information

7.1 On-Resistance

The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol R ON is used to denote on-resistance. Figure 7-1 shows the measurement setup used to measure RON. Voltage (V) and current (ISD) are measured using the following setup, where RON is computed as RON = V / ISD: V Dx VS ISD Sx RON Figure 7-1. On-Resistance

7.2 Off-Leakage Current

There are two types of leakage currents associated with a switch during the off state: 1. Source off-leakage current. 2. Drain off-leakage current. Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is off. This current is denoted by the symbol IS(OFF). Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off. This current is denoted by the symbol ID(OFF). Figure 7-2 shows the setup used to measure both off-leakage currents. GND VS D VD A Is (OFF) VDD VSS IS(OFF) GND VS D VD VDD VSS ID(OFF) ID (OFF) A Figure 7-2. Off-Leakage Measurement Setup TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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7.3 On-Leakage Current

Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch is on. This current is denoted by the symbol IS(ON). Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is on. This current is denoted by the symbol ID(ON). Either the source pin or drain pin is left floating during the measurement. Figure 7-3 shows the circuit used for measuring the on-leakage current, denoted by IS(ON) or ID(ON). GND VS DA Is (ON) VDD VSS IS(ON) GND VS D V VDD VSS ID(ON) ID (ON) A VS N.C. N.C. Figure 7-3. On-Leakage Measurement Setup

7.4 Transition Time

Transition time is defined as the time taken by the output of the device to rise or fall 90% after the address signal has risen or fallen past the logic threshold. The 90% transition measurement is utilized to provide the timing of the device. System level timing can then account for the time constant added from the load resistance and load capacitance. Figure 7-4 shows the setup used to measure transition time, denoted by the symbol tTRANSITION. 3 V VSEL 0 V 50% 50% tTRANSITION tTRANSITION 10% 90% Output tr < 20 ns tf < 20 ns RL CL VDD VSS VDD VSS 0.1 µF 0.1 µF GND D SEL Output

0 V VSEL

Figure 7-4. Transition-Time Measurement Setup www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TMUX7219

7.5 tON(EN) and tOFF(EN) Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level timing can then account for the time constant added from the load resistance and load capacitance. Figure 7-5 shows the setup used to measure turn-on time, denoted by the symbol tON(EN). Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level timing can then account for the time constant added from the load resistance and load capacitance. Figure 7-5 shows the setup used to measure turn-off time, denoted by the symbol tOFF(EN). 3 V VEN 0 V 50% 50% tON tOFF 10% 90% Output tr < 20 ns tf < 20 ns RL CL VDD VSS VDD VSS 0.1 µF 0.1 µF GND D EN Output

0 V VEN

Figure 7-5. Turn-On and Turn-Off Time Measurement Setup

7.6 Break-Before-Make

Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is switching. The output first breaks from the on-state switch before making the connection with the next on-state switch. The time delay between the break and the make is known as break-before-make delay. Figure 7-6 shows the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM). RL CL VDD VSS VDD VSS 0.1 µF 0.1 µF GND D SEL Output VSEL VS 3 V 0 V tBBM 1 80% Output 0 V tOPEN (BBM) = min ( tBBM 1, tBBM 2) tBBM 2 VSEL tr < 20 ns tf < 20 ns Figure 7-6. Break-Before-Make Delay Measurement Setup TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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7.7 tON (VDD) Time The tON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in the system. Figure 7-7 shows the setup used to measure turn on time, denoted by the symbol tON (VDD). VDD Supply Ramp 0 V 4.5 V tON 90% Output tr = 10 µs RL CL VDD VSS VSS 0.1 µF 0.1 µF GND D EN Output 0 V VDD VS SEL3 V Figure 7-7. tON (VDD) Time Measurement Setup

7.8 Propagation Delay

Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal has risen or fallen past the 50% threshold. Figure 7-8 shows the setup used to measure propagation delay, denoted by the symbol tPD. RL CL VDD VSS VDD VSS 0.1 µF 0.1 µF GND D Output VS 250 mV 0 V tPD 1 Output 0 V tProp Delay = max ( tPD 1, tPD 2) Input (VS) tr < 40 ps tf < 40 ps tPD 2 50% 50% 50% 50% 50 Ω Figure 7-8. Propagation Delay Measurement Setup www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TMUX7219

7.9 Charge Injection

The TMUX7219 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted by the symbol QC. Figure 7-9 shows the setup used to measure charge injection from source (Sx) to drain (D). VDD VSS VDD VSS 0.1 µF 0.1 µF GND D EN VEN VD VOUT Output VD 0 V 3 V VEN QINJ = CL × VOUT tr < 20 ns tf < 20 ns CL Output N.C. Figure 7-9. Charge-Injection Measurement Setup

7.10 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the source pin (Sx) of an off-channel. Figure 7-10 shows the setup used to measure, and the equation used to calculate off isolation. GND D VSIG Network Analyzer VOUT50 VDD VSS VDD VSS 0.1 µF 0.1 µF VS Figure 7-10. Off Isolation Measurement Setup TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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7.11 Crosstalk

Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied at the source pin (Sx) of an on-channel. Figure 7-11 shows the setup used to measure, and the equation used to calculate crosstalk. GND VSIG Network Analyzer VOUT50 VDD VSS VDD VSS 0.1 µF 0.1 µF VS D Figure 7-11. Crosstalk Measurement Setup

7.12 Bandwidth

Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure 7-12 shows the setup used to measure bandwidth. GND D VSIG Network Analyzer VOUT50 VDD VSS VDD VSS 0.1 µF 0.1 µF VS Figure 7-12. Bandwidth Measurement Setup www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TMUX7219

7.13 THD + Noise

The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux output. The on-resistance of the device varies with the amplitude of the input signal and results in distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as THD + N. GND D Audio Precision VOUT RL VDD VSS VDD VSS 0.1 µF 0.1 µF VS Other Sx pins Figure 7-13. THD + N Measurement Setup

7.14 Power Supply Rejection Ratio (PSRR)

PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave of 620 mV PP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the ACPSRR. A high ratio represents a high degree of tolerance to supply rail variation. This helps stabilize the supply and immediately filter as much of the supply noise as possible. 620 mVPP RL Network Analyzer VOUT VDD DC Bias Injector VIN CL VBIAS GND D VDD VSS VSS 0.1 µF With and Without Capacitor 50 Ω 50 Ω 50 Ω 0.1 µF Figure 7-14. ACPSRR Measurement Setup TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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8 Detailed Description

8.1 Overview

The TMUX7219 is a 2:1, 1-channel switch. Each input is turned on or turned off based on the state of the select line and enable pin.

8.2 Functional Block Diagram

The following figure shows the functional block diagram of the TMUX7219. EN D VDD VSS Decoder SEL

8.3 Feature Description

8.3.1 Bidirectional Operation

The TMUX7219 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each channel has very similar characteristics in both directions and supports both analog and digital signals.

8.3.2 Rail-to-Rail Operation

The valid signal path input and output voltage for TMUX7219 ranges from VSS to VDD. 8.3.3 1.8 V Logic Compatible Inputs The TMUX7219 has 1.8 V logic compatible control for all logic control inputs. 1.8 V logic level inputs allows the device to interface with processors that have lower logic I/O rails and eliminates the need for an external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches.

8.3.4 Integrated Pull-Up and Pull-Down Resistor on Logic Pins

The TMUX7219 has internal weak pull-up and pull-down resistors to GND to ensure the logic pins are not left floating. The value of this pull-down resistor is approximately 4 M Ω, but is clamped to about 1 µA at higher voltages. The EN pin integrates a pull-up resistor to V DD and the SEL pin integrates a pull-down resistor. This feature integrates up to two external components and reduces system size and cost.

8.3.5 Fail-Safe Logic

The TMUX7219 supports Fail-Safe Logic on the control input pins (EN and SEL) allowing for operation up to 44 V above ground, regardless of the state of the supply pins. This feature allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic feature allows the logic input pins of the TMUX7219 to be ramped to +44 V while V DD and VSS = 0 V. The logic control inputs are protected against positive faults of up to +44 V in powered-off condition, but do not offer protection against negative overvoltage conditions. www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TMUX7219

8.3.6 Latch-Up Immune

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the low impedance path. The TMUX72xx family of devices are constructed on Silicon on Insulator (SOI) based process where an oxide layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events due to overvoltage or current injections. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments. For more information on latch-up immunity refer to Using Latch Up Immune Multiplexers to Help Improve System Reliability.

8.3.7 Ultra-Low Charge Injection

Figure 8-1 shows how the TMUX7219 has a transmission gate topology. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed. S D CGDP CGDNCGSN CGSP OFF ON OFF ON Figure 8-1. Transmission Gate Topology The TMUX7219 contains specialized architecture to reduce charge injection on the source (Sx). To further reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the drain (D). This will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the drain (D) instead of the source (Sx). As a general rule, Cp should be 20× larger than the equivalent load capacitance on the source (Sx). Figure 8-2 shows charge injection variation with source voltage with different compensation capacitors on the drain side. Figure 8-2. Charge Injection Compensation TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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8.4 Device Functional Modes

When the EN pin of the TMUX7219 is pulled high, one of the switches is closed based on the state of the SEL pin. When the EN pin is pulled low, both of the switches are in an open state regardless of the state of the SEL pin. The control pins can be as high as 44 V. The TMUX7219 can operate without any external components except for the supply decoupling capacitors. The EN pin has an internal pull-up resistor of 4 M Ω, and SEL pin has internal pull-down resistor of 4 M Ω. If unused, EN pin must be tied to V DD and SEL pin must be tied to GND to ensure the device does not consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (S1, S2, or D) should be connected to GND.

8.5 Truth Tables

Table 8-1 show the truth tables for the TMUX7219. Table 8-1. TMUX7219 Truth Table EN SEL Selected Source Connected To Drain (D) Pin

0 X(1) All sources are off (HI-Z)

(1) X denotes do not care. www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TMUX7219

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

TMUX7219 is part of the precision switches and multiplexers family of devices. TMUX7219 offers low RON, low on and off leakage currents, and ultra-low charge injection performance. These properties make TMUX7219 ideal for implementing high precision industrial systems requiring selection of one of two inputs or outputs.

9.2 Typical Applications

9.2.1 Power Amplifier Gate Driver

One application of the TMUX7219 is for input control of a power amplifier gate driver. Utilizing a switch allows a system to control when the DAC is connected to the power amplifier, and can stop biasing the power amplifier by switching the gate to V SS. The wide dual supply range of ±4.5 V to ±22 V allows the switch to work with GaN power amplifiers and the wide single supply range 4.5 V to 44 V works well with LDMOS power amplifiers. Figure 9-1 shows the TMUX7219 configured for control of the power amplifier gate driver in GaN application. RF Tx/Rx TMUX7219 DAC VSS VDD RF InputMCU 1.8 V 8 V ±12 V/0 V ±12 V 0 V to 1.8 V Output voltage Figure 9-1. Power Amplifier Gate Driver

9.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 9-1. Table 9-1. Design Parameters PARAMETERS VALUES Supply (VDD) 8 V 5 V Supply (VSS) −12 V 0 V MUX I/O signal range −12 V to 8 V (Rail-to-Rail) 0 V to 5 V (Rail-to-Rail) Control logic thresholds 1.8 V compatiable (up to VDD) 1.8 V compatiable (up to VDD) EN EN pulled high to enable the switch EN pulled high to enable the switch TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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9.2.1.2 Detailed Design Procedure

The application shown in Figure 9-1 demonstrates how to toggle between the DAC output and low signal voltage for control of a GaN power amplifier using a single control input. The DAC output is utilized to bias the gate of the power amplifier and can be disconnected from the circuit using the select pin of the switch. The TMUX7219 can support 1.8 V logic signals on the control input, allowing the device to interface with low logic controls of an FPGA or MCU. The TMUX7219 can operate without any external components except for the supply decoupling capacitors. The select pin has an internal pull-down resistor to prevent floating input logic. All inputs to the switch must fall within the recommended operating conditions of the TMUX7219 including signal range and continuous current. For this design with a positive supply of 8 V on V DD and negative supply of −12 V on V SS, the signal range can be 8 V to −12 V. The maximum continuous current (IDC) can be up to 440 mA for a wide-range current measurement (for more information, refer to Section 6.4).

9.2.1.3 Application Curve

The low on and off leakage currents of TMUX7219 and ultra-low charge injection performance make this device ideal for implementing high precision industrial systems. The TMUX7219 contains specialized architecture to reduce charge injection on the source (Sx) (see Section 8.3.7 for more details). Figure 9-2 shows the plot for the charge injection versus source voltage for the TMUX7219. Figure 9-2. Charge Injection vs Source Voltage

9.2.2 Ultrasonic Sensing Gas Meter

Another application of the TMUX7219 is in the ultrasonic sensing gas meter. Ultrasonic sensing of gas flow uses the time of flight (ToF) of an ultrasonic wave and its dependency and behavior in the medium using two transducer pairs for upstream and downstream paths. Figure 9-3 shows a circuit example utilizing the MSP430FR6043 MCU, high voltage low distortion operational amplifiers (THS3091), along with TMUX7219, 2:1 precision switches. The TMUX7219 are needed to select the Rx and Tx path of the transducer. The TMUX7219 offers low on-state resistance and causes a very low signal distortion. The break-before-make feature allows transferring of a signal from one port to another, with a minimal signal distortion. This device also offers a low charge injection which makes this device suitable for high-performance audio and data acquisition systems. www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TMUX7219

+15 -15 TMUX7219 +15V -15V THS3091 +15 -15 +15V -15V TMUX7219 TMUX7219 TMUX7219 Figure 9-3. Ultrasonic Sensing Gas Meter System

9.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-2. Table 9-2. Design Parameters PARAMETERS VALUES Supply (VDD) 15 V Supply (VSS) −15 V MUX I/O signal range −15 V to 15 V (Rail-to-Rail) Control logic thresholds 1.8 V compatiable (up to VDD) EN EN pulled high to enable the switch Zero-flow drift (ZFD) ±250 ps (typical) Single-shot standard deviation (STD) <500 ps

9.2.2.2 Detailed Design Procedure

The TMUX7219 can operate without any external components except for the supply decoupling capacitors. All inputs passing through the switch must fall within the recommended operating conditions of the TMUX7219, including signal range and continuous current. For this design with a positive supply of 15 V on VDD and negative supply of −15 V on VSS, the signal range can be −15 V to +15 V and the maximum continuous current can be up to 440 mA, as shown in the Recommended Operating Conditions , for a wide-range current measurement. The TMUX7219 device is a bidirectional, single-pole double-throw (SPDT) switch that offers low on-resistance, low leakage, and low power. These features make this device suitable for portable and power sensitive applications such as ultrasonic gas metering systems. For a more detailed analysis of the ultrasonic flow transmitter system, refer to the reference design. TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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9.2.2.3 Application Curve

The TMUX7219 is capable of switching signals with minimal distortion because of the ultra-low leakage currents and excellent on-resistance flatness. Figure 9-4 shows how the on-resistance for the TMUX7219 varies with different supply voltages. TA = 25°C Figure 9-4. On-Resistance vs Source or Drain Voltage

10 Power Supply Recommendations

The TMUX7219 operates across a wide supply range of ±4.5 V to ±22 V (4.5 V to 44 V in single-supply mode). The device also performs well with asymmetrical supplies such as VDD = 12 V and VSS = –5 V. Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails to other components. Good power-supply decoupling is important to achieve optimum performance. For improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the VDD and VSS pins to ground. Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground and power planes. Always ensure the ground (GND) connection is established before supplies are ramped. www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TMUX7219

11 Layout

11.1 Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self-inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 11-1 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections. WORST BETTER BEST 1W min. W Figure 11-1. Trace Example Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points, through-hole pins are not recommended at high frequencies. Figure 11-2 and Figure 11-3 show an example of a PCB layout with the TMUX7219. Some key considerations are as follows:

• For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD/VSS and GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary.
• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground planes. TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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11.2 Layout Example

D GND SEL VDD TMUX721 9 EN Wide (low inductance) trace for power VSS C C Via to ground plane Wide (low inductance) trace for power C C Figure 11-2. TMUX7219DGK Layout Example C D S2 S1 VSS GND SEL EN C Via to ground plane C C Wide (low inductance) trace for power Wide (low inductance) trace for power VSS Figure 11-3. TMUX7219RQX Layout Example www.ti.com TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TMUX7219

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Improve Stability Issues with Low CON Multiplexers application brief
• Texas Instruments, Improving Signal Measurement Accuracy in Automated Test Equipment application brief
• Texas Instruments, Multiplexers and Signal Switches Glossary application report
• Texas Instruments, QFN/SON PCB Attachment application report
• Texas Instruments, Quad Flatpack No-Lead Logic Packages application report
• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief
• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application report
• Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit application report
• Texas Instruments, Ultrasonic sensing subsystem reference design for gas flow measurement reference design

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TMUX7219 SCDS407E – NOVEMBER 2020 – REVISED AUGUST 2022 www.ti.com

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www.ti.com 11-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTMUX7219RQXR ACTIVE WSON RQX 8 2500 TBD Call TI Call TI -40 to 125 Samples TMUX7219DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 X219 Samples TMUX7219RQXR ACTIVE WSON RQX 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 H219 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 11-Nov-2022 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMUX7219 :

• Automotive : TMUX7219-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMUX7219DGKR VSSOP DGK 8 2500 366.0 364.0 50.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 3.1 2.9 2.1 1.9 0.8 0.7 0.05 0.00 2X 1.5 6X 0.5 8X 0.45 0.35 8X 0.3 0.2 1.65 0.1 1.8 0.1 (0.2) TYP WSON - 0.8 mm max heightRQX0008A PLASTIC SMALL OUTLINE - NO LEAD 4225821/A 04/2020 0.08 C

0.1 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMMEXPOSED THERMAL PAD SYMM SCALE 5.000 AB

www.ti.com EXAMPLE BOARD LAYOUT 6X (0.5) (0.575) (R0.05) TYP

0.07 MAX

0.07 MIN

8X (0.6) 8X (0.25) (2.8) (1.65) (1.8) ( 0.2) TYP VIA WSON - 0.8 mm max heightRQX0008A PLASTIC SMALL OUTLINE - NO LEAD 4225821/A 04/2020 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SEE SOLDER MASK DETAIL 4 5 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 8X (0.6) 8X (0.25) 6X (0.5) (2.8) (1.51) (1.63) (R0.05) TYP WSON - 0.8 mm max heightRQX0008A PLASTIC SMALL OUTLINE - NO LEAD 4225821/A 04/2020 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 20X EXPOSED PAD 9 83% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 4 5

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