PTMUX6212PWR

TMUX6211 TI | Alldatasheet

Document overview

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Technical content

TMUX621x 36-V, Low-Ron, 1:1 (SPST), 4-Channel Precision Switches with 1.8-V Logic

1 Features

• Dual Supply Range: ±4.5 V to ±18 V
• Single Supply Range: 4.5 V to 36 V
• Low On-Resistance: 2 Ω
• –40°C to +125°C Operating Temperature
• Logic Levels: L8 V to VDD
• Fail-Safe Logic
• Rail-to-Rail Operation
• Bidirectional Operation
• Break-Before-Make Switching
• ESD Protection HBM: 2000 V

2 Applications

• Sample-and-Hold Circuits
• Feedback Gain Switching
• Signal Isolation
• Field Transmitters
• Programmable Logic Controllers (PLC)
• Factory Automation and Control
• Ultrasound Scanners
• Patient Monitoring & Diagnostics
• Electrocardiogram (ECG)
• Data Acquisition Systems (DAQ)
• Semiconductor Test Equipment
• LCD Test
• Instrumentation: Lab, Analytical, Portable
• Ultrasonic Smart Meters: Water and Gas
• Optical Networking
• Optical Test Equipment

3 Description

The TMUX6211, TMUX6212, and TMUX6213 are complementary metal-oxide semiconductor (CMOS) switches with four independently selectable 1:1, single-pole, singlethrow (SPST) switch channels. The devices work well with dual supplies (±4.5 V to ±18 V), a single supply (4.5 V to 36 V), or asymmetric supplies (such as V DD = 12 V, V SS = –5 V). The TMUX621x supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD. The switches of the TMUX6211 are turned on with Logic 0 on the appropriate logic control inputs, while Logic 1 is required to turn on switches in the TMUX6212. The four channels of the TMUX6213 are split with two switches supporting Logic 0, while the other two switches support Logic 1. The TMUX6213 exhibits break-before-make switching, allowing the device to be used in cross-point switching applications. The TMUX621x are part of the precision switches and multiplexers family of devices. These devices have very low on and off leakage currents and low charge injection, allowing them to be used in high precision measurement applications. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) TMUX6211 TSSOP (16) (PW) 5.00 mm × 4.40 mm TMUX6212 WQFN (16) (RUM) 4.00 mm x 4.00 mm TMUX6213 (1) For all available packages, see the package option addendum at the end of the data sheet. SEL1 SEL2 SEL3 SEL4 TMUX1111 TMUX1112 TMUX1113 SEL1 SEL2 SEL3 SEL4 SEL1 SEL2 SEL3 SEL4 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT TMUX621x Block Diagrams www.ti.com TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 1 Product Folder Links: TMUX6211 TMUX6212 TMUX6213 TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

12.2 Receiving Notification of Documentation Updates..19

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES October 2020 * Initial Release TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 www.ti.com ADVANCE INFORMATION

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Product Folder Links: TMUX6211 TMUX6212 TMUX6213

5 Device Comparison Table

TMUX6211 Low-Leakage-Current, Precision, 4-Channel, 1:1 (SPST) Switches (Normally Closed) TMUX6212 Low-Leakage-Current, Precision, 4-Channel, 1:1 (SPST) Switches (Normally Open) TMUX6213 Low-Leakage-Current, Precision, 4-Channel, 1:1 (SPST) Switches (Dual Open + Dual Closed)

6 Pin Configuration and Functions

5GND 12 N.C. 6S4 11 S3 7D4 10 D3 8SEL4 9 SEL3 Not to scale Figure 6-1. PW Package 16-Pin TSSOP Top View

16 D15D4

15 SEL16SEL4

14 SEL27SEL3

3GND 10 N.C.

13 D28D3

Figure 6-2. RUM Package 16-Pin WQFN Top View Table 6-1. Pin Functions PIN TYPE(1) DESCRIPTION(2) NAME TSSOP WQFN SEL1 1 15 I Logic control input 1, has internal pull-down resistor. Controls channel 1 state as shown in Section 8.5. D1 2 16 I/O Drain pin 1. Can be an input or output. S1 3 1 I/O Source pin 1. Can be an input or output. VSS 4 2 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VSS and GND. GND 5 3 P Ground (0 V) reference S4 6 4 I/O Source pin 4. Can be an input or output. D4 7 5 I/O Drain pin 4. Can be an input or output. SEL4 8 6 I Logic control input 4, has internal pull-down resistor. Controls channel 4 state as shown in Section 8.5. SEL3 9 7 I Logic control input 3, has internal pull-down resistor. Controls channel 3 state as shown in Section 8.5. D3 10 8 I/O Drain pin 3. Can be an input or output. S3 11 9 I/O Source pin 3. Can be an input or output. N.C. 12 10 - No internal connection. VDD 13 11 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. S2 14 12 I/O Source pin 2. Can be an input or output. D2 15 13 I/O Drain pin 2. Can be an input or output. SEL2 16 14 I Logic control input 2, has internal pull-down resistor. Controls channel 2 state as shown in Section 8.5. (1) I = input, O = output, I/O = input and output, P = power. (2) Refer to Section 8.4 for what to do with unused pins. www.ti.com TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TMUX6211 TMUX6212 TMUX6213

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2) (3) MIN MAX UNIT VDD–VSS Supply voltage 38 V VDD –0.5 38 V VSS –38 0.5 V VSEL or VEN Logic control input pin voltage (SELx)(4) –0.5 38 V ISEL or IEN Logic control input pin current (SELx)(4) –30 30 mA VS or VD Source or drain voltage (Sx, Dx)(4) VSS–0.5 VDD+0.5 V IIK Diode clamp current(4) –30 30 mA IS or ID (CONT) Source or drain continuous current (Sx, Dx) IDC + 10 %(5) mA TA Ambient temperature –55 135 °C Tstg Storage temperature –65 150 °C TJ Junction temperature 140 °C (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. (3) All voltages are with respect to ground, unless otherwise specified. (4) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings. (5) Refer to Source or Drain Continuous Current table for IDC specifications.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Thermal Information

THERMAL METRIC(1) TMUX721x UNITPW (TSSOP) RUM (WQFN)

16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 94.5 TBD °C/W RθJC(top) Junction-to-case (top) thermal resistance 25.5 TBD °C/W RθJB Junction-to-board thermal resistance 41.1 TBD °C/W ΨJT Junction-to-top characterization parameter 1.1 TBD °C/W ΨJB Junction-to-board characterization parameter 40.4 TBD °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A TBD °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 www.ti.com ADVANCE INFORMATION

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7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD - VSS (1) Power supply voltage differential 4.5 36 V VDD Positive power supply voltage 4.5 36 V VS or VD Signal path input/output voltage (source or drain pin) (Sx, D) VSS VDD V VSEL or VEN Address or enable pin voltage 0 36 V IS or ID (CONT) Source or drain continuous current (Sx, D) IDC (2) TA Ambient temperature –40 125 °C (1) V DD and VSS can be any value as long as 4.5 V ≤ (VDD – VSS) ≤ 36 V, and the minimum VDD is met. (2) Refer to Source or Drain Continuous Current table for IDC specifications.

7.5 Source or Drain Continuous Current

at supply voltage of VDD ± 10%, VSS ± 10 % (unless otherwise noted) CONTINUOUS CURRENT PER CHANNEL (IDC) TA = 25°C TA = 85°C TA = 125°C UNIT PACKAGE TEST CONDITIONS PW (TSSOP) ±15 V Dual Supply 370 240 145 mA +12 V Single Supply 270 190 120 mA ±5 V Dual Supply 260 180 118 mA +5 V Single Supply 200 140 100 mA www.ti.com TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TMUX6211 TMUX6212 TMUX6213

7.6 ±15 V Dual Supply: Electrical Characteristics VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = –10 V to +10 V ID = –10 mA 25°C 2 3 Ω –40°C to +85°C 3.9 Ω –40°C to +125°C 4.6 Ω ΔRON On-resistance mismatch between channels VS = –10 V to +10 V ID = –10 mA 25°C 0.05 0.2 Ω –40°C to +85°C 0.25 Ω –40°C to +125°C 0.3 Ω RON FLAT On-resistance flatness VS = –10 V to +10 V IS = –10 mA 25°C 0.45 0.65 Ω –40°C to +85°C 0.8 Ω –40°C to +125°C 0.95 Ω RON DRIFT On-resistance drift VS = 0 V, IS = –10 mA –40°C to +125°C 0.01 Ω/°C IS(OFF) Source off leakage current(1) VDD = 16.5 V, VSS = –16.5 V Switch state is off VS = +10 V / –10 V VD = –10 V / + 10 V 25°C 0.05 nA –40°C to +85°C 0.5 nA –40°C to +125°C –35 35 nA ID(OFF) Drain off leakage current(1) VDD = 16.5 V, VSS = –16.5 V Switch state is off VS = +10 V / –10 V VD = –10 V / + 10 V 25°C 0.05 nA –40°C to +85°C 1 nA –40°C to +125°C –60 60 nA IS(ON) ID(ON) Channel on leakage current(2) VDD = 16.5 V, VSS = –16.5 V Switch state is on VS = VD = ±10 V 25°C 0.05 nA –40°C to +85°C 1 nA –40°C to +125°C –60 60 nA LOGIC INPUTS (SEL / EN pins) VIH Logic voltage high –40°C to +125°C 1.3 36 V VIL Logic voltage low –40°C to +125°C 0 0.8 V IIH Input leakage current –40°C to +125°C 0.4 1.2 µA IIL Input leakage current –40°C to +125°C –0.1 –0.005 µA CIN Logic input capacitance –40°C to +125°C 3 pF POWER SUPPLY IDD VDD supply current VDD = 16.5 V, VSS = –16.5 V Logic inputs = 0 V, 5 V, or VDD 25°C 35 65 µA –40°C to +85°C 72 µA –40°C to +125°C 92 µA ISS VSS supply current VDD = 16.5 V, VSS = –16.5 V Logic inputs = 0 V, 5 V, or VDD 25°C 15 25 µA –40°C to +85°C 30 µA –40°C to +125°C 45 µA (1) When V S is positive, VD is negative, or when VS is negative, VD is positive. (2) When V S is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating. TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 www.ti.com ADVANCE INFORMATION

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7.7 ±15 V Dual Supply: Switching Characteristics VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT tTRAN Transition time from control input VS = 10 V RL = 300 Ω, CL = 35 pF 25°C 100 150 ns –40°C to +85°C 170 ns –40°C to +125°C 190 ns tON Turn-on time from control input VS = 10 V RL = 300 Ω, CL = 35 pF 25°C 130 170 ns –40°C to +85°C 190 ns –40°C to +125°C 210 ns tOFF Turn-off time from control input VS = 10 V RL = 300 Ω, CL = 35 pF 25°C 110 185 ns –40°C to +85°C 200 ns –40°C to +125°C 210 ns tPD Propagation delay RL = 50 Ω , CL = 5 pF 25°C 100 ps QINJ Charge injection VS = 0 V, CL = 1 nF 25°C 15 pC OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 0 V, f = 100 kHz 25°C –70 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 0 V, f = 100 kHz 25°C –100 dB BW –3dB Bandwidth RL = 50 Ω , CL = 5 pF VS = 0 V 25°C 45 MHz CS(OFF) Source off capacitance VS = 0 V, f = 1 MHz 25°C 30 pF CD(OFF) Drain off capacitance VS = 0 V, f = 1 MHz 25°C 45 pF CS(ON), CD(ON) On capacitance VS = 0 V, f = 1 MHz 25°C 145 pF www.ti.com TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TMUX6211 TMUX6212 TMUX6213

7.8 12 V Single Supply: Electrical Characteristics VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = 0 V to 10 V ID = –10 mA 25°C 4 6.2 Ω –40°C to +85°C 7.5 Ω –40°C to +125°C 8.5 Ω ΔRON On-resistance mismatch between channels VS = 0 V to 10 V ID = –10 mA 25°C 0.08 0.32 Ω –40°C to +85°C 0.4 Ω –40°C to +125°C 0.45 Ω RON FLAT On-resistance flatness VS = 0 V to 10 V IS = –10 mA 25°C 1.2 2.2 Ω –40°C to +85°C 2.6 Ω –40°C to +125°C 2.8 Ω RON DRIFT On-resistance drift VS = 6 V, IS = –10 mA –40°C to +125°C 0.015 Ω/°C IS(OFF) Source off leakage current(1) VDD = 13.2 V, VSS = 0 V Switch state is off VS = 10 V / 1 V VD = 1 V / 10 V 25°C 0.05 nA –40°C to +85°C 0.5 nA –40°C to +125°C –35 35 nA ID(OFF) Drain off leakage current(1) VDD = 13.2 V, VSS = 0 V Switch state is off VS = 10 V / 1 V VD = 1 V / 10 V 25°C 0.05 nA –40°C to +85°C 1 nA –40°C to +125°C –60 60 nA IS(ON) ID(ON) Channel on leakage current(2) VDD = 13.2 V, VSS = 0 V Switch state is on VS = VD = 10 V or 1 V 25°C 0.05 nA –40°C to +85°C 1 nA –40°C to +125°C –60 60 nA LOGIC INPUTS (SEL / EN pins) VIH Logic voltage high –40°C to +125°C 1.3 36 V VIL Logic voltage low –40°C to +125°C 0 0.8 V IIH Input leakage current –40°C to +125°C 0.4 1.2 µA IIL Input leakage current –40°C to +125°C –0.1 –0.005 µA CIN Logic input capacitance –40°C to +125°C 3 pF POWER SUPPLY IDD VDD supply current VDD = 13.2 V, VSS = 0 V Logic inputs = 0 V, 5 V, or VDD 25°C 35 55 µA –40°C to +85°C 68 µA –40°C to +125°C 80 µA (1) When V S is positive, VD is negative, or when VS is negative, VD is positive. (2) When V S is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating. TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 www.ti.com ADVANCE INFORMATION

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7.9 12 V Single Supply: Switching Characteristics VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT tTRAN Transition time from control input VS = 8 V RL = 300 Ω, CL = 35 pF 25°C 170 250 ns –40°C to +85°C 290 ns –40°C to +125°C 330 ns tON Turn-on time from control input VS = 8 V RL = 300 Ω, CL = 35 pF 25°C 170 200 ns –40°C to +85°C 250 ns –40°C to +125°C 275 ns tOFF Turn-off time from control input VS = 8 V RL = 300 Ω, CL = 35 pF 25°C 200 220 ns –40°C to +85°C 250 ns –40°C to +125°C 270 ns tPD Propagation delay RL = 50 Ω , CL = 5 pF 25°C 100 ps QINJ Charge injection VS = 6 V, CL = 1 nF 25°C 13 pC OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 6 V, f = 100 kHz 25°C –70 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 6 V, f = 100 kHz 25°C –95 dB BW –3dB Bandwidth RL = 50 Ω , CL = 5 pF VS = 6 V 25°C 80 MHz CS(OFF) Source off capacitance VS = 6 V, f = 1 MHz 25°C 35 pF CD(OFF) Drain off capacitance VS = 6 V, f = 1 MHz 25°C 50 pF CS(ON), CD(ON) On capacitance VS = 6 V, f = 1 MHz 25°C 142 pF www.ti.com TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TMUX6211 TMUX6212 TMUX6213

7.10 ±5 V Dual Supply: Electrical Characteristics VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VDD = +4.5 V, VSS = –4.5 V VS = –4.5 V to +4.5 V ID = –10 mA 25°C 4 7.3 Ω –40°C to +85°C 8.8 Ω –40°C to +125°C 9.8 Ω ΔRON On-resistance mismatch between channels VS = –4.5 V to +4.5 V ID = –10 mA 25°C 0.1 0.3 Ω –40°C to +85°C 0.35 Ω –40°C to +125°C 0.4 Ω RON FLAT On-resistance flatness VS = –4.5 V to +4.5 V ID = –10 mA 25°C 1.8 2.3 Ω –40°C to +85°C 2.8 Ω –40°C to +125°C 3.5 Ω RON DRIFT On-resistance drift VS = 0 V, IS = –10 mA –40°C to +125°C 0.02 Ω/°C IS(OFF) Source off leakage current(1) VDD = +5.5 V, VSS = –5.5 V Switch state is off 25°C 0.05 nA –40°C to +85°C 0.5 nA –40°C to +125°C –35 35 nA ID(OFF) Drain off leakage current(1) VDD = +5.5 V, VSS = –5.5 V Switch state is off 25°C 0.05 nA –40°C to +85°C 1 nA –40°C to +125°C –60 60 nA IS(ON) ID(ON) Channel on leakage current(2) VDD = +5.5 V, VSS = –5.5 V Switch state is on VS = VD = ±4.5 V 25°C 0.05 nA –40°C to +85°C 1 nA –40°C to +125°C –60 60 nA LOGIC INPUTS (SEL / EN pins) VIH Logic voltage high –40°C to +125°C 1.3 36 V VIL Logic voltage low –40°C to +125°C 0 0.8 V IIH Input leakage current –40°C to +125°C 0.4 1.2 µA IIL Input leakage current –40°C to +125°C –0.1 –0.005 µA CIN Logic input capacitance –40°C to +125°C 3 pF POWER SUPPLY IDD VDD supply current VDD = +5.5 V, VSS = –5.5 V Logic inputs = 0 V, 5 V, or VDD 25°C 33 50 µA –40°C to +85°C 55 µA –40°C to +125°C 65 µA ISS VSS supply current VDD = +5.5 V, VSS = –5.5 V Logic inputs = 0 V, 5 V, or VDD 25°C 4 10 µA –40°C to +85°C 15 µA –40°C to +125°C 25 µA (1) When V S is positive, VD is negative, or when VS is negative, VD is positive. (2) When V S is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating. TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 www.ti.com ADVANCE INFORMATION

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7.11 ±5 V Dual Supply: Switching Characteristics VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT tTRAN Transition time from control input VS = 3 V RL = 300 Ω, CL = 35 pF 25°C 270 400 ns –40°C to +85°C 465 ns –40°C to +125°C 510 ns tON Turn-on time from control input VS = 3 V RL = 300 Ω, CL = 35 pF 25°C 220 250 ns –40°C to +85°C 285 ns –40°C to +125°C 315 ns tOFF Turn-off time from control input VS = 3 V RL = 300 Ω, CL = 35 pF 25°C 170 270 ns –40°C to +85°C 300 ns –40°C to +125°C 315 ns tPD Propagation delay RL = 50 Ω , CL = 5 pF 25°C 100 ps QINJ Charge injection VS = 0 V, CL = 1 nF 25°C 15 pC OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 0 V, f = 100 kHz 25°C –70 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 0 V, f = 100 kHz 25°C –95 dB BW –3dB Bandwidth RL = 50 Ω , CL = 5 pF VS = 0 V 25°C 90 MHz CS(OFF) Source off capacitance VS = 0 V, f = 1 MHz 25°C 35 pF CD(OFF) Drain off capacitance VS = 0 V, f = 1 MHz 25°C 52 pF CS(ON), CD(ON) On capacitance VS = 0 V, f = 1 MHz 25°C 142 pF www.ti.com TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TMUX6211 TMUX6212 TMUX6213

8 Detailed Description

8.1 Overview

The TMUX6211, TMUX6212, and TMUX6213 are 1:1 (SPST), 4-Channel switches. The devices have four independently selectable single-pole, single-throw switches that are turned-on or turned-off based on the state of the corresponding select pin.

8.2 Functional Block Diagram

ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT Figure 8-1. TMUX621x Functional Block Diagram

8.3 Feature Description

8.3.1 Bidirectional Operation

The TMUX621x conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each channel has very similar characteristics in both directions and supports both analog and digital signals.

8.3.2 Rail-to-Rail Operation

The valid signal path input and output voltage for TMUX621x ranges from VSS to VDD. 8.3.3 1.8 V Logic Compatible Inputs The TMUX621x devices have 1.8-V logic compatible control for all logic control inputs. 1.8-V logic level inputs allows the TMUX621x to interface with processors that have lower logic I/O rails and eliminates the need for an external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches.

8.3.4 Fail-Safe Logic

The TMUX621x supports Fail-Safe Logic on the control input pins (SEL1, SEL2, SEL3, and SEL4) allowing for operation up to 36 V, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail- Safe Logic feature allows the select pins of the TMUX621x to be ramped to 36 V while V DD and VSS = 0 V. The logic control inputs are protected against positive faults of up to 36 V in powered-off condition, but do not offer protection against negative overvoltage conditions. TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 www.ti.com ADVANCE INFORMATION

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8.4 Device Functional Modes

The TMUX621x devices have four independently selectable single-pole, single-throw switches that are turned-on or turned-off based on the state of the corresponding select pin. The control pins can be as high as 36 V. The TMUX621x devices can be operated without any external components except for the supply decoupling capacitors. Unused logic control pins should be tied to GND or V DD in order to ensure the device does not consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs . Unused signal path inputs (Sx or Dx) should be connection to GND.

8.5 Truth Tables

Table 8-1, Table 8-2, and Table 8-3 show the truth tables for the TMUX6211, TMUX6212, and TMUX6213, respectively. Table 8-1. TMUX6211 Truth Table SEL x (1) CHANNEL x

0 Channel x ON

1 Channel x OFF

Table 8-2. TMUX6212 Truth Table SEL x (1) CHANNEL x

0 Channel x OFF

1 Channel x ON

Table 8-3. TMUX6213 Truth Table SEL x (1) CHANNEL 1 / CHANNEL 4 CHANNEL 2 / CHANNEL 3

0 OFF ON

1 ON OFF

(1) x denotes 1, 2, 3, or 4 for the corresponding channel. www.ti.com TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TMUX6211 TMUX6212 TMUX6213

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TMUX621x is part of the precision switches and multiplexers family of devices. These devices operate with dual supplies (±4.5 V to ±18 V), a single supply (4.5 V to 36 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V), and offer true rail-to-rail input and output.The TMUX621x offers low RON, low on and off leakage currents and ultra-low charge injection performance. These features makes the TMUX621x a family of precision, robust, high-performance analog multiplexer for high-voltage, industrial applications.

9.2 Typical Application

One example to take advantage of TMUX621x precision performance is the implementation of parametric measurement unit (PMU) in the semiconductor automatic test equipment (ATE) application. In Automated Test Equipment (ATE) systems, the Parametric Measurement Unit (PMU) is tasked to measure device (DUT) parametric information in terms of voltage and current. When measuring voltage, current is applied at the DUT pin, and current range adjustment can be done through changing the value of the internal sense resistor. There is sometimes a need, depending on the DUT, to use even higher testing current than natively supported by the system. A 4 channel SPST switch, together with external higher current amplifier and resistor, can be used to achieve the flexibility. The PMU operating voltage is typically in mid voltage (up tp 20 V). An appropriate switch like the TMUX621x with low leakage current (0.05 nA typical) works well in these applications to ensure measurement accuracy and low R ON and flat R ON_FLATNESS allows the current range to be controlled more precisely. Figure 9-1 shows simplified diagram of such implementations in memory and semiconductor test equipment. DAC ADC Force Amplifier Measure Voltage Amplifier Measure Current Amplifier DUT High Current Amplifier EN Internal Sense Resistor DAC + ADC Force Amplifier Measure Voltage Amplifier Measure Current Amplifier DUT High Current Amplifier EN External Sense Resistor Figure 9-1. High Current Range Selection Using External Resistor TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 www.ti.com ADVANCE INFORMATION

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9.3 Design Requirements

For this design example, use the parameters listed in Table 9-1. Table 9-1. Design Parameters PARAMETERS VALUES Supply (VDD) 20 V Supply (VSS) - 10 V Input / Output signal range -10 V to 20 V (Rail-to-Rail) Control logic thresholds 1.8 V compatible

9.4 Detailed Design Procedure

The application shown in High Current Range Selection Using External Resistor figure demonstrates how the TMUX621x can be used in semicoonductor test equipment for high-precision, high-voltage, multi-channel measurement applications. The TMUX621x can support 1.8-V logic signals on the control input, allowing the device to interface with low logic controls of an FPGA or MCU. The TMUX621x can be operated without any external components except for the supply decoupling capacitors. The select pins have an internal pull-down resistor to prevent floating input logic. All inputs to the switch must fall within the recommend operating conditions of the TMUX621x including signal range and continuous current. For this design with a positive supply of 20 V on VDD, and negative supply of -10 V on VSS, the signal range can be 20 V to -10 V. The max continuous current (IDC) can be up to 370 mA as shown in the Recommended Operating Conditions table for wide-range current measurement. www.ti.com TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TMUX6211 TMUX6212 TMUX6213

10 Power Supply Recommendations

The TMUX621x operates across a wide supply range of of ±4.5 V to ±18 V (4.5 V to 36 V in single-supply mode). The device also perform well with asymmetrical supplies such as VDD = 12 V and VSS= –5 V. Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails to other components. Good power-supply decoupling is important to achieve optimum performance. For improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the VDD and VSS pins to ground. Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. Always ensure the ground (GND) connection is established before supplies are ramped. TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 www.ti.com ADVANCE INFORMATION

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11 Layout

11.1 Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 11-1 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections. WORST BETTER BEST 1W min. W Figure 11-1. Trace Example Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points, through-hole pins are not recommended at high frequencies. Figure 11-2 illustrates an example of a PCB layout with the TMUX621x. Some key considerations are:

• Decouple the supply pins with a 0.1-µF and 1 µF capacitor, placed lowest value capacitor as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary.
• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground planes. www.ti.com TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TMUX6211 TMUX6212 TMUX6213

11.2 Layout Example

N.C. SEL3 GND SEL4 C C C Wide (low inductance) trace for power Wide (low inductance) trace for power Via to ground plane C Figure 11-2. TMUX621x Layout Example TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 www.ti.com ADVANCE INFORMATION

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

Texas Instruments, Sample & Hold Glitch Reduction for Precision Outputs Reference Design. Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit. Texas Instruments, Improve Stability Issues with Low CON Multiplexers. Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches. Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches. Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers. Texas Instruments, QFN/SON PCB Attachment. Texas Instruments, Quad Flatpack No-Lead Logic Packages.

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. www.ti.com TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TMUX6211 TMUX6212 TMUX6213

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TMUX6211, TMUX6212, TMUX6213 SCDS431 – OCTOBER 2020 www.ti.com ADVANCE INFORMATION

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www.ti.com 6-Nov-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTMUX6212PWR ACTIVE TSSOP PW 16 2000 TBD Call TI Call TI -40 to 125 TMUX6211PWR PREVIEW TSSOP PW 16 2000 TBD Call TI Call TI -40 to 125 TMUX6211RUMR PREVIEW WQFN RUM 16 3000 TBD Call TI Call TI -40 to 125 TMUX6212PWR PREVIEW TSSOP PW 16 2000 TBD Call TI Call TI -40 to 125 TMUX6212RUMR PREVIEW WQFN RUM 16 3000 TBD Call TI Call TI -40 to 125 TMUX6213PWR PREVIEW TSSOP PW 16 2000 TBD Call TI Call TI -40 to 125 TMUX6213RUMR PREVIEW WQFN RUM 16 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 6-Nov-2020 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 5.1 4.9 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

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