PTMUX5411DYYR

TMUX5411_V02 TI | Alldatasheet

Document overview

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Technical content

TMUX541x 50V, 21Ω, 1:1 (SPST) 4-Channel Switches with 1.8V Logic

1 Features

• Dual supply range: ±4.5V to ±25V
• Single supply range: 4.5V to 50V
• Asymmetric dual supply support (For example: VDD = 37.5V, VSS = -12.5V)
• 1.8V logic compatible
• Low on-resistance: 21Ω (typical)
• Low on-capacitance: 12pF (typical)
• Ultra-low on-resistance flatness: 0.005Ω (typical)
• Low on-leakage current: 0.002nA (typical), 40nA (maximum)
• Low charge injection: 13pC (typical)
• –40°C to +125°C operating temperature
• Rail-to-rail operation
• Bidirectional operation
• Break-before-make switching (TMUX5413)

2 Applications

• Sample-and-hold circuits
• Feedback gain switching
• Signal isolation
• Semiconductor test equipment
• Programmable logic controllers (PLC)
• Factory automation and control
• Professional Audio Equipment
• Instrumentation: lab, analytical, and portable
• Data acquisition systems (DAQ)
• Optical test equipment

3 Description

The TMUX541x is a general purpose complementary metal-oxide semiconductor (CMOS) switch device with four independently selectable 1:1, single-pole, single-throw (SPST) switch channels. The device works with a single supply (4.5V to 50V), dual supplies (±4.5V to ±25V), or asymmetric supplies (such as VDD = 37.5V, VSS = –12.5V). The TMUX541x supports bidirectional analog and digital signals on the source (Sx) and drain (Dx) pins ranging from V SS to VDD. The switches of the TMUX541x are controlled with appropriate logic control inputs on the SELx pins. The TMUX541x exhibits break-before-make switching, allowing the device to be used in cross-point and multiplexing applications. The TMUX541x is a part of the general purpose switches and multiplexers family of devices emphasizing uses in broad range of applications while reducing BOM cost.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TMUX5411 TMUX5412 TMUX5413 PW (TSSOP, 16) 5mm × 6.4mm DYY (SOT-23-THIN, 16) 3.26mm x 4.2mm (1) For all available packages, see the package option addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. SW SW SW SW SEL1 SEL2 SEL3 SEL4 VDD VSS VDD VSS SW SW SW SW VDD VSS SW SW SW SW SEL1 SEL2 SEL3 SEL4 SEL1 SEL2 SEL3 SEL4 TMUX5411 (SELx = Logic 1) TMUX5412 (SELx = Logic 1) TMUX5413 (SELx = Logic 1) TMUX541x Block Diagram TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 www.ti.com

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4 Pin Configuration and Functions

5GND 12 N.C. 6S4 11 S3 7D4 10 D3 8SEL4 9 SEL3 Not to scale Figure 4-1. 16-Pin PW (TSSOP) & DYY (SOT-23-THN) Package (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME TSSOP & SOT-23- THN D1 2 I/O Drain pin 1. Can be an input or output. D2 15 I/O Drain pin 2. Can be an input or output. D3 10 I/O Drain pin 3. Can be an input or output. D4 7 I/O Drain pin 4. Can be an input or output. GND 5 P Ground (0 V) reference. N.C. 12 — No internal connection. Can be shorted to GND or left floating S1 3 I/O Source pin 1. Can be an input or output. S2 14 I/O Source pin 2. Can be an input or output. S3 11 I/O Source pin 3. Can be an input or output. S4 6 I/O Source pin 4. Can be an input or output. SEL1 1 I Logic control input 1, has internal pull-down resistor. Controls channel 1 state as provided in Table 7-2. SEL2 16 I Logic control input 2, has internal pull-down resistor. Controls channel 2 state as provided in Table 7-2. SEL3 9 I Logic control input 3, has internal pull-down resistor. Controls channel 3 state as provided in Table 7-2. SEL4 8 I Logic control input 4, has internal pull-down resistor. Controls channel 4 state as provided in Table 7-2. VDD 13 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND VSS 4 P Negative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10 µF between VSS and GND. In single- supply applications, this pin should be connected to ground. (1) I = input, O = output, I/O = input and output, P = power. www.ti.com TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT VDD – VSS Supply voltage 55 V VDD –0.5 55 V VSS –55 0.5 V VSEL or VEN Logic control input pin voltage (SELx) –0.5 55 V ISEL or IEN Logic control input pin current (SELx) -30 30 mA VS or VD Source or drain voltage (Sx, Dx) VSS–0.5 VDD+0.5 V IS or ID (CONT) Source or drain continuous current (Sx, Dx) -30 30 mA Ipeak Source or drain pulse current (Sx, Dx: pulsed at 1ms, 10% duty cycle max) -100 100 mA TA Ambient temperature –55 125 °C Tstg Storage temperature –65 150 °C TJ Junction temperature 150 °C (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to ground, unless otherwise specified.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±2000 V V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 V (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 www.ti.com

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5.3 Thermal Information

THERMAL METRIC(1) TMUX541x UNITPW (TSSOP) DYY (SOT-23)

16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 109.7 120.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 44.8 57.0 °C/W RθJB Junction-to-board thermal resistance 67.2 53.7 °C/W ΨJT Junction-to-top characterization parameter 2,6 2.6 °C/W ΨJB Junction-to-board characterization parameter 66.5 53.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

5.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD – VSS (1) Power supply voltage differential 4.5 50 V VDD Positive power supply voltage 4.5 50 V VS or VD Signal path input/output voltage (source or drain pin) (Sx, D) VSS VDD V VSEL - VSS Address or enable pin voltage 0 48 V IS or ID (CONT) Source or drain continuous current (Sx, D) -30 30 mA TA Ambient temperature –40 125 °C VIH Logic Input High (2) Logic Inputs (SEL / EN pins) 1.3 48 V VIL Logic Input Low Logic Inputs (SEL / EN pins) 0 0.8 V (1) VDD and VSS can be any value as long as 4.5V ≤ (VDD – VSS) ≤ 50V, and the minimum VDD is met. (2) Please note the VIH is limited by the following constraints: VSEL - VSS ≤ 48V www.ti.com TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5

5.5 ±15V Dual Supply: Electrical Characteristics VDD = +15V ± 10%, VSS = –15V ±10%, GND = 0V (unless otherwise noted). Typical at VDD = +15V, VSS = –15V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = –10V to +10V ID = –10mA Refer to On-Resistance 25°C 21 26 Ω –40°C to +85°C 32 Ω –40°C to +125°C 37 Ω ΔRON On-resistance mismatch between channels VS = –10V to +10V ID = –10mA Refer to On-Resistance 25°C 0.15 0.75 Ω –40°C to +85°C 1.2 Ω –40°C to +125°C 1.5 Ω RON FLAT On-resistance flatness VS = –10V to +10V IS = –10mA Refer to On-Resistance 25°C 0.02 0.45 Ω –40°C to +85°C 0.6 Ω –40°C to +125°C 0.7 Ω RON DRIFT On-resistance drift VS = 0V, IS = –10mA Refer to On-Resistance –40°C to +125°C 0.085 Ω/°C IS(OFF) Source off leakage current(1) VDD = 16.5V, VSS = –16.5V Switch state is off VS = +10V / –10V VD = –10V / + 10V Refer to Off-Leakage Current 25°C 0.003 nA –40°C to +85°C -5 5 nA –40°C to +125°C -10 10 nA ID(OFF) Drain off leakage current(1) VDD = 16.5V, VSS = –16.5V Switch state is off VS = +10V / –10V VD = –10V / + 10V Refer to Off-Leakage Current 25°C 0.003 nA –40°C to +85°C -5 5 nA –40°C to +125°C -10 10 nA IS(ON) ID(ON) Channel on leakage current(2) VDD = 16.5V, VSS = –16.5V Switch state is on VS = VD = ±10V Refer to On-Leakage Current 25°C 0.002 nA –40°C to +85°C -20 20 nA –40°C to +125°C -40 40 nA LOGIC INPUTS (SEL / EN pins) IIH Input leakage current Logic Inputs = 50V –40°C to +125°C 1.4 µA IIH Input leakage current Logic Inputs = 1.8V - 5V –40°C to +125°C 0.6 µA IIL Input leakage current –40°C to +125°C -0.1 0.0000 4 0.1 µA CIN Logic input capacitance –40°C to +125°C 4 pF POWER SUPPLY IDD VDD supply current VDD = 16.5V, VSS = –16.5V Logic inputs = 0V, 5V, or VDD 25°C 105 140 µA –40°C to +85°C 155 µA –40°C to +125°C 170 µA IDDQ VDD quiescent supply current VDD = 16.5V, VSS = –16.5V All Switches OFF –40°C to +125°C 65 µA IDD (1.8V) VDD supply current VDD = 16.5V, VSS = –16.5V Logic inputs = 1.8V –40°C to +125°C 175 µA ISS VSS supply current VDD = 16.5V, VSS = –16.5V Logic inputs = 0V, 5V, or VDD 25°C 90 110 µA –40°C to +85°C 120 µA –40°C to +125°C 130 µA ISSQ VSS quiescent supply current VDD = 16.5V, VSS = –16.5V All Switches OFF –40°C to +125°C 25 µA ISS (1.8V) VSS supply current VDD = 16.5V, VSS = –16.5V Logic inputs = 1.8V –40°C to +125°C 130 µA (1) When VS is positive, VD is negative, or when VS is negative, VD is positive. TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 www.ti.com

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(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating. 5.6 ±15V Dual Supply: Switching Characteristics VDD = +15V ± 10%, VSS = –15V ± 10%, GND = 0V (unless otherwise noted) Typical at VDD = +15V, VSS = –15V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT tON Turn-on time from control input VS = 10V RL = 1kΩ, CL = 35pF 25°C 240 300 ns –40°C to +85°C 315 ns –40°C to +125°C 320 ns tOFF Turn-off time from control input VS = 10V RL = 1kΩ, CL = 35pF 25°C 80 100 ns –40°C to +85°C 105 ns –40°C to +125°C 110 ns tBBM Break-before-make time delay (TMUX5413Only) VS = 10V, RL = 1kΩ, CL = 35pF 25°C 180 ns –40°C to +85°C 205 ns –40°C to +125°C 210 ns tON (VDD) Device turn on time (VDD to output) VDD rise time = 1µs RL = 1kΩ, CL = 35pF 25°C 0.04 ms –40°C to +85°C 0.05 ms –40°C to +125°C 0.06 ms tPD Propagation delay RL = 50Ω , CL = 5pF 25°C 400 ps QINJ Charge injection VS = 0V, CL = 100pF 25°C 13 pC OISO Off-isolation RL = 50Ω , CL = 5pF VS = 0V, f = 100kHz 25°C -100 dB OISO Off-isolation RL = 50Ω , CL = 5pF VS = 0V, f = 1MHz 25°C -82 dB XTALK Crosstalk RL = 50Ω , CL = 5pF VS = 0V, f = 100kHz 25°C -110 dB XTALK Crosstalk RL = 50Ω , CL = 5pF VS = 0V, f = 1MHz 25°C -100 dB BW –3dB Bandwidth RL = 50Ω , CL = 5pF VS = 0V 25°C 430 MHz IL Insertion loss RL = 50Ω , CL = 5pF VS = 0V, f = 1MHz 25°C -1.6 dB ACPSRR AC Power Supply Rejection Ratio VPP = 0.62V on VDD and VSS RL = 50Ω , CL = 5pF, f = 1MHz 25°C -59 dB THD+N Total Harmonic Distortion + Noise VPP = 15V, VBIAS = 0V RL = 10kΩ , CL = 5pF, f = 20Hz to 20kHz 25°C 0.0004 % CS(OFF) Source off capacitance VS = 0V, f = 1MHz 25°C 5 pF CD(OFF) Drain off capacitance VS = 0V, f = 1MHz 25°C 5 pF CS(ON), CD(ON) On capacitance VS = 0V, f = 1MHz 25°C 12 pF www.ti.com TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7

5.7 48V Single Supply: Electrical Characteristics VDD = +48V, VSS = 0V, GND = 0V (unless otherwise noted) Typical at VDD = +48V, VSS = 0V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = 5V to 43V ID = –10mA Refer to On-Resistance 25°C 21 26 Ω –40°C to +85°C 32 Ω –40°C to +125°C 40 Ω ΔRON On-resistance mismatch between channels VS = 5V to 43V ID = –10mA Refer to On-Resistance 25°C 0.14 1 Ω –40°C to +85°C 1.6 Ω –40°C to +125°C 1.7 Ω RON FLAT On-resistance flatness VS = 5V to 43V ID = –10mA Refer to On-Resistance 25°C 0.04 0.6 Ω –40°C to +85°C 0.7 Ω –40°C to +125°C 0.8 Ω RON DRIFT On-resistance drift VS = 24V, IS = –10mA Refer to On-Resistance –40°C to +125°C 0.085 Ω/°C IS(OFF) Source off leakage current(1) VDD = 48V, VSS = 0V Switch state is off VS = 43V / 1V VD = 1V / 43V Refer to Off-Leakage Current 25°C 0.004 nA –40°C to +85°C –25 25 nA –40°C to +125°C –35 35 nA ID(OFF) Drain off leakage current(1) VDD = 48V, VSS = 0V Switch state is off VS = 43V / 1V VD = 1V / 43V Refer to Off-Leakage Current 25°C 0.004 nA –40°C to +85°C –25 25 nA –40°C to +125°C –35 35 nA IS(ON) ID(ON) Channel on leakage current(2) VDD = 44V, VSS = 0V Switch state is on VS = VD = 40V or 1V Refer to Section 6.3 25°C 0.004 nA –40°C to +85°C –25 25 nA –40°C to +125°C -35 35 nA LOGIC INPUTS (SEL / EN pins) IIL Input leakage current –40°C to +125°C -0.1 –0.001 0.1 µA CIN Logic input capacitance –40°C to +125°C 5 pF POWER SUPPLY IDD VDD supply current VDD = 48V, VSS = 0V Logic inputs = 0V, 5V, or VDD 25°C 125 155 µA –40°C to +85°C 170 µA –40°C to +125°C 180 µA IDD (1.8V) VDD supply current VDD = 48V, VSS = 0V Logic inputs = 1.8V –40°C to +125°C 190 µA IDDQ VDD quiescent supply current VDD = 48V, VSS = 0V All Switches OFF –40°C to +125°C 65 µA (1) When VS is positive, VD is negative, or when VS is negative, VD is positive. (2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating. TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 www.ti.com

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5.8 48V Single Supply: Switching Characteristics VDD = +48V, VSS = 0V, GND = 0V (unless otherwise noted) Typical at VDD = +48V, VSS = 0V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT tON Turn-on time from control input VS = 18V RL = 1kΩ, CL = 35pF 25°C 225 275 ns –40°C to +85°C 285 ns –40°C to +125°C 295 ns tOFF Turn-off time from control input VS = 18V RL = 1kΩ, CL = 35pF 25°C 90 115 ns –40°C to +85°C 120 ns –40°C to +125°C 125 ns tON (VDD) Device turn on time (VDD to output) VDD rise time = 1µs RL = 1kΩ, CL = 35pF –40°C to +125°C 0.01 ms tPD Propagation delay RL = 50Ω , CL = 5pF 25°C 475 ps QINJ Charge injection VS = 24V, CL = 100pF 25°C 13 pC OISO Off-isolation RL = 50Ω , CL = 5pF VS = 6V, f = 100kHz 25°C -100 dB OISO Off-isolation RL = 50Ω , CL = 5pF VS = 6V, f = 1MHz 25°C -82 dB XTALK Crosstalk RL = 50Ω , CL = 5pF VS = 6V, f = 100kHz 25°C -110 dB XTALK Crosstalk RL = 50Ω , CL = 5pF VS = 6V, f = 1MHz 25°C -100 dB BW –3dB Bandwidth RL = 50Ω , CL = 5pF VS = 6V 25°C 400 MHz IL Insertion loss RL = 50Ω , CL = 5pF VS = 6V, f = 1MHz 25°C -1.6 dB ACPSRR AC Power Supply Rejection Ratio VPP = 0.62V on VDD and VSS RL = 50Ω , CL = 5pF, f = 1MHz 25°C -62 dB THD+N Total Harmonic Distortion + Noise VPP = 24V, VBIAS = 24V RL = 10kΩ , CL = 5pF, f = 20Hz to 20kHz 25°C 0.0003 % CS(OFF) Source off capacitance VS = 24V, f = 1MHz 25°C 5 pF CD(OFF) Drain off capacitance VS = 24V, f = 1MHz 25°C 5 pF CS(ON), CD(ON) On capacitance VS = 24V, f = 1MHz 25°C 12 pF www.ti.com TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9

5.9 12 V Single Supply: Electrical Characteristics VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON On-resistance VS = 0 V to 10 V ID = –10 mA Refer to On-Resistance 25°C 42 50 Ω –40°C to +85°C 70 Ω –40°C to +125°C 75 Ω ΔRON On-resistance mismatch between channels VS = 0 V to 10 V ID = –10 mA Refer to On-Resistance 25°C 0.4 1.3 Ω –40°C to +85°C 1.5 Ω –40°C to +125°C 1.6 Ω RON FLAT On-resistance flatness VS = 0 V to 10 V IS = –10 mA Refer to On-Resistance 25°C 21 25 Ω –40°C to +85°C 35 Ω –40°C to +125°C 40 Ω RON DRIFT On-resistance drift VS = 6 V, IS = –10 mA Refer to On-Resistance –40°C to +125°C 0.085 Ω/°C IS(OFF) Source off leakage current(1) VDD = 13.2 V, VSS = 0 V Switch state is off VS = 10 V / 1 V VD = 1 V / 10 V Refer to Off-Leakage Current 25°C 0.01 nA –40°C to +85°C -25 25 nA –40°C to +125°C -35 35 nA ID(OFF) Drain off leakage current(1) VDD = 13.2 V, VSS = 0 V Switch state is off VS = 10 V / 1 V VD = 1 V / 10 V Refer to Off-Leakage Current 25°C 0.01 nA –40°C to +85°C -25 25 nA –40°C to +125°C -35 35 nA IS(ON) ID(ON) Channel on leakage current(2) VDD = 13.2 V, VSS = 0 V Switch state is on VS = VD = 10 V or 1 V Refer to On-Leakage Current 25°C 0.01 nA –40°C to +85°C –25 25 nA –40°C to +125°C –35 35 nA LOGIC INPUTS (SEL / EN pins) CIN Logic input capacitance –40°C to +125°C 5.5 pF POWER SUPPLY IDD VDD supply current VDD = 13.2 V, VSS = 0 V Logic inputs = 0 V, 5 V, or VDD 25°C 115 135 µA –40°C to +85°C 150 µA –40°C to +125°C 165 µA IDD (1.8V) VDD supply current VDD = 13.2 V, VSS = 0 V Logic inputs = 1.8 V –40°C to +125°C 170 µA IDDQ VDD quiescent supply current VDD = 13.2 V, VSS = 0 V All Switches OFF –40°C to +125°C 50 µA (1) When VS is positive, VD is negative, or when VS is negative, VD is positive. (2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating. TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 www.ti.com

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5.10 12V Single Supply: Switching Characteristics VDD = +12V ± 10%, VSS = 0V, GND = 0V (unless otherwise noted) Typical at VDD = +12V, VSS = 0V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT tON Turn-on time from control input VS = 8V RL = 1kΩ, CL = 35pF 25°C 250 300 ns –40°C to +85°C 310 ns –40°C to +125°C 320 ns tOFF Turn-off time from control input VS = 8V RL = 1kΩ, CL = 35pF 25°C 85 120 ns –40°C to +85°C 125 ns –40°C to +125°C 130 ns tON (VDD) Device turn on time (VDD to output) VDD rise time = 1µs RL = 1kΩ, CL = 35pF 25°C 0.06 ms tPD Propagation delay RL = 50Ω , CL = 5pF 25°C 500 ps QINJ Charge injection VS = 6V, CL = 100pF 25°C 7 pC OISO Off-isolation RL = 50Ω , CL = 5pF VS = 6V, f = 100kHz 25°C -100 dB OISO Off-isolation RL = 50Ω , CL = 5pF VS = 6V, f = 1MHz 25°C --82 dB XTALK Crosstalk RL = 50Ω , CL = 5pF VS = 6V, f = 100kHz 25°C --110 dB XTALK Crosstalk RL = 50Ω , CL = 5pF VS = 6V, f = 1MHz 25°C -100 dB BW –3dB Bandwidth RL = 50Ω , CL = 5pF VS = 6V 25°C 375 MHz IL Insertion loss RL = 50Ω , CL = 5pF VS = 6V, f = 1MHz 25°C -1.6 dB ACPSRR AC Power Supply Rejection Ratio VPP = 0.62V on VDD and VSS RL = 50Ω , CL = 5pF, f = 1MHz 25°C -56 dB THD+N Total Harmonic Distortion + Noise VPP = 6V, VBIAS = 6V RL = 10kΩ , CL = 5pF, f = 20Hz to 20kHz 25°C 0.004 % CS(OFF) Source off capacitance VS = 6V, f = 1MHz 25°C 6 pF CD(OFF) Drain off capacitance VS = 6V, f = 1MHz 25°C 6 pF CS(ON), CD(ON) On capacitance VS = 6V, f = 1MHz 25°C 14.5 pF www.ti.com TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11

5.11 Typical Characteristics

at TA = 25°C (unless otherwise noted) TA = 25° Figure 5-1. On-Resistance vs Source or Drain Voltage for Dual Supply V S o r V D - S o u r c e o r D r a i n V o l t a g e ( V ) On Resistance () 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 V D D = 1 2 , V S S = 0 V D D = 3 6 , V S S = 0 V D D = 4 8 , V S S = 0 TA = 25° Figure 5-2. On-Resistance vs Source or Drain Voltage for Single Supply V S o r V D - S o u r c e o r D r a i n V o l t a g e On Resistance () - 1 0 - 7 . 5 - 5 - 2 . 5 0 2 . 5 5 7 . 5 1 0 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 T A = - 4 0  C T A = 2 5  C T A = 8 5  C T A = 1 2 5  C VDD=15V, VSS=-15V Figure 5-3. On-Resistance vs Source or Drain Operational Voltage (Flat Region) V S o r V D - S o u r c e o r D r a i n V o l t a g e On Resistance () - 1 5 - 1 3 - 1 1 - 9 - 7 - 5 - 3 - 1 1 3 5 7 9 1 1 1 3 1 5 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 T A = - 4 0  C T A = 2 5  C T A = 8 5  C T A = 1 2 5  C VDD = 15V, VSS = -15V Figure 5-4. On-Resistance vs Source or Drain Voltage TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 www.ti.com

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5.11 Typical Characteristics (continued)

at TA = 25°C (unless otherwise noted) V S - S o u r c e o r D r a i n V o l t a g e Leakage Current (pA) - 1 5 - 1 2 - 9 - 6 - 3 0 3 6 9 1 2 1 5 - 2 5 - 2 0 - 1 5 - 1 0 - 5 1 0 1 5 2 0 2 5 I O N I S O F F VDD = 15V, VSS = -15V; TA = 25° Figure 5-5. Leakage Current vs Bias Voltage V S - S o u r c e V o l t a g e ( V ) Charge Injection (pC) - 5 1 0 1 5 2 0 2 5 3 0 3 5 T A = 2 5  C T A = 8 5  C T A = 1 2 5  C VDD = 15V, VSS = -15V Figure 5-6. Charge Injection vs Source Voltage F r e q u e n c y ( H z ) Magnitude (dB) - 1 0 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 1 0 0 k 1 M 1 0 M 1 0 0 M 5 0 0 M V D D / S S = ± 1 5 V VDD = 15V, VSS = -15V Figure 5-7. ±15V Bandwidth vs. Frequency F r e q u e n c y ( H z ) Magnitude (dB) - 1 0 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 1 0 0 k 1 M 1 0 M 1 0 0 M 5 0 0 M V D D = 4 8 V VDD = 48V, VSS = GND Figure 5-8. 48V Bandwidth vs. Frequency www.ti.com TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13

6 Parameter Measurement Information

6.1 On-Resistance

The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol R ON is used to denote on-resistance. Figure 6-1 shows the measurement setup used to measure RON. Voltage (V) and current (ISD) are measured using this setup, and RON is computed with RON = V / ISD: V Dx VS ISD Sx RON Figure 6-1. On-Resistance Measurement Setup

6.2 Off-Leakage Current

There are two types of leakage currents associated with a switch during the off state: 1. Source off-leakage current. 2. Drain off-leakage current. Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is off. This current is denoted by the symbol IS(OFF). Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off. This current is denoted by the symbol ID(OFF). Figure 6-2 shows the setup used to measure both off-leakage currents. GND VS VD A Is (OFF) VDD VSS IS(OFF) GND VS VD VDD VSS ID(OFF) ID (OFF) A VS A Is (OFF) VD S4 D4 ID (OFF) A VS VD Figure 6-2. Off-Leakage Measurement Setup TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 www.ti.com

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6.3 On-Leakage Current

Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch is on. This current is denoted by the symbol IS(ON). Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is on. This current is denoted by the symbol ID(ON). Either the source pin or drain pin is left floating during the measurement. Figure 6-3 shows the circuit used for measuring the on-leakage current, denoted by IS(ON) or ID(ON). GND VS D1A Is (ON) VDD VSS IS(ON) GND VD VDD VSS ID(ON) ID (ON) A VS A Is (ON) D4 S4 D4 ID (ON) A VD N.C. N.C. N.C. N.C. Figure 6-3. On-Leakage Measurement Setup 6.4 tON and tOFF Time Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level timing can then account for the time constant added from the load resistance and load capacitance. Figure 6-4 shows the setup used to measure turn-on time, denoted by the symbol tON. Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level timing can then account for the time constant added from the load resistance and load capacitance. Figure 6-4 shows the setup used to measure turn-off time, denoted by the symbol tOFF. 3 V VEN 0 V 50% 50% tON tOFF 90%90% Output tr < 20 ns tf < 20 ns VDD VSS VDD VSS 0.1 µF 0.1 µF GND0 V VSELx CL Sx Dx Output CLRL Figure 6-4. Turn-On and Turn-Off Time Measurement Setup www.ti.com TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15

6.5 Propagation Delay

Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal has risen or fallen past the 50% threshold. Figure 6-5 shows the setup used to measure propagation delay, denoted by the symbol tPD. RL CL VDD VSS VDD VSS 0.1 µF 0.1 µF GND D1 OutputVS 250 mV 0 V tPD 1 Output 0 V tProp Delay = max ( tPD 1, tPD 2) Input (VS) tr < 40ps tf < 40ps tPD 2 50% 50% 50% 50% RL CL OutputD4VS Figure 6-5. Propagation Delay Measurement Setup TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 www.ti.com

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6.6 Charge Injection

This device has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted by the symbol QC. Figure 6-6 shows the setup used to measure charge injection from source (Sx) to drain (Dx). VDD VSS VDD VSS 0.1 µF 0.1 µF GND SELx VSEL VOUT Output VS 0 V 3 V VSEL QINJ = CL × VOUT tr < 20 ns tf < 20 ns S1 D1 S4 D4 Output Output CL CL Figure 6-6. Charge-Injection Measurement Setup

6.7 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the source pin (Sx) of an off-channel. The characteristic impedance, Z 0, for the measurement is 50 Ω. Figure 6-7 shows the setup used to measure off isolation. Use off isolation equation to compute off isolation. GND VSIG VOUT50Ÿ 50Ÿ Network Analyzer 1BB +OKH=PEKJ = 20 × .KC 8176 VDD VSS VDD VSS 0.1 µF 0.1 µF 50Ÿ Sx/Dx VS Figure 6-7. Off Isolation Measurement Setup www.ti.com TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17

6.8 Channel-to-Channel Crosstalk

Crosstalk is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is applied at the source pin (Sx) of an on-channel. The characteristic impedance, Z 0, for the measurement is 50Ω. Figure 6-8 shows the setup used to measure, and the equation used to compute crosstalk. GND Network Analyzer VDD VSS VDD VSS 0.1 µF 0.1 µF %NKOOP=HG = 20 ×.KC 8176 50Ÿ 50Ÿ Sx/Dx VOUT VSIG 50Ÿ 50Ÿ Vs 50Ÿ Figure 6-8. Channel-to-Channel Crosstalk Measurement Setup

6.9 Bandwidth

Bandwidth is defined as the range of frequencies that are attenuated by less than 3dB when the input is applied to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The characteristic impedance, Z 0, for the measurement is 50Ω. Figure 6-9 shows the setup used to measure bandwidth. GND Sx Dx VSIG VOUT50Ÿ 50Ÿ Network Analyzer VDD VSS VDD VSS 0.1 µF 0.1 µF VS $=J@SE@PD = 20 ×.KC 8176 Figure 6-9. Bandwidth Measurement Setup TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 www.ti.com

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6.10 THD + Noise

The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux output. The on-resistance of the device varies with the amplitude of the input signal and results in distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as THD + N. GND SX Dx Audio Precision VOUT RL VDD VSS VDD VSS 0.1 µF 0.1 µF VS 40 Ÿ Figure 6-10. THD + N Measurement Setup

6.11 Power Supply Rejection Ratio (PSRR)

PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave of 100mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the AC PSRR. 620 mVPP RL Network Analyzer VOUT VDD DC Bias Injector VIN CL VBIAS GND VDD VSS VSS 0.1 µF 2544 = 20 ×.KC8176 8+0 0.1 µF With & Without Capacitor Other Sx/ Dx pins 50 Ÿ 50 Ÿ 50 Ÿ Figure 6-11. AC PSRR Measurement Setup www.ti.com TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19

7 Detailed Description

7.1 Overview

TMUX541x is a 1:1 (SPST), 4-channel switch. This device has four independently selectable single-pole, single- throw switches that are turned-on or turned-off based on the state of the corresponding select pin. This device works well with dual supplies, a single supply, or asymmetric supplies such as VDD = 37.5V, VSS = –12.5V.

7.2 Functional Block Diagram

(SELx = Logic 1) TMUX5412 (SELx = Logic 1) TMUX5413 (SELx = Logic 1)

7.3 Feature Description

7.3.1 Bidirectional Operation

The TMUX541x conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each channel has similar characteristics in both directions and supports both analog and digital signals.

7.3.2 Rail-to-Rail Operation

The valid signal path input and output voltage for TMUX541x ranges from VSS to VDD. 7.3.3 1.8 V Logic Compatible Inputs The TMUX541x has 1.8V logic compatible control for all logic control inputs. 1.8V logic level inputs allows the TMUX541x to interface with processors that have lower logic I/O rails and eliminates the need for an external translator, which saves both space and BOM cost. For more information on 1.8V logic implementations, refer to Simplifying Design with 1.8 V logic Muxes and Switches.

7.3.4 Flat On-Resistance

The TMUX541x is designed with a special switch architecture to produce ultra-flat on-resistance (RON) across most of the switch input operating region. The flat RON response allows the device to be used in a wide variety of applications since the RON is controlled regardless of the signals sampled. The architecture is implemented without a charge pump so unwanted noise is not produced from the device to affect sampling accuracy. This architecture also keeps RON the same regardless of the supply voltage. The flattest on-resistance region extends roughly from 5V above VSS to 5V below VDD. As long as this headroom is maintained, the TMUX541x exhibits an extremely linear response.

7.3.5 Power-Up Sequence Free

The TMUX541x supports any power up sequencing. With the supply rails (VDD and VSS), any rail can be powered on first. Similarly, when powering down the supply rails can be powered down in any order. TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 www.ti.com

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7.4 Device Functional Modes

The TMUX541x has four independently selectable single-pole, single-throw switches that are turned-on or turned-off based on the state of the corresponding select pin. The control pins operate down to 1.8V logic and can be as high as 48V. The TMUX541x devices can be operated without any external components except for the supply decoupling capacitors. The SELx pins have internal pull-down resistors.

7.4.1 Truth Tables

TMUX5412 Truth Table provides the truth table for TMUX541x. Table 7-1. TMUX5411 Truth Table SEL x (1) CHANNEL x

0 Channel x ON

1 Channel x OFF

Table 7-2. TMUX5412 Truth Table SEL x (1) CHANNEL x

0 Channel x OFF

1 Channel x ON

Table 7-3. TMUX5413 Truth Table SEL1 SEL2 SEL3 SEL4 ON / OFF CHANNELS(1)

0 X X X CHANNEL 1 OFF

1 X X X CHANNEL 1 ON

(1) x denotes 1, 2, 3, or 4 for the corresponding channel. www.ti.com TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TMUX541x is a part of the general purpose switches and multiplexers family of devices. The device operates with dual supplies (±4.5V to ±25V), a single supply (4.5V to 50V), or asymmetric supplies (such as VDD = 37.5V, VSS = –12.5V), and offers a true rail-to-rail input and output signal range. The TMUX541x offers a low RON, low on and off leakage currents, and high bandwidth. These features make the TMUX541x a great option for broad range of high-voltage industrial applications.

8.1.1 Typical Application - Gain Switching

In some applications, such as audio, changes in signal amplification are needed often. Commonly a multiplexer is used to switch between gain resistors, but when your system is operating at ±15V or higher it's challenging to find an appropriate option. TMUX541x is TI's first line of high-voltage general purpose multiplexers that give a cost-efficient option for high voltage applications such as these. Gain Switching Example Figure 8-1. On-Resistance vs Source or Drain Voltage TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 www.ti.com

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8.1.1.1 Design Requirements

For this design example, use the parameters listed in Table 8-1. Table 8-1. Design Parameters PARAMETERS VALUES Supply (VDD) 15V Supply (VSS) –15V Input / Output signal range –15V to 15V (Rail-to-Rail operation) –10V to 10V (Best performance with headroom) Max current through each channel 30mA Control logic thresholds 1.8V compatible

8.1.1.2 Application Curve

TMUX541x has very flat R ON; however, when the signal approaches within 5V of either supply the R ON increases. The plots below show two scenarios: 1. operating with the signal range 5V away from the supply rail and 2. operating with the signal range up to the supply rail. V S o r V D - S o u r c e o r D r a i n V o l t a g e On Resistance () - 1 5 - 1 3 - 1 1 - 9 - 7 - 5 - 3 - 1 1 3 5 7 9 1 1 1 3 1 5 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 V S = ± 1 0 V VDD = 15 V, VSS = -15 V Figure 8-2. On-Resistance vs Source or Drain Voltage up to ±10V V S o r V D - S o u r c e o r D r a i n V o l t a g e On Resistance () - 1 5 - 1 3 - 1 1 - 9 - 7 - 5 - 3 - 1 1 3 5 7 9 1 1 1 3 1 5 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 V S = ± 1 5 V VDD =15 V, VSS = -15 V Figure 8-3. On-Resistance vs Source or Drain Voltage up to ±15V

8.2 Power Supply Recommendations

The TMUX541x device operates across a wide supply range of ±4.5V to ±25V (4.5V to 50V in single-supply mode). The device also performs well with asymmetrical supplies such as VDD = 37.5V and VSS = –12.5V. Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails to other components. Good power-supply decoupling is important to achieve optimum performance. For improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10μF at both the V DD and VSS pins to ground. Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground and power planes. Always make sure a solid ground (GND) connection is established before supplies are ramped. www.ti.com TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23

8.3 Layout

8.3.1 Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 8-4 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections. WORST BETTER BEST 1W min. W Figure 8-4. Trace Example Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points, through-hole pins are not recommended at high frequencies. Figure 8-5 shows an example of a PCB layout with the TMUX541x. Some key considerations are:

• For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD/VSS and GND. We recommend a 0.1µF and 1µF capacitor, placing the lowest value capacitor as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary.
• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground planes.

8.3.2 Layout Example

N.C. SEL3 GND SEL4 C C C Wide (low inductance) trace for power Wide (low inductance) trace for power Via to ground plane C TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 www.ti.com

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C D1D4 S1 S2 SEL1SEL4 VSS VDD SEL2SEL3 GND NC D2D3 S4 S3 C Via to ground plane CC Wide (low inductance) trace for power Wide (low inductance) trace for power Figure 8-5. TMUX541x Layout Example www.ti.com TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25

9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, When to Replace a Relay with a Multiplexer application brief
• Texas Instruments, Improving Signal Measurement Accuracy in Automated Test Equipment application brief
• Texas Instruments, Sample & Hold Glitch Reduction for Precision Outputs Reference Design reference guide
• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief
• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application note
• Texas Instruments, QFN/SON PCB Attachment application note

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (July 2025) to Revision A (September 2025) Page DATE REVISION NOTES July 2025 * Initial Release TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 www.ti.com

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TMUX5411, TMUX5412, TMUX5413 SCDS485A – JULY 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27

www.ti.com 4-Dec-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PTMUX5411DYYR Active Preproduction SOT-23-THIN (DYY) | 16 3000 | LARGE T&R - Call TI Call TI -40 to 125 PTMUX5411PWR Active Preproduction TSSOP (PW) | 16 3000 | LARGE T&R - Call TI Call TI -40 to 125 PTMUX5412DYYR Active Preproduction SOT-23-THIN (DYY) | 16 3000 | LARGE T&R - Call TI Call TI -40 to 125 PTMUX5412PWR Active Preproduction TSSOP (PW) | 16 3000 | LARGE T&R - Call TI Call TI -40 to 125 PTMUX5413DYYR Active Preproduction SOT-23-THIN (DYY) | 16 3000 | LARGE T&R - Call TI Call TI -40 to 125 PTMUX5413PWR Active Preproduction TSSOP (PW) | 16 3000 | LARGE T&R - Call TI Call TI -40 to 125 TMUX5411DYYR Active Production SOT-23-THIN (DYY) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TM5411 TMUX5411PWR Active Production TSSOP (PW) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TM5411 TMUX5412DYYR Active Production SOT-23-THIN (DYY) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TM5412 TMUX5412PWR Active Production TSSOP (PW) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TM5412 TMUX5413DYYR Active Production SOT-23-THIN (DYY) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TM5413 TMUX5413PWR Active Production TSSOP (PW) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TM5413 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. Addendum-Page 1

www.ti.com 4-Dec-2025 (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TMUX5411DYYR SOT-23- THIN TMUX5412DYYR SOT-23- THIN TMUX5413DYYR SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMUX5411DYYR SOT-23-THIN DYY 16 3000 336.6 336.6 31.8 TMUX5411PWR TSSOP PW 16 3000 353.0 353.0 32.0 TMUX5412DYYR SOT-23-THIN DYY 16 3000 336.6 336.6 31.8 TMUX5412PWR TSSOP PW 16 3000 353.0 353.0 32.0 TMUX5413DYYR SOT-23-THIN DYY 16 3000 336.6 336.6 31.8 TMUX5413PWR TSSOP PW 16 3000 353.0 353.0 32.0 Pack Materials-Page 2

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AA PACKAGE OUTLINE 4224642/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0016A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.5 3.5 16X 0.3 0.11

0.1 C A B

1.1 MAX

C SEATING PLANE 0.2

0.08 TYP

0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 4X 0° - 15° 4X 4° - 15°

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224642/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0016A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 16X (0.3) 16X (1.05) (3) 14X (0.5) (R0.05) TYP 8 9 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224642/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0016A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 16X (0.3) 16X (1.05) (3) 14X (0.5) (R0.05) TYP 8 9

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

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