PTMUX4052DYYRQ1

TMUX4051-Q1_V03 TI | Alldatasheet

Document overview

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Technical content

TMUX405x-Q1 Automotive 24-V, 8:1, 1-Channel, and 4:1, 2-Channel Multiplexers with 1.8-V Logic

1 Features

• AEC-Q100 qualified for automotive applications – Device temperature grade 1: –40°C to 125°C ambient operating temperature
• Single supply range: 5 V to 24 V
• Dual supply range: up to ±12 V
• Low capacitance: 3 pF
• –55°C to +125°C operating temperature
• Bidirectional signal path
• Rail-to-rail operation
• 1.8 V logic compatible
• Break-before-make switching
• ESD protection HBM: 2000 V
• TMUX405x – pin compatible with: – Industry standard 4051 and 4052 muxes

2 Applications

• Analog multiplexing and demultiplexing
• Battery management systems (BMS)
• HVAC control module
• Telematics
• On-board (OBC) and wireless charging

3 Description

The TMUX405x-Q1 devices are general purpose complementary metal-oxide semiconductor (CMOS) multiplexers (MUX). The TMUX4051-Q1 is an 8:1, 1- channel multiplexer and the TMUX4052-Q1 is a 4:1, 2-channel multiplexer. The devices work with a single supply (5 V to 24 V), dual supplies (up to ±12 V), or asymmetric supplies (such as V DD = 12 V, V SS = –5 V). The wide supply voltage range allows the TMUX405x-Q1 devices to be used in a broad array of applications from battery testers to appliances. The TMUX405x-Q1 devices support bidirectional analog signals on the source (Sx) and drain (Dx) pins ranging from V SS to V DD. All logic inputs have 1.8 V logic compatible thresholds, which is compatible for both TTL and CMOS logic when operating with a valid supply voltage. Package Information(1)(2) PART NUMBER PACKAGE BODY SIZE (NOM) TMUX4051-Q1 TMUX4052-Q1 PW (TSSOP, 16) 5.00 mm × 4.40 mm DYY (SOT-23-THIN, 16) 4.20 mm × 2.00 mm BQB (WQFN, 16) 3.50 mm × 2.50 mm (1) For all available packages, see the package option addendum at the end of the data sheet. (2) See the Device Comparison Table TMUX4051-Q1 A2 A1 A0 EN D S3 1-OF-8 DECODER TMUX4052-Q1 S0A DB S1A S2A S3A S0B S1B S2B S3B DA A1 A0 EN 1-OF-4 DECODER TMUX4051-Q1 and TMUX4052-Q1 Block Diagram TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11.2 Receiving Notification of Documentation Updates.. 26

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (June 2022) to Revision A (March 2023) Page TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 www.ti.com

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5 Device Comparison Table

TMUX4051-Q1 8:1, 1-channel multiplexer TMUX4052-Q1 4:1, 2-channel multiplexer www.ti.com TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

6 Pin Configuration and Functions

Figure 6-1. TMUX4051-Q1 PW Package, 16-Pin TSSOP (Top View) 1S4 16 VDD 2S6 15 S2 3D 14 S1 4S7 13 S0 5S5 12 S3 6 11 A0 7VSS 10 A1 8GND 9 A2 Not to scale Figure 6-2. TMUX4051-Q1 DYY Package, 16-Pin SOT-23-THIN (Top View) Thermal Pad 2S6 4S7 5S5 7VSS 8GND 9A2 10 A1 11 A0 12 S3 13 S0 14 S1 15 S2

16 VDD

Figure 6-3. TMUX4051-Q1 BQB Package, 16-Pin WQFN (Top View) Table 6-1. Pin Functions TMUX4051-Q1 PIN TYPE(1) DESCRIPTION(2) NAME NO. S4 1 I/O Source pin 4. Signal path can be an input or output. S6 2 I/O Source pin 6. Signal path can be an input or output. D 3 I/O Drain pin (common). Signal path can be an input or output. S7 4 I/O Source pin 7. Signal path can be an input or output. S5 5 I/O Source pin 5. Signal path can be an input or output. EN 6 I Active low logic enable. When this pin is high, all switches are turned off. Table 9-1 lists how the A[2:0] address inputs determine which switch is turned on when this pin is low. VSS 7 P Negative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. GND 8 P Ground (0 V) reference A2 9 I Address line 2. Table 9-1 provides information about how A2 controls the switch configuration. A1 10 I Address line 1. Table 9-1 provides information about how A1 controls the switch configuration. A0 11 I Address line 0. Table 9-1 provides information about how A0 controls the switch configuration. S3 12 I/O Source pin 3. Signal path can be an input or output. S0 13 I/O Source pin 0. Signal path can be an input or output. S1 14 I/O Source pin 1. Signal path can be an input or output. S2 15 I/O Source pin 2. Signal path can be an input or output. VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. Thermal pad — The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to GND. (1) I = input, O = output, I/O = input and output, P = power. (2) For what to do with unused pins, refer to Section 9.3.4. TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 www.ti.com

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Figure 6-4. TMUX4052-Q1 PW Package, 16-Pin TSSOP (Top View) 1S0B 16 VDD 2S2B 15 S2A 3DB 14 S1A 4S3B 13 DA 5S1B 12 S0A 6 11 S3A 7VSS 10 A0 8GND 9 A1 Not to scale Figure 6-5. TMUX4052-Q1 DYY Package, 16-Pin SOT-23-THIN (Top View) Thermal Pad 2S2B 3DB 4S3B 5S1B 7VSS 8GND 9A1 10 A0

11 S3A

12 S0A

14 S1A

15 S2A

1 S0B

Figure 6-6. TMUX4052-Q1 BQB Package, 16-Pin WQFN (Top View) Table 6-2. Pin Functions TMUX4052-Q1 PIN TYPE(1) DESCRIPTION(2) NAME NO. S0B 1 I/O Source pin 0 of mux B. Can be an input or output. S2B 2 I/O Source pin 2 of mux B. Can be an input or output. DB 3 I/O Drain pin (common) of mux B. Can be an input or output. S3B 4 I/O Source pin 3 of mux B. Can be an input or output. S1B 5 I/O Source pin 1 of mux B. Can be an input or output. EN 6 I Active low logic enable. When this pin is high, all switches are turned off. When this pin is low, the A[1:0] address inputs determine which switch is turned on. VSS 7 P Negative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. GND 8 P Ground (0 V) reference A1 9 I Address line 1. Table 9-2 provides information about how A1 controls the switch configuration. A0 10 I Address line 0. Table 9-2 provides information about how A0 controls the switch configuration. S3A 11 I/O Source pin 3 of mux A. Can be an input or output. S0A 12 I/O Source pin 0 of mux A. Can be an input or output. DA 13 I/O Drain pin (common) of mux A. Can be an input or output. S1A 14 I/O Source pin 1 of mux A. Can be an input or output. S2A 15 I/O Source pin 2 of mux A. Can be an input or output. VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. Thermal pad — The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to GND. (1) I = input, O = output, I/O = input and output, P = power. (2) For what to do with unused pins, refer to Section 9.3.4 . www.ti.com TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (3) MIN MAX UNIT VDD – VSS Supply voltage 28 V VDD –0.5 28 V VSS –28 0.5 V VSEL or VEN Logic control input pin voltage (EN, Ax, SELx) –0.5 28 V ISEL or IEN Logic control input pin current (EN, Ax, SELx) –0.5 28 mA VS or VD Source or drain voltage (Sx, D) VSS–0.5 VDD+0.5 V IIK Diode clamp current(2) –30 30 mA IS or ID (CONT) Source or drain continuous current (Sx, D) –10 10 mA TJ Junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings. (3) To avoid drawing excess current from VDD, or into VSS, the voltage drop across the bidirectional switch path (ΔVswitch) must not exceed 1.2 V (600 mV for high temperature).

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) All pins ±2000 VCharged device model (CDM), per AEC Q100-011 All pins ±750 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 www.ti.com

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7.3 Thermal Information: TMUX4051-Q1

THERMAL METRIC (1) TMUX4051-Q1 UNITPW (TSSOP) DYY (SOT) BQB (WQFN)

16 PINS 16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 116.5 138.9 70.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 47.2 70.3 67.8 °C/W RθJB Junction-to-board thermal resistance 63.0 69.1 40.2 °C/W ΨJT Junction-to-top characterization parameter 6.4 5.1 3.9 °C/W ΨJB Junction-to-board characterization parameter 62.1 69.0 40.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 18.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information: TMUX4052-Q1

THERMAL METRIC (1) TMUX4052-Q1 UNITPW (TSSOP) DYY (SOT) BQB (WQFN) RθJA Junction-to-ambient thermal resistance 116.5 138.9 70.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 47.2 70.3 67.8 °C/W RθJB Junction-to-board thermal resistance 63.0 69.1 40.2 °C/W ΨJT Junction-to-top characterization parameter 6.4 5.1 3.9 °C/W ΨJB Junction-to-board characterization parameter 62.1 69.0 40.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 18.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD – VSS (1) Power supply voltage differential 5 24 V VDD Positive power supply voltage 5 24 V VSS Negative power supply voltage –15 0 V VS or VD Signal path input/output voltage (source or drain pin) (Sx, D) VSS VDD V VAx or VEN Address or enable pin voltage 0 VDD V IS or ID (CONT) Source or drain continuous current (Sx, D) –10 10 mA TA Ambient temperature –55 125 °C (1) VDD and VSS can be any value as long as 5 V ≤ (VDD – VSS) ≤ 24 V, and the minimum VDD and VSS are met. www.ti.com TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

7.6 Electrical Characteristics

Over operating free-air temperature range, Typical at TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS VDD VSS TA MIN TYP MAX UNIT POWER SUPPLY Supply current IDD Address inputs = 0 V, 5 V, or VDD EN = 0 V 5 V 0 V –55°C 60 µA 25°C 17 60 85°C 80 125°C 80 Address inputs = 0 V, 5 V, or VDD EN = 0 V 10 V 0 V –55°C 60 25°C 18 60 85°C 80 125°C 80 Address inputs = 0 V, 5 V, or VDD EN = 0 V 24 V 0 V –55°C 60 25°C 21 60 85°C 80 125°C 80 Address inputs = 0 V, 5 V, or VDD EN = 0 V 5 V –5 V –55°C 60 25°C 18 60 85°C 80 125°C 80 Address inputs = 0 V, 5 V, or VDD EN = 0 V 12 V –12 V –55°C 60 25°C 20 60 85°C 80 125°C 80 Negative supply current ISS Address inputs = 0 V, 5 V, or VDD EN = 0 V 5 V –5 V –55°C 20 µA 25°C 6 20 85°C 25 125°C 25 Address inputs = 0 V, 5 V, or VDD EN = 0 V 12 V –12 V –55°C 22 25°C 7 22 85°C 26 125°C 26 IDD disable EN = 5 V or VDD All 25°C 8 µA –55°C to 125°C 20 TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 www.ti.com

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7.6 Electrical Characteristics (continued)

Over operating free-air temperature range, Typical at TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS VDD VSS TA MIN TYP MAX UNIT ANALOG SWITCH RON Source to Drain ON- Resistance VS = VSS to VDD ID = –1 mA 5 V 0 V –55°C 800 Ω 25°C 75 1050 85°C 1200 125°C 1300 VS = VSS to VDD ID = –1 mA 10 V 0 V –55°C 310 25°C 60 400 85°C 520 125°C 550 VS = VSS to VDD ID = –1 mA 24 V 0 V –55°C 200 25°C 60 240 85°C 300 125°C 300 VS = VSS to VDD ID = –1 mA 5 V –5 V –55°C 310 25°C 60 400 85°C 520 125°C 550 VS = VSS to VDD ID = –1 mA 12 V –12 V –55°C 200 25°C 60 240 85°C 300 125°C 300 ΔRON VS = VSS to VDD ID = –1 mA All 25°C 2 Ω RON FLAT VS = VSS to VDD ID = –1 mA All 25°C 60 Ω–55°C to 85°C 150 –55°C to 125°C 150 IS(OFF) ID(OFF) Switch State is off VS = VSS / VDD VD = VDD / VSS

24 V 0 V

25°C ±0.3 ±100 nA–55°C to 85°C ±800 –55°C to 125°C ±1000 ION Switch State is on VS = VD = VSS or VDD 25°C ±0.3 ±100 nA–55°C to 85°C ±800 –55°C to 125°C ±1000 LOGIC INPUTS (ADDRESS / ENABLE pins) VIH Input High Voltage All –55°C to 125°C 1.35 VDD V VIL Input Low Voltage All –55°C to 125°C 0 0.8 V IIH IIL Logic Input Current VLOGIC = 0 V, 5 V, or VDD All 25°C ±0.6 µA –55°C to 125°C –1 1 CIN All 25°C 2 pF www.ti.com TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

7.7 AC Performance Characteristics

Typical at TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA = –55℃ to 125℃ UNIT CONDITION VDD VSS GPN MIN TYP MAX CAPACITANCE CS(OFF) VS = (VDD + VSS) / 2 V f = 1 MHz

5 V –5 V

24 V 0 V 3

CD(OFF) VS = (VDD + VSS) / 2 V f = 1 MHz

24 V 0 V 9

24 V 0 V 5

CS(ON) CD(ON) VS = (VDD + VSS) / 2 V f = 1 MHz

24 V 0 V 11

24 V 0 V 7

Bandwidth (BW) (Sine Wave Input) VBIAS = (VDD + VSS) / 2 (1) VS = 200 mVpp RL = 50 Ω, CL = 5 pF +5 V –5 V TMUX4051-Q1 280 MHz

24 V 0 V 430

+5 V –5 V TMUX4052-Q1 600

24 V 0 V 700

(Sine Wave Input) VBIAS = (VDD + VSS) / 2 (1) VS = 200 mVpp RL = 50 Ω, CL = 5 pF f = 1 MHz +5 V –5 V All –95 dB

24 V 0 V –95

(Sine Wave Input) VBIAS = (VDD + VSS) / 2 (1) VS = 200 mVpp RL = 50 Ω, CL = 5 pF f = 1 MHz +5 V –5 V All –90 dB

24 V 0 V –90

Charge Injection VS = (VDD + VSS) / 2 RS = 0 Ω, CL = 100 pF +5 V –5 V TMUX4051-Q1 pC

24 V 0 V 2

(1) Peak-to-Peak voltage symmetrical about (VDD + VSS) / 2. TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 www.ti.com

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7.8 Timing Characteristics

Over operating free-air temperature range, Typical at TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CONDITION VDD VSS TA Prop Delay Signal Input to Signal Output VS = VSS to VDD

5 V 0 V 25°C 4 20

10 V 0 V 25°C 4 20

24 V 0 V 25°C 3 20

5 V –5 V 25°C 4 20

12 V –12 V 25°C 3 20

tr , tf = 20 ns, CL = 50 pF, RL = 10 kΩ

5 V 0 V

25°C 105 ns –55°C to +125°C 190

10 V 0 V

25°C 100 –55°C to +125°C 190 25°C 110 –55°C to +125°C 230 25°C 100 –55°C to +125°C 190

12 V –12 V

25°C 100 –55°C to +125°C 190 tON (EN) Enable-to-Signal OUT Channel turning ON tr , tf = 20 ns, CL = 50 pF, RL = 10 kΩ 25°C 100 ns –55°C to +125°C 190 25°C 95 –55°C to +125°C 190 25°C 110 –55°C to +125°C 230 25°C 100 –55°C to +125°C 190 25°C 100 –55°C to +125°C 190 tOFF (EN) Enable-to-Signal OUT Channel turning OFF tr , tf = 20 ns, CL = 50 pF, RL = 10 kΩ 25°C 90 ns –55°C to +125°C 140 25°C 90 –55°C to +125°C 140 25°C 85 –55°C to +125°C 140 25°C 100 –55°C to +125°C 160 25°C 90 –55°C to +125°C 140 www.ti.com TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

7.8 Timing Characteristics (continued)

Over operating free-air temperature range, Typical at TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CONDITION VDD VSS TA tBBM CL = 15 pF, RL = 10 kΩ 25°C 60 ns –55°C to +125°C 1 25°C 45 –55°C to +125°C 1 25°C 45 –55°C to +125°C 1 25°C 55 –55°C to +125°C 1 25°C 75 –55°C to +125°C 1 TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 www.ti.com

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7.9 Typical Characteristics

at TA = 25°C, VDD = 5 V (unless otherwise noted) VDD = 5 V, VSS = -5 V Figure 7-1. On-Resistance vs Temperature V S or V D - Source or Drain Voltage (V) On Resistance (  ) 100 120 140 160 180 200 220 240 TA = 125 C TA = 85 C TA = 25 C TA = − 55 C VDD = 5 V Figure 7-2. On-Resistance vs Temperature VS or V D - Source or Drain Voltage (V) On Resistance ( ) 0 2 4 6 8 10 12 14 16 18 20 22 24 110 130 150 170 190 210 230 TA = 125 C TA = 85 C TA = 25 C TA = − 55 C VDD = 24 V Figure 7-3. On-Resistance vs Temperature Logic Voltage (V) Supply Current ( A) V DD = 24V V DD = 10V V DD = 15V V DD = 5V Figure 7-4. Supply Current vs Logic Voltage tr, t f - Signal Rise, Fall Time ( s) Settling Time (ns) -50 -25 100 125 150 175 200 225 250 Input 90% to Output 90% Input 80% to Output 80% Input 50% to Output 50% VDD = 5 V, Vsignal = 5 V RL = 200 kΩ, CL = 15 pF Figure 7-5. System Settling Time tr, t f - Signal Rise, Fall Time ( s) Settling Time (ns) 100 150 200 250 300 350 400 450 500 550 600 650 Input 90% to Output 90% Input 80% to Output 80% Input 50% to Output 50% VDD = 5 V, Vsignal = 5 V RL = 10 kΩ, CL = 15 pF Figure 7-6. System Settling Time www.ti.com TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

7.9 Typical Characteristics (continued)

at TA = 25°C, VDD = 5 V (unless otherwise noted) Frequency (Hz) Gain (dB) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 100k 1M 10M 100M 1G TMUX4051 TMUX4052 VDD = 12 V, VSS = -12 V Figure 7-7. Xtalk vs Frequency Frequency (Hz) Gain (dB) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 100k 1M 10M 100M 1G TMUX4051 TMUX4052 VDD = 12 V, VSS = -12 V Figure 7-8. Off-Isolation vs Frequency Frequency (Hz) Gain (dB) -14 -12 -10 100k 1M 10M 100M 1G TMUX4052 TMUX4051 VDD = 12 V, VSS = -12 V Figure 7-9. On Response vs Frequency TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 www.ti.com

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8 Parameter Measurement Information

8.1 On-Resistance

The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol R ON is used to denote on-resistance. The measurement setup used to measure R ON is shown in the following figure. Figure 8-1 shows how the R ON is computed with R ON = V / I SD, and the voltage (V) and current (I SD) are measured using this setup. V D VS ISD Sx Figure 8-1. On-Resistance Measurement Setup

8.2 Off-Leakage Current

There are two types of leakage currents associated with a switch during the off state: 1. Source off-leakage current. 2. Drain off-leakage current. Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is off. This current is denoted by the symbol IS(OFF). Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off. This current is denoted by the symbol ID(OFF). Figure 8-2 shows the setup used to measure both off-leakage currents. VDD VDD GND VS D VD A ID (OFF) VDD VDD GND VS D VD A Is (OFF) S6 S6 Figure 8-2. Off-Leakage Measurement Setup www.ti.com TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

8.3 On-Leakage Current

Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch is on. This current is denoted by the symbol IS(ON). Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is on. This current is denoted by the symbol ID(ON). Either the source pin or drain pin is left floating during the measurement. Figure 8-3 shows the circuit used for measuring the on-leakage current, denoted by IS(ON) or ID(ON). VDD VDD GND VS D VD ID (ON) VDD VDD GND VS D Vs A IS (ON) N.C. N.C.A Figure 8-3. On-Leakage Measurement Setup

8.4 Transition Time

Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal has risen or fallen past the 50% threshold. Figure 8-4 shows the setup used to measure transition time, denoted by the symbol tTRANSITION. 5 V VADDRESS 0 V 50% 50% tTRANSITION tTRANSITION 10% 90% Output tr < 20 ns tf < 20 ns RL CL VDD VSS VDD VSS 0.1 µF 0.1 µF GND D Output 0 V VADDRESS VS Figure 8-4. Transition-Time Measurement Setup TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 www.ti.com

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8.5 Break-Before-Make

Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is switching. The output first breaks from the on-state switch before making the connection with the next on-state switch. The time delay between the break and the make is known as break-before-make delay. Figure 8-5 shows the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM). VDD 0 V tBBM_1 90% Output 0 V tBBM = min ( tBBM_1, tBBM_2) tBBM_2 Input Select (VSEL) tr < 5ns tf < 5ns VDD OUTPUT S1-S6 D GND VSEL VDD 0.1 F RL CL EN Figure 8-5. Break-Before-Make Delay Measurement Setup 8.6 tON(EN) and tOFF(EN) Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen past the 50% threshold. The 10% measurement is utilized to provide the timing of the device, system level timing can then account for the time constant added from the load resistance and load capacitance. Figure 8-6 shows the setup used to measure transition time, denoted by the symbol tON(EN). Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen past the 50% threshold. The 90% measurement is utilized to provide the timing of the device, system level timing can then account for the time constant added from the load resistance and load capacitance. Figure 8-6 shows the setup used to measure transition time, denoted by the symbol tOFF(EN). Logic High 0 V VEN tON (EN) tOFF (EN) 90% 10% OUTPUT 0 V tr = 20nstf = 20ns VS OUTPUT D GND VEN VDD 0.1 F RL CL EN 50% 50% VSS 0.1 F Figure 8-6. Turn-On and Turn-Off Time Measurement Setup www.ti.com TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

8.7 Propagation Delay

Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal has risen or fallen past the 50% threshold. Figure 8-7 shows the setup used to measure propagation delay, denoted by the symbol tPD. RL CL VDD VSS VDD VSS 0.1 µF 0.1 µF GND D Output VS VDD VSS tPD 1 Output 0 V tProp Delay = max ( tPD 1, tPD 2) Input (VS) tPD 2 50% 50% 50% 50% Figure 8-7. Propagation Delay Measurement Setup

8.8 Charge Injection

Any mismatch in capacitance between the NMOS and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted by the symbol Q C. Figure 8-8 shows the setup used to measure charge injection from source (Sx) to drain (D). OUTPUT CL GND VOUT Output VS 0 V VDD QC = CL × VOUT VOUT VEN VDD VDD 0.1 F VS D VEN EN Figure 8-8. Charge-Injection Measurement Setup TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 www.ti.com

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Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

8.9 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the source pin (Sx) of an off-channel. Figure 8-9 shows the setup used to measure, and the equation to compute off isolation. GND NETWORK ANALYZER VOUT S D VSIG RL SX RL VS VDD 0.1 µF Figure 8-9. Off Isolation Measurement Setup O f f I s ol at i on = 20 × L og V OU T V S (1)

8.10 Crosstalk

Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied at the source pin (Sx) of an on-channel. Figure 8-10 shows the setup used to measure, and the equation used to compute crosstalk. NETWORK ANALYZER GND VSIG VOUT RL RL D SX RL VS VDD 0.1 µF Figure 8-10. Channel-to-Channel Crosstalk Measurement Setup C ℎ an n el − t o − C ℎ ann el C r os s t al k = 20 × L o g V OU T V S (2) www.ti.com TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

8.11 Bandwidth

Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure 8-11 shows the setup used to measure bandwidth. GND NETWORK ANALYZER VOUT S D VSIG RL VS VDD 0.1 µF SX RL Figure 8-11. Bandwidth Measurement Setup A tt en uat i o n = 20 × L og V 2 V 1 (3) TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 www.ti.com

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Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

9 Detailed Description

9.1 Overview

The TMUX4051-Q1 is an 8:1, single-ended (1-channel) mux and the TMUX4052-Q1 is a 4:1, differential (2- channel) multiplexer. Each channel is turned on or turned off based on the state of the address lines and enable pin.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Bidirectional Operation

The TMUX4051-Q1 and TMUX4052-Q1 devices conduct equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each signal path has very similar characteristics in both directions so they can be used as both multiplexers and demultiplexer to support analog signals.

9.3.2 Rail-to-Rail Operation

The valid signal path input and output voltage for the TMUX4051-Q1 and TMUX4052-Q1 ranges from V SS to VDD. 9.3.3 1.8 V Logic Compatible Inputs The TMUX4051-Q1 and TMUX4052-Q1 support 1.8-V logic compatible control for all logic control inputs. 1.8-V logic level inputs allows the multiplexers to interface with processors that have lower logic I/O rails and eliminates the need for an external voltage translator, which saves both space and BOM cost. For more information on 1.8-V logic implementation, refer to Simplifying Design with 1.8 V logic Muxes and Switches.

9.3.4 Device Functional Modes

When the EN pin of the TMUX405x-Q1 devices is pulled low, one of the switches is closed based on the state of the address or select pins. When the EN pin is pulled high, all the switches are in an open state regardless of the state of the address or select pins. Unused logic control pins must be tied to GND or V DD to be certain that the device does not consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs . Unused signal path inputs (Sx and Dx) should be connected to GND. www.ti.com TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

9.3.5 Truth Tables

Table 9-1 and Table 9-2 provides the truth tables for the TMUX4051-Q1 respectively. Table 9-1. TMUX4051-Q1 Truth Table EN A2 A1 A0 Selected Signal Path Connected To Drain (D) Pin 0 0 0 0 S0 0 0 0 1 S1 0 0 1 0 S2 0 0 1 1 S3 0 1 0 0 S4 0 1 0 1 S5 0 1 1 0 S6 0 1 1 1 S7

1 X(1) X(1) X(1) All inputs are unselected (HI-Z)

(1) X denotes do not care. Table 9-2. TMUX4052-Q1 Truth Table EN A1 A0 Selected Signal Path Connected To Drain (DA and DB) Pins 0 0 0 S0A to DA S0B to DB 0 0 1 S1A to DA S1B to DB 0 1 0 S2A to DA S2B to DB 0 1 1 S3A to DA S3B to DB

1 X(1) X(1) All inputs are unselected (HI-Z)

(1) X denotes do not care. TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 www.ti.com

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Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The TMUX405x-Q1 devices offer good system performance across a wide operating supply (5 V to 24 V). These devices include 1.8 V logic compatible control input pins that enable operation in systems with 1.8 V I/O rails. These features make the TMUX405x a family of general purpose multiplexers and switches that can reduce system complexity, board size, and overall system cost.

10.2 Typical Application

One useful application to take advantage of the TMUX405x-Q1 features is multiplexing various signals into an ADC that is integrated into an MCU. Utilizing an integrated ADC in an MCU allows a system to minimize cost with a potential tradeoff of system performance when compared to an external ADC. The multiplexer allows for multiple inputs or sensors to be monitored with a single ADC pin of the device, which is critical in systems with limited I/O. The TMUX4052-Q1 is suitable for a similar design example using differential signals, or as two 4:1 multiplexers. System Inputs and Sensors LDO #1 D Integrated 12-bit ADC A0 A1 A2 MCU LDO #2 LM20 Analog Temp. Sensor LM20 Analog Temp. Sensor GND VSS VDD VI/O

1.8 V Logic

Analog Temp. Sensor LDO #3 RAM FLASH Port I/O TIMERS EN VDD Figure 10-1. Multiplexing Signals to an Integrated ADC with TMUX4051 www.ti.com TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

10.3 Design Requirements

Table 10-1 lists the parameters that must be used for this design example. Table 10-1. Design Parameters PARAMETERS VALUES Supply (VDD) 12 V I/O signal range 0 V to VDD (rail-to-rail) Control logic thresholds 1.8 V compatible

10.4 Detailed Design Procedure

The TMUX4051-Q1 and TMUX4052-Q1 can operate without any external components except for the supply decoupling capacitors. The MCU can control the enable and address pins through GPIOs to toggle between various inputs of the multiplexer. The enable pin should be connected to ground if the functionality is not required in the system. All inputs being muxed to the ADC of the MCU must fall within the Recommended Operating Conditions, including signal range and continuous current. For this design with a supply of 12 V, the signal range can be 0 V to 12 V.

10.5 Application Curves

Frequency (Hz) Gain (dB) -14 -12 -10 100k 1M 10M 100M 1G TMUX4052 TMUX4051 TA = 25°C Figure 10-2. Bandwidth

10.6 Power Supply Recommendations

The TMUX4051-Q1 and TMUX4052-Q1 devices operate across a wide supply range of 5 V to 24 V. Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply pins to other components. Good power-supply decoupling is important to achieve optimum performance. For improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground and V SS to ground. Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems or systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 www.ti.com

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Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

10.7 Layout

10.7.1 Layout Guidelines

Route high-speed signals using minimal vias and corners, which reduces signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points, through-hole pins are not recommended at high frequencies. Figure 10-3 shows an example of a PCB layout with the TMUX4051-Q1 and TMUX4052-Q1 . Some key considerations are as follows:

• Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary.

10.7.2 Layout Example

D EN VDD TMUX4051-Q1 Via to GND plane C Wide (low inductance) trace for power VSS GND S0B S2B DB S3B S1B EN VDD S2A S1A DA S0A S3A TMUX4052-Q1 C Wide (low inductance) trace for power CTo VSS Figure 10-3. TMUX4051-Q1 and TMUX4052-Q1 Layout Example www.ti.com TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For releated documentation, see the following:

• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief
• Texas Instruments, QFN/SON PCB Attachment application report
• Texas Instruments, Quad Flatpack No-Lead Logic Packages application report

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TMUX4051-Q1, TMUX4052-Q1 SCDS463A – JUNE 2022 – REVISED MARCH 2023 www.ti.com

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Product Folder Links: TMUX4051-Q1 TMUX4052-Q1

www.ti.com 11-Aug-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTMUX4051DYYRQ1 ACTIVE SOT-23-THIN DYY 16 3000 TBD Call TI Call TI -55 to 125 Samples PTMUX4051PWRQ1 ACTIVE TSSOP PW 16 2500 TBD Call TI Call TI -55 to 125 Samples PTMUX4052DYYRQ1 ACTIVE SOT-23-THIN DYY 16 3000 TBD Call TI Call TI -55 to 125 Samples PTMUX4052PWRQ1 ACTIVE TSSOP PW 16 2000 TBD Call TI Call TI -55 to 125 Samples TMUX4051BQBRQ1 ACTIVE WQFN BQB 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4051Q Samples TMUX4051DYYRQ1 ACTIVE SOT-23-THIN DYY 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4051Q Samples TMUX4051PWRQ1 ACTIVE TSSOP PW 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4051Q Samples TMUX4052BQBRQ1 ACTIVE WQFN BQB 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4052Q Samples TMUX4052DYYRQ1 ACTIVE SOT-23-THIN DYY 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4052Q Samples TMUX4052PWRQ1 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4052Q Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

www.ti.com 11-Aug-2023 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMUX4051-Q1, TMUX4052-Q1 :

• Catalog : TMUX4051 , TMUX4052 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TMUX4051DYYRQ1 SOT-23- THIN TMUX4052DYYRQ1 SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMUX4051BQBRQ1 WQFN BQB 16 3000 210.0 185.0 35.0 TMUX4051DYYRQ1 SOT-23-THIN DYY 16 3000 336.6 336.6 31.8 TMUX4051PWRQ1 TSSOP PW 16 2500 356.0 356.0 35.0 TMUX4052BQBRQ1 WQFN BQB 16 3000 210.0 185.0 35.0 TMUX4052DYYRQ1 SOT-23-THIN DYY 16 3000 336.6 336.6 31.8 TMUX4052PWRQ1 TSSOP PW 16 2000 356.0 356.0 35.0 Pack Materials-Page 2

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