PTMUX1072DGSR | DigiCamel IC Datasheet

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ADVANCE□INFORMATION VCC NC2 NO1 OVP Logic Control GND TMUX1072 NO2 SEL1 SEL2 OE FLT NC1 COM1 COM2 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TMUX1072 SCDS382 –APRIL 2018 TMUX10722-Channel2:1AnalogMultiplexerwithOvervoltageDetectionandProtection

1 Features

1• Supply Range 2.3 V to 5.5 V

Powered Off Protection: I/O pins Hi-Z When VCC = 0 V
Overvoltage and Overtemperature detection
0-V to 20-V Overvoltage Protection (OVP) on Common Pins
Low RON of 6 Ω
BW of 1.2 GHz Typical
CON of 4.5 pF Typical
Low Power Disable Mode
1.8-V Compatible Logic Inputs
ESD Protection Exceeds JESD22 – 2000-V Human Body Model (HBM)
Small 2.00mm x 1.70mm QFN Package available

2 Applications

Data Aquisition (DAQ)
Field Instrumentation
Video Surveillance
HVAC Systems
Rear Camera

3 Description

The TMUX1072 is a high-speed, 2-channel, 2:1, analog switch with integrated overvoltage detection and powered off protection. The device is bidirectional and can be used as a 2:1 or 1:2 switch. The protection on the I/O pins of the TMUX1072 can tolerate up to 20 V with automatic shutoff circuitry to protect system components behind the switch. This protection is also used for power sequencing where some boards in the system maybe powered up before others are ready to receive signals. The device also detects overvoltage and overtemperature events and provides an open drain output signal through the FLT pin. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TMUX1072 UQFN (12) 2.00 mm × 1.70 mm VSSOP (10) 3.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic

12.2 Receiving Notification of Documentation Updates 18

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES April 2018 * initial release

ADVANCE□INFORMATION 1SEL1 2NO1 3GND 4NO2 5SEL2 6OE

7 COM2

8 NC2

9 VCC

10 NC1

11 COM1

5 Pin Configuration and Functions

SEL1 1 1 I Switch select 1 NO1 2 2 I/O Signal path NO1 GND 3 3 GND Ground NO2 4 4 I/O Signal path NO2 SEL2 5 5 I Switch select 2 OE 6 - I Output enable (Active low) COM2 7 6 I/O Common signal path 2 NC2 8 7 I/O Signal path NC2 VCC 9 8 PWR Supply Voltage NC1 10 9 I/O Signal path NC1 COM1 11 10 I/O Common signal path 1 FLT 12 - O Fault indicator output pin (Active low) - open drain

ADVANCE□INFORMATION TMUX1072 SCDS382 –APRIL 2018 www.ti.com Product Folder Links: TMUX1072 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. (3) All voltages are with respect to ground, unless otherwise specified.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT VCC Supply voltage(3) –0.5 6 V VI/O Input/Output DC voltage (COM1, COM2)(3) –0.5 20 V Input/Output DC voltage (NC1, NO1, NC2, NO2) (3) –0.5 6 V VI Digital input voltage (SEL1, SEL2, OE) –0.5 6 V VO Digital output voltage (FLT) –0.5 6 V IK Input-output port diode current (COM1, COM2,NC1, NO1, NC2, NO2) VIN < 0 –50 mA IIK Digital logic input clamp current (SEL1, SEL2, OE) (3) VI < 0 –50 mA ICC Continuous current through VCC 100 mA IGND Continuous current through GND –100 mA Tstg Storage temperature –65 150 °C TJ Operating Junction Temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

6.3 Recommended Operating Conditions

VCC Supply voltage 2.3 5.5 V VI/O Analog input/output COM1, COM2 0 18 V VI/O (NC1, NO1, NC2, NO2) 0 5.5 V II/O COM1, COM2 -50 50 mA II/O (NC1, NO1, NC2, NO2) -50 50 mA VI Digital input voltage SEL1, SEL2, OE 0 5.5 V VO Digital output voltage FLT 0 5.5 V II/O Analog input/output port continuous current (COM1, COM2, NC1, NO1, NC2, NO2) -50 50 mA IOL Digital output current 3 mA TA Operating free-air temperature –40 85 ºC TJ Junction temperature –40 125 ºC

ADVANCE□INFORMATION TMUX1072 www.ti.com SCDS382 –APRIL 2018 Product Folder Links: TMUX1072 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC (1) TMUX1072 UNITRUT (UQFN) DGS (VSSOP)

12 PINS 10 PINS

RθJA Junction-to-ambient thermal resistance 127 175 °C/W RθJC(top) Junction-to-case (top) thermal resistance 55.5 61.2 °C/W RθJB Junction-to-board thermal resistance 67.7 96.9 °C/W ψJT Junction-to-top characterization parameter 1.6 8.2 °C/W ψJB Junction-to-board characterization parameter 67.3 95.1 °C/W

6.5 Electrical Characteristics

TA = –40°C to +85°C , VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VCC Power supply voltage 2.3 5.5 V ICC Active supply current OE = 0 V SEL1, SEL2 = 0 V, 1.8 V or VCC 0 V < VI/O < 3.6 V 75 100 µA Supply current during OVP condition OE = 0 V SEL1, SEL2 = 0 V, 1.8 V or VCC VI/O > VPOS_THLD 65 100 µA ICC_PD Standby powered down supply current OE = 1.8 V or VCC SEL1 = 0 V, 1.8 V, or VCC SEL2 = 0 V, 1.8 V, or VCC 3 10 µA DC Characteristics RON ON-state resistance VI/O = 0 V to VCC ISINK = 8 mA Refer to ON-State Resistance Figure 6 15 Ω ΔRON ON-state resistance match between channels VI/O = 0 V to VCC ISINK = 8 mA Refer to ON-State Resistance Figure 0.07 0.3 Ω RON (FLAT) ON-state resistance flatness VI/O = 0 V to VCC ISINK = 8 mA Refer to ON-State Resistance Figure 2.5 6 Ω IOFF I/O pin OFF leakage current VCOM1/2 = 0 V or 3.6 V VCC = 2.3 V to 5.5 V VNC1/2 or VNO1/2 = 3.6 V or 0 V Refer to Off Leakage Figure 3.6 µA VCOM1/2 = 0 V or 20 V VCC = 2.3 V to 5.5 V VNC1/2 or VNO1/2 = 0 V Refer to Off Leakage Figure 165 µA ION ON leakage current VCOM1/2 = 0 V or 3.6 V VNC1/2 and VNO1/2 = high-Z Refer to On Leakage Figure 1.2 µA Digital Characteristics VIH Input logic high SEL1, SEL2, OE 1.4 V VIL Input logic low SEL1, SEL2, OE 0.5 V VOL Output logic low FLT IOL = 3 mA 0.4 V IIH Input high leakage current SEL1, SEL2, OE = 1.8 V, VCC -1 2 5 μA IIL Input low leakage current SEL1, SEL2, OE = 0 V -1 ±0.2 5 μA

ADVANCE□INFORMATION TMUX1072 SCDS382 –APRIL 2018 www.ti.com Product Folder Links: TMUX1072 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) TA = –40°C to +85°C , VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RPD Internal pull-down resistor on digital input pins SEL1, SEL2 6 MΩ OE 3 MΩ CI Digital input capacitance SEL1, SEL2 = 0 V, 1.8 V or VCC f = 1 MHz TBD pF Protection and Detection VOVP_TH OVP positive threshold 5.55 5.8 6.0 V VOVP_HYST OVP threshold hysteresis 40 100 300 mV TOTD_TH Overtemperature detection threshold 135 165 °C VCLAMP_V Maximum voltage to appear on NC1/2 and NO1/2 pins during OVP scenario VCOM1/2 = 0 to 18 V tRISE and tFALL(10% to 90 %) = 100 ns RL = Open Switch on or off OE = 0 V 0 9.6 V VCOM1/2 = 0 to 18 V tRISE and tFALL(10% to 90 %) = 100 ns RL = 50Ω Switch on or off OE = 0 V 0 9.0 V tEN_OVP OVP enable time RPU = 10 kΩ to VCC (FLT) CL = 35 pF Refer to OVP Timing Diagram Figure 0.6 3 μs tREC_OVP OVP recovery time RPU = 10 kΩ to VCC (FLT) CL = 35 pF Refer to OVP Timing Diagram Figure 1.5 5 μs

6.6 Dynamic Characteristics

TA = –40°C to +85°C , VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COFF COM1, COM2 off capacitance VCOM1/2 = 0 or 3.3 V, OE = VCC f = TBD MHz Switch OFF 1.2 TBD 6.2 pF NC1, NO1, NC2, NO2 off capacitance VCOM1/2 = 0 or 3.3 V, OE = VCC or OE = 0V with SEL1, SEL2 (switch not selected) f = TBD MHz Switch OFF or not selected 1.2 TBD 6.2 pF CON IO pins ON capacitance VCOM1/2 = 0 or 3.3 V, f = TBD MHz Switch ON 1.4 TBD 6.2 pF OISO Differential off isolation RL = 50 Ω CL = 5 pF f = 100 kHz Refer to Off Isolation Figure Switch OFF TBD dB RL = 50 Ω CL = 5 pF f = TBD MHz Refer to Off Isolation Figure Switch OFF TBD dB XTALK Channel to Channel crosstalk RL = 50 Ω CL = 5 pF f = 100 kHz Refer to Crosstalk Figure Switch ON TBD dB BW Bandwidth RL = 50 Ω; Refer to BW and Insertion Loss Figure Switch ON 1.2 GHz ILOSS Insertion loss RL = 50 Ω f = TBD MHz; Refer to BW and Insertion Loss Figure Switch ON TBD dB

6.7 Timing Requirements

TA = –40°C to +85°C , VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tswitch Switching time between channels (SEL1, SEL2 to output) VCOM1/2 = VCC Refer to Tswitch Timing Figure RL = 50 Ω, CL = 5 pF, VCC = 2.3 V to 5.5 V

0.9 TBD µs

ton Device turn on time (OE to output) VCOM1/2 = VCC Refer to Ton and Toff Figure 200 TBD µs toff Device turn off time (OE to output) VCOM1/2 = VCC Refer to Ton and Toff Figure 1 TBD µs tSK(P) Skew of opposite transitions of same output (between COM1 and COM2) VCOM1/2 = VCC Refer to Tsk Figure RL = 50 Ω, CL = 1 pF, VCC = 2.3 V to 5.5 V

9 TBD ps

tpd Propagation delay VCOM1/2 = VCC Refer to Tpd Figure RL = 50 Ω, CL = 5 pF, VCC = 2.3 V to 5.5 V

200 TBD ps

7 Parameter Measurement Information

Figure 1. ON-State Resistance (RON) Figure 2. Off Leakage Figure 3. On Leakage (2) CL includes probe and jig capacitance. Figure 4. tSWITCH Timing

(2) CL includes probe and jig capacitance. Figure 11. tSK

ADVANCE□INFORMATION OVP Control Logic VCC SEL2 OE FLT Switches SEL1 3 M 6 M 6 M VOVP VCOM2 VCOM1 VNC1 VNC2 VNO1 VNO2 TMUX1072 SCDS382 –APRIL 2018 www.ti.com Product Folder Links: TMUX1072 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TMUX1072 is a highspeed, 2-channel 2:1 analog switch with overvoltage protection. The device is bidirectional and can be used as a dual 2:1 or 1:2 switch but OVP only applies to the COM pins. The device also contains a fault detection pin which can signal to the system of either an overvoltage or overtemperature event. The device maintains excellent signal integrity through the optimization of both RON and BW while protecting the system with 0 V to 20 V OVP protection. The OVP implementation is designed to protect sensitive system components behind the switch that cannot survive a fault conditions.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Powered-off Protection

8.3.2 Overvoltage Detection

COM pin returns below the VOVP_TH.

8.3.3 Overtemperature Detection

output releases the FLT pin when the junction temperature returns below the TOTD_TH.

8.3.4 Overvoltage Protection

could pass through the device and damage components behind the device. Figure 12. Existing Solution Being Damaged by a Short, 20 V

Figure 13. Protecting During a 20-V Short Figure 14 is a waveform showing the voltage on the pins during an overvoltage scenario. Figure 14. Overvoltage Protection Waveform, 20 V

8.4 Device Functional Modes

8.4.1 Pin Functions

Table 1. Function Table

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

to cross switch single ended signals.

9.2 Typical Application

selected by default. The pull-down on OE enables the switch when power is applied. Figure 15. Typical TMUX1072 Application

9.2.1 Design Requirements

selected by default. The internal pull-down resistor on OE enables the switch when power is applied to VCC.

9.2.2 Detailed Design Procedure

device. TI does recommend a 100-nF bypass capacitor placed close to TMUX1072 VCC pin.

10 Power Supply Recommendations

Power to the device is supplied through the VCC pin. TI recommends placing a 100-nF bypass capacitor as close to the supply pin VCC as possible to help smooth out lower frequency noise to provide better load regulation across the frequency spectrum.

11 Layout

11.1 Layout Guidelines

Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the signal traces. 2. The high-speed traces should always be of equal length and must be no more than 4 inches; otherwise, the eye diagram performance may be degraded. 3. Route the high-speed signals using a minimum of vias and corners which will reduce signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the transmission line of the signal and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points on twisted pair lines; through-hole pins are not recommended. 4. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal traces by minimizing impedance discontinuities. 5. Do not route signal traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting holes, magnetic devices, or IC’s that use or duplicate clock signals. 6. Avoid stubs on the high-speed signals because they cause signal reflections. 7. Route all high-speed signal traces over continuous planes (VCC or GND), with no interruptions. 8. Avoid crossing over anti-etch, commonly found with plane splits. 9. For high frequency systems, a printed circuit board with at least four layers is recommended: two signal layers separated by a ground layer and a power layer. The majority of signal traces should run on a single layer, preferably Signal 1. Immediately next to this layer should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies. For more information on layout guidelines, see High Speed Layout Guidelines (SCAA082)

8 Bypass Capacitor

5 SEL2

11.2 Layout Example

Figure 16. Layout Example

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

High-Speed Layout Guidelines Application Report
High-Speed Interface Layout Guidelines

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 6-Apr-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTMUX1072DGSR ACTIVE VSSOP DGS 10 2500 TBD Call TI Call TI -40 to 125 TMUX1072DGSR PREVIEW VSSOP DGS 10 2500 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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Product Information

PTMUX1072DGSR specifications and overview.

Summary

2-Channel 2:1 Analog Multiplexer with Overvoltage Detection and Protection

Description

2-Channel 2:1 Analog Multiplexer with Overvoltage Detection and Protection

Source title PTMUX1072DGSR Datasheet(PDF) - Texas Instruments

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