PTMP6131LPGMQ1

TMP61-Q1_V01 TI1 | Alldatasheet

Document overview

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Technical content

VTemp = VBias X RTMP61 RBias + RTMP61 VTemp = IBias X RTMP61 VBias RBias RTMP61 VTEMP IBias VTEMP RTMP61 Temperature (qC) Resistance (k:) -40 -20 0 20 40 60 80 100 120 140 160 d001 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMP61-Q1 SNIS210B –APRIL 2019–REVISED SEPTEMBER 2019 TMP61-Q1AutomotiveGrade,10kΩLinearThermistorWithSmall0402andGrade0 PackageOptions

1 Features

1• AEC-Q100 qualified for automotive applications

• Temperature options: – TMP61QDEC Grade 1: –40°C to +125°C, TA – TMP61QLPG Grade 1: –40°C to +125°C, TA – TMP61ELPG Grade 0: –40°C to +150°C, TA
• Silicon-based thermistor with a Positive Temperature Coefficient (PTC)
• Linear resistance change across with temperature compared to non-linear thermistors – Simplifies resistance-to-temperature conversion methods – Reduces look up table memory requirements – Eliminates the need for linearization circuitry or multipoint calibration – Decreases the accuracy spread across a wide temperature range
• 10-kΩ nominal resistance at 25°C (R25) – ±1% maximum (0°C to 70°C)
• Consistent sensitivity across temperature – 6400 ppm/°C TCR (25°C) – 0.2% typical TCR tolerance across temperature (–40°C to 125°C)
• Fast thermal response time: – 0.6 second for DEC package
• Long lifetime and robust performance – Ultra low power consumption compared to traditional NTCs that lower errors due to self heating – Built-in fail-safe in case of short-circuit failures – <1% maximum drift after high temperature and high humidity stress tests
• Available package options: – X1SON (DEC/0402 footprint) – TO-92S (LPG)

2 Applications

• HEV/EV – On-board (OBC) and wireless chargers – DC/DC converters – Battery Management Systems
• Automotive infotainment & cluster – Automotive head unit – Automotive external amplifier – Automotive cluster display
• Automotive display module
• Automotive lighting – Headlights – Interior lights

3 Description

The TMP61-Q1 small silicon linear thermistors are designed for temperature measurement, protection, compensation, and control systems. Compared to traditional NTC thermistors, the TMP61-Q1 device offers enhanced linearity and consistent sensitivity across the full temperature range. The TMP61-Q1 offers robust performance due to device immunity to environmental variation and built-in fail-safe behaviors at high temperatures. This device is currently available in a 2-pin, surface-mount, 0402 footprint-compatible X1SON package and a 2-pin, through-hole, mini-sized transistor-outline TO-92S package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TMP61-Q1 X1SON (2) 0.60 mm × 1.00 mm TO-92S (2) 4.00 mm × 3.15 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Implementation Circuits Typical Resistances vs Ambient Temperature

SNIS210B –APRIL 2019–REVISED SEPTEMBER 2019 www.ti.com Product Folder Links: TMP61-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Table of Contents

12.2 Receiving Notification of Documentation Updates 21

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (June 2019) to Revision B Page Changes from Original (April 2019) to Revision A Page

www.ti.com SNIS210B –APRIL 2019–REVISED SEPTEMBER 2019 Product Folder Links: TMP61-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

5 Device Comparison Table

NUMBER RATING R25 TYP R25 %TOL PACKAGE TA TMP61QDEC Automotive Grade 1 10k 1% X1SON / DEC (0402) –40°C to 125°C TMP61QLPG Automotive Grade 1 TO92S / LPG –40°C to 125°C TMP61ELPG Automotive Grade 0 TO92S / LPG –40°C to 150°C

6 Pin Configuration and Functions

Top View (Angled) 2-Pin TO-92S Top View (Angled) Pin Functions PIN TYPE DESCRIPTION NAME X1SON (DEC) TO-92S (LPG) – 1 1 — Thermistor (–) and (+) terminals. For proper operation, ensure a positive bias where the + terminal is at a higher voltage potential than the – terminal.+ 2 2

SNIS210B –APRIL 2019–REVISED SEPTEMBER 2019 www.ti.com Product Folder Links: TMP61-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Voltage across the device 6 V Junction temperature (TJ) -40 150 °C Current through the device 450 µA Storage temperature (Tstg) -65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) HBM classification level 2 ±2000 V Charged-device model (CDM), per AEC Q100-011 CDM classification level C5 ±1000 V

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VSns Voltage Across Pins 2 (+) and 1 (–) 0 5.5 V ISns Current passing through the device 0 400 µA TA Operating free-air temperature (specified performance) (X1SON/DEC Package) –40 125 °C TA Operating free-air temperature (specified performance) (TO-92S/LPG Package) –40 150 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) For information on self-heating and thermal response time see Layout Guidelines section. (3) The junction to ambient thermal resistance (RθJA ) under natural convection is obtained in a simulation on a JEDEC-standard, High-K board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are included in the PCB, per JESD 51-5. (4) Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.

7.4 Thermal Information

THERMAL METRIC(1)(2) TMP61-Q1 UNITDEC (X1SON) LPG (TO-92)

2 PINS 2 PINS

RθJA Junction-to-ambient thermal resistance(3)(4) 443.4 215 °C/W RθJC(top) Junction-to-case (top) thermal resistance 195.7 99.9 °C/W RθJB Junction-to-board thermal resistance 254.6 191.7 °C/W ΨJT Junction-to-top characterization parameter 19.9 35.1 °C/W ΨJB Junction-to-board characterization parameter 254.5 191.7 °C/W

www.ti.com SNIS210B –APRIL 2019–REVISED SEPTEMBER 2019 Product Folder Links: TMP61-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Limits defined based on 4th order equation

7.5 Electrical Characteristics

TA = -40°C to 125°C (TMP61Q), TA = -40°C to 150°C (TMP61E), ISns = 200 μA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R25 Thermistor Resistance at 25°C(1) TA = 25°C 9.9 10 10.1 kΩ RTOL Resistance Tolerance(1) TA = 25°C –1 +1 %TA = 0°C to 70°C –1 +1 TCR-35 Temperature Coefficient of Resistance ppm/°CTCR25 T1 = 20°C, T2 = 30°C +6400 TCR85 T1 = 80°C, T2 = 90°C +5910 TCR-35 % Temperature Coefficient of Resistance Tolerance TCR85 % T1 = 80°C, T2 = 90°C ±0.3 ΔR Sensor Long Term Drift (Reliability) 96 hours continuous operation RH=85%, TA = 130°C, VBias = 5.5V 0.1 0.8 Sensor Long Term Drift (Reliability) 600 hours continuous operation TA = 150°C, VBias = 5.5V, DEC Package 0.1 1 Sensor Long Term Drift (Reliability) 1000 hours continuous operation TA = 150°C, VBias = 5.5V, LPG Package 0.1 1.1 % tRES (stirred liquid) Thermal response to 63% (DEC Package) T1=25°C in Still Air to T2=125°C in Stirred Liquid 0.6 s tRES (stirred liquid) Thermal response to 63% (LPG Package) T1=25°C in Still Air to T2=125°C in Stirred Liquid 2.9 s tRES (still air) Thermal response to 63% (DEC Package) T1=25°C to T2=70°C in Still Air 3.2 s tRES (still air) Thermal response to 63% (LPG Package) T1=25°C to T2=70°C in Still Air 20 s

7.6 Typical Characteristics

Figure 1. Resistance vs. Ambient Temperature Using Figure 2. Resistance vs. Ambient Temperature Using Figure 3. TCR as a Function of Sense Currents ISns Figure 4. TCR as a Function of Sense Voltages, VSns Figure 5. Supply Dependence R vs. IBias Figure 6. Supply Dependence R vs. VBias

8 Detailed Description

8.1 Overview

in a uniform and consistent temperature coefficient resistance (TCR) across a wide operating temperature range.

8.2 Functional Block Diagram

Figure 12. Typical Implementation Circuits

8.3 Feature Description

Figure 4. To fabricate the TMP61-Q1, the engineer can use a special silicon process where the device key negative terminal (which is tied to the substrate internally) should be connected to the lowest potential. Equation 1 can help the user approximate the TCR. error across temperature using a direct ideal bias current or an ideal voltage bias in a divider circuit.

• ISns: Current flowing through the TMP61-Q1.
• VSns: Voltage across the two TMP61-Q1 terminals.
• IBias: Current supplied by the biasing circuit.
• VBias: Voltage supplied by the biasing circuit.
• VTemp: Output voltage that corresponds to the measured temperature. Note that this is different from VSns. In a case of a voltage divider circuit with the TMP61-Q1 in the high side, VTemp is taken across RBias.

Table 1. TMP61-Q1 Transfer Table Using an Ideal IBias of 200 µA [DEC Package]

Table 2. TMP61-Q1 Transfer Table Using an Ideal IBias of 200 µA [LPG Package]

Table 3. TMP61-Q1 Transfer Table Using a Voltage Divider With an Ideal VBias of 2.5 V and RBias of 10 kΩ

Table 4. TMP61-Q1 Transfer Table Using a Voltage Divider With an Ideal VBias of 2.5 V and RBias of 10 kΩ

8.4 Device Functional Modes

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.2 Typical Application

9.2.1 Thermistor Biasing Circuits

Figure 13. Biasing Circuit Implementations With Linear Thermistor (Left) vs. Non-Linear Thermistor

9.2.1.1 Design Requirements

resistor can be biased directly using a precision current source (yielding the highest accuracy and voltage gain).

input for an active feedback control circuit.

9.2.1.2 Detailed Design Procedure

scale range, and ADC resolution is given in Equation 3. Figure 14. TMP61-Q1 Voltage Divider With an ADC

• FSR is the full-scale range of the ADC, which is the voltage at REF to GND (VREF)
• n is the resolution of the ADC (3) Equation 4 shows whenever VREF = VBIAS, VBIAS cancels out. (4)

Figure 17. TMP61-Q1 vs. NTC With Linearization Resistor (RP) Voltage Divider Circuits Figure 18. NTC With and Without a Linearization Resistor vs. TMP61-Q1 Temperature Voltages

9.2.1.2.1 Thermal Compensation

• R(T0) is the resistance
• the temperature coefficient, α, is specified (25°C)
• the change in temperature, ΔT, is the temperature of interest, T, minus T0 (25°C) (5) This circuit is shown in Figure 19.

Figure 19. TMP61-Q1 Thermal Compensation Circuit

9.2.1.2.2 Thermal Protection With Comparator

The engineer can use the TMP61-Q1, a voltage reference, and a comparator to program the thermal protection. comparator with built-in hysteresis or feedback resistors may be used. Figure 20. Temperature Switch Using TMP61-Q1 Voltage Divider and a Comparator

9.2.1.2.3 Thermal Foldback

One application that uses the output voltage of the TMP61-Q1 in an active control circuit is thermal foldback.

divider with RTMP61 and the input to the op amp to prevent loading and variations in VTEMP. Figure 21. Thermal Foldback Using TMP61-Q1 Voltage Divider and a Rail-to-Rail Op Amp dependent on the feedback network, RFB and R1, which varies the gain of the op amp, G, given by Equation 8.

Figure 22. Thermal Foldback Voltage Output Curve

9.2.1.3 Application Curve

Figure 23. VTEMP is shown with either VBIAS at 2 V in a resistor divider circuit (RBIAS = 10 kΩ ±1%) or IBIAS at 200 Figure 23. TMP61-Q1 Voltage Output and Temperature Error Based on the Bias Method

10 Power Supply Recommendations

through the device is 400 µA (ISns).

11 Layout

11.1 Layout Guidelines

11.2 Layout Examples

Figure 24. Recommended Layout: DEC Package

www.ti.com SNIS210B –APRIL 2019–REVISED SEPTEMBER 2019 Product Folder Links: TMP61-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following: MSL Ratings and Reflow Profiles (SPRABY1)

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 27-Sep-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTMP6131DECTQ1 ACTIVE X1SON DEC 2 250 TBD Call TI Call TI -40 to 125 PTMP6131ELPGMQ1 ACTIVE TO-92 LPG 2 3000 TBD Call TI Call TI -40 to 150 PTMP6131LPGMQ1 ACTIVE TO-92 LPG 2 3000 TBD Call TI Call TI -40 to 125 TMP6131ELPGMQ1 ACTIVE TO-92 LPG 2 3000 Green (RoHS & no Sb/Br) CU SN N / A for Pkg Type -40 to 150 TMP61 TMP6131QDECRQ1 ACTIVE X1SON DEC 2 10000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 EL TMP6131QDECTQ1 ACTIVE X1SON DEC 2 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 EL TMP6131QLPGMQ1 ACTIVE TO-92 LPG 2 3000 Green (RoHS & no Sb/Br) CU SN N / A for Pkg Type -40 to 125 TMP61 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 27-Sep-2019 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMP61-Q1 :

• Catalog: TMP61 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 24-Sep-2019 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMP6131QDECRQ1 X1SON DEC 2 10000 205.0 200.0 33.0 TMP6131QDECTQ1 X1SON DEC 2 250 205.0 200.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Sep-2019 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 0.50 0.41 0.05 0.00 0.65

0.1 C A B

2X 0.55 0.45 2X 0.3 0.2 A 1.05 0.95 B 0.65 0.55 4224506/A 08/2018 X1SON - 0.5 mm max heightDEC0002A PLASTIC SMALL OUTLINE - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.03 C 1 2 X0.125)(45 PIN 1 ID NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M 2. This drawing is subject to change without notice. SCALE 11.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND0.07 MAX ALL AROUND (R0.05) TYP (0.65) 2X (0.5) 2X (0.25) 4224506/A 08/2018 X1SON - 0.5 mm max heightDEC0002A PLASTIC SMALL OUTLINE - NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:60X NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK DETAILS METAL EDGE SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP (0.7) 2X (0.5) 2X (0.3) (0.05) 4224506/A 08/2018 X1SON - 0.5 mm max heightDEC0002A PLASTIC SMALL OUTLINE - NO LEAD NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:60X SYMM 1 2 SYMM PCB PAD METAL UNDER SOLDER PASTE

www.ti.com PACKAGE OUTLINE 4.1 3.9 15.5 15.1 3X 0.48 0.33 2X 1.27 0.05 3.25 3.05 3X 0.51 0.33 3X 0.51 0.40 2X ( )45° 0.86 0.66 1.62 1.42 2.64 2.44 2.68 2.28 5.05 MAX 6X 0.076 MAX 2.3 2.0

2 MAX

(0.55) 4221971/A 03/2015 TO-92 - 5.05 mm max heightLPG0002A TO-92 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 1 2 1 2 SCALE 1.300

www.ti.com EXAMPLE BOARD LAYOUT TYP ALL AROUND 0.05 MAX (1.07) (1.7) (1.27) (2.54) (1.7) 3X ( ) VIA0.75 4221971/A 03/2015 TO-92 - 5.05 mm max heightLPG0002A TO-92 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE:20X METAL TYP TYP OPENING SOLDER MASK 1 2

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