PTMA403033P1AZT

PTMA403033 TI | Alldatasheet

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47 µF (optional) VI− RTRIM(down) (optional) RTRIM(up) (optional) CO 47 µF (optional) VO+ VO− UDG−06003 PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 10-W, 36-V to 75-V INPUT, 1500-V ISOLATION, DC/DC CONVERTERS Intermediate Bus Architectures Input Voltage: V to V Telecom, High-End Computing Platforms 10-W Total Output Power Power Over Ethernet Voltages: 3.3 and V Multi-Rail Power Systems Output Voltage Trim 10% Up To 87% Efficiency Overcurrent Protection Input Undervoltage Lockout Output Overvoltage Protection Positive or Negative Logic Enable Control Option Synchronization Option Space-Saving Footprint (1.1 X 1.0 inch) Industry Standard Pinout Surface Mount Package 1500-Vdc Isolation Agency Approvals: UL/cUL 60950, EN 60950 The PTMA40XX is a series of 10-W rated isolated dc/dc converters, designed to operate from a standard -48-V telecom central office supply. Housed in an industry standard 1.1 in. 1.0 in. package, this series of isolated modules is set to one of the common intermediate bus voltages of 3.3 or The PTMA40XX series includes many modules. Operational (UVLO) and a dual-logic output enable control or sychronization option. Overcurrent protection ensures survival against load faults. Typical environments, power over ethernet, and particularly complex digital systems requiring multiple power supply rails. TYPICAL APPLICATION Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ABSOLUTE MAXIMUM RATINGS PACKAGE SPECIFICATIONS PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI website at www.ti.com PART NUMBERING SCHEME Input Output Output Enable Electrical Pin Style Shipping Voltage Current Voltage Options Package PTMA 050 P A D T V A 033 3.3 V A None None D Through-hole, Pb-free Blank Tray A 050 5.0 V N Negative V O Adjust S SMD, SnPb solder ball T Tape and Reel A 120 12.0 V P Positive V O Adjust Z SMD, SnAgCu solder Syncronization ball UNIT Continuous V V I Input Voltage Surge, s max 100 V (1) T A Operating temperature range Over V I range C to C Surface temperature of module or pins T WAVE Wave solder temperature AD suffix 260 C (2) (20 seconds) AS suffix 235 C (2) Surface temperature of module or pins T REFLOW Solder reflow temperature (20 seconds) AZ suffix 260 C (2) T STG Storage temperature C to 125 C P O Output Power W (1) The converter's internal protection circuitry may cause the output to turn off when the applied input voltage is greater than (2) During solder reflow of SMD package version, do not elevate the module PCB, pins, or internal component temperatures beyond this peak temperature. UNITS Weight 6.5 grams Flammability Meets UL94V-O Horizontal T/H (Suffix AD) G (1) Per Mil-STD-883D, Method 2002.3, ms, Mechanical shock Horizontal SMD (Suffix AS G (1) Sine, mounted AZ) Horizontal T/H (Suffix AD) 500 G (1) Mil-STD-883D, Method 2007.2, 20-2000 Hz, Mechanical vibration Horizontal SMD (Suffix AS 500 G (1) PCB mounted AZ) Reliability Telcordia SR-332 50% stress, T A ground benign MTBF 7.3 Hr (1) Qualification limit. Submit Documentation Feedback

www.ti.com PTMA403033 ELECTRICAL CHARACTERISTICS PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 T A V I V O 3.3 C I µ C O µ and I O I O max (Unless otherwise stated) PTMA403033 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX P O Output power Over V I range W I O Output current Over V I range 0.1 (1) (2) A I LIM Current Limit Threshold Shutdown, followed by autorecovery 4.25 A V I Input voltage range Over I O range V Set-point voltage tolerance (3) O Temperature variation -40 C T A C O Line regulation Over V I range mV V O Load regulation Over I O range mV Total output voltage variation Includes set-point, line, load, C T A C (3) O Trim adjust range Over V I range 3.0 3.6 V η Efficiency P O P O max 82% V O Ripple (peak-to-peak) 20-MHz bandwidth mV pp 0.1 µ s load step, Recovery time 750 µ s Transient response 50% to 100% V O over/undershoot 150 mV I O max Referenced to V I Input high voltage IH 4.5 Open (4) V Output enable input (pin Input low voltage IL 0.2 0.8 Input low current IL mA Standby input current Pin open mA UVLO Undervoltage lockout V OVP Output Overvoltage Protection 3.7 5.4 V ƒ S Switching frequency Over V I and I O ranges (non-Sync option) 250 300 350 kHz Free-running 180 215 (5) 250 Sync switching frequency kHz Synchronization range 250 (5) 350 (5) SYNC high-level input voltage 3.5 V low-level input voltage 0.3 0.5 V clock duty cycle C I External input capacitance µ F C O External output capacitance (6) 1000 µ F V ISO Isolation voltage 1,500 Vdc C ISO Isolation capacitance Primary-Secondary 1,100 pF R ISO Isolation resistance M Ω (1) The converter requires a minimum load current for proper operation. However, the converter is not damaged when operated under a no-load condition. (2) See temperature derating curves for safe operating area (SOA), to determine output current derating at elevated ambient temperatures. (3) The set-point voltage tolerance is affected by the tolerance and stability of R TRIM The stated limit is unconditionally met if R TRIM has a tolerance of 1%, with 100 ppm/ C temperature stability. (4) The Enable input (pin has an internal pullup resistor. Do not place an external pullup resistor on this input pin. If the enable feature is not used, for a positive enable device this input should be left open circuit and a negative enable device should be permanently connected to V I (pin 2). A discrete MOSFET or bipolar transistor is recommended for the enable control. The open-circuit voltage is typically less than See the Application Information for a more detailed description. (5) A device with the synchronization option has a reduced switching frequency of 215 kHz typical. The synchronization frequency can only be adjusted to a higher frequency, up to 350 kHz maximum. (6) An output capacitor is not required for proper operation. However, additional capacitance at the load improves the transient response. Submit Documentation Feedback

www.ti.com PTMA402050 ELECTRICAL CHARACTERISTICS PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 T A V I V O C I µ C O µ and I O I O max (Unless otherwise stated) PTMA402050 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX P O Output power Over V I range W I O Output current Over V I range 0.1 (1) (2) A I LIM Current Limit Threshold Shutdown, followed by autorecovery A V I Input voltage range Over I O range V Set-point voltage tolerance (3) O Temperature variation -40 C T A C O Line regulation Over V I range mV V O Load regulation Over I O range mV Total output voltage variation Includes set-point, line, load, C T A C (3) O Trim adjust range Over V I range 4.5 5.5 V η Efficiency P O P O max 85% V O Ripple (peak-to-peak) 20-MHz bandwidth mV pp 0.1 µ s load step, Recovery time 250 µ s Transient response 50% to 100% V O over/undershoot 150 mV I O max Referenced to V I Input high voltage IH 4.5 Open (4) V Output enable input (pin Input low voltage IL 0.2 0.8 Input low current IL mA Standby input current Pin open mA UVLO Undervoltage lockout V OVP Output Overvoltage Protection 5.6 7.9 V ƒ S Switching frequency Over V I range 250 300 350 kHz Free-running 180 215 (5) 250 Sync switching frequency kHz Synchronization range 250 (5) 350 (5) SYNC high-level input voltage 3.5 V low-level input voltage 0.3 0.5 V clock duty cycle C I External input capacitance µ F C O External output capacitance (6) 1000 µ F V ISO Isolation voltage 1,500 Vdc C ISO Isolation capacitance Primary-Secondary 1,100 pF R ISO Isolation resistance M Ω (1) The converter requires a minimum load current for proper operation. However, the converter is not damaged when operated under a no-load condition. (2) See temperature derating curves for safe operating area (SOA), to determine output current derating at elevated ambient temperatures. (3) The set-point voltage tolerance is affected by the tolerance and stability of R TRIM The stated limit is unconditionally met if R TRIM has a tolerance of 1%, with 100 ppm/ C temperature stability. (4) The Enable input (pin has an internal pullup resistor. Do not place an external pullup resistor on this input pin. If the enable feature is not used, for a positive enable device this input should be left open circuit and a negative enable device should be permanently connected to V I (pin 2). A discrete MOSFET or bipolar transistor is recommended for the enable control. The open-circuit voltage is typically less than See the Application Information for a more detailed description. (5) A device with the synchronization option has a reduced switching frequency of 215 kHz typical. The synchronization frequency can only be adjusted to a higher frequency, up to 350 kHz maximum. (6) An output capacitor is not required for proper operation. However, additional capacitance at the load will improve the transient response. Submit Documentation Feedback

www.ti.com PTMA401120 ELECTRICAL CHARACTERISTICS PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 T A V I V O C I µ C O µ and I O I O max (Unless otherwise stated) PTMA401120 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX P O Output power Over V I range W I O Output current Over V I range 0.1 (1) (2) A I LIM Current Limit Threshold Shutdown, followed by autorecovery 1.5 A V I Input voltage range Over I O range V Set-point voltage tolerance (3) O Temperature variation -40 C T A C O Line regulation Over V I range mV V O Load regulation Over I O range mV Total output voltage variation Includes set-point, line, load, C T A C (3) O Trim adjust range Over V I range 10.8 13.2 V η Efficiency P O P O max 87% V O Ripple (peak-to-peak) 20-MHz bandwidth mV pp 0.1 µ s load step, Recovery time 400 µ s Transient Response 50% to 100% V O over/undershoot 250 mV I O max Referenced to V I Input high voltage IH 4.5 Open (4) V Output enable input (pin Input low voltage IL 0.2 0.8 Input low current IL mA Standby input current Pin open mA UVLO Undervoltage lockout V OVP Output Overvoltage Protection 13.5 17.5 V ƒ S Switching frequency Over V I range 250 300 350 kHz Free-running 180 215 (5) 250 Sync switching frequency kHz Synchronization range 250 (5) 350 (5) SYNC high-level input voltage 3.5 V low-level input voltage 0.3 0.5 V clock duty cycle C I External input capacitance µ F C O External output capacitance (6) 220 µ F V ISO Isolation voltage 1,500 Vdc C ISO Isolation capacitance Primary-Secondary 1,100 pF R ISO Isolation resistance M Ω (1) The converter requires a minimum load current for proper operation. The converter is not damaged when operated under a no-load condition. (2) See temperature derating curves for safe operating area (SOA), to determine output current derating at elevated ambient temperatures. (3) The set-point voltage tolerance is affected by the tolerance and stability of R TRIM The stated limit is unconditionally met if R TRIM has a tolerance of 1%, with 100 ppm/ C temperature stability. (4) The Enable input (pin has an internal pullup resistor. Do not place an external pullup resistor on this input pin. If the enable feature is not used, for a positive enable device this input should be left open circuit and a negative enable device should be permanently connected to V I (pin 2). A discrete MOSFET or bipolar transistor is recommended for the enable control. The open-circuit voltage is typically less than See the Application Information for a more detailed description. (5) A device with the synchronization option has a reduced switching frequency of 215 kHz typical. The synchronization frequency can only be adjusted to a higher frequency, up to 350 kHz maximum. (6) An output capacitor is not required for proper operation. However, additional capacitance at the load will improve the transient response. Submit Documentation Feedback

www.ti.com (Top View) PTMA40XXXX PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 TERMINAL FUNCTIONS TERMINAL NO. The Enable input is an open-base logic input that is referenced to V I Two ON/OFF enable options are available, positve logic and negative logic. Positive logic devices are enabled by applying a logic high voltage (Open) and are disabled by applying a logic low voltage I Negative logic devices are enabled by applying a logic low voltage I and are disabled by applying a logic high voltage (Open). See the Application Information section for Enable/Sync (1) more detailed information. This pin also has the option of a synchronization input. A module that has the synchronization option does not have ON/OFF enable control. A 5-V logic signal greater than the free-running frequency but 350 kHz is required for synchronization control. See the Application Information section for more detailed information. The negative input supply for the module, and the 0-V reference for the Enable/Sync inputs. When powering the V I (1) module from a positive source, this input is connected to the input source return. The positive input for the module with respect to V I When powering the module from a negative input voltage, V I (1) this input is connected to the input source ground. V O This is the positive power output with respect to V O It is dc isolated from the input power pins. This pin allows the output voltage set point of the module to be increased or decreased up to Connecting a resistor between this terminal and V O decreases the output voltage set point. Connecting a resistor between this terminal and V O increases the output voltage set point. A 0.05-W rated resistor may be used, with tolerance Trim and temperature stability of and 100 ppm/ respectively. If left open circuit, the converter output voltage defaults to its nominal value. The specification table gives the standard resistor values for the most common output voltages. This is the output power return for the V O bus. This terminal should be connected to the common of the load V O circuit. (1) These functions indicate signals electrically common with the input. Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS PTMA403033 Characteristic Data O 3.3 (1) (2) 0.5 2.5 2.0 1.5 1.0 3.0 IO − Output Current − A VIN = 48 V VIN = 36 V VIN = 60 V VIN = 75 V PD − Power Dissipation −W 0.5 1.0 2.0 2.5 3.0 1.5 IO − Output Current − A VIN = 48 V VIN = 36 V VIN = 60 V VIN = 75 V η Efficiency − % IO − Output Current − A VO − Output Voltage Ripple − VPP mV VIN = 48 V VIN = 36 V VIN = 60 V VIN = 75 V IO − Output Current − A

200 LFM

TA − Ambient Temperature − ° C Natural Convection PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 EFFICIENCY POWER DISSIPATION vs OUTPUT CURRENT vs OUTPUT CURRENT Figure Figure OUTPUT VOLTAGE RIPPLE TEMPERATURE DERATING vs OUTPUT CURRENT vs OUTPUT CURRENT Figure Figure (1) All data listed in Figure Figure and Figure have been developed from actual products tested at This data is considered typical data for the dc-dc converter. (2) The temperature derating curves represent operating conditions at which internal components are at or below manufacturer's maximum rated operating temperature. Derating limits apply to modules soldered directly to a 100 mm 100 mm, double-sided PCB with oz. copper. For surface mount packages, multiple vias (plated through holes) are required to add thermal paths around the power pins. Please refer to the mechanical specification for more information. Applies to Figure Submit Documentation Feedback

www.ti.com PTMA402050 Characteristic Data O (3) (4) 0.4 1.6 1.2 0.8 2.0 0 0.5 1.0 2.01.5 IO − Output Current − A VIN = 48 V VIN = 36 V VIN = 60 V VIN = 75 V PD − Power Dissipation −W 0.5 1.0 2.0 2.5 3.0 1.5 IO − Output Current − A VIN = 48 V VIN = 36 V VIN = 60 V VIN = 75 V η Efficiency − % 0 0.5 1.0 2.01.5 IO − Output Current − A Natural Convection TA − Ambient Temperature − ° C 0 0.5 1.0 2.01.5 IO − Output Current − A VIN = 48 V VIN = 36 V VIN = 60 V VIN = 75 V VO − Output Voltage Ripple − VPP mV PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 TYPICAL CHARACTERISTICS (continued) EFFICIENCY POWER DISSIPATION vs OUTPUT CURRENT vs OUTPUT CURRENT Figure Figure OUTPUT VOLTAGE RIPPLE TEMPERATURE DERATING vs OUTPUT CURRENT vs OUTPUT CURRENT Figure Figure (3) All data listed in Figure Figure and Figure have been developed from actual products tested at This data is considered typical data for the dc-dc converter. (4) The temperature derating curves represent operating conditions at which internal components are at or below manufacturer's maximum rated operating temperature. Derating limits apply to modules soldered directly to a 100 mm 100 mm, double-sided PCB with oz. copper. For surface mount packages, multiple vias (plated through holes) are required to add thermal paths around the power pins. Please refer to the mechanical specification for more information. Applies to Figure Submit Documentation Feedback

www.ti.com PTMA401120 Characteristic Data O (5) (6) 0.2 0.4 0.8 10.6 I ! Output Current ! AO Efficiency VIN = 36 V V = 48 VIN VIN = 60 V VIN = 75 V 1.2 0.8 1.6 0.4 0 0.2 0.4 10.6 I ! Output Current ! AO P Power Dissipation D W VIN = 36 V V = 48 VIN VIN = 60 V VIN = 75 V 0.8 0 0.2 0.4 10.6 I ! Output Current ! AO V Output V oltage Ripple O V (mW) PP 0.8 VIN = 36 V V = 48 VIN VIN = 60 V VIN = 75 V 0 0.2 0.4 10.6 I ! Output Current ! AO Ambient T emperature Co 0.8 Natural Convection PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 TYPICAL CHARACTERISTICS (continued) EFFICIENCY POWER DISSIPATION vs OUTPUT CURRENT vs OUTPUT CURRENT Figure Figure 10. OUTPUT VOLTAGE RIPPLE TEMPERATURE DERATING vs OUTPUT CURRENT vs OUTPUT CURRENT Figure 11. Figure 12. (5) All data listed in Figure Figure and Figure have been developed from actual products tested at This data is considered typical data for the dc-dc converter. (6) The temperature derating curves represent operating conditions at which internal components are at or below manufacturer's maximum rated operating temperature. Derating limits apply to modules soldered directly to a 100 mm 100 mm, double-sided PCB with oz. copper. For surface mount packages, multiple vias (plated through holes) are required to add thermal paths around the power pins. Please refer to the mechanical specification for more information. Applies to Figure Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION Operating (primary) and the output terminals (secondary). All converters are tested to a withstand voltage of 1500 Vdc. This complies with UL/cUL 60950 and EN 60950 and the requirements for functional isolation. It allows the converter to be configured for either a positive or negative input voltage source. The data sheet Terminal Functions table provides guidance as to the correct reference that must be used for the external control signals. The undervoltage lockout (UVLO) is designed to prevent the operation of the converter until the input voltage is close to the minimum operating voltage. The converter is held off when the input voltage is below the UVLO threshold, and turns on when the input voltage rises above the threshold. This prevents high start-up current during normal power up of the converter, and minimizes the current drain from the input source during low input voltage conditions. The converter meets full specifications when the minimum specified input voltage is reached. The UVLO circuitry also overrides the operation of the enable or synchronization controls. Only when the input voltage is above the UVLO threshold does this input become functional. The module is protected from an overvoltage on the output using an internal clamp. This protects against a break in the feedback path as well as a ground fault on the external Trim resistor, which would cause the output voltage to increase. To protect against load faults, these converters incorporate output overcurrent protection. Applying a load to the output that exceeds the converter overcurrent threshold (see applicable specification) causes the output voltage to momentarily fold back, and then shut down. Following shutdown, the module periodically attempts to automatically recover by initiating a soft-start power up. This is often described as a hiccup mode of operation, whereby the module continues in the cycle of successive shutdown and power up until the load fault is removed. Once the fault is removed, the converter automatically recovers and returns to normal operation. When the converter is first powered, the internal soft-start circuit limits how fast the output voltage can rise. The soft-start circuit functions after a valid input source is applied and the output is enabled, after the converter output is enabled using the Enable input, or on a recovery from a load fault. The purpose of the soft-start feature is to limit the surge of current drawn from the input source when the converter begins to operate. By limiting the rate at which the output voltage rises, the magnitude of current required to charge up the load circuit capacitance is significantly reduced. Figure shows the power-up characteristic of a PTMA403033 converter. The output voltage is 3.3 The soft-start circuit causes a slow, soft rise of the output voltage. The output voltage will begin to rise after a time delay (typically ms-100 ms) once a valid input voltage is applied. The output then progressively rises to the voltage set-point. The waveforms were recorded with a resistive load of Submit Documentation Feedback

www.ti.com t − Time − 20 ms/div VOUT (1 V/div) VIN (10 V/div) IIN (100 mA/div) Output Voltage Trim Adjustment PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 APPLICATION INFORMATION (continued) Figure 13. Power-up Waveforms An external resistor is required to increase or decrease the output voltage set point of the module by The resistor, R TRIM must be connected between the TRIM pin (pin and V O (pin to decrease the output voltage, or between the TRIM pin and V O (pin to increase the output voltage. A 0.05-W rated resistor can be used. The tolerance should be 1%, with a temperature stability of 100 ppm/ C (or better). Place the resistor close to the converter and connect it using dedicated PCB traces (see Figure Table gives the nearest standard value of external resistor for the common voltages within each model's adjust range. Table Standard Values of R TRIM for Common Output Voltages PTMA403033 PTMA402050 PTMA401120 V O R TRIM Ω V O R TRIM Ω V O R TRIM Ω (required) (required) (required) down up down up down up 3.0 V 118 4.5 V 18.7 10.8 V 64.9 3.1 V 187 4.6 V 24.9 11.0 V 80.6 3.2 V 392 4.7 V 35.7 11.2 V 105 3.3 V open open 4.8 V 57.6 11.4 V 143 3.4 V 249 4.9 V 121 11.6 V 221 3.5 V 124 5.0 V open open 11.8 V 464 3.6 V 82.5 5.1 V 124 12.0 V open open 5.2 V 61.9 12.2 V 118 5.3 V 40.2 12.4 V 57.6 5.4 V 29.4 12.6 V 36.5 5.5 V 23.2 12.8 V 26.1 13.0 V 19.6 13.2 V 15.8 Submit Documentation Feedback

www.ti.com RTRIM(up) RO VR VO VSET RP (k) (1) RTRIM(dwn) RO VO VR VSET VO RP (k) (2) VO + VO + VO − TRIM TRIM RTRIM RTRIM CO CO VO + VO − VO − VO + VO − (a) TRIM DOWN (b) TRIM UP Thermal Considerations On/Off Enable Controls PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 For other output voltages, the value of the required trim resistor may be calculated using Equation to adjust the voltage up or Equation to adjust the voltage down. Table gives the required R TRIM equation constants for the converter model selected. To calculate the required value of R TRIM simply locate the applicable constants and substitute these into the formula along with the desired output voltage. Table Trim Adjust Equation Constants Constants PTMA403033 PTMA402050 PTMA401120 V R (V) 1.24 2.50 2.50 R O Ω 5.11 R P Ω 1.0 2.05 5.11 V SET (V) 3.3 5.0 12.0 V O (V) Desired Output Voltage Desired Output Voltage Desired Output Voltage Figure 14. Output Voltage Adjustment Airflow may be necessary to ensure that the module can supply the desired load current in environments with elevated ambient temperatures. The required airflow rate is determined from the safe operating area (SOA). The SOA is the area beneath the applicable airflow rate curve on the graph of temperature derating vs output current. (See the Typical Characteristics.) Operating the converter within the SOA limits ensures that all the internal components are at or below their stated maximum operating temperatures. On/Off enable options include positive logic or negative logic. A positive logic device enables the module's output when a logic high voltage is present on the Enable pin (pin and disables the output with a logic low voltage. A negative logic device disables the output when a logic high voltage is present on the Enable pin and enables the output during a logic low voltage. See the Electrical Characteristics table for logic high and logic low limits. The Enable pin is ideally controlled with an open-collector (or open-drain) discrete transistor. See Figure below for a typical On/Off Enable control circuit. For automatic start-up, the Enable pin should be left open for a positive logic module and should be shorted to V I (pin for a negative logic module. Both inputs are electrically referenced to V I on the primary (input) side of the converter. Do not place an external pull-up resistor on this input pin. Submit Documentation Feedback

www.ti.com Enable Control Schematic

3 ENABLE/SYNC

VI − VI + VI − On/Off Enable Turn-On Time t − Time − 1 ms/div VOUT (1 V/div) VENABLE (5 V/div) IIN (100 mA/div) PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 Figure 15. Typical On/Off Enable Control Circuit Once enabled, the converter executes a soft-start power up. The converter exibits a short delay of approximately 100 µ measured from the transition of the enable signal to the instance the V O Bus output begins to rise. The output is in regulation within 1.5 ms. Figure 16. Output Enable Power-Up Characteristic Submit Documentation Feedback

www.ti.com Synchronization VI − VI + VI − MECHANICALS Tape and Reel TOLERANCES UNLESS OTHERWISE SPECIFIED .XX = 0.005 HOLES = 0.001 .XXX = 0.003 ANGLES = 1/2! ± ± ± ± © This Document and the information contained herein is confidential and proprietary to Texas Instrumants, and may not be reproduced or used for any purpose without the expressed written permission of Texas Instruments. PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 The Synchronization option allows multiple power modules to be synchronized to a common frequency. Driving the Sync pin (pin with an external clock set to the desired frequency, synchronizes all connected modules to that frequency. Modules with the synchronization option have a reduced free-running switching frequency of 215 kHz typical. The synchronization frequency can only be adjusted to a higher frequency, up to 350 kHz. A 5-V logic signal is recommended for control. See Figure See the Electrical Characteristics table for synchronization limits. Figure 17. Synchronization Control Submit Documentation Feedback

www.ti.com Tray © This Document and the information contained herein is confidential and proprietary to Texas Instrumants, and may not be reproduced or used for any purpose without the expressed written permission of Texas Instruments. PTMA403033 PTMA402050 PTMA401120 SLTS259A FEBRUARY 2006 REVISED MARCH 2006 MECHANICALS (continued) Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PTMA401120A1AD ACTIVE DIP MOD ULE EEP 4 30 TBD Call TI Call TI PTMA401120A1AS ACTIVE DIP MOD ULE EET 4 30 TBD Call TI Call TI PTMA401120A1AST ACTIVE DIP MOD ULE EET 4 250 TBD Call TI Call TI PTMA401120A1AZ ACTIVE DIP MOD ULE BET 4 30 TBD Call TI Call TI PTMA401120A1AZT ACTIVE DIP MOD ULE BET 4 250 TBD Call TI Call TI PTMA401120A2AD ACTIVE DIP MOD ULE EEV 5 30 TBD Call TI Call TI PTMA401120A2AS ACTIVE DIP MOD ULE EEW 5 30 TBD Call TI Call TI PTMA401120A2AST ACTIVE DIP MOD ULE EEW 5 250 TBD Call TI Call TI PTMA401120A2AZ ACTIVE DIP MOD ULE BEW 5 30 TBD Call TI Call TI PTMA401120A2AZT ACTIVE DIP MOD ULE BEW 5 250 TBD Call TI Call TI PTMA401120A3AD ACTIVE DIP MOD ULE EEP 6 30 TBD Call TI Call TI PTMA401120A3AS ACTIVE DIP MOD ULE EET 6 30 TBD Call TI Call TI PTMA401120A3AST ACTIVE DIP MOD ULE EET 6 250 TBD Call TI Call TI PTMA401120A3AZ ACTIVE DIP MOD ULE BET 6 30 TBD Call TI Call TI PTMA401120A3AZT ACTIVE DIP MOD ULE BET 6 250 TBD Call TI Call TI PTMA401120N1AD ACTIVE DIP MOD ULE EEP 5 30 TBD Call TI Call TI PTMA401120N1AS ACTIVE DIP MOD ULE EET 5 30 TBD Call TI Call TI PTMA401120N1AST ACTIVE DIP MOD ULE EET 5 250 TBD Call TI Call TI PTMA401120N1AZ ACTIVE DIP MOD ULE BET 5 30 TBD Call TI Call TI PTMA401120N1AZT ACTIVE DIP MOD ULE BET 5 250 TBD Call TI Call TI PTMA401120N2AD ACTIVE DIP MOD ULE EEP 6 30 TBD Call TI Call TI PTMA401120N2AS ACTIVE DIP MOD ULE EET 6 30 TBD Call TI Call TI PTMA401120N2AST ACTIVE DIP MOD ULE EET 6 250 TBD Call TI Call TI PTMA401120N2AZ ACTIVE DIP MOD ULE BET 6 30 TBD Call TI Call TI PTMA401120N2AZT ACTIVE DIP MOD ULE BET 6 250 TBD Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PTMA401120P1AD ACTIVE DIP MOD ULE EEP 5 30 TBD Call TI Call TI PTMA401120P1AS ACTIVE DIP MOD ULE EET 5 30 TBD Call TI Call TI PTMA401120P1AST ACTIVE DIP MOD ULE EET 5 250 TBD Call TI Call TI PTMA401120P1AZ ACTIVE DIP MOD ULE BET 5 30 TBD Call TI Call TI PTMA401120P1AZT ACTIVE DIP MOD ULE BET 5 250 TBD Call TI Call TI PTMA401120P2AD ACTIVE DIP MOD ULE EEP 6 30 TBD Call TI Call TI PTMA401120P2AS ACTIVE DIP MOD ULE EET 6 30 TBD Call TI Call TI PTMA401120P2AST ACTIVE DIP MOD ULE EET 6 250 TBD Call TI Call TI PTMA401120P2AZ ACTIVE DIP MOD ULE BET 6 30 TBD Call TI Call TI PTMA401120P2AZT ACTIVE DIP MOD ULE BET 6 250 TBD Call TI Call TI PTMA402050A1AD ACTIVE DIP MOD ULE EEP 4 36 Pb-Free (RoHS) Call TI N / A for Pkg Type PTMA402050A1AS ACTIVE DIP MOD ULE EET 4 30 TBD Call TI Level-1-235C-UNLIM PTMA402050A1AST ACTIVE DIP MOD ULE EET 4 250 TBD Call TI Level-1-235C-UNLIM PTMA402050A1AZ ACTIVE DIP MOD ULE BET 4 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA402050A1AZT ACTIVE DIP MOD ULE BET 4 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA402050A2AD ACTIVE DIP MOD ULE EEV 5 30 Pb-Free (RoHS) Call TI N / A for Pkg Type PTMA402050A2AS ACTIVE DIP MOD ULE EEW 5 30 TBD Call TI Level-1-235C-UNLIM PTMA402050A2AST ACTIVE DIP MOD ULE EEW 5 250 TBD Call TI Level-1-235C-UNLIM PTMA402050A2AZ ACTIVE DIP MOD ULE BEW 5 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA402050A2AZT ACTIVE DIP MOD ULE BEW 5 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA402050A3AD ACTIVE DIP MOD ULE EEP 6 30 Pb-Free (RoHS) Call TI N / A for Pkg Type PTMA402050A3AS ACTIVE DIP MOD ULE EET 6 30 TBD Call TI Level-1-235C-UNLIM PTMA402050A3AST ACTIVE DIP MOD ULE EET 6 250 TBD Call TI Level-1-235C-UNLIM PTMA402050A3AZ ACTIVE DIP MOD ULE BET 6 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA402050A3AZT ACTIVE DIP MOD ULE BET 6 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA402050N1AD ACTIVE DIP MOD ULE EEP 5 30 Pb-Free (RoHS) Call TI N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 2

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PTMA402050N1AS ACTIVE DIP MOD ULE EET 5 30 TBD Call TI Level-1-235C-UNLIM PTMA402050N1AST ACTIVE DIP MOD ULE EET 5 250 TBD Call TI Level-1-235C-UNLIM PTMA402050N1AZ ACTIVE DIP MOD ULE BET 5 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA402050N1AZT ACTIVE DIP MOD ULE BET 5 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA402050N2AD ACTIVE DIP MOD ULE EEP 6 30 Pb-Free (RoHS) Call TI N / A for Pkg Type PTMA402050N2AS ACTIVE DIP MOD ULE EET 6 30 TBD Call TI Level-1-235C-UNLIM PTMA402050N2AST ACTIVE DIP MOD ULE EET 6 250 TBD Call TI Level-1-235C-UNLIM PTMA402050N2AZ ACTIVE DIP MOD ULE BET 6 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA402050N2AZT ACTIVE DIP MOD ULE BET 6 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA402050P1AD ACTIVE DIP MOD ULE EEP 5 30 Pb-Free (RoHS) Call TI N / A for Pkg Type PTMA402050P1AS ACTIVE DIP MOD ULE EET 5 30 TBD Call TI Level-1-235C-UNLIM PTMA402050P1AST ACTIVE DIP MOD ULE EET 5 250 TBD Call TI Level-1-235C-UNLIM PTMA402050P1AZ ACTIVE DIP MOD ULE BET 5 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA402050P1AZT ACTIVE DIP MOD ULE BET 5 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA402050P2AD ACTIVE DIP MOD ULE EEP 6 30 Pb-Free (RoHS) Call TI N / A for Pkg Type PTMA402050P2AS ACTIVE DIP MOD ULE EET 6 30 TBD Call TI Level-1-235C-UNLIM PTMA402050P2AST ACTIVE DIP MOD ULE EET 6 250 TBD Call TI Level-1-235C-UNLIM PTMA402050P2AZ ACTIVE DIP MOD ULE BET 6 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA402050P2AZT ACTIVE DIP MOD ULE BET 6 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033A1AD ACTIVE DIP MOD ULE EEP 4 30 Pb-Free (RoHS) Call TI N / A for Pkg Type PTMA403033A1AS ACTIVE DIP MOD ULE EET 4 30 TBD Call TI Level-1-235C-UNLIM PTMA403033A1AST ACTIVE DIP MOD ULE EET 4 250 TBD Call TI Level-1-235C-UNLIM PTMA403033A1AZ ACTIVE DIP MOD ULE BET 4 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033A1AZT ACTIVE DIP MOD ULE BET 4 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033A2AD ACTIVE DIP MOD ULE EEV 5 30 Pb-Free (RoHS) Call TI N / A for Pkg Type PTMA403033A2AS ACTIVE DIP MOD ULE EEW 5 30 TBD Call TI Level-1-235C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 3

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PTMA403033A2AST ACTIVE DIP MOD ULE EEW 5 250 TBD Call TI Level-1-235C-UNLIM PTMA403033A2AZ ACTIVE DIP MOD ULE BEW 5 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033A2AZT ACTIVE DIP MOD ULE BEW 5 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033A3AD ACTIVE DIP MOD ULE EEP 6 30 Pb-Free (RoHS) Call TI N / A for Pkg Type PTMA403033A3AS ACTIVE DIP MOD ULE EET 6 30 TBD Call TI Level-1-235C-UNLIM PTMA403033A3AST ACTIVE DIP MOD ULE EET 6 250 TBD Call TI Level-1-235C-UNLIM PTMA403033A3AZ ACTIVE DIP MOD ULE BET 6 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033A3AZT ACTIVE DIP MOD ULE BET 6 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033N1AD ACTIVE DIP MOD ULE EEP 5 30 Pb-Free (RoHS) Call TI N / A for Pkg Type PTMA403033N1AS ACTIVE DIP MOD ULE EET 5 30 TBD Call TI Level-1-235C-UNLIM PTMA403033N1AST ACTIVE DIP MOD ULE EET 5 250 TBD Call TI Level-1-235C-UNLIM PTMA403033N1AZ ACTIVE DIP MOD ULE BET 5 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033N1AZT ACTIVE DIP MOD ULE BET 5 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033N2AD ACTIVE DIP MOD ULE EEP 6 30 Pb-Free (RoHS) Call TI N / A for Pkg Type PTMA403033N2AS ACTIVE DIP MOD ULE EET 6 30 TBD Call TI Level-1-235C-UNLIM PTMA403033N2AST ACTIVE DIP MOD ULE EET 6 250 TBD Call TI Level-1-235C-UNLIM PTMA403033N2AZ ACTIVE DIP MOD ULE BET 6 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033N2AZT ACTIVE DIP MOD ULE BET 6 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033P1AD ACTIVE DIP MOD ULE EEP 5 30 Pb-Free (RoHS) Call TI N / A for Pkg Type PTMA403033P1AS ACTIVE DIP MOD ULE EET 5 30 TBD Call TI Level-1-235C-UNLIM PTMA403033P1AST ACTIVE DIP MOD ULE EET 5 250 TBD Call TI Level-1-235C-UNLIM PTMA403033P1AZ ACTIVE DIP MOD ULE BET 5 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033P1AZT ACTIVE DIP MOD ULE BET 5 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033P2AD ACTIVE DIP MOD ULE EEP 6 30 Pb-Free (RoHS) Call TI N / A for Pkg Type PTMA403033P2AS ACTIVE DIP MOD ULE EET 6 30 TBD Call TI Level-1-235C-UNLIM PTMA403033P2AST ACTIVE DIP MOD ULE EET 6 250 TBD Call TI Level-1-235C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 4

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PTMA403033P2AZ ACTIVE DIP MOD ULE BET 6 30 Pb-Free (RoHS) Call TI Level-3-260C-168 HR PTMA403033P2AZT ACTIVE DIP MOD ULE BET 6 250 Pb-Free (RoHS) Call TI Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 5

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