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  • PDF pages: 11

Technical content

Features

  • Designed for wide RF modulation bandwidths, and low memory effects
  • On-chip matching, integrated input DC block, 50-ohm input and ~ 8-ohm output
  • Typical GSM/EDGE performance, 940 MHz, 28 V - Output power = 15 W Avg. - Linear gain = 31 dB - Power added efficiency = 36% - EVM at 15 W = 1.7 % - ACPR at 400 kHz = –61 dBc - ACPR at 600 kHz = –73 dBc
  • Typical CW performance at 940 MHz, 28 V - Output power at P–1dB = 32 W - Linear gain (1 W) = 31 dB - Power added efficiency = 46%
  • Capable of handling 10:1 VSWR @ 28 V, 30 W (CW) output power
  • Integrated ESD protection. Meets HBM Class 1B (minimum), per JESD22-A114F
  • RoHS-compliant package RF Characteristics GSM/EDGE Measurements (not subject to production test—verified by design/characterization in Infineon test fixture) VDD = 28 V, IDQ1 = 120 mA, IDQ2 = 280 mA, ƒ = 920 to 960 MHz, POUT = 15 W Avg. Characteristic Symbol Min Typ Max Unit Gain Gps — 31 — dB Power-added Efficiency PAE — 36 — % Error Vector Magnitude EVM (RMS) — 1.7 — %

Data Sheet 2 of 11 Rev. 05.1, 2010-11-09 PTMA080302M Confidential, Limited Internal Distribution RF Characteristics (cont.) GSM/EDGE Measurements (cont.) VDD = 28 V, IDQ1 = 120 mA, IDQ2 = 280 mA, ƒ = 920 to 960 MHz, POUT = 15 W Avg. Characteristic Symbol Min Typ Max Unit Modulation Spectrum 400 kHz offset ACPR1 — –61 — dBc 600 kHz offset ACPR2 — –73 — dBc Input Return Loss IRL — –15 — dB Gain Flatness Δ G — 0.2 — dB Two-tone Measurements (tested in Infineon test fixture) VDD = 28 V, IDQ1 = 120 mA, IDQ2 = 280 mA, POUT = 32 W PEP, ƒ = 940 MHz, tone spacing = 1 MHz Characteristic Symbol Min Typ Max Unit Gain Gps 31 32 — dB Power-added Efficiency PAE 34 35 — % Intermodulation Distortion IMD — –33 –31 dBc Single-tone Measurements (not subject to production test—verified by design/characterization in Infineon test fixture ) VDD = 28 V, IDQ1 = 120 mA, IDQ2 = 280 mA, ƒ = 940 MHz Characteristic Symbol Min Typ Max Unit Gain Gps — 32 — dB Power-added Efficiency PAE — 46 — % Output Power P–1dB — 31 — W DC Characteristics Characteristic Conditions Symbol Min Typ Max Unit Drain-Source Breakdown Voltage VGS = 0 V, IDS = 10 mA V(BR)DSS 65 — — V Drain Leakage Current VDS = 28 V, VGS = 0 V IDSS — — 1.0 µA VDS = 63 V, VGS = 0 V IDSS — — 10.0 µA On-State Resistance Stage 1 VGS = 10 V, VDS = 0.1 V RDS(on) — 0.25 — Ω Stage 2 VGS = 10 V, VDS = 0.1 V RDS(on) — 1.85 — Ω Operating Gate Voltage VDS = 28 V, VGS 2.0 2.5 3.0 V IDQ1 = 120 mA, IDQ2 = 280 mA Gate Leakage Current VGS = 10 V, VDS = 0 V IGSS — — 1.0 µA

Data Sheet 3 of 11 Rev. 05.1, 2010-11-09 PTMA080302M Confidential, Limited Internal Distribution Maximum Ratings Parameter Symbol Value Unit Drain-Source Voltage VDSS 65 V Gate-Source Voltage VGS –0.5 to +12 V Junction Temperature TJ 200 °C Input Power PIN 16 dBm Total Device Dissipation PD 129.5 W Above 25°C derate by 0.74 W/°C Storage Temperature Range TSTG –40 to +150 °C Thermal Resistance (TCASE = 70°C) Stage 1 Rθ JC 6.7 °C/W Stage 2 Rθ JC 1.7 °C/W Moisture Sensitivity Level Level Test Standard Package Temperature Unit

3 IPC/JEDEC J-STD-020 260 °C

Ordering Information

Type and Version Package Outline Package Description Shipping PTMA080302M V1 PG-DSO-20-63 Copper heat slug, plastic EMC body Tape

Data Sheet 4 of 11 Rev. 05.1, 2010-11-09 PTMA080302M Confidential, Limited Internal Distribution Power Sweep at Selected Drain Voltages VDD1=28 V, VDD2 = 24 V, 28 V and 32 V, IDQ1 = 120 mA, ƒ = 940 MHz 29 31 33 35 37 39 41 43 45 47 Output Power (dBm) Power Gain (dB) 28 V 24 V 32 V EDGE Modulation Spectrum Performance VDD = 28 V, IDQ1 = 120 mA, IDQ2 = 280 mA, series show ƒ = 942 MHz at selected temperatures 30 32 34 36 38 40 42 44 46 Output Power (dBm) Gain (dB) 25 °C –25 °C 25 °C 90 °C Gain Typical Performance (data taken in a production test fixture) CW Power Performance VDD = 28 V, IDQ1 = 120 mA, IDQ2 = 280 mA, ƒ = 920, 940, 960 MHz 28 32 36 40 44 48 Output Power (dBm) Gain (dB) Power Added Efficiency (%) Efficiency Gain

920 MHz

940 MHz

960 MHz

VDD = 28 V, IDQ1 = 120 mA, IDQ2 = 280 mA, selected frequencies -70 -60 -50 -40 -30 -20 27 29 31 33 35 37 39 41 43 Output Power (dBm) IMD3 (dBc) Power Added Efficiency (%) Efficiency IMD3

Data Sheet 5 of 11 Rev. 05.1, 2010-11-09 PTMA080302M Confidential, Limited Internal Distribution EDGE Modulation Spectrum Performance VDD = 28 V, IDQ1 = 120 mA, IDQ2 = 280 mA, series are at selected frequencies 30 32 34 36 38 40 42 44 Output Power (dBm) Power Added Efficiency (%) -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 Edge Modulation Spectrum (dBc) Efficiency 600 kHz 400 kHz

925.2 MHz

942.6 MHz

959.8 MHz

EDGE Modulation Spectrum Performance VDD = 28 V, IDQ1 = 120 mA, IDQ2 = 280 mA, series show ƒ = 942 MHz at selected temperatures 30 32 34 36 38 40 42 44 Output Power (dBm) Power Added Efficiency (%) -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 Edge Modulation Spectrum (dBc) Efficiency 600 kHz 400 kHz –25 °C 25 °C 90 °C Typical Performance (cont.) EDGE EVM VDD = 28 V, IDQ1 = 120 mA, I DQ2 = 280 mA, series show ƒ = 942 MHz at selected temperatures 30 32 34 36 38 40 42 44 Output Power (dBm) Power Added Efficiency (%) Error Vector Magnitude(%) Efficiency EVM –25 °C 25 °C 90 °C EDGE EVM VDD = 28 V, IDQ1 = 120 mA, IDQ2 = 280 mA, series are at selected frequencies 30 32 34 36 38 40 42 44 Output Power (dBm) Power Added Efficiency (%) Error Vector Magnitude(%) Efficiency EVM

Data Sheet 6 of 11 Rev. 05.1, 2010-11-09 PTMA080302M Confidential, Limited Internal Distribution Broadband Circuit Impedance 0.1 0.3 0.2 0.4 0.1 0. 1 0.2 AVELENGTHS TO W ARD G ENER <---W AVELENG THS TOW ARD LOAD - 0.0

700 MHz

1000 MHz

Z0 = 50 Ω Frequency Z Load W MHz R jX 700 11.7 –4.5 720 11.0 –4.0 740 10.3 –3.6 760 9.8 –3.1 780 9.3 –2.6 800 8.9 –2.1 820 8.6 –1.6 840 8.3 –1.0 860 8.0 –0.5 880 7.8 0.0 900 7.7 0.6 920 7.6 1.1 940 7.5 1.7 960 7.4 2.3 980 7.4 2.9 1000 7.5 3.5 Gate – Source Voltage vs. Temperature VDD = 28 V, IDQ1 = 120 mA, IDQ2 = 280 mA 0.85 0.90 0.95 1.00 1.05 1.10 1.15 -30 -10 10 30 50 70 90 Temperature (°C) Normalized Gate – Source Voltage (threshold), V Slope = –1.3 mV/°C VGS1 VGS2 Typical Performance (cont.) Z LoadD S IN

Data Sheet 7 of 11 Rev. 05.1, 2010-11-09 PTMA080302M Confidential, Limited Internal Distribution Reference Circuit — for evaluation only Reference circuit schematic for ƒ = 940 MHz Circuit Assembly Information DUT PTMA080302M LDMOS IC PCB 0.76 mm [.030"] thick, εr = 3.48 Rogers RO4350 1 oz. copper Microstrip Electrical Characteristics at 940 MHz Dimensions: L x W (mm) Dimensions: L x W (in.) C16 10µF C14 0.1µF C17 100µF 50V C25 33pF C20 10µF C21 100µF 50V C24 6.8pF l8 l9 l10 C15 1µF C19 1µF C18 0.1µF C22 0.6pFl3 C23 0.6pF PTMA080302M 47pF DUT VD1 10µF 100µF 50V 0.1µF 10µF 0.1µF 47pF C11 1µF C12 0.1µF C13 47pF 1µF 1µF C10 10µF G2V G1V

Data Sheet 8 of 11 Rev. 05.1, 2010-11-09 PTMA080302M Confidential, Limited Internal Distribution RF_OUT a080302 m _cd _ 1 - 30 - 09 RF_IN VD2 VG1 VG2 VD1 RO4350, .030 C11 C12 C10 C17 C21 C13 C18 C19 C16 VD2 C14 C24 C15 C23 C22 C25 C20 Q2Q1 VD1 PTMA080302M_01 Reference Circuit (cont.) Reference circuit asembly diagram* (not to scale) Component Description Suggested Manufacturer P/N or Comment C1, C17, C21 Electrolytic capacitor, 100 µF, 50 V Digi-Key PCE3718CT-ND C2, C6, C10, Ceramic capacitor, 10 µF Murata GRM422Y5V106Z050AL C16, C20 C3, C7, C11, Ceramic capacitor, 1 µF Digi-Key 445-1411-2-ND C15, C19 C4, C8, C12, Capacitor, 0.1 µF Digi-Key 399-1267-2-ND C14, C18 C5, C9, C13 Ceramic capacitor, 47 pF ATC 600F470JT C22, C23 Ceramic capacitor, 0.6 pF ATC 600S0R6BT C24 Ceramic capacitor, 6.8 pF ATC 600S6R8CT C25 Ceramic capacitor, 33 pF ATC 600F330JT Q1 , Q2 Transistor Infineon Technologies BCP56 R1, R2 Resistor, 0 Ω Digi-Key 603 R3, R4 Potentiometer 2k Ω Digi-Key 3224W-202ETR-ND *Gerber Files for this circuit available on request

Data Sheet 9 of 11 Rev. 05.1, 2010-11-09 PTMA080302M Confidential, Limited Internal Distribution Package Outline Specifications Package PG-DSO-20-63 2X 2.90 [0.114] MAX (2 PLS) 13.00 [0.512] MAX 110 11 20 INDEX PIN 1 14.20±0.30 11.00 [0.433] 9 X 1.27 = 11.43 9 X .050 = .450 1.10 [0.043] MAX (2 PLS) 2.95 [0.116] 6.00 [0.236] TOP VIEW BOTTOM VIEW [0.559±0.012] 0.40+0.13 [0.015+0.005] 0.25mm C A B 15.90±0.10 [0.626±0.004] 1.27 [0.050] 14°±1° (2 PLS) TOP/BOTTOM ALL SIDES 11.00±0.10 [0.433±0.004] 3.50 [0.137] MAX SEE DETAIL A SIDE VIEW END VIEW M S S 0.95±0.15 [0.037±0.006] 0.35 [0.014] GAUGE PLANE 0.15 [0.006] REF 0+0.1 [0+0.004] STANDOFF 1.60 [0.063] REF 0.25+0.07 –0.02 [0.010 ]+0.003 – 0.001 DETAIL A PG-DSO- 20- 63_ po _02 -19 -2010 Diagram Notes—unless otherwise specified: 1. Interpret dimensions and tolerances per ASME Y14.5M-1994. 3. JEDEC drawing number: MO-166. 4. Does not include plastic or metal protrusion of 0.15 mm max per side. 5. Does not include dambar protrusion; maximum allowable dambar protrusion shall be 0.08 mm. 6. Bottom metallization. 7. Sn plating (matte) : 5 – 15 micron [196.85 – 590.55 microinch]. Refer to Application Note “Recommendations for Printed Circuit Board Assembly of Infineon DSO and SSOP Packages” for additional information.

Data Sheet 10 of 11 Rev. 05.1, 2010-11-09 PTMA080302M Confidential, Limited Internal Distribution Source: Plated copper heatslug on backside of package Pinout Diagram PTMA080302M Thermal FET a080302 m_ pd _ 8 -19 -10 VDD 1 VDD 1 RF In VG Thermal FET VD Thermal FET RF In VG 1 VG 2 NC NC NC VDD 2, RF Out VDD 2, RF Out VDD 2, RF Out VDD 2, RF Out VDD 2, RF Out VDD 2, RF Out NC NC NC Find the latest and most complete information about products and packaging at the Infineon Internet page http://www.infineon.com/rfpower

Data Sheet 11 of 11 Rev. 05.1, 2010-11-09 PTMA080302M V1 Confidential, Limited Internal Distribution Revision History: 2010-11-09 Data Sheet Previous Revision: 2010-04-16, Data Sheet Page Subjects (major changes since last revision)

7 Revise circuit measurments

81726 Munich, Germany

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