TLV758P_18 TI1 | Alldatasheet
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ADVANCE□INFORMATION IN OUT GND EN N/C TLV758P VOUTVIN FB C IN C OUT VEN R 2 R 1 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TLV758P SBVS351 – APRIL 2018 TLV758P500-mALDOinSmall2-mm×2-mmWSONPackage
1 Features
1• Input Voltage Range: 1.5 V to 6.0 V
- Adjustable Output Voltage: – 0.55 V to 5.5 V
- Low Dropout: – 125 mV (max) at 500 mA (3.3 VOUT)
- IQ: 25 µA (Typical)
- Output Accuracy: 1% (Maximum)
- Built-In Soft-Start With Monotonic VOUT Rise
- Package: – 2-mm × 2-mm WSON-6 (DRV)
- Active Output Discharge
2 Applications
- Set-Top Boxes, Gaming Consoles
- Home Theater and Entertainment
- Desktops, Notebooks, Ultrabooks
- Printers
- Servers
- Thermostat and Lighting Control
- Electronic Point of Sale (EPOS)
3 Description
The TLV758P is an adjustable 500-mA low-dropout (LDO) regulator. This device is available in a small, 6- pin, 2-mm × 2-mm WSON package and consumes very low quiescent current and provides fast line and load transient performance. The TLV758P features an ultra-low dropout of 125 mV at 500 mA that can help improve the power efficiency of the system. The TLV758P is stable with small ceramic output capacitors, allowing for a small overall solution size. A precision band-gap and error amplifier provides a maximum accuracy of 1%. This device includes integrated thermal shutdown, current limit, and undervoltage lockout (UVLO) features. The TLV758P has an internal foldback current limit that helps reduce the thermal dissipation during short-circuit events. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLV758P WSON (6) 2.00 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application
ADVANCE□INFORMATION TLV758P SBVS351 – APRIL 2018 www.ti.com Product Folder Links: TLV758P Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Table of Contents
11.2 Receiving Notification of Documentation Updates 13
12 Mechanical, Packaging, and Orderable
4 Revision History
April 2018 * Initial release.
ADVANCE□INFORMATION GND OUT IN 2 NC 5FB EN TLV758P www.ti.com SBVS351 – APRIL 2018 Product Folder Links: TLV758P Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated
5 Pin Configuration and Functions
EN 4 Input Enable pin. Drive EN greater than VHI to turn on the regulator. Drive EN less than VLO to put the LDO into shutdown mode. FB 2 — This pin is used as an input to the control loop error amplifier and is used to set the output voltage of the LDO. GND 3 — Ground pin IN 6 Input Input pin. A minimum of 0.22-µF capacitance is required from this pin to ground. OUT 1 Output Regulated output voltage pin. For best transient response, use a small 1-µF ceramic capacitor from this pin to ground; see the Input and Output Capacitor Selection section. NC 5 — Not connected. Thermal pad Pad — The thermal pad is electrically connected to the GND node. Connect to the GND plane for improved thermal performance.
ADVANCE□INFORMATION TLV758P SBVS351 – APRIL 2018 www.ti.com Product Folder Links: TLV758P Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The absolute maximum rating is VIN + 0.3 V or 6.5 V, whichever is smaller.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage Supply, VIN –0.3 6.5 VEnable, VEN –0.3 VIN + 0.3 Output, VOUT –0.3 VIN + 0.3(2) Current Enable, IEN TBD µA Temperature Operating junction, TJ –40 150 Storage, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) The maximum enable toggle frequency must be below 10 kHz.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage 1.5 6.0 V VOUT Output voltage 0.55 5.5 V IOUT Output current 0 500 mA CIN Input capacitor 1 µF COUT Output capacitor 1 200 µF VEN Enable voltage(1) 0 6.0 V
ADVANCE□INFORMATION TLV758P www.ti.com SBVS351 – APRIL 2018 Product Folder Links: TLV758P Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.4 Thermal Information(1)
THERMAL METRIC(1) TLV758P UNITDRV (WSON)
6 PINS
RθJA Junction-to-ambient thermal resistance 80.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 98.7 °C/W RθJB Junction-to-board thermal resistance 44.8 °C/W ψJT Junction-to-top characterization parameter 6.1 °C/W ψJB Junction-to-board characterization parameter 45.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 20.8 °C/W
6.5 Electrical Characteristics
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage 1.5 6.0 V VOUT Output voltage 0.55 5.5 V VFB Feedback voltage TJ = 25°C 0.545 0.55 0.555 V Output accuracy –40°C ≤ TJ ≤ +85°C, 0.55 V ≤ VOUT < 1.0 V –10 10 mV –40°C ≤ TJ ≤ +125°C, 0.55 V ≤ VOUT < 1 V –15 15 mV Line regulation VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.0 V 2 mV Load regulation 0.1 mA ≤ IOUT ≤ 500 mA 0.050 V/A IGND Ground current TJ = 25°C, IOUT = 0 mA 14 25 33 µA–40°C ≤ TJ ≤ +85°C, IOUT = 0 mA 35 –40°C ≤ TJ ≤ +125°C, IOUT = 0 mA 45 ISHDN Shutdown current VEN ≤ 0.4 V, 1.4 V ≤ VIN ≤ 6.0 V 0.1 1 µA IFB Feedback pin current 0.01 0.1 µA ICL Output current limit VIN = VOUT + 0.5 V VOUT = VOUT – 0.2 V, VOUT ≤ 1 V 600 720 865 mA VOUT = 0.9 V × VOUT, 1.0 V < VOUT ≤ 5.5 V 600 720 865 ISC Short-circuit current limit VOUT = 0 V 350 mA VDO Dropout voltage IOUT = 500 mA, –40°C ≤ TJ ≤ +125°C, VOUT = 0.95 × VOUT(NOM) 0.6 V ≤ VOUT < 0.8 V 720 890 mV 0.8 V ≤ VOUT < 1.0 V 585 750 1.0 V ≤ VOUT < 1.2 V 420 575 1.2 V ≤ VOUT < 1.5 V 285 405 1.5 V ≤ VOUT < 1.8 V 180 235 1.8 V ≤ VOUT < 2.5 V 140 175 2.5 V ≤ VOUT < 3.3 V 102 125 3.3 V ≤ VOUT < 5.5 V 95 115 PSRR Power-supply rejection ratio VIN = VOUT + 1 V, IOUT = 50 mA f = 1 kHz 66 dBf = 100 kHz 45 f = 1 MHz 30 VN Output noise voltage BW = 10 Hz to 100 kHz, VOUT = 0.6 V 30 µVRMS VUVLO Undervoltage lockout VIN rising 1.27 1.33 1.42 V VUVLO, HYST Undervoltage lockout hysteresis VIN falling 45 mV
ADVANCE□INFORMATION TLV758P SBVS351 – APRIL 2018 www.ti.com Product Folder Links: TLV758P Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTR Startup time From EN low-to-high transition to VOUT = VOUT × 95% 500 µs VHI EN pin high voltage (enabled) 1.0 V VLO EN pin low voltage (enabled) 0.3 V IEN Enable pin current VIN = EN = 6.0 V 10 nA RPULL DOWN Pulldown resistance VIN = 6.0 V 120 Ω TSD Thermal shutdown Shutdown, temperature increasing 170 Reset, temperature decreasing 155
ADVANCE□INFORMATION /c116= 120□·□RL 120□+□RL
- □COUT Band Gap Thermal Shutdown UVLO Logic Current Limit 120 IN EN GND OUT FB TLV758P www.ti.com SBVS351 – APRIL 2018 Product Folder Links: TLV758P Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The TLV758P belongs to a family of next-generation, low-dropout regulators (LDOs). This device consumes low quiescent current and delivers excellent line and load transient performance. These characteristics, combined with low noise and good PSRR with low dropout voltage, makes this device ideal for portable consumer applications. This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature for this device is –40°C to +125°C.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TLV758P uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is greater than the rising UVLO voltage (VUVLO). This circuit ensures that the device does not exhibit any unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry. When VIN is less than VUVLO, the output is connected to ground with a 120-Ω pulldown resistor.
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VHI. Turn off the device by forcing the EN pin to drop below VLO. If shutdown capability is not required, connect EN to IN. The TLV758P has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel with the 120-Ω pulldown resistor. Equation 1 calculates the time constant: (1)
(1) All table conditions must be met. (2) The device is disabled when any condition is met.
7.3.3 Internal Foldback Current Limit
device cycles between current limit and thermal shutdown. excessively high current may flow through the body diode.
7.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 170°C. dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits regulator dissipation, protecting the LDO from damage as a result of overheating. thermal protection is triggered; use worst-case loads and signal conditions. in normal operation. Continuously running the TLV758P into thermal shutdown degrades device reliability.
7.4 Device Functional Modes
Table 1 lists a comparison between the normal, dropout, and disabled modes of operation. Table 1. Device Functional Modes Comparison
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Adjustable Output
Figure 1. Adjustable Operation Use Equation 2 to calculate R1 and R2 for any output voltage range.
- VFB = 0.55 V (2)
8.1.2 Input and Output Capacitor Selection
maximum recommended output capacitance is 100 µF. anticipated, or if the device is located several inches from the input power source.
8.1.3 Dropout Voltage
(VIN – VOUT) approaches dropout operation.
8.1.4 Power Dissipation
the device. The addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness. product of the output current and voltage drop across the output pass element. does not operate continuously above a junction temperature of 125°C. Figure 2. Maximum Ambient Temperature vs Device Power Dissipation
8.2 Typical Application
Figure 3. TLV758P Typical Application
8.2.1 Design Requirements
Use the parameters listed in Table 2 for typical linear regulator applications. Table 2. Design Parameters
8.2.2 Detailed Design Procedure
and Output Capacitor Selection section for details. Adjustable Output section for details.
9 Power Supply Recommendations
Connect a low output impedance power supply directly to the IN pin of the TLV758P.
10 Layout
10.1 Layout Guidelines
- Place input and output capacitors as close to the device as possible.
- Use copper planes for device connections, in order to optimize thermal performance.
- Place thermal vias around the device to distribute the heat.
- Do not place a thermal via directly beneath the thermal pad of the DRV package. A via can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder joint on the thermal pad.
10.2 Layout Example
Figure 4. DRV Package Layout Example
ADVANCE□INFORMATION TLV758P www.ti.com SBVS351 – APRIL 2018 Product Folder Links: TLV758P Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following: Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 20-Nov-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTLV75801PDRVR ACTIVE WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 TLV75801PDRVR PREVIEW WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1MHH TLV75801PDRVT PREVIEW WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1MHH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
www.ti.com 20-Nov-2018 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 22-Nov-2018 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV75801PDRVR WSON DRV 6 3000 210.0 185.0 35.0 TLV75801PDRVR WSON DRV 6 3000 205.0 200.0 33.0 TLV75801PDRVT WSON DRV 6 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 22-Nov-2018 Pack Materials-Page 2
Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. DRV 6 WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4206925/F
www.ti.com PACKAGE OUTLINE C 6X 0.35 0.25 1.6 0.1 6X 0.3 0.2 1.3 1 0.1 4X 0.65 0.8 0.7 0.05 0.00 B 2.1 1.9 A 2.1 1.9 (0.2) TYP WSON - 0.8 mm max heightDRV0006A PLASTIC SMALL OUTLINE - NO LEAD 4222173/B 04/2018 PIN 1 INDEX AREA SEATING PLANE 0.08 C 3 4 (OPTIONAL) PIN 1 ID
0.1 C A B
0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 5.500
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MIN
0.07 MAX
(1) 4X (0.65) (1.95) 6X (0.3) 6X (0.45) (1.6) (R0.05) TYP ( 0.2) VIA TYP (1.1) WSON - 0.8 mm max heightDRV0006A PLASTIC SMALL OUTLINE - NO LEAD 4222173/B 04/2018 SYMM 3 4 SYMM LAND PATTERN EXAMPLE SCALE:25X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)
www.ti.com EXAMPLE STENCIL DESIGN 6X (0.3) 6X (0.45) 4X (0.65) (0.7) (1) (1.95) (R0.05) TYP (0.45) WSON - 0.8 mm max heightDRV0006A PLASTIC SMALL OUTLINE - NO LEAD 4222173/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD #7 88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:30X SYMM 3 4 SYMM METAL
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