PTLV75710PDRVR

TLV757P TI1 | Alldatasheet

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ADVANCE□INFORMATION IINRUSH 200 mA/div VOUT

1 V/div

Copyright © 2017, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TLV757P SBVS322 – OCTOBER 2017 TLV757P1-A,LowIQ,SmallSize,LowDropoutRegulator

1 Features

1• Input Voltage Range: 1.4 V to 5.5 V

Available in Fixed-Output Voltages: – 0.6 V to 5 V (50-mV Steps)
Low IQ: 25 µA (Typical)
Low Dropout: – 350 mV (Maximum) at 1 A (3.3 VOUT)
Output Accuracy: 1% (Typical)
Built-In Soft-Start With Monotonic VOUT Rise
Foldback Current Limit
Active Output Discharge
High PSRR: 45 dB at 100 kHz
Stable With a 1-µF Ceramic Output Capacitor
Packages: – SOT-23-5 – 2 mm × 2 mm (WSON-6)

2 Applications

Set Top Boxes, TV, and Gaming Consoles
Portable and Battery-Powered Equipment
Desktop, Notebooks, and Ultrabooks
Tablets and Remote Controls
White Goods and Appliances
Grid Infrastructure and Protection Relays
Camera Modules and Image Sensors

3 Description

The TLV757P low-dropout regulator (LDO) is an ultra- small, low quiescent current LDO that sources 1 A with good line and load transient performance. The TLV757P is optimized for wide variety of applications by supporting an input voltage range from 1.4 V to 5.5 V. To minimize cost and solution size, the device is offered in fixed output voltages ranging from 0.6 V to 5 V to support the lower core voltages of modern MCUs. Additionally, the TLV757P has a low IQ with enable functionality to minimize standby power. This device features an internal soft-start to lower the inrush current which provides a controlled voltage to the load and minimizes the input voltage drop during start up. When shutdown, the device actively pulls down the output to quickly discharge the outputs and ensure a known start-up state. The TLV757P is stable with small ceramic output capacitors allowing for a small overall solution size. A precision band-gap and error amplifier provides a typical accuracy of 1%. All device versions have integrated thermal shutdown, current limit, and undervoltage lockout (UVLO). The TLV757P has an internal foldback current limit that helps to reduce the thermal dissipation during short circuit events. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLV757P SON (6) 2.00 mm × 2.00 mm SOT-23 (5) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Startup Waveform

11.2 Receiving Notification of Documentation Updates 15

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES October 2017 * Initial release.

ADVANCE□INFORMATION 1IN 2GND 3EN 4 NC

5 OUT

5 Pin Configuration and Functions

NC- no internal connection 6-Pin SON With Exposed Thermal Pad Top View (1) The nominal input and output capacitance must be greater than 0.47 µF; throughout this document the nominal derating on these capacitors is 50%. Take care to ensure that the effective capacitance at the pin is greater than 0.47 µF. Pin Functions PIN I/O DESCRIPTION NAME DBV DRV EN 3 4 I Enable pin. Drive EN greater than VHI to turn on the regulator. Drive EN less than VLO to place the LDO into shutdown mode. GND 2 3 — Ground pin. IN 1 6 I Input pin. A capacitor with a value of 1 µF or larger is required from this pin to ground(1). See the Input and Output Capacitor Selection section for more information. NC 4 2, 5 — No internal connection. OUT 5 1 O Regulated output voltage pin. A capacitor with a value of 1 µF or larger is required from this pin to ground(1). See the Input and Output Capacitor Selection section for more information. Thermal pad — Pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The absolute maximum rating is VIN + 0.3 V or 6 V, whichever is smaller

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage Supply, VIN –0.3 6 VEnable, VEN –0.3 6 Output, VOUT –0.3 VIN + 0.3(2) Temperature Operating junction, TJ –40 150 Storage, Tstg –65 150

ADVANCE□INFORMATION TLV757P SBVS322 – OCTOBER 2017 www.ti.com Product Folder Links: TLV757P Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT CIN Input capacitor 1 µF COUT Output capacitor 1 200 µF VIN Input voltage 1.4 5.5 V VOUT Output voltage 0.6 5 V IOUT Output current 0 1 A VEN Enable voltage 0 5.5 V fEN Enable toggle frequency 10 kHz TJ Junction temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TLV757P UNITDBV (SOT-23) DRV (SON)

5 PINS 6 PINS

RθJA Junction-to-ambient thermal resistance 231.1 100.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 118.4 108.5 °C/W RθJB Junction-to-board thermal resistance 64.4 64.3 °C/W ψJT Junction-to-top characterization parameter 28.4 10.4 °C/W ψJB Junction-to-board characterization parameter 63.8 64.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 34.7 °C/W (1) VIN = 1.4 V for VOUT < 0.9 V.

6.5 Electrical Characteristics

over operating free-air temperature range (TJ = –40°C to +125°C), VIN = VOUT + 0.5 V or 1.4 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage 1.4 5.5 V VOUT Output voltage 0.6 5 V Output accuracy TJ = 25°C –1% 1% –40°C ≤ TJ ≤ +85°C, 0.6 V ≤ VOUT < 1 V –15 15 mV

0.6 V ≤ VOUT < 1 V –25 25 mV

(ΔVOUT)ΔVIN/ VOUT Line regulation VOUT + 0.5 V(1) ≤ VIN ≤ 5.5 V VOUT ≤ 1.5 V 0.05% 0.25% ΔVOUT/ ΔIOUT Load regulation 0.1 mA ≤ IOUT ≤ 1 A, VIN ≥ 2 V DRV package 0.044 0.066 V/A DBV package 0.060 0.099

ADVANCE□INFORMATION TLV757P www.ti.com SBVS322 – OCTOBER 2017 Product Folder Links: TLV757P Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature range (TJ = –40°C to +125°C), VIN = VOUT + 0.5 V or 1.4 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) Dropout is measured when VOUT is 5% below VOUT(NOM). IGND Ground current TJ = 25°C, IOUT = 0 mA 14 25 29 µA–40°C ≤ TJ ≤ +85°C, IOUT = 0 mA 40 –40°C ≤ TJ ≤ +125°C, IOUT = 0 mA 50 ISHDN Shutdown current VEN= 0 V, 1.4 V ≤ VIN ≤ 5.5 V, TJ = 25°C 0.1 1 µA ICL Output current limit VIN = VOUT + VDO(MAX) + 0.1 V VOUT = VOUT – 0.2 V, VOUT ≤ 1.5 V 1.2 1.55 1.73 A VOUT = 0.9 × VOUT, ISC Short-circuit current limit VOUT = 0 V 755 mA VDO Dropout voltage(2) IOUT = 1 A, 0.6 V ≤ VOUT < 0.8 V 2200 mV

0.8 V ≤ VOUT < 1 V 1800

1 V ≤ VOUT < 1.2 V 1500 1.2 V ≤ VOUT < 1.5 V 1200 1.5 V ≤ VOUT < 1.8 V 750 1.8 V ≤ VOUT < 2.5 V 560 2.5 V ≤ VOUT < 3.3 V 520 3.3 V ≤ VOUT ≤ 5.0 V 440 IOUT = 1 A, 0.6 V ≤ VOUT < 0.8 V 2500

0.8 V ≤ VOUT < 1 V 2000

1 V ≤ VOUT < 1.2 V 1700 1.2 V ≤ VOUT < 1.5 V 1400 1.5 V ≤ VOUT < 1.8 V 950 1.8 V ≤ VOUT < 2.5 V 660 2.5 V ≤ VOUT < 3.3 V 580 3.3 V ≤ VOUT ≤ 5.0 V 540 PSRR Power-supply rejection ratio f = 1 kHz, VIN = VOUT + 1 V, IOUT = 1 A 48 dBf = 100 kHz. VIN = VOUT + 1 V, IOUT = 1 A 55 f = 1 MHz, VIN = VOUT + 1 V, IOUT = 1 A 35 Vn Output noise voltage BW = 10 Hz to 100 kHz, VOUT = 1.2 V, IOUT = 1 A 71.5 µVRMS VUVLO Undervoltage lockout VIN rising 1.23 1.3 1.37 V VUVLO, HYST Undervoltage lockout hysteresis VIN falling 40 mV tSTR Startup time Time from EN assertion to 0.95 × VOUT 400 µs VHI EN pin high voltage (enabled) 0.9 V VLO EN pin low voltage (enabled) 0.4 V IEN Enable pin current EN = 5.5 V, VIN = 5.5V 10 nA RPULLDOWN Pulldown resistance VIN = 3.3 V 120 Ω TSD Thermal shutdown Shutdown, temperature increasing 165 Reset, temperature decreasing 155

6.6 Typical Characteristics

Figure 1. Power-Supply Rejection Ratio vs IOUT Figure 2. Line Transient Figure 3. 3.3-V, 1-mA to 1-A Load Transient Figure 4. VIN = VEN Power-Up Figure 5. VIN = VEN Shutdown

ADVANCE□INFORMATION /c116= 120□·□RL 120□+□RL

□COUT Bandgap Thermal Shutdown UVLO Logic Current Limit 120 IN EN GND OUT R 1 R 2 TLV757P www.ti.com SBVS322 – OCTOBER 2017 Product Folder Links: TLV757P Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TLV757P belongs to a family of next-generation, low-dropout regulators (LDOs). This device consumes low quiescent current and delivers excellent line and load transient performance. The TLV757P is optimized for wide variety of applications by supporting an input voltage range from 1.4 V to 5.5 V. To minimize cost and solution size, the device is offered in fixed output voltages ranging from 0.6 V to 5 V to support the lower core voltages of modern MCUs. This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature is –40°C to +125°C.

7.2 Functional Block Diagram

(1) R1 + R2 = TBD.

7.3 Feature Description

7.3.1 Undervoltage Lockout (UVLO)

An undervoltage lockout (UVLO) circuit disables the output until the input voltage is greater than the rising UVLO voltage (VUVLO). This circuit ensures that the device does not exhibit any unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry. When VIN is less than VUVLO, the output is connected to ground with a 120-Ω pulldown resistor.

7.3.2 Enable (EN)

The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VHI. Turn off the device by forcing the EN pin below VLO. If shutdown capability is not required, connect EN to IN. The device has an internal pull-down that connects a 120-Ω resistor to ground when the device is disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel with the 120-Ω pulldown resistor. Equation 1 calculates the time constant τ: (1)

7.3.3 Internal Foldback Current Limit

between current limit and thermal shutdown. has risen to the nominal voltage. Figure 6. TLV757P Current Limit vs VOUT

7.3.4 Thermal Shutdown

Thermal shutdown protection disables the output when the junction temperature rises to approximately 165°C. dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits regulator dissipation which protects the circuit from damage as a result of overheating. thermal protection is triggered; use worst-case loads and signal conditions. operation. Continuously running the device into thermal shutdown degrades device reliability.

(1) All table conditions must be met. (2) The device is disabled when any condition is met.

7.4 Device Functional Modes

Table 1 lists a comparison between the normal, dropout, and disabled modes of operation. Table 1. Device Functional Modes Comparison

7.4.1 Normal Operation

The device regulates to the nominal output voltage when all of the following conditions are met.

The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO)
The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased below the enable falling threshold
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)

7.4.2 Dropout Operation

result in large output-voltage deviations. VOUT(NOM) + VDO, VOUT can overshoot VOUT(NOM) during fast transients.

7.4.3 Disabled

the output to ground. The active pulldown is on when sufficient input voltage is provided.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Input and Output Capacitor Selection

output capacitance value of 200 µF. inches from the input power source.

8.1.2 Dropout Voltage

approaches dropout operation. See Figure 7 for typical dropout values. Figure 7. Dropout vs VIN

8.1.3 Exiting Dropout

LDO to overshoot on start-up when the slew rate and voltage levels are in the correct range, as Figure 8 shows. Use an enable signal to avoid this condition.

Figure 8. Startup into Dropout

8.1.4 Reverse Current

As with most LDOs, excessive reverse current can damage this device.

Degradation caused by electromigration
Excessive heat dissipation
Potential for a latch-up condition Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT > VIN + 0.3 V:
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply If reverse current flow is expected in the application, external protection must be used to protect the device. Figure 9 shows one approach of protecting the device.

Figure 9. Example Circuit for Reverse Current Protection Using a Schottky Diode

ADVANCE□INFORMATION /c89 /c89 /c89 /c180 JT J T JT D: T = T + P/c89 /c180 JB J B JB D: T = T + P TLV757P SBVS322 – OCTOBER 2017 www.ti.com Product Folder Links: TLV757P Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Application Information (continued)

8.1.5 Power Dissipation (PD)

Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must be as free of other heat-generating devices as possible that cause added thermal stresses. As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. Use Equation 2 to approximate PD: PD = (VIN – VOUT) × IOUT (2) It is important to minimize power dissipation to achieve greater efficiency. This minimizing process is achieved by selecting the correct system voltage rails. Proper selection helps obtain the minimum input-to-output voltage differential . The low dropout of the device allows for maximum efficiency across a wide range of output voltages. The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to inner plane areas or to a bottom-side copper plane. The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (θJA) of the combined PCB, device package, and the temperature of the ambient air (TA), according to Equation 3. TJ = TA + θJA × PD (3) Unfortunately, this thermal resistance (θJA) is dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The θJA value recorded in the table is determined by the JEDEC standard, PCB, and copper-spreading area. The θJA value is only used as a relative measure of package thermal performance. θJA is the sum of the VQFN package junction-to-case (bottom) thermal resistance (θJCbot) plus the thermal resistance contribution by the PCB copper.

8.1.5.1 Estimating Junction Temperature

The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not thermal resistances, but offer practical and relative means of estimating junction temperatures. These psi metrics are independent of the copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are shown in the table and are used in accordance with Equation 4. where:

PD is the power dissipated as shown in Equation 2
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge (4)

8.2 Typical Application

Figure 10. TLV757P Typical Application

8.2.1 Design Requirements

Table 2. Design Parameters

8.2.2 Detailed Design Procedure

8.2.2.1 Input Current

During normal operation, the input current to the LDO is approximately equal to the output current of the LDO. Equation 5 to calculate the current through the input.

VOUT(t) is the instantaneous output voltage of the turnon ramp
dVOUT(t) / dt is the slope of the VOUT ramp
RLOAD is the resistive load impedance (5)

8.2.2.2 Thermal Dissipation

temperature (TA) to calculate the junction temperature (TJ) as Equation 7 shows. If the (TJ(MAX)) value does not exceed 125°C calculate the maximum ambient temperature as Equation 8 shows. Equation 9 calculates the maximum ambient temperature with a value of 74.58°C.

9 Power Supply Recommendations

supply impedance over frequency.

10 Layout

10.1 Layout Guidelines

Place input and output capacitors as close as possible to the device.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device to distribute the heat.

10.2 Layout Examples

Figure 11. Layout Example: DBV Package Figure 12. Layout Example: DRV Package

device product folder on www.ti.com. (2) Output voltages from 0.6 V to 5 V in 50-mV increments are available. Contact the factory for details and availability.

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Table 3. Device Nomenclature(1)(2) in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). discharge the output when the device is disabled. yyy is the package designator. z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).

11.2 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 22-Nov-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTLV75709PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75709PDRVR ACTIVE WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 PTLV75710PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75710PDRVR ACTIVE WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 PTLV75712PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75712PDRVR ACTIVE WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 PTLV75715PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75715PDRVR ACTIVE WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 PTLV75718PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75718PDRVR ACTIVE WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 PTLV75719PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75719PDRVR ACTIVE WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 PTLV75725PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75725PDRVR ACTIVE WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 PTLV75728PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75728PDRVR ACTIVE WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 PTLV75729PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75730PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75730PDRVR ACTIVE WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 PTLV75733PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125

www.ti.com 22-Nov-2017 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTLV75733PDRVR ACTIVE WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 PTLV75740PDRVR ACTIVE WSON DRV 6 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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Summary

1-A, Low IQ, Small Size, Low Dropout Regulator

Description