PTLV75512PDBVR

TLV755P_18 TI1 | Alldatasheet

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ADVANCE□INFORMATION IINRUSH 200 mA/div VOUT

1 V/div

Copyright © 2017, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TLV755P SBVS320 – NOVEMBER 2017 TLV755P500-mA,LowIQ,SmallSize,LowDropoutRegulator

1 Features

1• Input Voltage Range: 1.44 V to 5.5 V

Available in Fixed-Output Voltages: – 0.6 V to 5 V (50-mV Steps)
Low IQ: 25 µA (Typical)
Low Dropout: – 220 mV (Maximum) at 500 mA (3.3 VOUT)
Output Accuracy: 1% (Typical)
Built-In Soft-Start With Monotonic VOUT Rise
Foldback Current Limit
Active Output Discharge
High PSRR: 45 dB at 100 kHz
Stable With a 1-µF Ceramic Output Capacitor
Packages: – 2.9-mm × 1.6-mm SOT-23-5 – 1-mm x 1-mm X2SON-4 – 2 mm × 2 mm WSON-6

2 Applications

Set-Top Boxes, TV, and Gaming Consoles
Portable and Battery-Powered Equipment
Desktop, Notebooks, and Ultrabooks
Tablets and Remote Controls
White Goods and Appliances
Grid Infrastructure and Protection Relays
Camera Modules and Image Sensors

3 Description

The TLV755P low-dropout regulator (LDO) device is an ultra-small, low quiescent current LDO that sources 500 mA with good line and load transient performance. The TLV755P is optimized for a wide variety of applications by supporting an input voltage range from 1.44 V to 5.5 V. To minimize cost and solution size, the device is offered in fixed output voltages ranging from 0.6 V to 5 V to support the lower core voltages of modern microcontroller (MCUs). Additionally, the TLV755 has a low IQ with enable functionality to minimize standby power. This device features an internal soft-start to lower inrush current, thus providing a controlled voltage to the load and minimizing the input voltage drop during start up. When shutdown, the device actively pulls down the output to quickly discharge the outputs and ensure a known start-up state. The TLV755P is stable with small ceramic output capacitors allowing for a small overall solution size. A precision band-gap and error amplifier provides a typical accuracy of 1%. All device versions have integrated thermal shutdown, current limit, and undervoltage lockout (UVLO). The TLV755P has an internal foldback current limit that helps reduce the thermal dissipation during short-circuit events. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLV755P X2SON (4) 1.00 mm × 1.00 mm SOT-23 (5) 2.90 mm × 1.60 mm SON (6) 2.00 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Startup Waveform

11.2 Receiving Notification of Documentation Updates 17

12 Mechanical, Packaging, and Orderable

4 Revision History

November 2017 * Initial release.

ADVANCE□INFORMATION 1OUT 6 IN 2NC 5 NC 3GND 4 EN Not to scale Thermal Pad 1IN 2GND 3EN 4 NC

5 OUT

5 Pin Configuration and Functions

6-Pin WSON With Exposed Thermal Pad Top View NC = no internal connection. (1) The nominal input and output capacitance must be greater than 0.47 µF; throughout this document the nominal derating on these capacitors is 50%. Take care to ensure that the effective capacitance at the pin is greater than 0.47 µF. Pin Functions PIN I/O DESCRIPTION NAME DQN DBV DRV EN 3 3 4 I Enable pin. Drive EN greater than VHI to turn on the regulator. Drive EN less than VLO to place the LDO into shutdown mode. GND 2 2 3 — Ground pin. IN 4 1 6 I Input pin. A capacitor with a value of 1 µF or larger is required from this pin to ground(1). See the Input and Output Capacitor Selection section for more information. NC — 4 2, 5 — No internal connection. OUT 1 5 1 O Regulated output voltage pin. A capacitor with a value of 1 µF or larger is required from this pin to ground(1). See the Input and Output Capacitor Selection section for more information. Thermal pad — — Pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

ADVANCE□INFORMATION TLV755P SBVS320 – NOVEMBER 2017 www.ti.com Product Folder Links: TLV755P Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The absolute maximum rating is VIN + 0.3 V or 6 V, whichever is smaller.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage Supply, VIN –0.3 6 VEnable, VEN –0.3 6 Output, VOUT –0.3 VIN + 0.3(2) Temperature Operating junction, TJ –40 150 Storage, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT CIN Input capacitor 1 µF COUT Output capacitor 1 200 µF VIN Input voltage 1.44 5.5 V VOUT Output voltage 0.6 5 V IOUT Output current 0 500 mA VEN Enable voltage 0 5.5 V fEN Enable toggle frequency 10 kHz TJ Junction temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TLV755P UNITDQN (X2SON) DBV (SOT-23) DRV (WSON)

4 Pins 5 PINS 6 PINS

RθJA Junction-to-ambient thermal resistance 168.4 231.1 100.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 139.1 118.4 108.5 °C/W RθJB Junction-to-board thermal resistance 101.4 64.4 64.3 °C/W ψJT Junction-to-top characterization parameter 5.6 28.4 10.4 °C/W ψJB Junction-to-board characterization parameter 101.7 63.8 64.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 88.4 N/A 34.7 °C/W

ADVANCE□INFORMATION TLV755P www.ti.com SBVS320 – NOVEMBER 2017 Product Folder Links: TLV755P Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) VIN = 1.44 V for VOUT < 0.9 V. (2) Dropout is measured when VOUT is 5% below VOUT(NOM).

6.5 Electrical Characteristics

over operating free-air temperature range (TJ = –40°C to +125°C), VIN = VOUT + 0.5 V or 1.44 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage 1.44 5.5 V VOUT Output voltage 0.6 5 V Output accuracy TJ = 25°C –1% 1% –40°C ≤ TJ ≤ +85°C, 0.6 V ≤ VOUT < 1 V –10 10 mV

0.6 V ≤ VOUT < 1 V –15 15 mV

(ΔVOUT)ΔVIN/ VOUT Line regulation VOUT + 0.5 V(1) ≤ VIN ≤ 5.5 V VOUT > 1.5 V 0.01% ΔVOUT/ ΔIOUT Load regulation 0.1 mA ≤ IOUT ≤ 500 mA, VIN ≥ 2.4 V DQN package 0.018 V/ADBV package 0.030 DRV package 0.022 IGND Ground current TJ = 25°C, IOUT = 0 mA 14 25 31 µA–40°C ≤ TJ ≤ +85°C, IOUT = 0 mA 33 –40°C ≤ TJ ≤ +125°C, IOUT = 0 mA 40 ISHDN Shutdown current VEN= 0 V, 1.44 V ≤ VIN ≤ 5.5 V, –40°C ≤ TJ ≤ +125°C 0.1 1 µA ICL Output current limit VIN = VOUT + VDO(MAX) + 0.25 V VOUT = VOUT – 0.2 V, VOUT ≤ 1.5 V 600 720 865 mA VOUT = 0.9 × VOUT, 1.5 V < VOUT ≤ 4.5 V 600 720 865 ISC Short-circuit current limit VOUT = 0 V 355 mA VDO Dropout voltage(2) IOUT = 500 mA, –40°C ≤ TJ ≤ +85°C 0.6 V ≤ VOUT < 0.8 V 675 700 mV

0.8 V ≤ VOUT < 1 V 600 650

1 V ≤ VOUT < 1.2 V 550 575 1.2 V ≤ VOUT < 1.5 V 500 525 1.5 V ≤ VOUT < 1.8 V 350 400 1.8 V ≤ VOUT < 2.5 V 325 375 2.5 V ≤ VOUT < 3.3 V 250 300 3.3 V ≤ VOUT ≤ 5.0 V 150 212 IOUT = 500 mA, 0.6 V ≤ VOUT < 0.8 V 725

0.8 V ≤ VOUT < 1 V 675

1 V ≤ VOUT < 1.2 V 600 1.2 V ≤ VOUT < 1.5 V 550 1.5 V ≤ VOUT < 1.8 V 425 1.8 V ≤ VOUT < 2.5 V 400 2.5 V ≤ VOUT < 3.3 V 325 3.3 V ≤ VOUT ≤ 5.0 V 238 PSRR Power-supply rejection ratio f = 1 kHz, VIN = VOUT + 1 V, IOUT = 50 mA 52 dBf = 100 kHz, VIN = VOUT + 1 V, IOUT = 50 mA 46 f = 1 MHz, VIN = VOUT + 1 V, IOUT = 50 mA 52 Vn Output noise voltage BW = 10 Hz to 100 kHz, VOUT = 1.2 V, IOUT = 50 mA 71.5 µVRMS VUVLO Undervoltage lockout VIN rising 1.21 1.3 1.44 V VUVLO, HYST Undervoltage lockout hysteresis VIN falling 40 mV

ADVANCE□INFORMATION TLV755P SBVS320 – NOVEMBER 2017 www.ti.com Product Folder Links: TLV755P Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature range (TJ = –40°C to +125°C), VIN = VOUT + 0.5 V or 1.44 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTR Startup time Time from EN assertion to 0.95 × VOUT 400 µs VHI EN pin high voltage (enabled) 0.9 V VLO EN pin low voltage (enabled) 0.4 V IEN Enable pin current EN = 5.5 V, VIN = 5.5 V 10 nA RPULLDOWN Pulldown resistance VIN = 3.3 V 120 Ω TSD Thermal shutdown Shutdown, temperature increasing 165 Reset, temperature decreasing 155

6.6 Typical Characteristics

Figure 1. PSRR vs Frequency and IOUT Figure 2. Line Transient Figure 3. 1-mA to 500-mA Load Transient Figure 4. VIN = VEN Power-Up Figure 5. VIN = VEN Shutdown

ADVANCE□INFORMATION /c116= 120□·□RL 120□+□RL

□COUT Bandgap Thermal Shutdown UVLO Logic Current Limit 120 IN EN GND OUT R 1 R 2 TLV755P SBVS320 – NOVEMBER 2017 www.ti.com Product Folder Links: TLV755P Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TLV755P belongs to a family of next-generation, low-dropout regulators (LDOs). This device consumes low quiescent current and delivers excellent line and load transient performance. The TLV755P is optimized for a wide variety of applications by supporting an input voltage range from 1.4 V to 5.5 V. To minimize cost and solution size, the device is offered in fixed output voltages ranging from 0.6 V to 5 V to support the lower core voltages of modern MCUs. This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature is –40°C to +125°C.

7.2 Functional Block Diagram

NOTE: R1 + R2 = TBD.

7.3 Feature Description

7.3.1 Undervoltage Lockout (UVLO)

An undervoltage lockout (UVLO) circuit disables the output until the input voltage is greater than the rising UVLO voltage (VUVLO). This circuit ensures that the device does not exhibit any unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry. When VIN is less than VUVLO, the output is connected to ground with a 120-Ω pulldown resistor.

7.3.2 Enable (EN)

The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VHI. Turn off the device by forcing the EN pin below VLO. If shutdown capability is not required, connect EN to IN. The device has an internal pulldown resistor that connects a 120-Ω resistor to ground when the device is disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel with the 120-Ω pulldown resistor. Equation 1 calculates the time constant τ: (1)

7.3.3 Internal Foldback Current Limit

between current limit and thermal shutdown. rises to the nominal voltage. Figure 6. TLV755 Current Limit vs VOUT

7.3.4 Thermal Shutdown

Thermal shutdown protection disables the output when the junction temperature rises to approximately 165°C. dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits regulator dissipation and protects the circuit from damage as a result of overheating. thermal protection is triggered; use worst-case loads and signal conditions. operation. Continuously running the device into thermal shutdown degrades device reliability.

(1) All table conditions must be met. (2) The device is disabled when any condition is met.

7.4 Device Functional Modes

Table 1 lists a comparison between the normal, dropout, and disabled modes of operation. Table 1. Device Functional Modes Comparison

7.4.1 Normal Operation

The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO)
The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased below the enable falling threshold
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)

7.4.2 Dropout Operation

result in large output-voltage deviations. VOUT(NOM) + VDO, VOUT can overshoot VOUT(NOM) during fast transients.

7.4.3 Disabled

the output to ground. The active pulldown resistor is on when sufficient input voltage is provided.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Input and Output Capacitor Selection

output capacitance value of 200 µF. inches from the input power source.

8.1.2 Dropout Voltage

approaches dropout operation. Figure 7 shows typical dropout values. Figure 7. Dropout vs VIN

8.1.3 Exiting Dropout

supply causes an LDO to overshoot on start-up when the slew rate and voltage levels are in the correct range. Use an enable signal to avoid this condition. Figure 8. Startup Into Dropout

8.1.4 Reverse Current

As with most LDOs, excessive reverse current can damage this device.

Degradation caused by electromigration
Excessive heat dissipation
Potential for a latch-up condition

If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply If reverse current flow is expected in the application, external protection must be used to protect the device. Figure 9 shows one approach of protecting the device.

Figure 9. Example Circuit for Reverse Current Protection Using a Schottky Diode

8.1.5 Power Dissipation (PD)

be as free of other heat-generating devices as possible that cause added thermal stresses. differential. The low dropout of the device allows for maximum efficiency across a wide range of output voltages. conduct heat to inner plane areas or to a bottom-side copper plane. The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA value recorded in the table is determined by the JEDEC standard, PCB, and copper-spreading area.

8.1.5.1 Estimating Junction Temperature

PD is the power dissipated as described in Equation 2
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge (4)

8.2 Typical Application

Figure 10. TLV755P Typical Application

8.2.1 Design Requirements

Table 2 lists the design requirements for this application. Table 2. Design Parameters

ADVANCE□INFORMATION I =OUT(t) COUT OUT/c180dV (t) dt VOUT(t) RLOAD TLV755P www.ti.com SBVS320 – NOVEMBER 2017 Product Folder Links: TLV755P Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

8.2.2 Detailed Design Procedure

8.2.2.1 Input Current

During normal operation, the input current to the LDO is approximately equal to the output current of the LDO. During startup, the input current is higher as a result of the inrush current charging the output capacitor. Use Equation 5 to calculate the current through the input. where:

VOUT(t) is the instantaneous output voltage of the turnon ramp
dVOUT(t) / dt is the slope of the VOUT ramp
RLOAD is the resistive load impedance (5)

8.2.2.2 Thermal Dissipation

The junction temperature can be determined using the junction-to-ambient thermal resistance (RθJA) and the total power dissipation (PD). Use Equation 6 to calculate the power dissipation. As Equation 7 shows, multiply PD by RθJA and add the ambient temperature (TA) to calculate the junction temperature (TJ). PD = (IGND+ IOUT) × (VIN – VOUT) (6) TJ = RθJA × PD + TA (7) If the (TJ(MAX)) value does not exceed 125°C, use Equation 8 to calculate the maximum ambient temperature. Equation 9 calculates the maximum ambient temperature with a value of 103.39°C. TA(MAX) = TJ(MAX) – RθJA × PD (8)

9 Power Supply Recommendations

Connect a low output impedance power supply directly to the IN pin of the TLV755P. If the input source is reactive, consider using multiple input capacitors in parallel with the 1-µF input capacitor to lower the input supply impedance over frequency.

10 Layout

10.1 Layout Guidelines

Place input and output capacitors as close as possible to the device
Use copper planes for device connections to optimize thermal performance
Place thermal vias around the device to distribute the heat

10.2 Layout Examples

Figure 11. Layout Example: DQN Package Figure 12. Layout Example: DBV Package Figure 13. Layout Example: DRV Package

device product folder on www.ti.com. (2) Output voltages from 0.6 V to 5 V in 50-mV increments are available. Contact the factory for details and availability.

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Table 3. Device Nomenclature(1)(2) in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). the output when the device is disabled. yyy is the package designator. z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).

11.2 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 24-Apr-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTLV75507PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 PTLV75509PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75510PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75510PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 PTLV75512PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75512PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 PTLV75515PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75515PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 PTLV75518PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75518PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 PTLV75519PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75519PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 PTLV75525PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75525PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 PTLV75528PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75528PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 PTLV75529PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75530PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV75530PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 PTLV75533PDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125

www.ti.com 24-Apr-2018 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTLV75533PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 TLV75507PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 KD TLV75507PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 KD TLV75509PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TLV75509PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AX TLV75509PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AX TLV75510PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 1FPF TLV75510PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 KE TLV75510PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 KE TLV75512PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TLV75512PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AG TLV75512PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AG TLV75515PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TLV75515PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 KF TLV75515PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 KF TLV75518PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TLV75518PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AI TLV75518PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AI

www.ti.com 24-Apr-2018 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLV75519PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TLV75519PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 B5 TLV75519PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 B5 TLV75525PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TLV75525PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AJ TLV75525PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AJ TLV75528PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TLV75528PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 KG TLV75528PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 KG TLV75529PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TLV75530PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TLV75530PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 KI TLV75530PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 KI TLV75533PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TLV75533PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AN TLV75533PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

www.ti.com 24-Apr-2018 Addendum-Page 4 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com PACKAGE OUTLINE C TYP0.22 0.08 0.25 3.0 2.6 2X 0.95 1.9

1.45 MAX

TYP0.15 0.00 5X 0.5 0.3 TYP0.6 0.3 TYP8 1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/C 04/2017 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

DQN0004A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4215302/E 12/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. 4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes. 5. Shape of exposed side leads may differ. 6. Number and location of exposed tie bars may vary. www.ti.com B A SEATING PLANE C 0.08 PIN 1 INDEX AREA

0.1 C A B

0.05 C PIN 1 ID (OPTIONAL) NOTE 4 EXPOSED THERMAL PAD 2 3 1.05 0.95 1.05 0.95

0.4 MAX

2X 0.65 0.48+0.12 -0.1 3X 0.30 0.15 0.3 0.2 4X 0.28 0.15 0.05 0.00 (0.11) NOTE 5 NOTE 6 NOTE 6 (0.07) TYP (0.05) TYP

DQN0004A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4215302/E 12/2016 NOTES: (continued) 7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented. www.ti.com SOLDER MASK DEFINED SOLDER MASK DETAIL

0.05 MIN

SCALE: 40X SYMM SYMM 4X (0.21) 4X (0.36) (0.65) (0.86) ( 0.48) SEE DETAIL 4X (0.18) (0.22) TYP EXPOSED METAL CLEARANCE (0.03) EXPOSED METAL

DQN0004A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4215302/E 12/2016 NOTES: (continued) 9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com SOLDER PASTE EXAMPLE BASED ON 0.075 - 0.1mm THICK STENCIL EXPOSED PAD 88% PRINTED SOLDER COVERAGE BY AREA SCALE: 60X SYMM SYMM SOLDER MASK EDGE 4X (0.21) 4X (0.4) (0.65) (0.9) ( 0.45) 4X (0.03) 4X (0.235) 4X (0.22)

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Summary

500-mA, Low IQ, Small Size, Low Dropout Regulator

Description