PTLV73325PQDBVRQ1

TLV733P-Q1_1812 TI1 | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 30

Technical content

IOUT (mA) VDO (mV) 0 30 60 90 120 150 180 210 240 270 300 100 120 140 160 180 D020 VOUT = 3.3 V VOUT = 1.8 V TLV733P-Q1 IN EN OUT GND C OUT C IN OptionalOptional ON OFF Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLV733P-Q1 SBVS283D – AUGUST 2016– REVISED DECEMBER 2018 TLV733P-Q1 Capacitor-Free,300-mA,LowDropout(LDO)LinearRegulator

1 Features

1• Qualified for Automotive Applications

• AEC-Q100 Qualified: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C4B
• Device Junction Temperature Range: –40°C to 150°C
• Input Voltage Range: 1.4 V to 5.5 V
• Stable Operation With or Without Capacitors
• Foldback Overcurrent Protection
• Package: – 2.0-mm × 2.0-mm WSON-6 – 2.9-mm × 1.6-mm SOT-23
• Very Low Dropout: 125 mV at 300 mA (3.3 VOUT)
• Accuracy: 1% Typical, 1.4% Maximum
• Low IQ: 34 µA
• Available in Fixed-Output Voltages: 1.0 V to 3.3 V
• High PSRR: 50 dB at 1 kHz
• Active Output Discharge

2 Applications

• Camera Modules
• Automotive Infotainment
• Navigation Systems

3 Description

The TLV733P-Q1 family of low dropout (LDO) linear regulators are ultra-small, low quiescent current LDOs that can source 300 mA with good line and load transient performance. These devices provide a typical accuracy of 1%. The TLV733P-Q1 family is designed with a modern capacitor-free architecture to ensure stability without an input or output capacitor. The removal of the output capacitor allows for a very small solution size, and can eliminate inrush current at startup. Furthermore, the TLV733P-Q1 family is also stable with ceramic output capacitors if an output capacitor is necessary. The TLV733P-Q1 family also provides foldback current control during device power-up and enabling if an output capacitor is used. This functionality is especially important in battery- operated devices. The TLV733P-Q1 family provides an active pulldown circuit to quickly discharge output loads when disabled. The TLV733P-Q1 family is available in the 6-pin DRV (WSON) and 5-pin DBV (SOT-23) packages. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLV733P-Q1 WSON (6) 2.00 mm × 2.00 mm SOT-23 (5) 2.90 mm × 1.60 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Typical Application Circuit Dropout Voltage vs Output Current

SBVS283D –AUGUST 2016– REVISED DECEMBER 2018 www.ti.com Product Folder Links: TLV733P-Q1 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Table of Contents

11.2 Receiving Notification of Documentation Updates 18

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (October 2018) to Revision D Page Changes from Revision B (August 2018) to Revision C Page Changes from Revision A (August 2016) to Revision B Page

• Changed Electrical Characteristics conditions statement from TJ, TA = –40°C to +125°C to TJ = –40°C to +150°C, TA Changes from Original (August 2016) to Revision A Page

5 OUT

www.ti.com SBVS283D – AUGUST 2016–REVISED DECEMBER 2018 Product Folder Links: TLV733P-Q1 Submit Documentation FeedbackCopyright © 2016–2018, Texas Instruments Incorporated

5 Pin Configuration and Functions

NOTE: NC – No internal connection. 5-Pin SOT-23 Top View Pin Functions NAME NO. I/O DESCRIPTIONDRV DBV EN 4 3 I Enable pin. Drive EN greater than 0.9 V to turn on the regulator. Drive EN less than 0.35 V to put the LDO into shutdown mode. GND 3 2 — Ground pin IN 6 1 I Input pin. A small capacitor is recommended from this pin to ground. See the Input and Output Capacitor Selection section for more details. NC 2, 5 4 — No internal connection OUT 1 5 O Regulated output voltage pin. For best transient response, use a small 1-μF ceramic capacitor from this pin to ground. See the Input and Output Capacitor Selection section for more details. Thermal pad — — The thermal pad is electrically connected to the GND node. Connect to the GND plane for improved thermal performance.

SBVS283D –AUGUST 2016– REVISED DECEMBER 2018 www.ti.com Product Folder Links: TLV733P-Q1 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted); all voltages are with respect to GND(1) MIN MAX UNIT Voltage VIN –0.3 6.0 VVEN –0.3 VIN + 0.3 VOUT –0.3 3.6 Current IOUT Internally limited A Output short-circuit duration Indefinite Temperature Operating junction, TJ –40 150 Storage, Tstg –65 160 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 All pins ±500 Corner pins (1, 3, 4, and 6) ±750

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input range 1.4 5.5 V VOUT Output range 1.0 3.3 V IOUT Output current 0 300 mA VEN Enable range 0 VIN V TJ Junction temperature –40 150 °C TA Ambient temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TLV733P-Q1 UNITDRV (WSON) DBV (SOT-23)

6 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 92.5 198.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 123.9 118.4 °C/W RθJB Junction-to-board thermal resistance 61.9 65.8 °C/W ψJT Junction-to-top characterization parameter 9.7 42.4 °C/W ψJB Junction-to-board characterization parameter 62.3 65.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 30.9 n/a °C/W

www.ti.com SBVS283D – AUGUST 2016–REVISED DECEMBER 2018 Product Folder Links: TLV733P-Q1 Submit Documentation FeedbackCopyright © 2016–2018, Texas Instruments Incorporated (1) Dropout voltage for the TLV73310P is not valid at room temperature. The device engages undervoltage lockout (VIN < UVLOFALL) before the dropout condition is met.

6.5 Electrical Characteristics

at operating temperature range (TJ = –40°C to +150°C, TA = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage 1.4 5.5 V DC output accuracy TJ = 25°C –1% 1% UVLO Undervoltage lockout VIN rising 1.3 1.4 V VIN falling 1.25 ΔVO(ΔVI) Line regulation ΔVI = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater) to

5.5 V 1 mV

ΔVO(ΔIO) Load regulation ΔIO = 1 mA to 300 mA 25 mV VDO Dropout voltage(1) VOUT = 0.98 × VOUT(nom), IOUT = 300 mA VOUT = 1.1 V, –40°C ≤ TJ ≤ +125°C 510 mV 1.2 V ≤ VOUT < 1.5 V, –40°C ≤ TJ ≤ 125°C 450 1.5 V ≤ VOUT < 1.8 V, –40°C ≤ TJ ≤ 125°C 400 1.8 V ≤ VOUT < 2.5 V, –40°C ≤ TJ ≤ 125°C 300 2.5 V ≤ VOUT < 3.3 V, –40°C ≤ TJ ≤ 125°C 290 VOUT = 3.3 V, –40°C ≤ TJ ≤ 125°C 125 270 VOUT = 1.1 V, –40°C ≤ TJ ≤ 150°C 560 1.2 V ≤ VOUT < 1.5 V, –40°C ≤ TJ ≤ 150°C 490 1.5 V ≤ VOUT < 1.8 V, –40°C ≤ TJ ≤ 150°C 440 1.8 V ≤ VOUT < 2.5 V, –40°C ≤ TJ ≤ 150°C 340 2.5 V ≤ VOUT < 3.3 V, –40°C ≤ TJ ≤ 150°C 330 VOUT = 3.3 V, –40°C ≤ TJ ≤ 150°C 320 IGND Ground pin current IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C 34 62 µA IOUT = 0 mA, –40°C ≤ TJ ≤ 150°C 78 ISHDN Shutdown current VEN ≤ 0.35 V, 2.0 V ≤ VIN ≤ 5.5 V, TJ = 25°C 0.1 1 µA PSRR Power-supply rejection ratio VOUT = 1.8 V, IOUT = 300 mA f = 100 Hz 68 dBf = 10 kHz 35 f = 100 kHz 28 Vn Output noise voltage BW = 10 Hz to 100 kHz, VOUT = 1.8 V, IOUT = 10 mA 120 µVRMS VEN(HI) EN pin high voltage (enabled) 0.9 0.63 V VEN(LO) EN pin low voltage (disabled) 0.52 0.35 V IEN EN pin current VEN = 5.5 V 0.01 µA Pulldown resistor VIN = 2.3 V 120 Ω ILIM Output current limit 360 mA IOS Short-circuit current limit VOUT shorted to GND, VOUT = 1.0 V 150 mA VOUT shorted to GND, VOUT = 3.3 V 170 Tsd Thermal shutdown Shutdown, temperature increasing 160 Reset, temperature decreasing 140

6.6 Timing Requirements

Time from EN assertion to 98% × VOUT(nom), VOUT = 1.0 V, IOUT = 0 mA 250 µs Time from EN assertion to 98% × VOUT(nom), VOUT = 3.3 V, IOUT = 0 mA 800

6.7 Typical Characteristics

Figure 1. 1.8-V Regulation vs VIN (Line Regulation) and Figure 2. Ground Pin Current vs IOUT and Temperature Figure 3. Ground Pin Current vs VIN Figure 4. Shutdown Current vs VIN and Temperature Figure 5. Enable Threshold vs Temperature Figure 6. Output Voltage vs 1.0-V Foldback Current Limit

SBVS283D –AUGUST 2016– REVISED DECEMBER 2018 www.ti.com Product Folder Links: TLV733P-Q1 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TLV733P-Q1 belongs to a family of low dropout (LDO) linear regulators. These devices consume low quiescent current and deliver excellent line and load transient performance. These characteristics, combined with low noise and good PSRR with low dropout voltage, make this family of devices ideal for portable consumer applications. This family of regulators offers foldback current limit, shutdown, and thermal protection. The operating junction temperature for this family of devices is –40°C to +150°C.

7.2 Functional Block Diagram

/c116= 120□·□RL 120□+□RL

• □COUT TLV733P-Q1 www.ti.com SBVS283D – AUGUST 2016–REVISED DECEMBER 2018 Product Folder Links: TLV733P-Q1 Submit Documentation FeedbackCopyright © 2016–2018, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 Undervoltage Lockout (UVLO)

The TLV733P-Q1 family uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is greater than the rising UVLO voltage. This circuit ensures that the device does not exhibit any unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry. During UVLO disable, the output is connected to ground with a 120-Ω pulldown resistor.

7.3.2 Shutdown

The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI) (0.9 V, minimum). Turn off the device by forcing the EN pin to drop below 0.35 V. If shutdown capability is not required, connect EN to IN. The TLV733P-Q1 has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel with the 120-Ω pulldown resistor. The time constant is calculated in Equation 1: (1)

7.3.3 Internal Foldback Current Limit

The TLV733P-Q1 has an internal foldback current limit that protects the regulator during fault conditions. The current allowed through the device is reduced when the output voltage falls. When the output is shorted, the LDO supplies a typical current of 150 mA. The output voltage is not regulated when the device is in current limit. In this condition, the output voltage is the product of the regulated current and the load resistance. When the device output is shorted, the PMOS pass transistor dissipates power [(VIN – VOUT) × IOS] until thermal shutdown is triggered and the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the fault condition continues, the device cycles between current limit and thermal shutdown; see the Thermal Information table for more details. The foldback current-limit circuit limits the current allowed through the device to current levels lower than the minimum current limit at a nominal VOUT current limit (ILIM) during startup. See Figure 6 to Figure 8 for typical foldback current limit values. If the output is loaded by a constant-current load during startup, or if the output voltage is negative when the device is enabled, then the load current demanded by the load can exceed the foldback current limit and the device may not rise to the full output voltage. For constant-current loads, disable the output load until the TLV733P-Q1 has fully risen to the nominal output voltage. The TLV733P-Q1 PMOS pass element has an intrinsic body diode that conducts current when the voltage at the OUT pin exceeds the voltage at the IN pin. Do not force the output voltage to exceed the input voltage because excessively high current can flow through the body diode.

7.3.4 Thermal Shutdown

Thermal shutdown protection disables the output when the junction temperature rises to approximately 160°C. Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit can cycle on and off. This cycling limits regulator dissipation, protecting the device from damage as a result of overheating. Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product of the (VIN – VOUT) voltage and the load current. For reliable operation, limit junction temperature to 150°C (maximum). To estimate the margin of safety in a complete design, increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. The TLV733P-Q1 internal protection circuitry protects against overload conditions but is not intended to be activated in normal operation. Continuously running the TLV733P-Q1 into thermal shutdown degrades device reliability.

7.4 Device Functional Modes

7.4.1 Normal Operation

• The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO falling threshold.
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased below the enable falling threshold.
• The output current is less than the current limit.
• The device junction temperature is less than the thermal shutdown temperature.

7.4.2 Dropout Operation

LDO. Line or load transients in dropout can result in large output voltage deviations.

7.4.3 Disabled

• The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold.
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold.
• The device junction temperature is greater than the thermal shutdown temperature. When the device is disabled, the active pulldown resistor discharges the output. Table 1 shows the conditions that lead to the different modes of operation.

Table 1. Device Functional Mode Comparison

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Input and Output Capacitor Selection

and equivalent series resistance (ESR) over temperature. output capacitance is 100 µF. Figure 21. Output Voltage Deviation vs Load Step Slew Rate

SBVS283D –AUGUST 2016– REVISED DECEMBER 2018 www.ti.com Product Folder Links: TLV733P-Q1 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Application Information (continued)

8.1.2 Dropout Voltage

The TLV733P-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade when (VIN – VOUT) approaches dropout operation.

8.2 Typical Applications

8.2.1 DC-DC Converter Post Regulation

Figure 22. DC-DC Converter Post Regulation

8.2.1.1 Design Requirements

Table 2. Design Parameters

8.2.1.2 Design Considerations

values of 1 µF are selected to give the maximum output capacitance in a small, low-cost package.

8.2.1.3 Application Curve

Figure 23 shows the TLV733P-Q1 startup, regulation, and shutdown as specified in Figure 22. Figure 23. 1.8-V to 1.5-V Regulation at 300 mA

8.2.2 Capacitor-Free Operation from a Battery Input Supply

Figure 24. Capacitor-Free Operation from a Battery Input Supply

8.2.2.1 Design Requirements

Table 3. Design Parameters

8.2.2.2 Design Considerations

required for this design because of the direct low impedance connection to the battery. 200-mA maximum input current is not exceeded.

8.2.2.3 Application Curve

Figure 25 shows no inrush with the capacitor-free startup. Figure 25. No Inrush Startup, 3.0-V to 1.0-V Regulation

9 Power Supply Recommendations

load transient events. If inductive impedances are unavoidable, use an input capacitor.

10 Layout

10.1 Layout Guidelines

• Place input and output capacitors as close to the device as possible.
• Use copper planes for device connections, in order to optimize thermal performance.
• Place thermal vias around the device to distribute the heat. Figure 26 shows an example of how the TLV733P-Q1 is laid out on a printed circuit board (PCB).

10.2 Layout Examples

Figure 26. WSON Layout Example Figure 27. SOT-23 Layout Example

device product folder on www.ti.com. (2) Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Evaluation Module

Instruments website through the product folders or purchased directly from the TI eStore.

11.1.2 Device Nomenclature

Table 4. Device Nomenclature(1)(2) in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). discharge the output when the device is disabled. yyy is the package designator. z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).

11.2 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

www.ti.com SBVS283D – AUGUST 2016–REVISED DECEMBER 2018 Product Folder Links: TLV733P-Q1 Submit Documentation FeedbackCopyright © 2016–2018, Texas Instruments Incorporated

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 12-Dec-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTLV73310PQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV73311PQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV73312PQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV73315PQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV73318PQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV73325PQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 150 PTLV73328PQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 150 PTLV73330PQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 150 PTLV73333PQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 150 TLV73310PQDBVRQ1 PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 TLV73310PQDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 150 12P TLV73311PQDBVRQ1 PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 TLV73311PQDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 150 12Q TLV73312PQDBVRQ1 PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 TLV73312PQDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 150 12R TLV73315PQDBVRQ1 PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 TLV73315PQDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 150 12S TLV73318PQDBVRQ1 PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 TLV73318PQDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 150 12T TLV73325PQDBVRQ1 PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 TLV73325PQDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 150 12U

www.ti.com 12-Dec-2018 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLV73328PQDBVRQ1 PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 TLV73328PQDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 150 12V TLV73330PQDBVRQ1 PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 TLV73333PQDBVRQ1 PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 TLV73333PQDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 150 12W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 12-Dec-2018 Addendum-Page 3 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV733P-Q1 :

• Catalog: TLV733P NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2018 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV73310PQDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TLV73311PQDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TLV73312PQDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TLV73315PQDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TLV73318PQDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TLV73325PQDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TLV73328PQDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 TLV73333PQDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2018 Pack Materials-Page 2

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. DRV 6 WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4206925/F

www.ti.com PACKAGE OUTLINE C 6X 0.35 0.25 1.6 0.1 6X 0.3 0.2 1.3 1 0.1 4X 0.65 0.8 0.7 0.05 0.00 B 2.1 1.9 A 2.1 1.9 (0.2) TYP WSON - 0.8 mm max heightDRV0006A PLASTIC SMALL OUTLINE - NO LEAD 4222173/B 04/2018 PIN 1 INDEX AREA SEATING PLANE 0.08 C 3 4 (OPTIONAL) PIN 1 ID

0.1 C A B

0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 5.500

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

(1) 4X (0.65) (1.95) 6X (0.3) 6X (0.45) (1.6) (R0.05) TYP ( 0.2) VIA TYP (1.1) WSON - 0.8 mm max heightDRV0006A PLASTIC SMALL OUTLINE - NO LEAD 4222173/B 04/2018 SYMM 3 4 SYMM LAND PATTERN EXAMPLE SCALE:25X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 6X (0.3) 6X (0.45) 4X (0.65) (0.7) (1) (1.95) (R0.05) TYP (0.45) WSON - 0.8 mm max heightDRV0006A PLASTIC SMALL OUTLINE - NO LEAD 4222173/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD #7 88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:30X SYMM 3 4 SYMM METAL

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2018, Texas Instruments Incorporated