PTLV70933PKR

TLV709_V03 TI | Alldatasheet

Document overview

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Technical content

TLV709 150-mA, 30-V, 3.2-μA Quiescent Current, Low-Dropout Linear Regulator

1 Features

• Input voltage range: 2.5 V to 30 V
• Available output voltage options: – Fixed: 1.2 V to 5 V – Adjustable: 1.2 V to 28 V
• Output current: Up to 150 mA
• Very-low IQ: 3.2 μA at 150-mA load current
• Stable with output capacitor ≥ 0.47 μF
• Overcurrent protection
• Packages: – 4-pin SOT-89 (PK) (fixed configuration only) – 5-pin SOT-23 (DBV) (both fixed and adjustable configurations)
• Operating junction temperature: –40°C to +125°C

2 Applications

• Home and building automation
• Retail automation and payment
• Grid infrastructure
• Medical applications
• Lighting applications

3 Description

The TLV709 low-dropout (LDO) linear voltage regulator is a low quiescent current device that offers the benefits of a wide input voltage range and low-power operation in miniaturized packaging. The TLV709 is optimized to power microcontrollers and other low power loads for battery-powered applications. The TLV709 LDO supports a low dropout of typically 600 mV at 100 mA of load current. The low quiescent current (3.2 μA typically) does not vary across the entire range of output load current (0 mA to 150 mA). The TLV709 also features an internal soft-start to lower the inrush current during start-up. The built-in overcurrent limit protection helps protect the regulator in the event of a load short or fault condition. The TLV709 is available in a 2.90-mm × 1.60-mm, 5-pin SOT-23 (DBV) package for fixed and adjustable outputs, and in a 4.50-mm × 2.5-mm, 3-pin SOT-89 (PK) package for fixed outputs.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TLV709 DBV (SOT-23, 5) 2.9 mm × 2.8 mm PK (SOT-89, 3) 4.5 mm × 4.095 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. Output Current (mA) Ground Current ( A) 0 30 60 90 120 150 2.5 3.5 4.5 5.5 6.5 -55°C -40°C 0°C 25°C 85°C 125°C 150°C VIN = 4.3 V, VOUT = 3.3 V Quiescent Current vs Load Current TLV70933 IN OUT GND MCU Li-Ion Battery 12V 0.1µF 0.47µF CIN COUT Typical Application TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (May 2023) to Revision B (June 2023) Page Changes from Revision * (February 2023) to Revision A (May 2023) Page TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 www.ti.com

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5 Pin Configuration and Functions

Figure 5-1. DBV Package (Fixed), 5-Pin SOT-23 (Top View) IN GND NC OUT FB 3 4 Figure 5-2. DBV Package (Adjustable), 5-Pin SOT-23 (Top View) GND IN OUT IN Figure 5-3. TLV709xxPKR PK Package (IN Tab), 3-Pin SOT-89 (Top View) OUT GND IN GND Figure 5-4. TLV709AxxPKR PK Package (GND Tab), 3-Pin SOT-89 (Top View) Table 5-1. Pin Functions PIN TYPE DESCRIPTION NAME DBV (Fixed) DBV (Adj) PK (IN Tab) PK (GND Tab) GND 2 2 1 2, tab — Ground pin. IN 1 1 2, tab 3 I Input supply pin. See the Recommended Operating Conditions table and the Input and Output Capacitor Requirements section for more information. OUT 5 5 3 1 O Output of the regulator. See the Recommended Operating Conditions table and the Input and Output Capacitor Requirements section for more information. FB — 4 — — I In the adjustable configuration, this pin sets the output voltage with the help of a feedback divider. NC 3, 4 3 — — — Not internally connected. This pin can be left open or tied to ground for improved thermal performance. www.ti.com TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TLV709

6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT Voltage VIN –0.3 30 V VOUT (for fixed device only) –0.3 2 × VOUT(typ) or VIN + 0.3 or 5.5 (whichever is lower) VOUT (for adjustable device only) –0.3 VIN + 0.3 VFB –0.3 2.4 Current Peak output current Internally limited Temperature Junction, TJ –40 150 Storage, Tstg –65 150 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the ground terminal.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1) MIN NOM MAX UNIT VIN Input supply voltage 2.5 30 V VOUT Output voltage (for adjustable device only) 1.205 28 Output voltage (for fixed device only) 1.205 5.0 IOUT Output current 0 150 mA CIN Input capacitor(2) 0.47 µF COUT Output capacitor(3) 1 TJ Operating junction temperature –40 125 °C (1) All voltages are with respect to GND. (2) An input capacitor is not required for LDO stability. However, an input capacitance with an effective value of 0.1 μF minimum is recommended to counteract the effect of source resistance and inductance, which may in some cases cause symptoms of systemlevel instability such as ringing or oscillation, especially in the presence of load transients. (3) All capacitor values listed are the nominal value and the effective capacitance is assumed to derate to 50% of the nominal capacitor value. TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 www.ti.com

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6.4 Thermal Information

THERMAL METRIC(1) TLV709 (2) UNITDBV [SOT-23] PK [SOT-89]

5 PINS 4 PINS

RθJA Junction-to-ambient thermal resistance 195.7 131.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 88.2 65.8 °C/W RθJB Junction-to-board thermal resistance 40.7 32.4 °C/W ψJT Junction-to-top characterization parameter 11.2 69.8 °C/W ψJB Junction-to-board characterization parameter 40.5 96.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. (2) Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. www.ti.com TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TLV709

6.5 Electrical Characteristics

over operating junction temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 1 V, IOUT = 100 µA, and COUT = 1 μF, unless otherwise noted; typical values are at TJ = 25°C. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage (2) IO = 10 mA 2.5 30 V10 mA ≤ IO < 50 mA 3.0 30 50 mA ≤ IO ≤ 150 mA 3.5 30 VOUT Output voltage range (TLV70901) 1.205 28 V VFB Internal reference(2) 1.12 1.205 1.24 VOUT (5) Output voltage accuracy (1) (2) (3) Over VIN, IOUT, and temp VOUT + 1.0 V ≤ VIN ≤ 30 V 100 µA ≤ IOUT ≤ 150 mA –4 4 Over VIN, temp and IOUT = 10 mA VOUT + 1.0 V ≤ VIN ≤ 30 V IOUT = 10 mA -4 4 Over VIN , IOUT, and TJ = 25℃ VOUT + 1 V ≤ VIN ≤ 30 V 100 µA ≤ IOUT ≤ 150 mA and TJ = 25℃ –2 2 IGND Ground pin current (1) (4) IOUT = 0 mA 3.2 μA 100 µA ≤ IOUT ≤ 150 mA , TJ = –40°C to 85°C 3.2 4.2 100 µA ≤ IOUT ≤ 150 mA 3.2 4.8 100 µA ≤ IOUT ≤ 150 mA , VIN = 30 V 10 ΔVOUT (ΔIOUT) Load regulation (1) VOUT ≥ 3.3 V, 100 µA < IOUT < 10 mA 1 %/AVOUT ≥ 3.3 V, 100 µA < IOUT < 50 mA 1 VOUT ≥ 3.3 V, 100 µA < IOUT < 150 mA 1 2.5 ΔVOUT (ΔVIN) Line regulation (1) VOUT(NOM) + 1 V ≤ VIN ≤ 30 V 0.02 0.05 %/V Vn Output noise voltage BW = 10 Hz to 100 kHz, COUT = 10 μF IOUT = 1 mA 487 μVrms IOUT = 50 mA 577 ICL Output current limit VOUT = 0 V, VIN ≥ 3.5 V 160 1000 mA VOUT = 0 V, VIN < 3.5 V 90 1000 mA PSRR Power-supply ripple rejection f = 100 kHz, COUT = 10 μF 60 dB VDO Dropout voltage VIN = VOUT(nom) – 0.1 V, IOUT = 10 mA 75 150 mVVIN = VOUT(nom) – 0.1 V, IOUT = 50 mA 400 VIN = VOUT(nom) – 0.1 V, IOUT = 150 mA 1000 1600 (1) TLV709 is stable and fuctional over the entire load current range from 0 mA to ICL. (2) Minimum VIN = VOUT + 1 V or the value shown for Input voltage in this table, whichever is greater. (3) For adjustable device, output accuracy excludes the tolerance and mismatch associated with external resistors used for setting up the output voltage. (4) See Leakage null control circuit . The TLV709 family employs a leakage null control circuit. This circuit is active only if output current is less than pass FET leakage current. The circuit is typically active when output load is less than 5 μA, VIN is greater than 18 V, and die temperature is greater than 100°C. (5) Minimum VIN used for IOUT = 150 mA is VOUT + 1.6 V. TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 www.ti.com

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6.6 Typical Characteristics

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), VOUT(typ) = 3.3 V, IOUT = 1 mA, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted) Input Voltage (V) Output Voltage (V) 4 8 12 16 20 24 3.26 3.27 3.28 3.29 3.3 3.31 3.32 3.33 3.34 -55°C -40°C 0°C 25°C 85°C 125°C 150°C VOUT = 3.3 V, IOUT = 5 mA Figure 6-1. Line Regulation Output Current (mA) Output Voltage (V) 0 30 60 90 3.26 3.28 3.3 3.32 3.34 -55°C -40°C 0°C 25°C 85°C 125°C 150°C VIN = 4.3 V, VOUT = 3.3 V, 0 mA ≤ IOUT ≤ 100 mA Figure 6-2. Load Regulation Output Current (mA) Output Voltage (V) 0 30 60 90 120 150 3.1 3.2 3.3 3.4 3.5 3.6 -55°C -40°C 0°C 25°C 85°C 125°C 150°C VIN = 4.3 V, VOUT = 3.3 V, 0 mA ≤ IOUT ≤ 150 mA Figure 6-3. Load Regulation Junction Temperature (  C) Output Voltage (V) -55 -25 5 35 65 95 125 150 3.28 3.29 3.3 3.31 3.32 1mA 80mA VIN = 4.3 V, VOUT = 3.3 V Figure 6-4. VOUT vs Temperature and IOUT Input Voltage (V) Dropout Voltage ( mV) 100 120 -55°C -40°C 0°C 25°C 85°C 125°C 150°C VOUT = 3.3 V, IOUT = 10 mA Figure 6-5. VDO vs VIN Output Current (mA) Dropout Voltage (mV) 0 30 60 90 120 150 300 600 900 1200 1500 1800 2100 -55°C -40°C 0°C 25°C 85°C 125°C 150°C VOUT = 3.3 V Figure 6-6. VDO vs IOUT www.ti.com TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TLV709

6.6 Typical Characteristics (continued)

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), VOUT(typ) = 3.3 V, IOUT = 1 mA, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted) Junction Temperature ( C) Ground Current ( A) -55 -25 5 35 65 95 125 150 2.5 3.5 4.5 VIN = 4.3 V, VOUT = 3.3 V, IOUT = 0 mA, COUT = 1 μF Figure 6-7. Ground Current vs Temperature Input Voltage (V) Ground Current (  A) 3 6 9 12 15 18 21 24 0.5 1.5 2.5 3.5 4.5 V OUT = 3.3V -55°C -40°C 0°C 25°C 85°C 125°C 150°C VOUT = 3.3 V, IOUT = 0 mA, COUT = 1 μF Figure 6-8. Ground Current vs VIN Output Current (mA) Ground Current ( A) 0 30 60 90 120 150 2.5 3.5 4.5 5.5 6.5 -55°C -40°C 0°C 25°C 85°C 125°C 150°C VIN = 4.3 V, VOUT = 3.3 V, COUT = 1 μF Figure 6-9. Ground Current vs IOUT Temperature (  C) Current Limit (mA) -55 -25 5 35 65 95 125 150 100 150 200 250 300 VIN = 4.8 V, VOUT = 3.3 V Figure 6-10. ICL vs Temperature f - Frequency (Hz) PSRR - Power Supply Ripple Rejection - dB 1x10 1 1x10 2 1x10 3 1x10 4 1x10 5 1x10 6 1x10 7 100 1mA 50mA VIN = 4.3 V, VOUT = 3.3 V, COUT = 10 μF Figure 6-11. PSRR vs Frequency f - Frequency - Hz Output Spectral Noise Density -  V/  Hz 1x10 1x10 1x10 1x10 1x10 1x10 1x10 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 2020 Integrated Noise from 10Hz to 100KHz 1mA : 487  V RMS 50mA : 577  V RMS 1mA 50mA VIN = 4.3 V, VOUT = 3.3 V, COUT = 10 μF Figure 6-12. Output Noise (VN) vs Frequency TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 www.ti.com

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at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), VOUT(typ) = 3.3 V, IOUT = 1 mA, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted) t - Time - ms VOUT - Output Voltage - V V IN - Input Voltage - V 0 2 4 6 8 10 12 14 16 18 20 22 V OUT V IN VIN = 4.3 V, VOUT = 3.3 V, COUT = 10 μF, IOUT = 50 mA Figure 6-13. Power-Up, Power-Down With VIN Ramp t - Time -  s VIN - Input Voltage - V AC Coupled Output Voltage -mV 0 50 100 150 200 250 300 350 400 4 -300 4.5 -250 5 -200 5.5 -150 6 -100 6.5 -50 7 0 7.5 50 8 100 8.5 150 V IN  V OUT VOUT = 3.3 V, COUT = 10 µF, ramp rate = 0.2 V/µs Figure 6-14. VIN Line Transient Response (4.3 V to 5.3 V) t - Time -  s I OUT - Output Current - mA AC Coupled Output Voltage - mV 0 300 600 900 1200 1500 1800 2100 2400 2700 3000 0 -1000 20 -800 40 -600 60 -400 80 -200 100 0 120 200 140 400 160 600 V IN = 4.3 V V OUT = 3.3 V C OUT = 10  F dI/dt = 0.5 A/  s I OUT  V OUT VIN = 4.3 V, VOUT = 3.3 V, COUT = 10 µF, ramp rate = 0.5 A/µs Figure 6-15. IOUT Transient From 1 mA to 50 mA Time ( s) Output Current (mA) AC Coupled Output Voltage - mV 600 1000 1400 1800 2200 2600 3000 3400 0 -1000 50 -800 100 -600 150 -400 200 -200 250 0 300 200 350 400 400 600 IOUT VOUT VIN = 4.3 V, VOUT = 3.3 V, COUT = 10 µF ramp rate = 0.5 A/µs Figure 6-16. IOUT Transient From 1 mA to 80 mA t - Time -  s V IN - Input Voltage - V V OUT - Output Voltage - V 0 2000 4000 6000 8000 10000 0 -1 5 0 10 1 15 2 20 3 25 4 30 5 VIN COUT = 10  F dV/dt = 1.15V/  s V OUT (1mA) V OUT (50mA) VOUT = 5 V, COUT = 10 µF, ramp rate = 1.15 V/µs Figure 6-17. Dropout Exit Line Transient (2.5 V to 14 V for VOUT = 5 V) t - Time - ms V IN - Inout Voltage - V V OUT - Output Voltage - V 0 0.5 1 1.5 2 2.5 3 3.5 4 0 1 5 2 10 3 15 4 20 5 25 6 30 7 I OUT = 50mA C OUT = 10  F dV/dt = 0.66V/  s V IN V OUT VOUT = 5 V, COUT = 10 µF, ramp rate = 0.66 V/µs Figure 6-18. VIN Line Transient (5 V to 14 V for VOUT = 5 V) www.ti.com TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLV709

7 Detailed Description

7.1 Overview

The TLV709 low-dropout regulator (LDO) consumes only 3.2 μA (typ) of quiescent current across the entire output current range, while offering a wide input voltage range and low-dropout voltage in small packaging. The device, which operates over an input range of 2.5 V to 30 V, is stable with any output capacitor greater than or equal to 1 μF. The low quiescent current across the complete load current range makes the TLV709 a great choice for powering battery-operated applications. The TLV709 has an internal soft-start to control inrush current into the output capacitor. This LDO also has overcurrent protection during a load-short or fault condition on the output.

7.2 Functional Block Diagrams

VREF = 1.205 V GND R1R2 GND V(IN) V(OUT) FBGND Figure 7-1. Functional Block Diagram: Adjustable Version Bandgap Reference Current Sense Leakage Null Control Circuit GND ILIM VREF = 1.205 V GND R1R2 GND V(IN) V(OUT) GND Figure 7-2. Functional Block Diagram: Fixed Version TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 www.ti.com

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7.3 Feature Description

7.3.1 Wide Supply Range

This device has an operational input supply range of 2.5 V to 30 V, allowing for a wide range of applications. This wide supply range is designed for applications that have either large transients or high DC voltage supplies.

7.3.2 Low Quiescent Current

This device only requires 3.2 μA (typical) of quiescent current across the complete load current range (0 mA to 150 mA) at room temperature and 4.8 μA (max) across the temperature range of –40°C to +125°C.

7.3.3 Dropout Voltage (VDO)

Dropout voltage (VDO) is defined as the input voltage minus the output voltage (V IN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. I RATED is the maximum I OUT listed in the Recommended Operating Conditions table. In dropout operation, the pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the value required to maintain output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source, on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device. (1)

7.3.4 Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(V IN – V OUT) × I CL]. For more information on current limits, see the Know Your Limits application note. Figure 7-3 shows a diagram of the current limit. VOUT(NOM) 0 V 0 mA VOUT ICLIRATED IOUT Brickwall Figure 7-3. Current Limit www.ti.com TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TLV709

7.3.5 Leakage Null Control Circuit

This device has a built-in leakage-null control circuit. At high temperatures, pass-transistor leakage increases and starts impacting the V OUT accuracy at no-load (I OUT = 0 mA) conditions. This leakage becomes more aggravated with higher headroom across the LDO (V IN – V OUT). The TLV709 has a built-in leakage-null control circuit that detects pass-transistor leakage and provides a ground discharge path for the leakage. This circuitry helps the TLV709 maintain much tighter V OUT accuracy across wide V IN and temperature (–40°C to +125°C ) ranges.

7.4 Device Functional Modes

Table 7-1 provides a quick comparison between the normal and dropout modes of operation. Table 7-1. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN IOUT Normal VIN > VOUT(nom) + VDO IOUT < ICL Dropout VIN < VOUT(nom) + VDO IOUT < ICL

7.4.1 Normal Operation

The device regulates to the nominal output voltage under the following conditions:

• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is greater than –40°C and less than +125°C

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, V IN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (V OUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TLV709 LDO regulator is a good choice for battery-powered applications and is a good supply for low-power microcontrollers, such as the MSP430, because of the device low IQ performance across load current range. The ultra-low-supply current of the TLV709 maximizes efficiency at light loads and the high input voltage range and flexibility of output voltage selection in adjustable configuration and fixed output levels makes the device optimal as a supply in building automation and power tools.

8.2 Typical Application

0.1μF GND 0.47μF Figure 8-1. Typical Application Circuit (Fixed-Voltage Version) TLV70901 IN OUT FBGND 0.1μF VIN R1R2 GND GND CFB GND VOUT 0.47µF Figure 8-2. TLV70901 Adjustable LDO Regulator Programming NOTE: Dotted lines indicate an optional input capacitor. See the Recommended Operating Conditions table and the Input and Output Capacitor Requirements section. Table 8-1. Adjustable Output Voltage for Resistors R1 and R2 OUTPUT VOLTAGE (V) R1 (MΩ) R2 (MΩ) 1.8 0.499 1 2.8 1.33 1 5.0 3.16 1

8.2.1 Design Requirements

Table 8-2 summarizes the design requirements for Figure 8-1. Table 8-2. Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 12 V Output voltage 3.3 V Output current 100 mA www.ti.com TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TLV709

8.2.2 Detailed Design Procedure

8.2.2.1 Setting VOUT for the TLV70901 Adjustable LDO

As illustrated in Figure 8-2 , the TLV709 contains an adjustable version (the TLV70901) that sets the output voltage using an external resistor divider. The output voltage operating range is 1.2 V to 28 V, and is calculated using: OUT REF R1V V 1 R2 /c230 /c246/c61 /c180 /c43 /c231 /c247 /c232 /c248 (2) where:

• VREF = 1.205 V (typical) Choose resistors R1 and R2 to allow approximately 1.5 μA of current through the resistor divider. Lower value resistors can be used for improved noise performance, but consume more power. Avoid higher resistor values because leakage current into or out of FB across R1 / R2 creates an offset voltage that is proportional to V OUT divided by V REF. The recommended design procedure is to choose R2 = 1 MΩ to set the divider current at 1.5 μA, and then calculate R1 using Equation 3: R 1 = V O U T V RE F − 1 × R 2 (3) Figure 8-2 depicts this configuration.

8.2.2.2 External Capacitor Requirements

The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value.

8.2.2.3 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Dynamic performance of the device is improved by using a larger output capacitor. The TLV709 requires an output capacitor of 1 μF or larger (0.47 μF or larger capacitance) for stability and an equivalent series resistance (ESR) between 0.001 Ω and 1 Ω. For best transient performance, use X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for the capacitor. Higher output voltages cause a significant derating of the capacitor. Use an output capacitor within the range specified in the Recommended Operating Conditions table for stability. TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 www.ti.com

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8.2.2.4 Reverse Current

Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the PMOS pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. These conditions are:

• If the device has a large COUT and the input supply collapses with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. Limit reverse current to 5% or less of the rated output current of the device in the event this current cannot be avoided. Figure 8-3 shows one approach for protecting the device. IN OUT GND CIN GND GND COUT GND Internal Body Diode Schottky Diode Figure 8-3. Example Circuit for Reverse Current Protection Using a Schottky Diode

8.2.2.5 Feed-Forward Capacitor (CFF)

For the adjustable-voltage version device, a feed-forward capacitor (C FF) can be connected from the OUT pin to the FB pin. C FF improves transient, noise, and PSRR performance, but is not required for regulator stability. Recommended C FF values are listed in the Recommended Operating Conditions table. A higher capacitance CFF can be used; however, the start-up time increases. For a detailed description of C FF tradeoffs, see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note. CFF and R 1 form a zero in the loop gain at frequency f Z, while C FF, R1, and R 2 form a pole in the loop gain at frequency fP. CFF zero and pole frequencies can be calculated from the following equations: CFF ≥ 10 pF is required for stability if the feedback divider current is less than 5 μA. Equation 6 calculates the feedback divider current. IFB_Divider = VOUT / (R1 + R2) (6) To avoid start-up time increases from CFF, limit the product CFF × R1 < 50 µs. For an output voltage of 1.205 V with the FB pin tied to the OUT pin, no CFF is used. www.ti.com TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TLV709

8.2.2.6 Power Dissipation (PD)

Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT (7) Note Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation, use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (T A) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (R θJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) (8) Thermal resistance (R θJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, R θJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization.

8.2.2.7 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi ( Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (T J), as described in the following equations. Use the junction-to-top characterization parameter ( ψJT) with the temperature at the center-top of device package (T T) to calculate the junction temperature. Use the junction-to-board characterization parameter ( ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD (9) where:

• PD is the dissipated power
• TT is the temperature at the center-top of the device package TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 www.ti.com

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TJ = TB + ψJB × PD (10) where:

• TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note.

8.3 Best Design Practices

Place at least one 0.47-µF capacitor as close as possible to the OUT and GND pins of the regulator. Do not connect the output capacitor to the regulator using a long, thin trace. Connect an input capacitor as close as possible to the IN and GND pins of the regulator for best performance. Do not exceed the absolute maximum ratings.

8.4 Power Supply Recommendations

The TLV709 is designed to operate from an input voltage supply range between 2.5 V and 30 V. The input voltage range provides adequate headroom in order for the device to have a regulated output. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance.

8.5 Layout

8.5.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the printed circuit board (PCB) and as near as practical to the respective LDO pin connections. Place ground return connections for the input and output capacitors as close to the GND pin as possible, using wide, component-side, copper planes. Do not use vias and long traces to create LDO circuit connections to the input capacitor, output capacitor, or the resistor divider because this practice negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage and shield the LDO from noise.

8.5.1.1 Power Dissipation

To ensure reliable operation, worst-case junction temperature must not exceed 125°C. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, P D(max), and the actual dissipation, P D, which must be less than or equal to PD(max). Equation 11 determines the maximum-power-dissipation limit: J A D(max) JA T max TP R/c113 /c45/c61 (11) where:

• TJmax is the maximum allowable junction temperature
• RθJA is the thermal resistance junction-to-ambient for the package (see the Thermal Informationtable)
• TA is the ambient temperature Equation 12 calculates the regulator dissipation: D IN OUT OUTP (V V ) I/c61 /c45 /c180 (12) www.ti.com TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TLV709

8.5.2 Layout Examples

Figure 8-4. Example Layout for the TLV70901DBV OUTPUTGND INPUT Tab 1 32 GND CIN COUT Figure 8-5. Example Layout for the TLV709xxPK (IN Tab) TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 www.ti.com

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Figure 8-6. Example Layout for the TLV709AxxPK (GND Tab) www.ti.com TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TLV709

9 Device and Documentation Support

9.1 Device Support

9.1.1 Development Support

9.1.1.1 Evaluation Module

An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV709. The TPS71533EVM evaluation module (and related user's guide) can be requested at the TI website through the product folders or purchased directly from the TI eStore.

9.1.1.2 Spice Models

Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TLV709 is available through the product folders under Tools & Software.

9.1.2 Device Nomenclature

Table 9-1. Device Nomenclature(1) PRODUCT VOUT TLV709AxxDBVz In the SOT-23 (DBV) package: XX is the nominal output voltage (for example, 33 = 3.3 V, 50 = 50 V, 01 = Adjustable). Z is the package quantity. TLV709xxPKz In the SOT-89 (PK) package with an IN tab: XX is the nominal output voltage (for example, 33 = 3.3 V, 50 = 50 V). Z is the package quantity. TLV709AxxPKz In the SOT-89 (PK) package with a GND tab: XX is the nominal output voltage (for example, 33 = 3.3 V, 50 = 50 V). Z is the package quantity. (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, TPS71533EVM LDO Regulator Evaluation Module user guide

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 www.ti.com

20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

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9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TLV709

www.ti.com 9-Jul-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTLV70933PKR ACTIVE SOT-89 PK 3 3000 TBD Call TI Call TI -40 to 125 Samples PTLV70950PKR ACTIVE SOT-89 PK 3 3000 TBD Call TI Call TI -40 to 125 Samples PTLV709A33DBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 Samples TLV709A01DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 2V8F Samples TLV709A33DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 2V6F Samples TLV709A33PKR ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 125 NT Samples TLV709A50DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 2V7F Samples TLV709A50PKR ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 125 NW Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

www.ti.com 9-Jul-2023 (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Jul-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Jul-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV709A01DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TLV709A33DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TLV709A33PKR SOT-89 PK 3 1000 190.0 190.0 30.0 TLV709A50DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TLV709A50PKR SOT-89 PK 3 1000 190.0 190.0 30.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 (0.1) (0.15) A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/G 03/2023 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/G 03/2023 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/G 03/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

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