TLV7011_V01 TI1 | Alldatasheet
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US dime (18x18x1.35 mm3) 5-Pin X2SON 5-Lead SC70 Input Overdrive (mV) Propagation Delay (Ps) 10 20 30 40 50 60 70 80 90 100 0.2 0.25 0.3 0.35 0.4 TLV7 Rising Edge Falling Edge Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLV7011, TLV7021, TLV7012, TLV7022 SLVSDM5E –SEPTEMBER 2017–REVISED NOVEMBER 2019 TLV701xandTLV702xSmall-Size,Low-Power,Low-VoltageComparators
1 Features
1• Ultra-small package: X2SON (0.8 × 0.8 mm2)
- Standard packages: SOT23, SC70, VSSOP
- Wide supply voltage range of 1.6 V to 6.5 V
- Quiescent supply current of 5 µA
- Low propagation delay of 260 ns
- Rail-to-rail common-mode input voltage
- Internal hysteresis
- Push-pull and open-drain output options
- No phase reversal for over driven inputs
- –40°C to 125°C Operating ambient temperature
2 Applications
- Mobile phones and tablets
- Portable and battery-powered devices
- IR receivers
- Level translators
- Threshold detectors and discriminators
- Window comparators
- Zero-crossing detectors
3 Description
The TLV7011/7021 (single-channel) and TLV7012/7022 (dual-channel) are micro-power comparators that feature low-voltage operation with rail-to-rail input capability. These comparators are available in an ultra-small, leadless package measuring 0.8 mm × 0.8 mm and standard leaded packages, making them applicable for space-critical designs like smartphones and other portable or battery-powered applications. The TLV701x and TLV702x offer an excellent speed- to-power combination with a propagation delay of 260 ns and a quiescent supply current of 5 μA. This combination of fast response time at micropower enables power conscious systems to monitor and respond quickly to fault conditions. With an operating voltage range of 1.6 V to 6.5 V, these comparators are compatible with 3-V and 5-V systems. These comparators also feature no output phase inversion with overdriven inputs and internal hysteresis. These features make this family of comparators well suited for precision voltage monitoring in harsh, noisy environments where slow- moving input signals must be converted into clean digital outputs. The TLV701x have push-pull output stages capable of sinking and sourcing milliamps of current when controlling an LED or driving a capacitive load. The TLV702x have open-drain output stages that can be pulled beyond VCC, making it appropriate for level translators and bipolar to single-ended converters. Device Information(1) PART NUMBERS PACKAGE (PINS) BODY SIZE (NOM) TLV7011, TLV7021 X2SON (5) 0.80 mm × 0.80 mm SC70 (5) 2.00 mm × 1.25 mm SOT-23 (5) 2.90 mm × 1.60 mm TLV7012, TLV7022 VSSOP (8) 3 mm × 3 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. TLV70x1 Family of Low Power Comparators PART NUMBERS OUTPUT IQ (TYP) tPD (TYP) TLV701x Push-pull 5 µA 260 ns TLV702x Open-drain 5 µA 260 ns TLV703x Push-pull 335 nA 3 µs TLV704x Open-drain 335 nA 3 µs TA = 25°C, VCC = 5 V, CL = 15 pF
TLV7011, TLV7021, TLV7012, TLV7022 SLVSDM5E –SEPTEMBER 2017–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: TLV7011 TLV7021 TLV7012 TLV7022 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated Table of Contents
11.3 Receiving Notification of Documentation Updates 26
12 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Revision D (February 2019) to Revision E Page Changes from Revision C (March 2018) to Revision D Page Changes from Revision B (November 2017) to Revision C Page Changes from Revision A (July 2017) to Revision B Page
4 IN ±
5 IN+
TLV7011, TLV7021, TLV7012, TLV7022 www.ti.com SLVSDM5E –SEPTEMBER 2017–REVISED NOVEMBER 2019 Product Folder Links: TLV7011 TLV7021 TLV7012 TLV7022 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated (1) I = Input, O = Output, P = Power Changes from Original (May 2017) to Revision A Page
5 Pin Configuration and Functions
I/O/P(1) DESCRIPTION NAME X2SON SOT-23, SC70 OUT 1 1 O Output VCC 2 5 P Positive (highest) power supply VEE 3 2 P Negative (lowest) power supply IN– 4 4 I Inverting input IN+ 5 3 I Noninverting input
TLV7011, TLV7021, TLV7012, TLV7022 SLVSDM5E –SEPTEMBER 2017–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: TLV7011 TLV7021 TLV7012 TLV7022 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated TLV7012/22 DGK Packages 8-Pin VSSOP Top View Pin Functions: TLV7012/22 PIN I/O DESCRIPTION NAME NO. INA– 2 I Inverting input, channel A INA+ 3 I Noninverting input, channel A INB– 6 I Inverting input, channel B INB+ 5 I Noninverting input, channel B OUTA 1 O Output, channel A OUTB 7 O Output, channel B VEE 4 — Negative (lowest) supply or ground (for single-supply operation) VCC 8 — Positive (highest) supply
TLV7011, TLV7021, TLV7012, TLV7022 www.ti.com SLVSDM5E –SEPTEMBER 2017–REVISED NOVEMBER 2019 Product Folder Links: TLV7011 TLV7021 TLV7012 TLV7022 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input terminals are diode-clamped to VEE. Input signals that can swing 0.3V below VEE must be current-limited to 10mA or less. (3) Output maximum is (VCC + 0.3V) or 6V, whichever is less. (4) Short-circuit to ground, one comparator per package.
6 Specifications
6.1 Absolute Maximum Ratings (Single)
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage (VS = VCC – VEE) 6 V Input pins (IN+, IN–)(2) VEE – 0.3 6 V Current into Input pins (IN+, IN–)(2) ±10 mA Output (OUT) TLV7011/7012(3) VEE – 0.3 VCC + 0.3 V TLV7021/7022 VEE – 0.3 6 Output short-circuit duration(4) 10 s Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input terminals are diode-clamped to VEE. Input signals that can swing 0.3V below VEE must be current-limited to 10mA or less (3) Output maximum is (VCC + 0.3 V) or 7 V, whichever is less. (4) Short-circuit to ground, one comparator per package.
6.2 Absolute Maximum Ratings (Dual)
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage VS = VCC - VEE –0.3 7 V Input pins (IN+, IN-)(2) VEE – 0.3 7 V Current into Input pins (IN+, IN-) ±10 mA Output (OUT) (TLV7012)(3) VEE – 0.3 VCC + 0.3 V Output (OUT) (TLV7022) VEE – 0.3 7 V Output short-circuit duration(4) 10 s Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
6.4 Recommended Operating Conditions (Single)
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage (VS = VCC – VEE) 1.6 5.5 V Input Voltage Range VEE – 0.1 VCC + 0.2 V Ambient temperature, TA –40 125 °C
TLV7011, TLV7021, TLV7012, TLV7022 SLVSDM5E –SEPTEMBER 2017–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: TLV7011 TLV7021 TLV7012 TLV7022 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated
6.5 Recommended Operating Conditions (Dual)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply voltage VS = VCC – VEE 1.6 6.5 V Input voltage range VCC – 0.1 VEE + 0.2 V Ambient temperature, TA –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.6 Thermal Information (Single)
THERMAL METRIC(1) TLV7011/TLV7021 UNITDPW (X2SON) DBV (SOT23) DCK (SC70)
5 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 497.5 306.3 278.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 275.5 228.4 188.6 °C/W RθJB Junction-to-board thermal resistance 372.2 166.5 113.2 °C/W ΨJT Junction-to-top characterization parameter 55.5 138.5 82.3 °C/W ΨJB Junction-to-board characterization parameter 370.3 165.3 112.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 165.1 N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.7 Thermal Information (Dual)
THERMAL METRIC(1) TLV7012/TLV7022 UNITDGK (VSSOP)
8 PINS
RθJA Junction-to-ambient thermal resistance 211.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 96.1 °C/W RθJB Junction-to-board thermal resistance 133.5 °C/W ΨJT Junction-to-top characterization parameter 28.3 °C/W ΨJB Junction-to-board characterization parameter 131.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
TLV7011, TLV7021, TLV7012, TLV7022 www.ti.com SLVSDM5E –SEPTEMBER 2017–REVISED NOVEMBER 2019 Product Folder Links: TLV7011 TLV7021 TLV7012 TLV7022 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated
6.8 Electrical Characteristics (Single)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted). Typical values are at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input offset voltage VS = 1.8 V and 5 V, VCM = VS / 2 ±0.5 ±8 mV VHYS Hysteresis VS = 1.8 V and 5 V, VCM = VS / 2 1.2 4.2 14 mV VCM Common-mode voltage range VS = 2.5 V to 5 V VEE VCC + 0.1 V VS = 1.8 V to 2.5 V VEE + 0.1 VCC + 0.1 IB Input bias current 5 pA IOS Input offset current 1 pA VOH Output voltage high (for TLV7011 only) VS = 5 V, IO = 3 mA 4.7 4.8 V VOL Output voltage low VS = 5 V, IO = 3 mA 120 220 mV ILKG Open-drain output leakage current (TLV7021 only) VS = 5 V, VID = +0.1 V (output high), VPULLUP = VCC 100 pA CMRR Common-mode rejection ratio VEE < VCM < VCC, VS = 5 V 78 dB PSRR Power supply rejection ratio VS = 1.8 V to 5 V, VCM = VS / 2 78 dB ISC Short-circuit current VS = 5 V, sourcing 65 mA VS = 5 V, sinking 44 ICC Supply current VS = 1.8 V, no load, VID = –0.1 V (Output Low) 5 10 µA (1) During power on, VS must exceed 1.6 V for tON before the output tracks the input.
6.9 Switching Characteristics (Single)
Typical values are at TA = 25°C, VCC = 5 V, VCM = 2.5 V; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPHL Propagation delay time, high-to-low (RP = 2.5 kΩ TLV7021 only) Midpoint of input to midpoint of output, VOD = 100 mV 260 ns tPLH Propagation delay time, low-to-high (RP = 2.5 kΩ TLV7021 only) Midpoint of input to midpoint of output, VOD = 100 mV 310 ns tR Rise time (for TLV7011 only) 20% to 80% 5 ns tF Fall time 80% to 20% 5 ns tON Power-up time (1) 20 µs
6.10 Electrical Characteristics (Dual)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted). Typical values are at TA = 25°C.
6.11 Switching Characteristics (Dual)
Typical values are at TA = 25°C, VS = 5 V, VCM = VS / 2; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
6.12 Timing Diagrams
Figure 1. Start-Up Time Timing Diagram (IN+ > IN–)
Figure 2. Propagation Delay Timing Diagram
6.13 Typical Characteristics
Figure 3. TLV7011 Propagation Delay (L-H) vs. Input Figure 4. Propagation Delay (H-L) vs. Input Overdrive Figure 5. TLV7011 Propagation Delay (L-H) vs. Input Figure 6. Propagation Delay (H-L) vs. Input Overdrive Figure 7. TLV7021 Propagation Delay (L-H) vs. Input Figure 8. Hysteresis vs. Temperature
Copyright © 2017, Texas Instruments Incorporated TLV7011, TLV7021, TLV7012, TLV7022 SLVSDM5E –SEPTEMBER 2017–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: TLV7011 TLV7021 TLV7012 TLV7022 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The TLV701x and TLV702x devices are single-channel, micro-power comparators with push-pull and open-drain outputs. Operating down to 1.6 V and consuming only 5 µA, the TLV701x and TLV702x are ideally suited for portable and industrial applications. The comparators are available in leadless and leaded packages to offer significant board space saving in space-challenged designs.
7.2 Functional Block Diagram
7.3 Feature Description
The TLV701x (push-pull) and TLV702x (open-drain) devices are micro-power comparators that are capable of operating at low voltages. The TLV701x and TLV702x feature a rail-to-rail input stage capable of operating up to 100 mV beyond the VCC power supply rail. The comparators also feature a push-pull and open-drain output stage with internal hysteresis.
7.4 Device Functional Modes
The TLV701x and TLV702x have a Power-on-Reset (POR) circuit. While the power supply (VS) is ramping up or ramping down, the POR circuitry will be activated. For the TLV701x, the POR circuit will hold the output low (at VEE) while activated. For the TLV702x, the POR circuit will keep the output high impedance (logical high) while activated. When the supply voltage is greater than, or equal to, the minimum supply voltage, the comparator output reflects the state of the differential input (VID).
7.4.1 Inputs
The TLV701x and TLV702x input common-mode extends from VEE to 100 mV above VCC. The differential input voltage (VID) can be any voltage within these limits. No phase-inversion of the comparator output will occur when the input pins exceed VCC and VEE.
maintaining the same high input impedance when VCC is unpowered or within the recommended operating range. higher voltage is applied to the input. exponentially. Input bias current typically doubles for 10°C temperature increases.
7.4.2 Internal Hysteresis
- VTH is the actual set voltage or threshold trip voltage.
- VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip point at which the comparator must respond to change output states.
- VHYST is the internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise (4.2 mV for the TLV7011).
Figure 37. Hysteresis Transfer Curve
7.4.3 Output
external source independent of the supply voltage.
1 M/c87R2
1 M/c87
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
and portable, handheld designs.
8.1.1 Inverting Comparator With Hysteresis for TLV701x
|| R3 in series with R2. Equation 1 defines the high-to-low trip voltage (VA1). Equation 3 defines the total hysteresis provided by the network. Figure 38. TLV701x in an Inverting Configuration With Hysteresis
8.1.2 Noninverting Comparator With Hysteresis for TLV701x
to high, VIN must rise to VIN1. Use Equation 4 to calculate VIN1. such that VA is equal to VREF. Use Equation 5 to calculate VIN2. The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in Equation 6. Figure 39. TLV701x in a Noninverting Configuration With Hysteresis
8.2 Typical Applications
8.2.1 Window Comparator
simple window comparator circuit. Figure 40. Window Comparator
8.2.1.1 Design Requirements
- Alert (logic low output) when an input signal is less than 1.1 V
- Alert (logic low output) when an input signal is greater than 2.2 V
- Alert signal is active low
- Operate from a 3.3-V power supply
8.2.1.2 Detailed Design Procedure
the sensor is in the range of 1.1 V to 2.2 V.
8.2.1.3 Application Curve
Figure 41. Window Comparator Results
8.2.2 IR Receiver Analog Front End
Figure 42. IR Receiver Analog Front End Using TLV7011
8.2.2.1 Design Requirements
- Use a proper resistor (R1) value to generate an adequate signal amplitude applied to the inverting input of the comparator.
- The low input bias current IB (2 pA typical) ensures that a greater value of R1 to be used.
- The RC constant value (R2 and C1) must support the targeted data rate (that is, 9,600 bauds) to maintain a valid tripping threshold.
- The hysteresis introduced with R3 and R4 helps to avoid spurious output toggles.
8.2.2.2 Detailed Design Procedure
To reduce the current drain from the coin cell battery, data transmission must be short and infrequent.
8.2.2.3 Application Curve
Figure 43. IR Receiver AFE Waveforms
8.2.3 Square-Wave Oscillator
Square-wave oscillator can be used as low cost timing reference or system supervisory clock source. Figure 44. Square-Wave Oscillator
8.2.3.1 Design Requirements
which may help to reduce BOM cost and board space.
8.2.3.2 Detailed Design Procedure
Figure 45. Square-Wave Oscillator Timing Thresholds equal to the noninverting input. The value of VA at the point is calculated by Equation 7.
8.2.3.3 Application Curve
- R1 = R2 = R3 = R4 = 100 kΩ
- C1 = 100 pF, CL = 20 pF
- V+ = 5 V, V– = GND
- Cstray (not shown) from VA TO GND = 10 pF
Figure 46. Square-Wave Oscillator Output Waveform
9 Power Supply Recommendations
that the logic low level of the comparator output is referenced to VEE.
10 Layout
10.1 Layout Guidelines
connected to the ground trace or plane on the bottom layer. circumstance, the system would benefit from a bypass capacitor across the supply pins.
10.2 Layout Example
Figure 47. Layout Example
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
Texas Instruments website through the product folder or purchased directly from the TI eStore.
11.2 Related Links
resources, tools and software, and quick access to sample or buy. Table 1. Related Links
11.3 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
from the experts. Search existing answers or ask your own question to get the quick design help you need. not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 3-Dec-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTLV7022DGKR ACTIVE VSSOP DGK 8 2500 TBD Call TI Call TI -40 to 125 TLV7011DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 1IC2 TLV7011DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 19N TLV7011DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 19N TLV7011DPWR ACTIVE X2SON DPW 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7N TLV7021DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 1ID2 TLV7021DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 19O TLV7021DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 19O TLV7021DPWR ACTIVE X2SON DPW 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7P TLV7022DGKR PREVIEW VSSOP DGK 8 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
www.ti.com 3-Dec-2019 Addendum-Page 2 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 30-Oct-2019 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV7011DBVR SOT-23 DBV 5 3000 183.0 183.0 20.0 TLV7011DCKR SC70 DCK 5 3000 190.0 190.0 30.0 TLV7011DCKT SC70 DCK 5 250 190.0 190.0 30.0 TLV7011DPWR X2SON DPW 5 3000 205.0 200.0 33.0 TLV7021DBVR SOT-23 DBV 5 3000 183.0 183.0 20.0 TLV7021DCKR SC70 DCK 5 3000 190.0 190.0 30.0 TLV7021DCKT SC70 DCK 5 250 190.0 190.0 30.0 TLV7021DPWR X2SON DPW 5 3000 205.0 200.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 30-Oct-2019 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 0.22
0.08 TYP
0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15
0.00 TYP
5X 0.5 0.3 0.6
0.3 TYP
0 TYP
1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.
0.2 C A B
0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/E 09/2019 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4
www.ti.com PACKAGE OUTLINE C 4X 0.27 0.17 3X 0.32 0.23
0.4 MAX
0.05 0.002X 0.48 0.27 0.17 0.25 0.1 B 0.85 0.75 A 0.85 0.75 (0.1) (0.06) 4X (0.05) (0.25) 2X (0.26) X2SON - 0.4 mm max heightDPW0005A PLASTIC SMALL OUTLINE - NO LEAD 4223102/B 09/2017 PIN 1 INDEX AREA SEATING PLANE NOTE 3
0.1 C A B
0.05 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The size and shape of this feature may vary. NOTE 3 SCALE 12.000
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MIN
(0.21) TYP EXPOSED METAL CLEARANCE (0.48) (0.78) 4X (0.42) 4X (0.22) ( 0.25) 4X (0.26) 4X (0.06) ( 0.1) VIA (R0.05) TYP X2SON - 0.4 mm max heightDPW0005A PLASTIC SMALL OUTLINE - NO LEAD 4223102/B 09/2017 SYMM SYMM LAND PATTERN EXAMPLE SOLDER MASK DEFINED SCALE:60X SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK TYP NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com EXAMPLE STENCIL DESIGN (0.48) (0.78) 4X (0.42) 4X (0.22) 4X (0.26) 4X (0.06) ( 0.24) (0.21) TYP (R0.05) TYP X2SON - 0.4 mm max heightDPW0005A PLASTIC SMALL OUTLINE - NO LEAD 4223102/B 09/2017 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 92% PRINTED SOLDER COVERAGE BY AREA SCALE:100X SYMM SYMM EDGE SOLDER MASK
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