PTL103WBIDDFR

TL103W_V03 TI | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 32

Technical content

TL103Wx Dual Operational Amplifiers With Internal Reference

1 Features

New TL103WB, a pin-compatible upgrade to the TL103W and TL103WA
Improved specifications of B version amplifiers: – Supply range: 3V to 36 V – Low maximum input offset voltage: ±2mV (25°C) and ±2.5mV (full temperature) – Gain bandwidth: 1.2MHz – Total supply current: 550μA – EMI rejection: integrated RF and EMI filter – Temperature range: -40°C to 125°C
Improved specifications of B version reference: – Fixed 2.5V reference – Tight tolerance maximum of 0.44% (25°C) and 1.04% (full temperature) – Wide sink-current range: 0.2mA (typical) to 100mA

2 Applications

Battery chargers
Switch-mode power supplies
Linear voltage regulation
Data-acquisition systems
Precision constant current sink

3 Description

The TL103Wx devices combine the building blocks of a dual operational amplifier and a fixed voltage reference – both of which are often used in the control circuitry of switch-mode and linear power supplies. OP AMP1 has the non-inverting input internally tied to a fixed 2.5V reference, while OP AMP2 is independent, with both inputs uncommitted. The upgraded TL103WB features improvements such as a wider supply range (up to 36V), lower supply current (275 μA/amp) and tighter voltage regulation. This regulation can be achieved through low offset voltages for both operational amplifiers (0.3mV typical) and tight tolerances for the voltage reference (0.44% at 25°C and 1.04% over operating temperature range). The TL103WB has a widened temperature range of –40°C to 125°C. Device Information PART NUMBER CHANNEL COUNT PACKAGE(1) PACKAGE SIZE(3) TL103W TL103WA Dual + Reference D (SOIC, 8) 4.9mm × 6mm TL103WB D (SOIC, 8) 4.9mm × 6mm DDF (SOT-23, 8) (2) 2.9mm × 2.8mm (1) For more information, see Section 10. (2) This package is preview only. (3) The package size (length × width) is a nominal value and includes pins, where applicable. SMPS OP AMP2 OP AMP1 TL103WB Current Sense AC Line Opto Emulator Battery R3 R4 R5 R9Constant Voltage Control Constant Current Control 2.5 V VREF SiO2 Typical Application Circuit TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

5.5 Electrical Characteristics: OP AMP1 (VREF at

5.6 Electrical Characteristics: OP AMP2

10 Mechanical, Packaging, and Orderable

TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 www.ti.com

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TL103W TL103WA TL103WB

4 Pin Configuration and Functions

1IN– 2IN+ 2IN– 2OUT VREF OP AMP 1 + - OP AMP 2 VCC- Figure 4-1. D and DDF Packages, 8-Pin SOIC and SOT-23-THN (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. 1OUT 1 O Opamp 1 output 1IN– 2 I Opamp 1 inverting input 1IN+ 3 I Opamp 1 non-inverting input and Shunt reference cathode terminal VCC– 4 I Negative Supply Voltage 2IN+ 5 I Opamp 2 non-inverting input 2IN– 6 I Opamp 2 inverting input 2OUT 7 O Opamp 2 output VCC+ 8 I Positive Supply Voltage (1) I = input, O = output www.ti.com TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TL103W TL103WA TL103WB

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC± Supply voltage TL103W/TL103WA 0 36 V TL103WB 0 40 VID Operational amplifier input differential voltage 36 V VI Operational amplifier input voltage range(2) (VCC-) - 0.3 VCC+ V IKA Voltage reference cathode current 100 mA TJ Maximum junction temperature 150 °C Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Not applicable to pin 4 (1IN+)

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC± Supply voltage TL103W/TL103WA 3 32 V TL103WB 3 36 VICR Input common-mode voltage range VCC- (VCC+) - 2 V IK Cathode current TL103W/TL103WA 0.5 100 mA TL103WB 0.2 100 TA Operating free-air temperature TL103W/TL103WA –40 105 TL103WB –40 125 TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 www.ti.com

4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TL103W TL103WA TL103WB

5.4 Thermal Information

THERMAL METRIC(1) TL103Wx UNITSOIC (D) SOT-23 (DDF)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 135.4 170.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 77.3 89.7 °C/W RθJB Junction-to-board thermal resistance 78.9 87.5 °C/W ΨJT Junction-to-top characterization parameter 27.4 7.5 °C/W ΨJB Junction-to-board characterization parameter 78.1 87.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance – – °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Electrical Characteristics: OP AMP1 (VREF at Noninverting input)

VCC+ = 5V, VCC- = GND, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT AMPLIFIER VIO Input offset voltage VICM = 0V TL103W ±1 ±4 mV Full range ±5 TL103WA ±0.5 ±3.0 Full range ±5 TL103WB ±0.3 ±2 Full range ±2.5 αVIO Input offset-voltage drift TL103W/TL103WA Full range ±7 µV/°C TL103WB Full range ±2 IIB Input bias current (negative input) TL103W/TL103WA -20 nA TL103WB -15 AVD Large-signal voltage gain VCC+ = 15V, RL = 2kΩ, VICM = 0 V TL103W/TL103WA 100 V/mV TL103WB 210 PSRR Supply-voltage rejection ratio VCC+ = 5V to 30V, VICM = 0V TL103W/TL103WA 65 100 dB TL103WB 99 114 IO Output current VCC+ = 15V, VO = 2V, VID = 1V Source 20 40 mA Sink TL103W/TL103WA 10 12 TL103WB 10 24 VCC+ = 15V, VO = 0.2V, VID = -1V Sink TL103W/TL103WA 12 50 μA TL103WB 60 100 ISC Short-circuit to GND VCC+ = 15V ±40 ±68 mA VO Voltage output swing from rail VCC+ = 30V, RL = 2kΩ Positive Rail (VCC+) TL103W/TL103WA 26 27 V Full range 26 TL103WB 27.4 28.3 Full range 27.4 VCC+ = 30V, RL = 10kΩ Positive Rail (VCC+) TL103W/TL103WA 27 28 Full range 27 TL103WB 27.6 28.6 Full range 27.6 RL = 10kΩ Negative Rail (VCC-) 5 20 mV Full range 20 SR Slew rate at unity gain VCC+ = 15V, CL = 100pF, RL = 2kΩ, VI = 0.5V to 2V, unity gain TL103W/TL103WA 0.2 0.4 V/µs TL103WB 0.2 0.5 GBW Gain bandwidth product VCC+ = 30V, VI = 10mV, CL = 100pF, RL = 2kΩ, f = 100kHz TL103W/TL103WA 0.5(1) 0.9 MHz VCC+ = 36V, VI = 10mV, CL = 100pF, RL = 2kΩ, f = 100kHz TL103WB 0.7(1) 1.2 www.ti.com TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TL103W TL103WA TL103WB

5.5 Electrical Characteristics: OP AMP1 (VREF at Noninverting input) (continued)

VCC+ = 5V, VCC- = GND, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT THD Total harmonic distortion VCC+ = 30V, VO = 2VPP, CL = 100pF, RL = 2kΩ, f = 1kHz, AV = 20dB TL103W/TL103WA 0.02 VCC+ = 36V, VO = 2VPP, CL = 100pF, RL = 2kΩ, f = 1kHz, AV = 20dB TL103WB 0.005 ICC Total supply current, excluding cathode-current reference (both amplifiers) VCC+ = 5V, no load TL103W/TL103WA 0.7 1.2 mA VCC+ = 30V, no load Full range 2 VCC+ = 5V, no load TL103WB 0.55 0.77 VCC+ = 36V, no load Full range 1.35 VOLTAGE REFERENCE Vref Reference Voltage IK = 10mA TL103W 2.482 2.5 2.518 V Full Range 2.465 2.535 V TL103WA/TL103WB 2.489 2.5 2.511 V Full Range 2.474 2.526 V ΔVref Reference input voltage deviation over temperature range IK = 10mA TL103W Full Range 7 35(1) mV TL103WA/TL103WB Full Range 7 26(1) mV Imin Minimum cathode current for regulation TL103W/TL103Wx 0.5 1 mA TL103WB 0.2 1 |ZKA| Dynamic impedance IKA = 1mA to 100mA, f < 1kHz 0.45 0.8 Ω (1) Not tested in production, limits set by characterization and simulation.

5.6 Electrical Characteristics: OP AMP2 (Independent Amplifier)

VCC+ = 5V, VCC- = GND, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT VIO Input offset voltage VICM = 0V TL103W ±1 ±4 mV Full range ±5 TL103WA ±0.5 ±3.0 Full range ±5 TL103WB ±0.3 ±2 Full range ±2.5 αVIO Input offset-voltage drift TL103W/TL103WA Full range ±7 µV/°C TL103WB Full range ±2 IIO Input offset current TL103W/TL103WA ±2 ±75 nA Full range ±150 TL103WB ±0.5 ±4 Full range ±5 IIB Input bias current TL103W/TL103WA -20 -150 nA Full range -200 TL103WB -15 -35 Full range -50 AVD Large-signal voltage gain VCC+ = 15V, RL = 2kΩ, VO = 1.4V to 11.4V TL103W/TL103WA 50 100 V/mV Full range 25 100 TL103WB 77 210 Full range 45 210 PSRR Supply-voltage rejection ratio VCC+ = 5V to 30V TL103W/TL103WA 65 100 dB TL103WB 99 114 VICR Input common-mode voltage range VCC+ = 30V VCC- (VCC+) – 1.5 V Full range VCC- (VCC+) – 2 CMRR Common-mode rejection ratio VCC+ = 30V TL103W/TL103WA 70 95 dB Full range 60 TL103WB 93 104 Full range 70 TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 www.ti.com

6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TL103W TL103WA TL103WB

5.6 Electrical Characteristics: OP AMP2 (Independent Amplifier) (continued)

VCC+ = 5V, VCC- = GND, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT IO Output current VCC+ = 15V, VO = 2V, VID = 1V Source 20 40 mA Sink TL103W/TL103WA 10 12 TL103WB 10 24 VCC+ = 15V, VO = 0.2V, VID = -1V Sink TL103W/TL103WA 12 50 μA TL103WB 60 100 ISC Short-circuit to GND VCC+ = 15V ±40 ±68 mA VO Voltage output swing from rail VCC+ = 30V, RL = 2kΩ Positive Rail (VCC+) TL103W/TL103WA 26 27 V Full range 26 TL103WB 27.4 28.3 Full range 27.4 VCC+ = 30V, RL = 10kΩ Positive Rail (VCC+) TL103W/TL103WA 27 28 Full range 27 TL103WB 27.6 28.6 Full range 27.6 RL = 10kΩ Negative Rail (VCC-) 5 20 mV Full range 20 SR Slew rate at unity gain VCC+ = 15V, CL = 100pF, RL = 2kΩ, VI = 0.5V to 2V, unity gain TL103W/TL103WA 0.2 0.4 V/µs TL103WB 0.2 0.5 GBW Gain bandwidth product VCC+ = 30V, VI = 10mV, CL = 100pF, RL = 2kΩ, f = 100kHz TL103W/TL103WA 0.5(1) 0.9 MHz VCC+ = 36V, VI = 10mV, CL = 100pF, RL = 2kΩ, f = 100kHz TL103WB 0.7(1) 1.2 THD Total harmonic distortion VCC+ = 30V, VO = 2VPP, CL = 100pF, RL = 2kΩ, f = 1kHz, AV = 20dB TL103W/TL103WA 0.02 VCC+ = 36V, VO = 2VPP, CL = 100pF, RL = 2kΩ, f = 1kHz, AV = 20dB TL103WB 0.005 Vn Equivalent input noise voltage VCC+ = 30V, RS = 100 Ω, f = 1kHz TL103W/TL103WA 50 nV/√Hz VCC+ = 36V, RS = 100 Ω, f = 1kHz TL103WB 38 ICC Total supply current, excluding cathode-current reference (both amplifiers) VCC+ = 5V, no load TL103W/TL103WA 0.7 1.2 mA VCC+ = 30V, no load Full range 2 VCC+ = 5V, no load TL103WB 0.55 0.77 VCC+ = 36V, no load Full range 1.35 (1) Not tested in production, limits set by characterization and simulation. www.ti.com TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TL103W TL103WA TL103WB

5.7 Typical Characteristics: TL103WB

at TA ≅ 25°C, VCC = 36V (±18V), VCM = VCC / 2, RL = 10kΩ connected to VCC / 2 (unless otherwise noted) Input Offset Voltage (mV) Population (%) VCC = 5V, No. of devices = 34 μ = 61.4 µV, σ = 166.5 µV Figure 5-1. Offset Voltage Distribution Histogram Input Offset Voltage Drift (  V/ C) Population (%) 2.5 7.5 12.5 17.5 22.5 27.5 VCC = 5V, No. of devices = 34 μ = 1.18 µV/°C, σ = 0.81 µV/°C Figure 5-2. Offset Voltage Drift Distribution Histogram No. of devices = 34 Figure 5-3. Offset Voltage vs Common-Mode Temperature (°C) Input Bias Current (nA) -40 -20 0 20 40 60 80 100 120 140 -24 -22 -20 -18 -16 -14 -12 IB - IB + VCC = 5V Figure 5-4. Bias Current vs Temperature Temperature (°C) Quiescent Current (mA) -40 -20 0 20 40 60 80 100 120 140 0.4 0.6 0.8 1.2 V CC = 5 V V CC = 36 V Figure 5-5. Quiescent Current vs Temperature Frequency (Hz) Gain (dB) Phase ( ) -20 -30 0 0 20 30 40 60 60 90 80 120 100 150 100 1k 10k 100k 1M Gain, V CC = 36 V Phase, V CC = 36 V Gain, V CC = 5 V Phase, V CC = 5 V RL = 2kΩ Figure 5-6. Open-Loop Gain and Phase vs Frequency TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 www.ti.com

8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TL103W TL103WA TL103WB

5.7 Typical Characteristics: TL103WB (continued)

at TA ≅ 25°C, VCC = 36V (±18V), VCM = VCC / 2, RL = 10kΩ connected to VCC / 2 (unless otherwise noted) Frequency (Hz) Open-Loop Output Impedance (  ) 100 500 1000 2000 1k 10k 100k 1M 10M IOUT = 0 mA IOUT = 5 mA Figure 5-7. Open-Loop Output Impedance vs Frequency Figure 5-8. Closed-Loop Gain vs Frequency Output Current (mA) Output Voltage (V) 0 5 10 15 20 25 30 35 40 45 -21 -18 -15 -12 -40°C 25°C 125°C Figure 5-9. Output Voltage vs Output Current (Sinking) Figure 5-10. Output Voltage vs Output Current (Sourcing) Frequency (Hz) PSRR/CMRR (dB) 100 110 120 10 100 1k 10k 100k 1M 10M PSRR+ PSRR- CMRR Figure 5-11. PSRR and CMRR vs Frequency Temperature (°C) PSRR (µV/V) -40 -20 0 20 40 60 80 100 120 140 102 104 106 108 110 112 VCC = 5V to 36V Figure 5-12. Supply-Voltage Rejection Ratio vs Temperature www.ti.com TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TL103W TL103WA TL103WB

at TA ≅ 25°C, VCC = 36V (±18V), VCM = VCC / 2, RL = 10kΩ connected to VCC / 2 (unless otherwise noted) Temperature (°C) Common-Mode Rejection Ratio ( V/V) -40 -20 0 20 40 60 80 100 120 140 100 105 110 V CC = 5 V V CC = 36 V Figure 5-13. CMRR vs Temperature Frequency (Hz) Voltage Noise (nV/ Hz) 10 100 1k 10k Figure 5-14. Input Voltage Noise Spectral Density vs Frequency Frequency (Hz) Total Harmonic Distortion (dB) -110 -105 -100 -95 -90 -85 -80 -75 -70 20 100 1k 10k VCC = 30V, VOUT = 2VPP, RL = 2kΩ, CL = 100pF, AV = 20dB Figure 5-15. Total Harmonic Distortion vs Frequency Frequency (Hz) Total Harmonic Distortion + Noise (dB) -100 -95 -90 -85 -80 -75 -70 20 100 1k 10k VOUT = 2VPP, RL = 2kΩ, BW = 80kHz, AV = 0dB Figure 5-16. Total Harmonic Distortion + Noise vs Frequency Amplitude (V PP ) THD+N (dB) -100 -90 -80 -70 -60 -50 -40 -30 -20 1m 10m 100m 1 f = 1kHz, RL = 2kΩ, BW = 80kHz, AV = 0dB Figure 5-17. Total Harmonic Distortion + Noise vs Amplitude Temperature (°C) Reference Voltage (V) -40 -20 0 20 40 60 80 100 120 2.494 2.496 2.498 2.5 2.502 2.504 VCC = 5V, IK= 10 mA Figure 5-18. Reference Voltage vs Temperature TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 www.ti.com

10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TL103W TL103WA TL103WB

at TA ≅ 25°C, VCC = 36V (±18V), VCM = VCC / 2, RL = 10kΩ connected to VCC / 2 (unless otherwise noted) Cathode Voltage (V) Cathode current (mA) -1 -0.5 0 0.5 1 1.5 2 2.5 3 -100 -60 -20 100 VCC = 5V Figure 5-19. Cathode Current vs Cathode Voltage Temperature (°C) Dynamic Impedance (  ) -40 -20 0 20 40 60 80 100 120 140 0.4 0.45 0.5 0.55 0.6 VCC = 5V Figure 5-20. Reference Dynamic Impedance vs Temperature Frequency (Hz) Dynamic Impedance (  ) 0.1 100 1k 10k 100k 1M 10M VCC = 5V, IK = 10 mA Figure 5-21. Reference Dynamic Impedance vs Frequency Load Capacitance (  F) Cathode Current (mA) 1 10 100 1000 10000 Stable RegionStable Region The area under the curve represents typical conditions that can cause the device to oscillate Figure 5-22. Reference Stability vs Capacitive Load Frequency (Hz) EMIRR (dB) 1M 10M 100M 1G Figure 5-23. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency www.ti.com TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TL103W TL103WA TL103WB

6 Detailed Description

6.1 Overview

The TL103Wx features two high-voltage amplifiers and a shunt voltage reference to allow for cost-sensitive and compact battery charger CC/CV feedback circuits. The upgraded TL103WB features is designed to provide a wide supply range (up to 36V), low offset voltage (±0.3mV typical) and a 1.2MHz bandwidth. The integrated voltage reference is tied to the non-inverting pin of one of OP AMP 1 and provides a fixed 2.5V referenced to the negative supply of the device. The shunt reference of the TL103WA/TL103WB features a tight tolerance of 0.44% at 25°C. When a single supply voltage of 5V is used (or ±2.5V split supply), the TL103Wx internal reference allows for a more accurate and power-efficient mid-supply signal to be used throughout your circuit. The TL103W/ TL103WA devices are characterized for operation from -40°C to 85°C, the TL103WB devices are characterized for operation from –40°C to 125°C.

6.2 Functional Block Diagram

1IN– 2IN+ 2IN– 2OUT VREF OP AMP 1 + - OP AMP 2 VCC-

6.3 Feature Description

6.3.1 Internal Reference

The TL103Wx family features an internal shunt reference, tied to the non-inverting pin of one of the devices amplifiers. When supplied with enough voltage headroom ( ≥ 2.5V) and cathode current (0.5mA typical), the reference of the TL103Wx is forced to a fixed 2.5V. To not exceed the maximum cathode current, be sure that the reference input is current limited. Unlike many linear regulators, the reference of the TL103W is internally compensated to be stable without an output capacitor between the cathode and anode. If the reference is used to supply a load, stability criteria shown in Figure 5-22 needs to be met. Reference voltage tolerance varies based off the device grade chosen. At 25°C the TL103W features a reference tolerance of 0.72%, while the TL103WA/TL103WB both feature reference tolerances of 0.44%.

6.3.2 Input Common Mode Range

The valid common mode range is from device ground to V CC+ – 1.5V (V CC+ – 2V across temperature). Inputs may exceed V CC+ up to the absolute maximum voltage without device damage. At least one input must be in the valid input common-mode range for the output to be the correct phase. If both inputs exceed the valid range, then the output phase is undefined. If either input is more than 0.3V below V CC- then input current should be limited to 1mA and the output phase is undefined. TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 www.ti.com

12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TL103W TL103WA TL103WB

6.3.3 EMI Rejection

The TL103WB uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications (radio frequency interference - RFI) and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the TL103WB benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10MHz to 6GHz. Figure 6-1 shows the results of this testing on the TL103WB. Table 6-1 shows the EMIRR IN+ values for the TL103WB at particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational Amplifiers application report contains detailed information on the topic of EMIRR performance relating to op amps and is available for download from www.ti.com. Frequency (Hz) EMIRR (dB) 1M 10M 100M 1G Figure 6-1. EMIRR Testing Table 6-1. TL103WB EMIRR IN+ for Frequencies of Interest FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+ 400MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications 62dB 900MHz Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6GHz), GSM, aeronautical mobile, UHF applications 75dB 1.8GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2GHz) 70dB 2.4GHz 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-band (2GHz to 4GHz) 65dB 3.6GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88dB 5GHz 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4GHz to 8GHz) 71dB

6.4 Device Functional Modes

This device has one mode of operation that applies when operated within the recommended operating conditions. www.ti.com TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TL103W TL103WA TL103WB

7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Application Information

The TL103Wx family offers a cost-effective and compact device for applications requiring both an accurate DC signal and signal conditioning. These devices offer a fixed 2.5V reference, wide bandwidth (1 to 1.2 MHz) and a low total supply current (0.55 to 0.7mA).

7.2 Typical Applications

7.2.1 Isolated Flyback CC/CV Feedback

As shown in Figure 7-1 , the TL103Wx is often used alongside an opto-coupler/ opto-emulator to provide feedback to an isolated flyback. Utilizing the TL103Wx in this way allows for both an accurate and cost-optimized battery charger design that can achieve a stable CC/CV (Constant Current/Constant Voltage) charging profile. In this example, a simplified design procedure will be discussed. Additional details can be found in Designing CC-CV Feedback Circuits With the TL103WB. SMPS OP AMP2 OP AMP1 TL103WB Current Sense AC Line Opto Emulator Battery R3 R4 R5 R9Constant Voltage Control Constant Current Control 2.5 V VREF SiO2 Typical Application Circuit TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 www.ti.com

14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TL103W TL103WA TL103WB

7.2.1.1 Design Requirements

The objective is to design an accurate CC-CV feedback circuit with the requirements provided in Table 7-1. Table 7-1. Design Parameters PARAMETER VALUE Maximum Charge Current 6A Battery Voltage Range 6V to 20V

7.2.1.2 Detailed Design Procedure

To switch between CV control and CC control, diodes are utilized to achieve an OR logic function as shown in Figure 7-1. Designing the circuit in this way allows one of the amplifiers (configured in either CC or CV mode) to dominate the feedback in the design. In this design, GND refers to the negative node at the secondary side of the switch-mode power supply. The fixed 2.5V of the TL103Wx reference provides a stable DC voltage that is used to specify the CC current and CV voltage. One of the requirements of achieving this fixed value, however, is that the cathode of the reference must be supplied with a voltage of 2.5V or above.

7.2.1.2.1 Constant Current Circuit

For the constant current feedback circuit, the amplifier is configured in a low-side current sense configuration. Resistor R6 is used as the current sensing resistor to sense the current flowing between the battery and flyback converter. This is shown in Equation 1, where I BAT is the output current delivered to the battery. The voltage at the non-inverting input of the amplifier specifies the maximum current (or constant current) that is delivered to the battery. V B AT − = I B AT × R 6 (1) The reference of the TL103Wx is powered by the battery voltage. To be able to achieve a constant current, this reference needs to be provided with 2.5V or greater to provide a fixed 2.5V. The first step in designing a constant current circuit is to specify that 2.5V can be achieved at the battery's minimum voltage. The value of R5 must also be designed so that a sink-current between 0.5mA to 100 mA (for TL103W or TL103WA) is achieved across the specified range of the battery voltage. These two steps are shown below. V B AT m i n × R 4 + R 3 R 4 + R 3 + R 5 + R 6 ≥ 2.5 V (2) 0.5 mA ≤ V B AT − V RE F R 5 ≤ 100 m A (3) For this design R5 is chosen to be 2kΩ. Knowing this and the specified battery range of 6V to 20V, we can calculate that the reference sinks anywhere from 1.75mA to 10mA using Equation 2. Once a fixed 2.5V reference is achieved, we can use this accurate DC voltage to specify a constant current target on the non-inverting input of the amplifier. This can be done by calculating the voltage at the amplifier's inverting input when a constant current target is achieved. Specifying R6 to be 10m Ω along with a constant current design target of 6A, we find that this voltage to be 60 mV using Equation 1 . The voltage at the non-inverting pin of the amplifier is specified by Equation 4. V I N + = 2.5 V × R 3 R 4 + R 3 (4) Using the component values and design targets calculated so far, Equation 2 and Equation 4 can be updated to:

6 V × R 4 + R 3

R 4 + R 3 + 2 k Ω + 10 m Ω ≥ 2.5 V (5) www.ti.com TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TL103W TL103WA TL103WB

60 mV = 2.5 V × R 3 R 4 + R 3 (6) Using both Equation 5 and Equation 6, we calculate that R3 needs to be greater than around 34.28Ω. Adding additional headroom to this, we can calculate R3 = 36Ω and R4 = 1464Ω. 10 m 2 k 1464 Battery SMPS GND VBAT- VREF 2.5 V Figure 7-1. Constant Current Feedback Circuit

7.2.1.2.2 Constant Voltage Circuit

For the constant voltage feedback circuit, resistors R8 and R9 divide down the battery voltage to compare against the TL103Wx's reference. This is shown in Figure 7-2. The voltage at the inverting input of the amplifier is designed to equal 2.5V when the battery reaches its maximum specified voltage (or desired constant voltage value). This is shown in for a maximum voltage of 20V provided in Table 7-1. V B AT × R 9 R 8 + R 9 = 2.5 V (7)

20 V × R 9

R 8 + R 9 = 2.5 V (8) To mimic the constant current circuit and achieve a total impedance and 2kΩ across the battery, R8 is set to 1.96kΩ and R9 to 280Ω. 1.96 k 280 VREF2.5 V VBAT- Battery VBAT Figure 7-2. Constant Voltage Circuit TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 www.ti.com

16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TL103W TL103WA TL103WB

7.2.2 Constant Current Sink

Figure 7-3 shows the use of the TL103Wx along with a transistor to provide a constant current sink source. This type of circuit is common in LED drivers and can provide accurate performance and high bandwidth with minimal external components. Accuracy of this circuit is dominated by the reference voltage tolerance, amplifier offset voltage, and resistor tolerance. RLIM is placed to limit the shunt current of the circuit's reference to a maximum of 100mA. I SI NK = V RE F × R 2 R 1 + R 2 × R S (9) VREF 2.5 V RS ISINK RLIM VCC+ Figure 7-3. TL103Wx as Constant Current Sink

7.3 Power Supply Recommendations

Place 0.1µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section 7.4

7.4 Layout

7.4.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supply applications. – If a bypass capacitor is needed to help stabilize the reference, place this capacitor as close to the reference pin as possible.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If not possible to keep them separate, cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Section 7.4.2.
Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. www.ti.com TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TL103W TL103WA TL103WB

For applications shunting high currents through the reference, pay attention to the cathode and anode traces. Ensure the width of these traces are designed with proper current density.

7.4.2 Layout Example

Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors Use low-ESR, ceramic bypass capacitor Ground (GND) plane on another layer VREF Only needed for dual-supply operation Place close to device if needed for reference stability VMID OP AMP 1 OP AMP 2 Figure 7-4. Operational Amplifier Board Layout for Inverting Configuration RG RLIM VIN RF VCC+ VREF VCC- VMIDOP AMP 1 OP AMP 2 Figure 7-5. Operational Amplifier Schematic for Inverting Configuration TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 www.ti.com

18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TL103W TL103WA TL103WB

8 Device and Documentation Support

8.1 Documentation Support

8.1.1 Related Documentation

For related documentation, see the following:

Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
Texas Instruments, Designing CC-CV Feedback Circuits With the TL103WB

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. Bluetooth® is a registered trademark of Bluetooth SIG, Inc. All trademarks are the property of their respective owners.

8.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision P (November 2023) to Revision Q (December 2023) Page Changes from Revision O (October 2023) to Revision P (November 2023) Page

Added footnote in Electrical Characteristics tables to specify specifications which have limits set by
Updated maximum limit of total supply current for TL103WB at full temperature range from 1.6mA to www.ti.com TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TL103W TL103WA TL103WB

Updated minimum limit of large-signal voltage gain for TL103WB at full temperature range from 35V/mV to Changes from Revision N (August 2023) to Revision O (October 2023) Page
Changed maximum input offset voltage, reference tolerance, total supply current and sink-current range in
Maximum reference input voltage deviation over temperature range for TL103W was changed from 30mV to
Maximum reference input voltage deviation over temperature range for TL103WA was changed from 30mV to Changes from Revision M (October 2016) to Revision N (August 2023) Page Changes from Revision L (February 2016) to Revision M (October 2016) Page
Changed positive and negative terminals OP AMP 2 in the D Package image of Pin Configuration and Changes from Revision K (October 2010) to Revision L (February 2016) Page
Added the Device Information table, Pin Configuration and Functions, ESD Ratings, Thermal Information,

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TL103W, TL103WA, TL103WB SLOS437Q – APRIL 2004 – REVISED DECEMBER 2023 www.ti.com

Product Folder Links: TL103W TL103WA TL103WB

www.ti.com 1-Mar-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTL103WBIDDFR ACTIVE SOT-23-THIN DDF 8 3000 TBD Call TI Call TI -40 to 125 Samples TL103WAID LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 Z103WA TL103WAIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 Z103WA Samples TL103WBIDR ACTIVE SOIC D 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TL103D Samples TL103WID LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 Z103W TL103WIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 Z103W Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

www.ti.com 1-Mar-2024 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Jan-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Jan-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL103WAIDR SOIC D 8 2500 340.5 338.1 20.6 TL103WBIDR SOIC D 8 3000 356.0 356.0 35.0 TL103WIDR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Jan-2024 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TL103WAID D SOIC 8 75 507 8 3940 4.32 TL103WID D SOIC 8 75 507 8 3940 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 2.95

2.65 TYP

1.1 MAX

6X 0.65 8X 0.38 0.22 1.95 0.20

0.08 TYP

0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 A 2.95 2.85 NOTE 3 B 1.65 1.55 4222047/C 10/2022 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT (2.6) 8X (1.05) 8X (0.45) 6X (0.65) (R0.05) TYP 4222047/C 10/2022 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R0.05) TYP 4222047/C 10/2022 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2024, Texas Instruments Incorporated

Summary

TL103Wx Dual Operational Amplifiers With Internal Reference DECEMBER 2023

Description

TL103Wx Dual Operational Amplifiers With Internal Reference DECEMBER 2023

Source title PTL103WBIDDFR Datasheet(PDF) - Texas Instruments

Read PTL103WBIDDFR online.

TL103W_V03 TI | Alldatasheet

Document overview

Technical content

1 Features

2 Applications

3 Description

5.5 Electrical Characteristics: OP AMP1 (VREF at

5.6 Electrical Characteristics: OP AMP2

10 Mechanical, Packaging, and Orderable

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

4 Pin Configuration and Functions

5 Specifications

5.1 Absolute Maximum Ratings

5.2 ESD Ratings

5.3 Recommended Operating Conditions

4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

5.4 Thermal Information

8 PINS 8 PINS

5.5 Electrical Characteristics: OP AMP1 (VREF at Noninverting input)

5.5 Electrical Characteristics: OP AMP1 (VREF at Noninverting input) (continued)

5.6 Electrical Characteristics: OP AMP2 (Independent Amplifier)

6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

5.6 Electrical Characteristics: OP AMP2 (Independent Amplifier) (continued)

5.7 Typical Characteristics: TL103WB

8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

5.7 Typical Characteristics: TL103WB (continued)

10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

6 Detailed Description

6.1 Overview

6.2 Functional Block Diagram

6.3 Feature Description

6.3.1 Internal Reference

6.3.2 Input Common Mode Range

12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

6.3.3 EMI Rejection

6.4 Device Functional Modes

7 Application and Implementation

7.1 Application Information

7.2 Typical Applications

7.2.1 Isolated Flyback CC/CV Feedback

14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

7.2.1.1 Design Requirements

7.2.1.2 Detailed Design Procedure

7.2.1.2.1 Constant Current Circuit

6 V × R 4 + R 3

7.2.1.2.2 Constant Voltage Circuit

20 V × R 9

16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

7.2.2 Constant Current Sink

7.3 Power Supply Recommendations

7.4 Layout

7.4.1 Layout Guidelines

7.4.2 Layout Example

18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

8 Device and Documentation Support

8.1 Documentation Support

8.1.1 Related Documentation

8.2 Receiving Notification of Documentation Updates

8.3 Support Resources

8.4 Trademarks

8.5 Electrostatic Discharge Caution

8.6 Glossary

9 Revision History

10 Mechanical, Packaging, and Orderable Information

20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

2.65 TYP

1.1 MAX

0.08 TYP

0.1 C A B

PTL103WBIDDFR specifications and overview.

More parts from the same family.