PTL071HIDBVR

TL071_V03 TI | Alldatasheet

Document overview

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Technical content

TL07xx Low-Noise FET-Input Operational Amplifiers

1 Features

• High slew rate: 20 V/μs (TL07xH, typ)
• Low offset voltage: 1 mV (TL07xH, typ)
• Low offset voltage drift: 2 μV/°C
• Low power consumption: 940 μA/ch (TL07xH, typ)
• Wide common-mode and differential voltage ranges – Common-mode input voltage range includes VCC+
• Low input bias and offset currents
• Low noise: Vn = 18 nV/√Hz (typ) at f = 1 kHz
• Output short-circuit protection
• Low total harmonic distortion: 0.003% (typ)
• Wide supply voltage: ±2.25 V to ±20 V, 4.5 V to 40 V

2 Applications

• Solar energy: string and central inverter
• Motor drives: AC and servo drive control and power stage modules
• Single phase online UPS
• Three phase UPS
• Pro audio mixers
• Battery test equipment

3 Description

The TL07xH (TL071H, TL072H, and TL074H) family of devices are the next-generation versions of the industry-standard TL07x (TL071, TL072, and TL074) devices. These devices provide outstanding value for cost-sensitive applications, with features including low offset (1 mV, typical), high slew rate (20 V/ μs), and common-mode input to the positive supply. High ESD (1.5 kV, HBM), integrated EMI and RF filters, and operation across the full –40°C to 125°C enable the TL07xH devices to be used in the most rugged and demanding applications. Device Information PART NUMBER(1) PACKAGE BODY SIZE (NOM) TL071x PDIP (8) 9.59 mm × 6.35 mm SC70 (5) 2.00 mm × 1.25 mm SO (8) 6.20 mm × 5.30 mm SOIC (8) 4.90 mm × 3.90 mm SOT-23 (5) 1.60 mm × 1.20 mm TL072x PDIP (8) 9.59 mm × 6.35 mm SO (8) 6.20 mm × 5.30 mm SOIC (8) 4.90 mm × 3.90 mm SOT-23 (8) 2.90 mm × 1.60 mm TSSOP (8) 4.40 mm × 3.00 mm TL072M CDIP (8) 9.59 mm × 6.67 mm CFP (10) 6.12 mm × 3.56 mm LCCC (20) 8.89 mm × 8.89 mm TL074x PDIP (14) 19.30 mm × 6.35 mm SO (14) 10.30 mm × 5.30 mm SOIC (14) 8.65 mm × 3.91 mm SOT-23 (14) 4.20 mm × 2.00 mm SSOP (14) 6.20 mm × 5.30 mm TSSOP (14) 5.00 mm × 4.40 mm TL074M CDIP (14) 19.56 mm × 6.92 mm CFP (14) 9.21 mm × 6.29 mm LCCC (20) 8.89 mm × 8.89 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. IN+ IN− OUT IN+ IN− OUT TL072 (each amplifier) TL074 (each amplifier) TL071 OFFSET N1 OFFSET N2 Copyright © 2017, Texas Instruments Incorporated Logic Symbols TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

6.2 Absolute Maximum Ratings: All Devices Except

6.6 Recommended Operating Conditions: All

6.7 Thermal Information for Single Channel: TL071H ... 13 6.12 Thermal Information for Quad Channel: TL074H ...15

6.18 Electrical Characteristics: TL071C, TL072C,

6.19 Electrical Characteristics: TL071AC, TL072AC,

6.20 Electrical Characteristics: TL071BC, TL072BC,

6.21 Electrical Characteristics: TL071I, TL072I,

6.25 Switching Characteristics: TL07xC, TL07xAC,

6.27 Typical Characteristics: All Devices Except

12.1 Receiving Notification of Documentation Updates..45

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision Q (June 2021) to Revision R (June 2021) Page Changes from Revision P (November 2020) to Revision Q (June 2021) Page

• Added D, DCK, and DBV package thermal information in Thermal Information for Single Channel: TL071H
• Added D, DDF, and PW package thermal information in Thermal Information for Dual Channel: TL072H TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

Changes from Revision O (October 2020) to Revision P (November 2020) Page

• Added SOIC and TSSOP package thermal information in Thermal Information for Quad Channel: TL074H Changes from Revision N (July 2017) to Revision O (October 2020) Page
• Added SOT-23 (14), VSSOP (8), SOT-23 (8), SC70 (5), and SOT-23 (5) packages to the Device Information Changes from Revision M (February 2014) to Revision N (July 2017) Page
• Changed common-mode voltage maximum value from VCC+ – 4 V to VCC+ in the Recommended Operating
• Changed devices in Recommended Operating Conditions table from TL07xA and TL07xB to TL07xAC and
• Added TL07xI operating free-air temperature minimum value of –40°C to Recommended Operating www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

Changes from Revision L (February 2014) to Revision M (February 2014) Page

• Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Changes from Revision K (January 2014) to Revision L (February 2014) Page TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

5 Pin Configuration and Functions

2V± 3IN+ 4 IN ± 5 V+ Not to scale Figure 5-1. TL071H DBV and DCK Package 5-Pin SOT-23, and SC70 Top View 1NC 8 NC 2IN– 7 VCC+ 3IN+ 6 OUT 4VCC– 5 NC Not to scale NC- no internal connection Figure 5-2. TL071H D Package 8-Pin SOIC Top View Table 5-1. Pin Functions: TL071H PIN I/O DESCRIPTION NAME DBV, DCK D IN– 4 2 I Inverting input IN+ 3 3 I Noninverting input NC 8 — Do not connect NC 1 — Do not connect NC 5 — Do not connect OUT 1 6 O Output VCC– 2 4 — Power supply VCC+ 5 7 — Power supply www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

2IN± 7 VCC+ 3IN+ 6 OUT 4VCC± 5 OFFSET N2 Not to scale NC- no internal connection Figure 5-3. TL071x D, P, and PS Package 8-Pin SOIC, PDIP, and SO Top View Table 5-2. Pin Functions: TL071x PIN I/O DESCRIPTION NAME NO. IN– 2 I Inverting input IN+ 3 I Noninverting input NC 8 — Do not connect OFFSET N1 1 — Input offset adjustment OFFSET N2 5 — Input offset adjustment OUT 6 O Output VCC– 4 — Power supply VCC+ 7 — Power supply TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

21IN± 7 2OUT 31IN+ 6 2IN ± 4VCC± 5 2IN+ Not to scale Figure 5-4. TL072x D, DDF, JG, P, PS, and PW Package 8-Pin SOIC, SOT-23 (8), CDIP, PDIP, SO, and TSSOP Top View Table 5-3. Pin Functions: TL072x PIN I/O DESCRIPTION NAME NO. 1IN– 2 I Inverting input 1IN+ 3 I Noninverting input 1OUT 1 O Output 2IN– 6 I Inverting input 2IN+ 5 I Noninverting input 2OUT 7 O Output VCC– 4 — Power supply VCC+ 8 — Power supply www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

31IN± 8 2OUT 41IN+ 7 2IN ± 5VCC± 6 2IN+ Not to scale NC- no internal connection Figure 5-5. TL072x U Package 10-Pin CFP Top View Table 5-4. Pin Functions: TL072x PIN I/O DESCRIPTION NAME NO. 1IN– 3 I Inverting input 1IN+ 4 I Noninverting input 1OUT 2 O Output 2IN– 7 I Inverting input 2IN+ 6 I Noninverting input 2OUT 8 O Output NC 1, 10 — Do not connect VCC– 5 — Power supply VCC+ 9 — Power supply TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

51IN± 6NC 71IN+ 8NC 9NC 10VCC± 11NC 122IN+ 13NC 14 NC 15 2IN ± 16 NC 17 2OUT 18 NC 19 NC

20 VCC+

NC- no internal connection Figure 5-6. TL072 FK Package 20-Pin LCCC Top View Table 5-5. Pin Functions: TL072x PIN I/O DESCRIPTION NAME NO. 1IN– 5 I Inverting input 1IN+ 7 I Noninverting input 1OUT 2 O Output 2IN– 15 I Inverting input 2IN+ 12 I Noninverting input 2OUT 17 O Output NC 1, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 19 — Do not connect VCC– 10 — Power supply VCC+ 20 — Power supply www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

21IN± 13 4IN ± 31IN+ 12 4IN+ 4VCC+ 11 VCC ± 52IN+ 10 3IN+ 62IN± 9 3IN ± 72OUT 8 3OUT Not to scale Figure 5-7. TL074x D, N, NS, PW, J, DYY, and W Package 14-Pin SOIC, PDIP, SO, TSSOP, CDIP, SOT-23 (14), and CFP Top View Table 5-6. Pin Functions: TL074x PIN I/O DESCRIPTION NAME NO. 1IN– 2 I Inverting input 1IN+ 3 I Noninverting input 1OUT 1 O Output 2IN– 6 I Inverting input 2IN+ 5 I Noninverting input 2OUT 7 O Output 3IN– 9 I Inverting input 3IN+ 10 I Noninverting input 3OUT 8 O Output 4IN– 13 I Inverting input 4IN+ 12 I Noninverting input 4OUT 14 O Output VCC– 11 — Power supply VCC+ 4 — Power supply TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

92IN± 102OUT 11NC 123OUT 133IN± 14 3IN+ 15 NC

16 VCC ±

19 4IN ± 20 4OUT 1 NC 2 1OUT 3 1IN ± Not to scale NC- no internal connection Figure 5-8. TL074 FK Package 20-Pin LCCC Top View Table 5-7. Pin Functions: TL074x PIN I/O DESCRIPTION NAME NO. 1IN– 3 I Inverting input 1IN+ 4 I Noninverting input 1OUT 2 O Output 2IN– 9 I Inverting input 2IN+ 8 I Noninverting input 2OUT 10 O Output 3IN– 13 I Inverting input 3IN+ 14 I Noninverting input 3OUT 12 O Output 4IN– 19 I Inverting input 4IN+ 18 I Noninverting input 4OUT 20 O Output 17 — Do not connect VCC– 16 — Power supply VCC+ 6 — Power supply www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

6 Specifications

6.1 Absolute Maximum Ratings: TL07xH

over operating ambient temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage, VS = (VCC+) – (VCC–) 0 42 V Signal input pins Common-mode voltage (3) (VCC–) – 0.5 (VCC+) + 0.5 V Differential voltage (3) VS + 0.2 V Current (3) –10 10 mA Output short-circuit (2) Continuous Operating ambient temperature, TA –55 150 °C Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Short-circuit to ground, one amplifier per package. (3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less.

6.2 Absolute Maximum Ratings: All Devices Except TL07xH

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC+ - VCC– Supply voltage –0.3 36 V VI Input voltage (3) VCC– – 0.3 VCC– + 36 V IIK Input clamp current –50 mA Duration of output short circuit(2) Unlimited TJ Operating virtual junction temperature 150 °C Case temperature for 60 seconds - FK package 260 °C Lead temperature 1.8 mm (1/16 inch) from case for 10 seconds 300 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The output may be shorted to ground or to either supply. Temperature and supply voltages must be limited to ensure that the dissipation rating is not exceeded. (3) Differential voltage only limited by input voltage.

6.3 ESD Ratings: TL07xH

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 TL072H V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

6.4 ESD Ratings: All Devices Except TL07xH

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.5 Recommended Operating Conditions: TL07xH

over operating ambient temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage, (VCC+) – (VCC–) 4.5 40 V VI Input voltage range (VCC–) + 2 (VCC+) + 0.1 V TA Specified temperature –40 125 °C

6.6 Recommended Operating Conditions: All Devices Except TL07xH

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC+ Supply voltage (1) 5 15 V VCC– Supply voltage (1) –5 –15 V VCM Common-mode voltage VCC– + 4 VCC+ V TA Operating free-air temperature TL07xM –55 125 TL08xQ –40 125 TL07xI –40 85 TL07xAC, TL07xBC, TL07xC 0 70 (1) VCC+ and VCC– are not required to be of equal magnitude, provided that the total VCC (VCC+ – VCC–) is between 10 V and 30 V.

6.7 Thermal Information for Single Channel: TL071H

THERMAL METRIC (1) TL071H UNITD (2) (SOIC) DCK(2) (SC70) DBV (2) (SOT-23)

8 PINS 5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 158.8 217.5 212.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 98.6 113.1 111.1 °C/W RθJB Junction-to-board thermal resistance 102.3 63.8 79.4 °C/W ψJT Junction-to-top characterization parameter 45.8 34.8 51.8 °C/W ψJB Junction-to-board characterization parameter 101.5 63.5 79.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) This package option is preview for TL071H. www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

6.8 Thermal Information: TL071x

THERMAL METRIC(1) TL071x UNITD (SOIC) P (PDIP) PS (SO)

8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 97 85 95 °C/W RθJC(top) Junction-to-case (top) thermal resistance — — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.9 Thermal Information for Dual Channel: TL072H

THERMAL METRIC (1) TL072H UNITD (SOIC) DDF (SOT-23) PW (TSSOP) RθJA Junction-to-ambient thermal resistance 147.8 181.5 200.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 88.2 112.5 89.4 °C/W RθJB Junction-to-board thermal resistance 91.4 98.2 131.0 °C/W ψJT Junction-to-top characterization parameter 36.8 17.2 22.2 °C/W ψJB Junction-to-board characterization parameter 90.6 97.6 129.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.10 Thermal Information: TL072x

THERMAL METRIC(1) TL072x UNITD (SOIC) JG (CDIP) P (PDIP) PS (SO)

8 PINS 8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 97 — 85 95 °C/W RθJC(top) Junction-to-case (top) thermal resistance — 15.05 — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

6.11 Thermal Information: TL072x (cont.) THERMAL METRIC(1) TL072x UNITPW (TSSOP) U (CFP) FK (LCCC)

8 PINS 10 PINS 20 PINS

RθJA Junction-to-ambient thermal resistance 150 169.8 — °C/W RθJC(top) Junction-to-case (top) thermal resistance — 62.1 5.61 °C/W RθJB Junction-to-board thermal resistance — 176.2 — °C/W ψJT Junction-to-top characterization parameter — 48.4 — °C/W ψJB Junction-to-board characterization parameter — 144.1 — °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — 5.4 — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.12 Thermal Information for Quad Channel: TL074H

THERMAL METRIC (1) TL074H UNITD (SOIC) DYY (2) (SOT-23) PW (TSSOP)

14 PINS 14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance 114.2 TBD 134.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 70.3 TBD 62.6 °C/W RθJB Junction-to-board thermal resistance 70.2 TBD 77.6 °C/W ψJT Junction-to-top characterization parameter 28.8 TBD 13.0 °C/W ψJB Junction-to-board characterization parameter 69.8 TBD 77.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A TBD N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) This package option is preview for TL074H.

6.13 Thermal Information: TL074x

THERMAL METRIC(1) TL074x UNITD (SOIC) N (PDIP) NS (SO) RθJA Junction-to-ambient thermal resistance 86 80 76 °C/W RθJC(top) Junction-to-case (top) thermal resistance — — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

6.14 Thermal Information: TL074x (cont). THERMAL METRIC(1) TL074x UNITJ (CDIP) PW (TSSOP) W (CFP) RθJA Junction-to-ambient thermal resistance — 113 128.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 14.5 — 56.1 °C/W RθJB Junction-to-board thermal resistance — — 127.6 °C/W ψJT Junction-to-top characterization parameter — — 29 °C/W ψJB Junction-to-board characterization parameter — — 106.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — 0.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.15 Thermal Information: TL074x (cont). THERMAL METRIC(1) TL074x UNITFK (LCCC)

20 PINS

RθJA Junction-to-ambient thermal resistance — °C/W RθJC(top) Junction-to-case (top) thermal resistance 5.61 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.16 Thermal Information

THERMAL METRIC(1) TL071/TL072/TL074 UNITD (SOIC) FK (LCCC) J (CDIP) N (PDIP) NS (SO) PW (TSSOP)

8 PINS 14

RθJA Junction-to-ambient thermal resistance 97 86 — — — 85 80 95 76 150 113 °C/W RθJC(top) Junction-to-case (top) thermal resistance — — 5.61 15.05 14.5 — — — — — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

6.17 Electrical Characteristics: TL07xH

For VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage ±1 ±4 mV TA = –40°C to 125°C ±5 dVOS/dT Input offset voltage drift TA = –40°C to 125°C ±2 µV/℃ PSRR Input offset voltage versus power supply VS = 5 V to 40 V, VCM = VS /

2 TA = –40°C to 125°C ±1 ±10 μV/V

Channel separation f = 0 Hz 10 µV/V INPUT BIAS CURRENT IB Input bias current ±1 ±120 pA DCK and DBV packages ±1 ±300 pA TA = –40°C to 125°C (1) ±5 nA IOS Input offset current ±0.5 ±120 pA DCK and DBV packages ±0.5 ±250 pA TA = –40°C to 125°C (1) ±5 nA NOISE EN Input voltage noise f = 0.1 Hz to 10 Hz 9.2 μVPP 1.4 µVRMS eN Input voltage noise density f = 1 kHz 37 nV/√Hz f = 10 kHz 21 iN Input current noise f = 1 kHz 80 fA/√Hz INPUT VOLTAGE RANGE VCM Common-mode voltage range (VCC–) + 1.5 (VCC+) V CMRR Common-mode rejection ratio VS = 40 V, (VCC–) + 2.5 V < VCM < (VCC+) – 1.5 V 100 105 dB CMRR Common-mode rejection ratio TA = –40°C to 125°C 95 dB CMRR Common-mode rejection ratio VS = 40 V, (VCC–) + 2.5 V < VCM < (VCC+) 90 105 dB CMRR Common-mode rejection ratio TA = –40°C to 125°C 80 dB INPUT CAPACITANCE ZID Differential 100 || 2 MΩ || pF ZICM Common-mode 6 || 1 TΩ || pF OPEN-LOOP GAIN AOL Open-loop voltage gain VS = 40 V, VCM = VS / 2, (VCC–) + 0.3 V < VO < (VCC+) – 0.3 V TA = –40°C to 125°C 118 125 dB AOL Open-loop voltage gain VS = 40 V, VCM = VS / 2, RL = 2 kΩ, (VCC–) + 1.2 V < VO < (VCC+) – 1.2 V TA = –40°C to 125°C 115 120 dB FREQUENCY RESPONSE GBW Gain-bandwidth product 5.25 MHz SR Slew rate VS = 40 V, G = +1, CL = 20 pF 20 V/μs tS Settling time To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 0.63 μs To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 0.56 To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 0.91 To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 0.48 Phase margin G = +1, RL = 10kΩ, CL = 20 pF 56 ° Overload recovery time VIN × gain > VS 300 ns www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

6.17 Electrical Characteristics: TL07xH (continued)

For VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THD+N Total harmonic distortion + noise VS = 40 V, VO = 6 VRMS, G = +1, f = 1 kHz 0.00012 % EMIRR EMI rejection ratio f = 1 GHz 53 dB OUTPUT Voltage output swing from rail Positive rail headroom VS = 40 V, RL = 10 kΩ 115 210 mV VS = 40 V, RL = 2 kΩ 520 965 Negative rail headroom VS = 40 V, RL = 10 kΩ 105 215 VS = 40 V, RL = 2 kΩ 500 1030 ISC Short-circuit current ±26 mA CLOAD Capacitive load drive 300 pF ZO Open-loop output impedance f = 1 MHz, IO = 0 A 125 Ω POWER SUPPLY IQ Quiescent current per amplifier IO = 0 A 937.5 1125 µA IO = 0 A, (TL071H) 960 1156 IO = 0 A TA = –40°C to 125°C 1130 IO = 0 A, (TL072H) 1143 IO = 0 A, (TL071H) 1160 Turn-On Time At TA = 25°C, VS = 40 V, VS ramp rate > 0.3 V/µs 60 μs (1) Max IB and Ios data is specified based on characterization results. TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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6.18 Electrical Characteristics: TL071C, TL072C, TL074C

VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS (1) (2) MIN TYP MAX UNIT VIO Input offset voltage VO = 0 RS = 50 Ω TA = 25°C 3 10 mV TA = Full range 13 α Temperature coefficient of input offset voltage VO = 0 RS = 50 Ω TA = Full range 18 µV/°C IIO Input offset current VO = 0 TA = 25°C 5 100 pA TA = Full range 10 nA IIB Input bias current (3) VO = 0 TA = 25°C 65 200 pA TA = Full range 7 nA VICR Common-mode input voltage range TA = 25°C ±11 –12 to 15 V VOM Maximum peak output voltage swing RL= 10 kΩ TA = 25°C ±12 ±13.5 VRL≥ 10 kΩ TA = Full range ±12 RL≥ 2 kΩ ±10 AVD Large-signal differential voltage amplification VO = ±10 V RL≥ 2 kΩ TA = 25°C 25 200 V/mV TA = Full range 15 B1 Utility-gain bandwidth TA = 25°C 3 MHz rI Input resistance TA = 25°C 1012 Ω CMRR Common-mode rejection ratio VIC = VICR(min) VO = 0 RS = 50 Ω TA = 25°C 70 100 dB kSVR Supply voltage rejection ratio (ΔVCC±/ΔVIO) VCC = ±9 V to ±15 V VO = 0 RS = 50 Ω TA = 25°C 70 100 dB ICC Supply current (each amplifier) VO = 0; no load TA = 25°C 1.4 2.5 mA VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25°C 120 dB (1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. (2) Full range is TA = 0°C to 70°C. (3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Input Bias Current vs Free-Air Temperature. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

6.19 Electrical Characteristics: TL071AC, TL072AC, TL074AC

VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS (1) (2) MIN TYP MAX UNIT VIO Input offset voltage VO = 0 RS = 50 Ω TA = 25°C 3 6 mV TA = Full range 7.5 α Temperature coefficient of input offset voltage VO = 0 RS = 50 Ω TA = Full range 18 µV/°C IIO Input offset current VO = 0 TA = 25°C 5 100 pA TA = Full range 2 nA IIB Input bias current (3) VO = 0 TA = 25°C 65 200 pA TA = Full range 7 nA VICR Common-mode input voltage range TA = 25°C ±11 –12 to 15 V VOM Maximum peak output voltage swing RL= 10 kΩ TA = 25°C ±12 ±13.5 VRL≥ 10 kΩ TA = Full range ±12 RL≥ 2 kΩ ±10 AVD Large-signal differential voltage amplification VO = ±10 V RL≥ 2 kΩ TA = 25°C 50 200 V/mV TA = Full range 25 B1 Utility-gain bandwidth TA = 25°C 3 MHz rI Input resistance TA = 25°C 1012 Ω CMRR Common-mode rejection ratio VIC = VICR(min) VO = 0 RS = 50 Ω TA = 25°C 75 100 dB kSVR Supply-voltage rejection ratio (ΔVCC± / ΔVIO) VCC = ±9 V to ±15 V VO = 0 RS = 50 Ω TA = 25°C 80 100 dB ICC Supply current (each amplifier) VO = 0; no load TA = 25°C 1.4 2.5 mA VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25°C 120 dB (1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. (2) Full range is TA = 0°C to 70°C. (3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Input Bias Current vs Free-Air Temperature. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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6.20 Electrical Characteristics: TL071BC, TL072BC, TL074BC

VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS (1) (2) MIN TYP MAX UNIT VIO Input offset voltage VO = 0 RS = 50 Ω TA = 25°C 2 3 mV TA = Full range 5 α Temperature coefficient of input offset voltage VO = 0 RS = 50 Ω TA = Full range 18 µV/°C IIO Input offset current VO = 0 TA = 25°C 5 100 pA TA = Full range 2 nA IIB Input bias current (3) VO = 0 TA = 25°C 65 200 pA TA = Full range 7 nA VICR Common-mode input voltage range TA = 25°C ±11 –12 to 15 V VOM Maximum peak output voltage swing RL= 10 kΩ TA = 25°C ±12 ±13.5 VRL≥ 10 kΩ TA = Full range ±12 RL≥ 2 kΩ ±10 AVD Large-signal differential voltage amplification VO = ±10 V RL ≥ 2 kΩ TA = 25°C 50 200 V/mV TA = Full range 25 B1 Utility-gain bandwidth TA = 25°C 3 MHz rI Input resistance TA = 25°C 1012 Ω CMRR Common-mode rejection ratio VIC = VICR(min) VO = 0 RS = 50 Ω TA = 25°C 75 100 dB kSVR Supply-voltage rejection ratio (ΔVCC±/ΔVIO) VCC = ±9 V to ±15 V VO = 0 RS = 50 Ω TA = 25°C 80 100 dB ICC Supply current (each amplifier) VO = 0; no load TA = 25°C 1.4 2.5 mA VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25°C 120 dB (1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. (2) Full range is TA = 0°C to 70°C. (3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Input Bias Current vs Free-Air Temperature. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

6.21 Electrical Characteristics: TL071I, TL072I, TL074I

VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS (1) (2) MIN TYP MAX UNIT VIO Input offset voltage VO = 0 RS = 50 Ω TA = 25°C 3 6 mV TA = Full range 8 α Temperature coefficient of input offset voltage VO = 0 RS = 50 Ω TA = Full range 18 µV/°C IIO Input offset current VO = 0 TA = 25°C 5 100 pA TA = Full range 2 nA IIB Input bias current (3) VO = 0 TA = 25°C 65 200 pA TA = Full range 7 nA VICR Common-mode input voltage range TA = 25°C ±11 –12 to 15 V VOM Maximum peak output voltage swing RL= 10 kΩ TA = 25°C ±12 ±13.5 VRL ≥ 10 kΩ TA = Full range ±12 RL ≥ 2 kΩ ±10 AVD Large-signal differential voltage amplification VO = ±10 V RL ≥ 2 kΩ TA = 25°C 50 200 V/mV TA = Full range 25 B1 Utility-gain bandwidth TA = 25°C 3 MHz rI Input resistance TA = 25°C 1012 Ω CMRR Common-mode rejection ratio VIC = VICR(min) VO = 0 RS = 50 Ω TA = 25°C 75 100 dB kSVR Supply-voltage rejection ratio (ΔVCC±/ΔVIO) VCC = ±9 V to ±15 V VO = 0 RS = 50 Ω TA = 25°C 80 100 dB ICC Supply current (each amplifier) VO = 0; no load TA = 25°C 1.4 2.5 mA VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25°C 120 dB (1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. (2) TA = –40°C to 85°C. (3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Input Bias Current vs Free-Air Temperature. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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6.22 Electrical Characteristics: TL071M, TL072M

VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS (1) (2) MIN TYP MAX UNIT VIO Input offset voltage VO = 0 RS = 50 Ω TA = 25°C 3 6 mV TA = Full range 9 αVIO Temperature coefficient of input offset voltage VO = 0 RS = 50 Ω TA = Full range 18 μV/°C IIO Input offset current VO = 0 TA = 25°C 5 100 pA TA = Full range 20 nA IIB Input bias current VO = 0 TA = 25°C 65 200 pA TA = Full range 50 nA VICR Common-mode input voltage range TA = 25°C ±11 –12 to 15 V VOM Maximum peak output voltage swing RL = 10 kΩ TA = 25°C ±12 ±13.5 VRL ≥ 10 kΩ TA = Full range ±12 RL ≥ 2 kΩ ±10 AVD Large-signal differential voltage amplification VO = ±10 V RL ≥ 2 kΩ TA = 25°C 35 200 V/mV TA = Full range 15 B1 Unity-gain bandwidth 3 MHz ri Input resistance 1012 Ω CMRR Common-mode rejection ratio VIC = VICR(min), VO = 0 RS = 50 Ω TA = 25°C 80 86 dB kSVR Supply-voltage rejection ratio (ΔVCC±/ΔVIO) VCC = ±9 V to ±15 V VO = 0 RS = 50 Ω TA = 25°C 80 86 dB ICC Supply current (each amplifier) VO = 0; no load TA = 25°C 1.4 2.5 mA VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25°C 120 dB (1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Input Bias Current vs Free-Air Temperature. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must be used. (2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = –55°C to +125°C. www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

6.23 Electrical Characteristics: TL074M

VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS (1) (2) MIN TYP MAX UNIT VIO Input offset voltage VO = 0 RS = 50 Ω TA = 25°C 3 9 mV TA = Full range 15 αVIO Temperature coefficient of input offset voltage VO = 0, RS = 50 Ω TA = Full range 18 μV/°C IIO Input offset current VO = 0 TA = 25°C 5 100 pA TA = Full range 20 nA IIB Input bias current VO = 0 TA = 25°C 65 200 pA TA = Full range 20 nA VICR Common-mode input voltage range TA = 25°C ±11 –12 to 15 V VOM Maximum peak output voltage swing RL = 10 kΩ TA = 25°C ±12 ±13.5 VRL ≥ 10 kΩ TA = Full range ±12 RL ≥ 2 kΩ ±10 AVD Large-signal differential voltage amplification VO = ±10 V RL ≥ 2 kΩ TA = 25°C 35 200 V/mV TA = Full range 15 B1 Unity-gain bandwidth 3 MHz ri Input resistance 1012 Ω CMRR Common-mode rejection ratio VIC = VICR(min) VO = 0 RS = 50 Ω TA = 25°C 80 86 dB kSVR Supply-voltage rejection ratio (ΔVCC±/ΔVIO) VCC = ±9 V to ±15 V VO = 0 RS = 50 Ω TA = 25°C 80 86 dB ICC Supply current (each amplifier) VO = 0; no load TA = 25°C 1.4 2.5 mA VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25°C 120 dB (1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Input Bias Current vs Free-Air Temperature. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must be used . (2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = –55°C to +125°C. TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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6.24 Switching Characteristics: TL07xM

VCC± = ±15 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Slew rate at unity gain VI = 10 V CL = 100 pF RL = 2 kΩ See Figure 7-1 5 13 V/μs tr Rise-time overshoot factor VI = 20 V CL = 100 pF RL = 2 kΩ See Figure 7-1 0.1 μs 20% Vn Equivalent input noise voltage RS = 20 Ω f = 1 kHz 18 nV/√ Hz f = 10 Hz to 10 kHz 4 μV In Equivalent input noise current RS = 20 Ω f = 1 kHz 0.01 pA/√ Hz THD Total harmonic distortion VIrms = 6 V RL ≥ 2 kΩ f = 1 kHz AVD = 1 RS ≤ 1 kΩ 0.003%

6.25 Switching Characteristics: TL07xC, TL07xAC, TL07xBC, TL07xI

VCC± = ±15 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Slew rate at unity gain VI = 10 V CL = 100 pF RL = 2 kΩ See Figure 7-1 8 13 V/μs tr Rise-time overshoot factor VI = 20 V CL = 100 pF RL = 2 kΩ See Figure 7-1 0.1 μs 20% Vn Equivalent input noise voltage RS = 20 Ω f = 1 kHz 18 nV/√ Hz f = 10 Hz to 10 kHz 4 μV In Equivalent input noise current RS = 20 Ω f = 1 kHz 0.01 pA/√ Hz THD Total harmonic distortion VIrms = 6 V RL ≥ 2 kΩ f = 1 kHz AVD = 1 RS ≤ 1 kΩ 0.003% www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

6.26 Typical Characteristics: TL07xH

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted) TA = 25°C Figure 6-1. Offset Voltage Production Distribution Figure 6-2. Offset Voltage Drift Distribution VCM = VS / 2 Figure 6-3. Offset Voltage vs Temperature TA = 25°C Figure 6-4. Offset Voltage vs Common-Mode Voltage TA = 125°C Figure 6-5. Offset Voltage vs Common-Mode Voltage TA = –40°C Figure 6-6. Offset Voltage vs Common-Mode Voltage TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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6.26 Typical Characteristics: TL07xH (continued)

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted) Figure 6-7. Offset Voltage vs Power Supply Figure 6-8. Open-Loop Gain and Phase vs Frequency Figure 6-9. Closed-Loop Gain vs Frequency Figure 6-10. Input Bias Current vs Common-Mode Voltage Figure 6-11. Input Bias Current vs Temperature Figure 6-12. Output Voltage Swing vs Output Current (Sourcing) www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted) Figure 6-13. Output Voltage Swing vs Output Current (Sinking) Figure 6-14. CMRR and PSRR vs Frequency f = 0 Hz Figure 6-15. CMRR vs Temperature (dB) f = 0 Hz Figure 6-16. PSRR vs Temperature (dB) Figure 6-17. 0.1-Hz to 10-Hz Noise Figure 6-18. Input Voltage Noise Spectral Density vs Frequency TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted) BW = 80 kHz, VOUT = 1 VRMS Figure 6-19. THD+N Ratio vs Frequency BW = 80 kHz, f = 1 kHz Figure 6-20. THD+N vs Output Amplitude VCM = VS / 2 Figure 6-21. Quiescent Current vs Supply Voltage Figure 6-22. Quiescent Current vs Temperature Figure 6-23. Open-Loop Voltage Gain vs Temperature (dB) Figure 6-24. Open-Loop Output Impedance vs Frequency www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted) G = –1, 25-mV output step Figure 6-25. Small-Signal Overshoot vs Capacitive Load G = 1, 10-mV output step Figure 6-26. Small-Signal Overshoot vs Capacitive Load Figure 6-27. Phase Margin vs Capacitive Load VS = ±10 V, VIN = VOUT Figure 6-28. No Phase Reversal G = –10 Figure 6-29. Positive Overload Recovery G = –10 Figure 6-30. Negative Overload Recovery TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted) CL = 20 pF, G = 1, 10-mV step response Figure 6-31. Small-Signal Step Response, Rising CL = 20 pF, G = 1, 10-mV step response Figure 6-32. Small-Signal Step Response, Falling CL = 20 pF, G = 1 Figure 6-33. Large-Signal Step Response (Rising) CL = 20 pF, G = 1 Figure 6-34. Large-Signal Step Response (Falling) CL = 20 pF, G = 1 Figure 6-35. Large-Signal Step Response Figure 6-36. Short-Circuit Current vs Temperature www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted) Figure 6-37. Maximum Output Voltage vs Frequency Figure 6-38. Channel Separation vs Frequency Figure 6-39. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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6.27 Typical Characteristics: All Devices Except TL07xH

IIB− Input Bias Current − nA TA − Free-Air Temperature − °C IBI 0.1 0.01 100 −75 −50 −25 0 25 50 75 100 125 VCC± = ±15 V Figure 6-40. Input Bias Current vs Free-Air Temperature RL = 10 kΩ TA = 25°C See Figure 2 ±15 ±12.5 ±10 ±7.5 ±2.5 VOM Maximum Peak Output V oltage V f − Frequency − Hz 100 1 k 10 k 100 k 1 M 10 M VOM VCC± = ±5 V VCC± = ±10 V VCC± = ±15 V Figure 6-41. Maximum Peak Output Voltage vs Frequency

10 M1 M100 k10 k1 k100

f − Frequency − Hz VOM − Maximum Peak Output V oltage − V ±2.5 ±7.5 ±10 ±12.5 ±15 See Figure 2 TA = 25°C RL = 2 kΩ VCC± = ±10 V VCC± = ±5 V VOM VCC± = ±15 V Figure 6-42. Maximum Peak Output Voltage vs Frequency Figure 6-43. Maximum Peak Output Voltage vs Frequency −75 VOM − Maximum Peak Output V oltage − V TA − Free-Air Temperature − °C 125 ±15 −50 −25 0 25 50 75 100 ±2.5 ±7.5 ±10 ±12.5 RL = 10 kΩ VCC± = ±15 V See Figure 2VOM RL = 2 kΩ Figure 6-44. Maximum Peak Output Voltage vs Free-Air Temperature 0.1 RL − Load Resistance − k Ω ±15 ±2.5 ±7.5 ±10 ±12.5 VCC± = ±15 V TA = 25°C See Figure 2 0.2 0.4 0.7 1 2 4 7 VOM − Maximum Peak Output V oltage − V VOM 8 Figure 6-45. Maximum Peak Output Voltage vs Load Resistance www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

6.27 Typical Characteristics: All Devices Except TL07xH (continued)

VOM − Maximum Peak Output V oltage − V |VCC±| − Supply V oltage − V ±15 2 4 6 8 10 12 14 ±2.5 ±7.5 ±10 ±12.5 RL = 10 kΩ TA = 25°C VOM Figure 6-46. Maximum Peak Output Voltage vs Supply Voltage −75 Voltage Amplification − V/mV TA − Free-Air Temperature − °C 125 1000 −50 −25 0 25 50 75 100 100 200 400 VCC± = ±15 V VO = ±10 V RL = 2 kΩ AVD − Large-Signal DifferentialA VD Figure 6-47. Large-Signal Differential Voltage Amplification vs Free-Air Temperature Figure 6-48. Large-Signal Differential Voltage Amplification and Phase Shift vs Frequency 1.02 1.01 0.99 0.98 1.03 0.97 −75 0.7 Normalized Unity-Gain Bandwidth TA − Free-Air Temperature − °C 125 1.3 −50 −25 0 25 50 75 100 0.8 0.9 1.1

1.2 Unity-Gain Bandwidth

VCC± = ±15 V RL = 2 kΩ f = B1 for Phase Shift Phase Shift Normalized Phase Shift Figure 6-49. Normalized Unity-Gain Bandwidth and Phase Shift vs Free-Air Temperature −75 CMRR − Common-Mode Rejection Ratio − dB TA − Free-Air Temperature − °C 125 −50 −25 0 25 50 75 100 VCC± = ±15 V RL = 10 kΩ Figure 6-50. Common-Mode Rejection Ratio vs Free-Air Temperature |VCC±| − Supply Voltage − V 2 4 6 8 10 12 14 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 TA = 25°C No Signal No Load ICC − Supply Current Per Amplifier − mA CC I Figure 6-51. Supply Current Per Amplifier vs Supply Voltage TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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−75 TA − Free-Air Temperature − °C 125 −50 −25 0 25 50 75 100 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 VCC± = ±15 V No Signal No Load ICC − Supply Current Per Amplifier − mA CC I Figure 6-52. Supply Current Per Amplifier vs Free-Air Temperature −75 TA − Free-Air Temperature −C° 125 250 −50 −25 0 25 50 75 100 100 125 150 175 200 225 VCC± = 15 V± No Signal No Load TL074 TL071 TL072 − Total Power Dissipation − mW PD Figure 6-53. Total Power Dissipation vs Free-Air Temperature Figure 6-54. Normalized Slew Rate vs Free-Air Temperature − Equivalent Input Noise V oltage − nV/Hz f − Frequency − Hz 100 k VCC± = ±15 V AVD = 10 RS = 20 Ω TA = 25°C 40 100 400 1 k 4 k 10 k 40 k nV/ Hz Vn Figure 6-55. Equivalent Input Noise Voltage vs Frequency 0.001 THD − T otal Harmonic Distortion − % 40 k10 k4 k1 k400 100 k f − Frequency − Hz 100 0.004 0.01 0.04 0.1 0.4 VCC± = ±15 V AVD = 1 VI(RMS) = 6 V TA = 25°C Figure 6-56. Total Harmonic Distortion vs Frequency t − Time − µs 3.5 0 0.5 1 1.5 2 2.5 3 Output Input VCC± = ±15 V RL = 2 kΩ TA = 25°C CL = 100 pF VO VI − Input and Output V oltages − V and Figure 6-57. Voltage-Follower Large-Signal Pulse Response www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

Figure 6-58. Output Voltage vs Elapsed Time VCM (V) VIO (mV) -13 -11 -9 -7 -5 -3 -1 1 3 5 7 9 11 13 15 17 -10 D003 VCCr = r15 V Figure 6-59. VIO vs VCM TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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7 Parameter Measurement Information

CL = 100 pF RL = 2 kΩ OUT Figure 7-1. Unity-Gain Amplifier VI 10 kΩ 1 kΩ RL CL = 100 pF OUT Figure 7-2. Gain-of-10 Inverting Amplifier Figure 7-3. Input Offset-Voltage Null Circuit www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

8 Detailed Description

8.1 Overview

The TL07xH (TL071H, TL072H, and TL074H) family of devices are the next-generation versions of the industry- standard TL07x (TL071, TL072, and TL074) devices. These devices provide outstanding value for cost-sensitive applications, with features including low offset (1 mV, typ), high slew rate (25 V/ μs, typ), and common-mode input to the positive supply. High ESD (1.5 kV, HBM), integrated EMI and RF filters, and operation across the full –40°C to 125°C enable the TL07xH devices to be used in the most rugged and demanding applications. The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from −40°C to +85°C. The M-suffix devices are characterized for operation over the full military temperature range of −55°C to +125°C.

8.2 Functional Block Diagram

VCC− 1080 Ω 1080 Ω IN− TL071 Only 64 Ω 128 Ω 64 Ω All component values shown are nominal. OFFSET OFFSET OUT 18 pF COMPONENT COUNT† COMPONENT TYPE TL071 TL072 TL074 Resistors 1 1 22 44Resistors Transistors 1 1 Transistors JFET 6JFET Diodes Diodes Capacitors Capacitors epi-FET † Includes bias and trim circuitry TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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8.3 Feature Description

The TL07xH family of devices improve many specifications as compared to the industry-standard TL07x family. Several comparisons of key specifications between these families are included below to show the advantages of the TL07xH family.

8.3.1 Total Harmonic Distortion

Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These devices have a very low THD of 0.003% meaning that the TL07 x device adds little harmonic distortion when used in audio signal applications.

8.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier can change the output when there is a change on the input. These devices have a 13-V/μs slew rate.

8.4 Device Functional Modes

These devices are powered on when the supply is connected. These devices can be operated as a single-supply operational amplifier or dual-supply amplifier depending on the application. www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

A typical application for an operational amplifier is an inverting amplifier. This amplifier takes a positive voltage on the input, and makes the voltage a negative voltage. In the same manner, the amplifier makes negative voltages positive.

9.2 Typical Application

Figure 9-1. Inverting Amplifier

9.2.1 Design Requirements

The supply voltage must be selected so the supply voltage is larger than the input voltage range and output range. For instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to accommodate this application.

9.2.2 Detailed Design Procedure

V o = V i + V i o * 1 + 1 M Ω 1 k Ω (1) Determine the gain required by the inverting amplifier: V VOUTA = VIN (2) V (3) Once the desired gain is determined, select a value for RI or RF. Selecting a value in the kilohm range is desirable because the amplifier circuit uses currents in the milliamp range. This ensures the part does not draw too much current. This example uses 10 k Ω for RI which means 36 k Ω is used for RF. This is determined by Equation 4. V RFA = RI/c45 (4) TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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9.2.3 Application Curve

-1.5 -0.5 0.5 1.5 0 0.5 1 1.5 2 Volts Time (ms) VIN VOUT Figure 9-2. Input and Output Voltages of the Inverting Amplifier

9.3 Unity Gain Buffer

Copyright © 2017, Texas Instruments Incorporated VIN Figure 9-3. Single-Supply Unity Gain Amplifier

9.3.1 Design Requirements

• VCC must be within valid range per Section 6.6. This example uses a value of 12 V for VCC.
• Input voltage must be within the recommended common-mode range, as shown in Section 6.6. The valid common-mode range is 4 V to 12 V (VCC– + 4 V to VCC+).

9.3.2 Detailed Design Procedure

• Avoid input voltage values below 1 V to prevent phase reversal where output goes high.
• Avoid input values below 4 V to prevent degraded VIO that results in an apparent gain greater than 1. This may cause instability in some second-order filter designs. www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

9.3.3 Application Curves

VIN (V) VOUT (V) 0 2 4 6 8 10 12 D001 Figure 9-4. Output Voltage vs Input Voltage VIN (V) Gain (V/V) 0 2 4 6 8 10 12 -1.5 -0.5 0.5 1.5 D002 Figure 9-5. Gain vs Input Voltage

9.4 System Examples

Figure 9-6. 0.5-Hz Square-Wave Oscillator Input C1 C1 Output VCC– VCC+ o R1 R2 2R3 1.5 M C3C 1 C2 110 pF2 1f 1 kHz2 R1 C 1 /c61 /c61 /c61 /c87 /c61 /c61 /c61 /c61 /c61/c112 Figure 9-7. High-Q Notch Filter Figure 9-8. 100-kHz Quadrature Oscillator Figure 9-9. AC Amplifier TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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10 Power Supply Recommendations

Supply voltages larger than 36 V for a single-supply or outside the range of ±18 V for a dual-supply can permanently damage the device (see Section 6.2). Place 0.1- μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from VCC+ to ground is applicable for single- supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically separate digital and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Section 11.2.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

11.2 Layout Example

VCC+IN1í IN1+ VCCí NC OUT NC RG RIN RF GND VIN VS-GND VS+ GND Run the input traces as far away from the supply lines as possible Only needed for dual-supply operation Place components close to device and to each other to reduce parasitic errors Use low-ESR, ceramic bypass capacitor (or GND for single supply) Ground (GND) plane on another layerVOUT Figure 11-1. Operational Amplifier Board Layout for Noninverting Configuration RIN RG RF VOUT VIN Figure 11-2. Operational Amplifier Schematic for Noninverting Configuration TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 www.ti.com

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080R – SEPTEMBER 1978 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M

www.ti.com 14-Jun-2021 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 81023052A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 81023052A TL072MFKB 8102305HA ACTIVE CFP U 10 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102305HA TL072M 8102305PA ACTIVE CDIP JG 8 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102305PA TL072M 81023062A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 81023062A TL074MFKB 8102306CA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102306CA TL074MJB 8102306DA ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102306DA TL074MWB JM38510/11905BPA ACTIVE CDIP JG 8 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510 /11905BPA M38510/11905BPA ACTIVE CDIP JG 8 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510 /11905BPA PTL071HIDBVR ACTIVE SOT-23 DBV 5 3000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 PTL071HIDCKR ACTIVE SC70 DCK 5 3000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 PTL071HIDR ACTIVE SOIC D 8 3000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 PTL072HIDR ACTIVE SOIC D 8 3000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 PTL072HIPWR ACTIVE TSSOP PW 8 3000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 TL071ACD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071AC TL071ACDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071AC TL071ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071AC TL071ACP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL071ACP

www.ti.com 14-Jun-2021 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL071BCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071BC TL071BCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071BC TL071BCP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL071BCP TL071CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C TL071CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C TL071CDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C TL071CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C TL071CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL071CP TL071CPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL071CP TL071CPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T071 TL071ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL071I TL071IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL071I TL071IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL071I TL071IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL071IP TL072ACD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC TL072ACDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC TL072ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC TL072ACDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC TL072ACDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC TL072ACP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072ACP TL072ACPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072ACP

www.ti.com 14-Jun-2021 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL072BCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC TL072BCDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC TL072BCDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC TL072BCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC TL072BCDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC TL072BCP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072BCP TL072BCPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072BCP TL072CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072CP TL072CPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072CP TL072CPS ACTIVE SO PS 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPSRE4 ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPSRG4 ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPWRE4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072

www.ti.com 14-Jun-2021 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL072CPWRG4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I TL072IDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I TL072IDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I TL072IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I TL072IDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I TL072IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I TL072IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL072IP TL072IPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL072IP TL072MFKB ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 81023052A TL072MFKB TL072MJG ACTIVE CDIP JG 8 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 TL072MJG TL072MJGB ACTIVE CDIP JG 8 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102305PA TL072M TL072MUB ACTIVE CFP U 10 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102305HA TL072M TL074ACD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC TL074ACDE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC TL074ACDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC TL074ACDRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC TL074ACDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC TL074ACN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074ACN TL074ACNE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074ACN

www.ti.com 14-Jun-2021 Addendum-Page 5 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL074ACNSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074A TL074BCD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC TL074BCDE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC TL074BCDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC TL074BCDRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC TL074BCDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC TL074BCN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074BCN TL074BCNE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074BCN TL074CD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074C TL074CDBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074 TL074CDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074C TL074CDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 70 TL074C TL074CDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074C TL074CN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074CN TL074CNE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074CN TL074CNSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074 TL074CNSRG4 ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074 TL074CPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074 TL074CPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074 TL074CPWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074 TL074CPWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074

www.ti.com 14-Jun-2021 Addendum-Page 6 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL074HIDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TL074HID TL074HIPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TL074PW TL074ID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I TL074IDE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I TL074IDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I TL074IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I TL074IDRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I TL074IDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I TL074IN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL074IN TL074MFK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 TL074MFK TL074MFKB ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 81023062A TL074MFKB TL074MJ ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 TL074MJ TL074MJB ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102306CA TL074MJB TL074MWB ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102306DA TL074MWB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

www.ti.com 14-Jun-2021 Addendum-Page 7 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TL072, TL072M, TL074, TL074M :

• Catalog : TL072, TL074
• Enhanced Product : TL072-EP, TL072-EP, TL074-EP, TL074-EP
• Military : TL072M , TL074M NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2021 Pack Materials-Page 1

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL071ACDR SOIC D 8 2500 340.5 338.1 20.6 TL071BCDR SOIC D 8 2500 340.5 338.1 20.6 TL071CDR SOIC D 8 2500 853.0 449.0 35.0 TL071CDR SOIC D 8 2500 340.5 338.1 20.6 TL071CPSR SO PS 8 2000 853.0 449.0 35.0 TL071IDR SOIC D 8 2500 340.5 338.1 20.6 TL072ACDR SOIC D 8 2500 340.5 338.1 20.6 TL072BCDR SOIC D 8 2500 340.5 338.1 20.6 TL072CDR SOIC D 8 2500 853.0 449.0 35.0 TL072CDR SOIC D 8 2500 340.5 338.1 20.6 PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2021 Pack Materials-Page 2

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL072CPSR SO PS 8 2000 853.0 449.0 35.0 TL072CPWR TSSOP PW 8 2000 853.0 449.0 35.0 TL072IDR SOIC D 8 2500 853.0 449.0 35.0 TL072IDR SOIC D 8 2500 340.5 338.1 20.6 TL074ACDR SOIC D 14 2500 333.2 345.9 28.6 TL074ACNSR SO NS 14 2000 853.0 449.0 35.0 TL074BCDR SOIC D 14 2500 333.2 345.9 28.6 TL074CDBR SSOP DB 14 2000 853.0 449.0 35.0 TL074CDR SOIC D 14 2500 333.2 345.9 28.6 TL074CDRG4 SOIC D 14 2500 333.2 345.9 28.6 TL074CNSR SO NS 14 2000 853.0 449.0 35.0 TL074CPWR TSSOP PW 14 2000 853.0 449.0 35.0 TL074HIDR SOIC D 14 2500 853.0 449.0 35.0 TL074HIPWR TSSOP PW 14 2000 853.0 449.0 35.0 TL074IDR SOIC D 14 2500 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2021 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE .27 MAX GLASS .27 MAX GLASS .005 MIN TYP -.003 5X .32 .01 10X .017 .002 8X .050 .005 .045 MAX TYP .010 .002 .005 .001 .067+.013 -.012 .045 .026 CFP - 2.03 mm max heightU0010A CERAMIC FLATPACK 4225582/A 01/2020 PIN 1 ID 5 6 NOTES: 1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SCALE 1.400

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/E 09/2019 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C 14X .008-.014 [0.2-0.36]TYP -150 AT GAGE PLANE -.314 .308 -7.97 7.83 [ ] 14X -.026 .014 -1.65 1.15 [ ] .2 MAX TYP [5.08] .13 MIN TYP [3.3] TYP-.060 .015 -1.52 0.38 [ ] 4X .005 MIN [0.13] 12X .100 [2.54] .015 GAGE PLANE [0.38] A -.785 .754 -19.9419.15 [ ] B -.283 .245 -7.19 6.22 [ ] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. 7 8 PIN 1 ID (OPTIONAL) SCALE 0.900 SEATING PLANE .010 [0.25] C A B

www.ti.com EXAMPLE BOARD LAYOUT ALL AROUND [0.05] MAX .002 .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING METAL (.063) [1.6] (R.002 ) TYP [0.05] 14X ( .039) [1] ( .063) [1.6] 12X (.100 ) [2.54] (.300 ) TYP [7.62] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X SEE DETAIL A SEE DETAIL B SYMM SYMM 7 8 DETAIL A SCALE: 15X SOLDER MASK OPENING METAL DETAIL B 13X, SCALE: 15X

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

MCER001A – JANUARY 1995 – REVISED JANUARY 1997 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) Seating Plane 4040107/C 08/96 0.065 (1,65) 0.045 (1,14) 0.020 (0,51) MIN 0.400 (10,16) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) MAX 0.130 (3,30) MIN 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0°–15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2

1.2 MAX

6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8)

0.05 MAX

0.05 MIN

8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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