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TIOL112 and TIOL112x IO-Link Device Transceivers with Low Residual Voltage and Integrated Surge Protection in Small Packages
1 Features
- 7-V to 36-V supply voltage
- PNP, NPN or IO-Link configurable output – IEC 61131-9 COM1, COM2 and COM3 Data Rate Support
- Functional safety-capable – Documentation available to aid in functional safety system design
- Pin-compatible with TIOL111(x) with improved performance – Low residual Voltage of 0.5 V (typical) at 200 mA – Active driver current limiting capability – Improved thermal performance of the package – Slower driver slew rates to reduce overshoots: maximum of 750 ns
- Integrated protection features for robust systems – Configurable driver overcurrent limit: 50 mA to 350 mA – Active reverse polarity protection of up to 65 V on L+, CQ and L- – Fault indicator for overcurrent, overtemperature and UVLO faults – Safe and fast demagnetization of inductive loads – Extended ambient temperature operation: –40°C to 125°C
- Integrated EMC protection on L+ and CQ – ±8 kV IEC 61000-4-2 ESD contact discharge – ±4 kV IEC 61000-4-4 electrical fast transient – ±1.2 kV/500 Ω IEC 61000-4-5 surge
- Large capacitive load driving capability
- < 2-µA CQ leakage current
- < 1.5-mA quiescent supply current
- Integrated LDO options for up to 20 mA current – TIOL1123: 3.3-V LDO – TIOL1125: 5-V LDO
- Remote wake-up indication and wake-up generation
- Small space-saving package options – 3 mm x 3 mm 10-pin VSON package: pin-compatible with TIOL111 – 2.45 mm x 1.7 mm BGA package
2 Applications
- Field Transmitters and actuators
- Factory automation
- Process automation
- IO-link PHY in remote IO
3 Description
The TIOL112(x) family of transceivers implements the IO-Link interface for industrial bidirectional, point-to- point communication. When the device is connected to an IO-Link master through a three-wire interface, the master can initiate communication and exchange data with the remote node while the TIOL112(x) acts as a complete physical layer for the communication. These devices are capable of withstanding up to 1.2 kV (500 Ω) of IEC 61000-4-5 surge and feature integrated reverse polarity protection. A simple pin- programmable interface allows easy interfacing with the controller circuits. The output current limit can be configured using an external resistor. TIOL112(x) can be configured to generate wake-up pulse and be used in IO-link master applications. Fault reporting and internal protection functions are provided for undervoltage, overcurrent and overtemperature conditions. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) TIOL112(2) VSON (10) 3.00 mm x 3.00 mmTIOL1123 TIOL1125(2) TIOL112 DSBGA (12)(2) 2.45 mm x 1.70 mm TIOL1123 (1) For all available devices, see the orderable addendum at the end of the data sheet. (2) Advanced Information 1 µF 10 V Microcontroller 0.1 µF 100 V 10 k 10 k Sensor Front-End IO-Link Master PHY VOLTAGE REGULATOR DIAGNOSTICS & CONTROL CONTRO L LOGIC ILIM_ADJ CUR_OK EN TX PWR_OK CQ TMP_OK WAKE RX NFAULT Rev. Polarity Protection Rev. Polarity Protection ESD and Surge Protection ESD and Surge Protection VCC_OUT Typical Application Diagram TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
12.1 Receiving Notification of Documentation Updates..26
13 Mechanical, Packaging, and Orderable
4 Revision History
February 2022 * Initial release TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 www.ti.com
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5 Pin Configuration and Functions
ILIM_ADJ CQ WAKEVCC_IN Figure 5-1. TIOL112 DRC (VSON), 10-Pin (Top View) Thermal Pad 6EN TX RX NFAULT ILIM_ADJ CQ WAKEVCC_OUT Figure 5-2. TIOL1123, TIOL1125 DRC (VSON), 10-Pin (Top View) Table 5-1. Pin Functions (VSON Package) PIN NO PIN NAME TYPE DESCRIPTION TIOL112 TIOL1123 TIOL1125 1 VCC_IN VCC_OUT P VCC_IN (TIOL112): External 3.3-V or 5-V logic supply input pin. VCC_OUT (TIOL1123, TIOL1125): 3.3-V or 5-V linear regulator output 2 NFAULT NFAULT O Fault indicator output signal to the microcontroller. A low level indicates either an over- current, an undervoltage supply or an overtemperature condition.
3 RX RX O Receive data output to the local microcontroller
4 TX TX I Transmit data input from the local microcontroller. No effect if EN is low. Logic high sets low-side switch. Logic low sets high-side switch. Weak internal pull-up. 5 EN EN I Driver enable input signal from the local microcontroller. Logic low sets the CQ output at Hi-Z. Weak internal pull-down. 6 ILIM_ADJ ILIM_ADJ I Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and L-.
7 L- L- GND IO-Link ground potential
8 CQ CQ I/O IO-Link data signal (bidirectional)
9 L+ L+ P IO-Link supply voltage (24 V nominal)
10 WAKE WAKE O Wake-up indicator to the local microcontroller. Open-drain output, connect this pin via pull-up resistor to VCC_IN/OUT. Thermal Pad Thermal Pad — Connect to L- for optimal thermal and electrical performance www.ti.com TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TIOL112 TIOL1123 TIOL1125
_ADJ L- VCC_ OUT WAKEVSEL NFAU LT RX TX EN 1 2 3 A B C D Figure 5-3. TIOL1123 YAH (DSBGA), 12-Pin (Top View) L- CQ L+ ILIM _ADJ L- VCC_ IN WAKENC NFAU LT RX TX EN 1 2 3 A B C D Figure 5-4. TIOL112 YAH (DSBGA), 12-Pin (Top View) Table 5-2. Pin Functions (DSBGA) PIN NO PIN NAME TYPE DESCRIPTION TIOL112 TIOL1123 B3 VCC_IN VCC_OUT P VCC_IN (TIOL112): External 3.3-V or 5-V logic supply input pin. VCC_OUT (TIOL1123): 3.3-V or 5-V linear regulator output C3 NFAULT NFAULT O Fault indicator output signal to the microcontroller. A low level indicates either an over- current, an undervoltage supply or an overtemperature condition. D1 RX RX O Receive data output to the local controller D2 TX TX I Transmit data input from the local controller. No effect if EN is low. Logic high sets low-side switch. Logic low sets high-side switch. Weak internal pull-up. D3 EN EN I Driver enable input signal from the local controller. Logic low sets the CQ output at Hi-Z. Weak internal pull-down. B1 ILIM_ADJ ILIM_ADJ O Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and L-. A1, B2 L- L- GND IO-Link ground potential A2 CQ CQ I/O IO-Link data signal (bidirectional) A3 L+ L+ P IO-Link supply voltage (24 V nominal) C1 NC VSEL I TIOL112 (NC): Leave floating. Do not connect. TIOL1123 (VSEL): Connect to GND for 5V LDO output. Please leave this pin floating for 3.3V LDO output. VSEL has an internal pull-up of 1 MΩ C2 WAKE WAKE O Wake-up indicator to the local controller. Open-drain output, connect this pin via pull-up resistor to VCC_IN/OUT. TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 www.ti.com
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage Steady state voltage for L+ and CQ –65 65 V Transient pulse width < 100 µs for L+ and CQ –70 70 V Voltage difference |V(L+) – V(CQ)| 65 V Logic supply voltage (TIOL112) VCC_IN –0.3 6 V Input logic voltage TX, EN, VSEL –0.3 min(VCC_IN+ 0.3, 6) V Output current RX, WAKE, NFAULT –5 5 mA Storage temperature, Tstg -55 170 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. All voltages are with reference to the L- pin, unless otherwise specified.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins ±4000 V V(ESD) Electrostatic discharge Charged Device Model (CDM), per ANSI/ESDA/JEDEC JS-002 (2) All pins ±750 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings - IEC Specifications
V(ESD) Electrostatic discharge IEC 61000-4-2 ESD (Contact Discharge), L+, CQ and L- (1) (2) ±8,000 VElectrostatic discharge IEC 61000-4-5, 1.2 µs/50 µs Surge with 500 Ω in series, L+, CQ and L- (1) ±1,200 Electrostatic discharge IEC 61000-4-4 EFT (Fast transient or burst), L+, CQ and L- (1) ±4,000 (1) Minimum 100-nF capacitor is required between L+ and L-. Minimum 1-µF capacitor is required between VCC_IN/VCC_OUT and L-. (2) Passing level is ±4500 V if the device is powered and EN=TX=HIGH.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V(L+) Supply voltage 7 24 36 V V(VCC_IN) Logic level input voltage (TIOL112 only) 3.3 V configuration 3 3.3 3.6 V 5 V configuration 4.5 5 5.5 V RSET External resistor for CQ current limit 0 110 kΩ 1/tBIT Data rate (Communication mode) 250 kbps I(VCC_OUT) LDO output current (TIOL112L only) 20 mA TA Operating ambient temperature –40 125 °C TJ Junction temperature 150 °C www.ti.com TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TIOL112 TIOL1123 TIOL1125
6.5 Thermal Information
THERMAL METRIC(1) TIOL112, TIOL1123, TIOL1125 TIOL112, TIOL1123 UNIT DRC (10 Pins) YAH (12 Pins) RθJA Junction-to-ambient thermal resistance 45.9 79.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 45.9 0.3 °C/W RθJB Junction-to-board thermal resistance 17.9 19.5 °C/W ψJT Junction-to-top characterization parameter 0.7 0.1 °C/W ψJB Junction-to-board characterization parameter 17.8 19.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 4.7 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.6 Electrical Characteristics
Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical values are at L+ = 24 V, VVCC_IN = 3.3 V, VVCC_OUT = 3.3 V and TA = 25 ℃ unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (L+) I(L+) Quiescent supply current EN = LOW, no load 1 1.5 mA EN = HIGH, no load 2 2.95 mA LOGIC-LEVEL INPUTS (EN, TX, VSEL) VIL Input logic low voltage 0.8 V VIH Input logic high voltage 2 V RPD Pull-down (EN) resistance 100 kΩ RPU Pull-up (TX) resistance 200 kΩ RPU Pull-up (VSEL) resistance 1000 kΩ CONTROL OUTPUTS (WAKE, NFAULT) VOL Output logic low voltage IO = 4 mA 0.5 V IOZ Output high impedance leakage Output in Hi-Z, VO = 0 V or VCC_IN/OUT –1 1 µA DRIVER OUTPUT (CQ) RDS(ON) High-side driver on-resistance 2.5 4.5 Ω VDS(ON) High-side driver residual voltage I = 200 mA 0.5 0.9 V I = 100 mA 0.25 0.5 V RDS(ON) Low-side driver on-resistance 2.5 4.5 Ω VDS(ON) Low-side driver residual voltage I = 200 mA 0.5 0.9 V I = 100 mA 0.25 0.5 V IOZ(CQ) CQ leakage EN = LOW, 0 ≤ V(CQ) ≤ (V(L+) - 0.1 V) –2 2 µA ILLM CQ load discharge current EN = LOW, RSET = 0 to 5 kΩ (2), V(CQ) >= 5 V 5 15 mA IO(LIM) Driver output current limit RSET = 110 kΩ; V(CQ)= (VL+ - 3) V or 3 V 35 50 70 mA RSET = 10 kΩ 300 350 400 mA RSET = 0 to 5 kΩ (2) V(CQ)= (VL+ - 3) V or 3 V TJ < T(SDN) or t < 200 µs (3) 500 mA (Fast-detect mode) RSET = OPEN(1)V(CQ)= (VL+ - 3) V or 3 V 260 330 400 mA RECEIVER INPUT (CQ) V(THH) Input threshold “H” V(L+) > 18 V, EN= LOW 10.5 13 V V(THL) Input threshold “L" 8 11.5 V V(HYS) Receiver Hysteresis (V(THH) - V(THL)) 0.75 V V(THH) Input threshold “H” V(L+) < 18 V, EN= LOW See Note (4) See Note (5) V TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 www.ti.com
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6.6 Electrical Characteristics (continued)
Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical values are at L+ = 24 V, VVCC_IN = 3.3 V, VVCC_OUT = 3.3 V and TA = 25 ℃ unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(THL) Input threshold “L" V(L+) < 18 V, EN= LOW See Note (6) See Note (7) V V(HYS) Receiver Hysteresis (V(THH) - V(THL)) 0.75 V VOL RX output low voltage IOL = 4 mA 0.4 V VOH RX output high voltage IOL = –4 mA VCC_IN/ OUT–0.5 V PROTECTION CIRCUITS V(UVLO) L+ under voltage lockout L+ falling; NFAULT = Hi-Z 6 6.3 V L+ rising; NFAULT = LOW 6.5 6.8 V V(UVLO,HYS) L+ under voltage hysteresis Rising to falling threshold 200 mV V(UVLO_IN) VCC_IN under voltage lockout (No LDO option) VCC_IN falling; NFAULT = Hi-Z 2.3 V VCC_IN rising; NFAULT = LOW 2.5 V V(UVLO,HYS) VCC_IN under voltage hysteresis (No LDO option) Rising to falling threshold 190 mV T(WRN) Thermal warning Die temperature TJ 125 °C T(SDN) Thermal shutdown 150 160 °C T(HYS) Thermal hysteresis for shutdown 14 °C T(WRN) Thermal hysteresis for warning Die temperature TJ Die temperature TJ 14 °C IREV Leakage current in reverse polarity EN=LOW, TX=x; V(CQ) < V(L-) or V(CQ) > V(L+), up to |36 V| 60 µA EN=LOW, TX=x; V(CQ) < V(L-) or V(CQ) > V(L+), up to |65 V| 110 µA EN = HIGH, TX = LOW; V(CQ to L+) = 3 V 640 µA EN = HIGH, TX = HIGH; V(CQ to L-) = -3 V 10 µA LINEAR REGULATOR (LDO) V(VCC_OUT) Voltage regulator output TIOL1125 4.75 5 5.25 V TIOL1123 3.13 3.3 3.46 V V(DROP) Voltage regulator drop-out voltage (V(L+) – V(VCC_OUT)) ICC = 20 mA load current TIOL1125 0.75 1.9 V TIOL1123 0.75 2.3 V REG Line regulation (dV(VCC_OUT)/ dV(L+)) I(VCC_OUT) = 1 mA 1.7 mV/V LREG Load regulation (dV(VCC_OUT)/ V(VCC_OUT)) V(L+) = 24 V, I(VCC_OUT) = 100 µA to 20 mA 1% PSSR Power Supply Rejection Ratio 100 kHz, I(VCC_OUT) = 20 mA 40 dB (1) Current fault indication will be active. Current fault auto recovery will be de-activated. (2) Current fault indication and current fault auto recovery will be de-activated. (3) If operating continuosly with this current limit, ensure that the current through the device does not cause the TJ to be greater than T(SDN) for a given ambient temperature and thermal porperty of the system. For pulse durations t < 200 µs, the device can source or sink current of at least 500 mA across the recommended operating conditions. (4) VTHH (min) = 5 V + (11/18) [V(L+) - 8 V] (6) VTHL (min) = 4 V + (8/18) [V(L+) -8 V] (7) VTHL (max) = 6 V + (11/18) [V(L+) -8 V] www.ti.com TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TIOL112 TIOL1123 TIOL1125
6.7 Switching Characteristics
Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical values are at L+ = 24 V, VVCC_IN = 3.3 V, VVCC_OUT = 3.3 V and TA = 25 ℃ unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DRIVER tPLH, tPHL Driver propagation delay See Figure 7-1 See Figure 7-2 See Figure 7-3 RL = 2 kΩ CL = 5 nF R(SET) = 10 kΩ 600 1200 ns tP(skew) Driver propagation delay skew. |tPLH - tPHL | 75 ns tPZH, tPZL Driver enable delay 4 µs tPHZ, tPLZ Driver disable delay 4 µs tr, tf Driver output rise, fall time 200 700 ns |tr – tf| Difference in rise and fall time 50 ns tWU1 Wake-up recognition begin See Figure 7-5 45 60 75 µs tWU2 Wake-up recognition end 85 100 145 µs tpWAKE Wake-up output delay 150 µs tSC Current fault blanking time 175 200 µs tpSC Current fault indication delay 280 µs tWUL Wake output pulse duration on wake detection in EN=L mode See Figure 7-6 175 225 285 µs tSCEN Current fault driver re-enable wait time 15 ms t(UVLO) CQ re-enable delay after UVLO (1) V(UVLO) rising threshold crossing time to CQ enable time 10 30 50 ms RECEIVER tND Noise suppression time (2) 250 ns tPLH, tPHL Receiver propagation delay See Figure 7-4 15-pF load on RX, 150 300 ns (1) CQ output remains Hi-Z for this time (2) Noise suppression time is defined as the permissible duration of a receive signal above/below the detection threshold without detection taking place. TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 www.ti.com
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6.8 Typical Characteristics
L+ Supply Voltage (V) L+ Supply Current (mA) 6 9 12 15 18 21 24 27 30 33 36 39 0.8 1.2 1.4 1.6 1.8 2.2 2.4 2.6 EN=L EN=H No Load TX = Open TA = 25°C Figure 6-1. Supply Current vs Supply Voltage Load Current (mA) Driver Residual Voltage (V) 0 25 50 75 100 125 150 175 200 225 250 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 T A = -40 C T A = 25 C T A = 125 C spacer Figure 6-2. Residual Voltage vs Load Current: High Side Load Current (mA) Driver Residual Voltage (V) 0 25 50 75 100 125 150 175 200 225 250 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 T A = -40 C T A = 25 C T A = 125 C spacer Figure 6-3. Residual Voltage vs Load Current: Low Side R SET (k ) Driver Current Limit (mA) 0 10 20 30 40 50 60 70 80 90 100 110 100 200 300 400 500 600 700 800 For R SET below 5 k , TIOL112(x) can generate wake-up pulse and enables CQ load discharge current (I LLM ) High-side Low-side For RSET in the 0-5 kΩ range, TIOL112(x) can source/sink 500 mA required for wake-up pulse generation in IO-link applications. For RSET in the 0-5 kΩ range, TIOL112(x) also activates a pull-down current source (ILLM) when the driver is disabled. TA = 25°C Figure 6-4. Current Limit vs RSET L+ (V) Receiver Threshold (V) 7 11 15 19 23 27 31 35 VTHH VTHL TA = 25°C Figure 6-5. Receiver Threshold Boundaries R SET (k ) Driver Current Limit (mA) 0 10 20 30 40 50 60 70 80 90 100 110 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 TIOL112 TIOL111 TA = 25°C Figure 6-6. Current limit vs RSET: TIOL112(x) vs TIOL111(x) www.ti.com TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TIOL112 TIOL1123 TIOL1125
7 Parameter Measurement Information
Copyright © 2016, Texas Instruments Incorporated Figure 7-1. Test Circuit for Driver Switching tr tf VOH VOL 80% 20% 80% 20% TX CQ 50% 50% tPHL tPLH VOL VOH VOL CQ VOH CQ Figure 7-2. Waveforms for Driver Output Switching Measurements EN CQ 50% 50% tPZL tPLZ 20% EN CQ 50% 50% tPZH tPHZ 80% V(L+) / 2 VOH TX = LOWTX = HIGH VOL V(L+) / 2 Figure 7-3. Waveforms for Driver Enable or Disable Time Measurements CQ RX 50% 50% tPLH tPHL Figure 7-4. Receiver Switching Measurements TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 www.ti.com
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8 Detailed Description
8.1 Overview
Figure 8-1 shows that the TIOL112 or TIOL112x driver output (CQ) can be used in either push-pull, high-side, or low-side configuration using the enable (EN) and transmit data (TX) input pins. The internal receiver converts the 24-V signal on the CQ line to standard logic levels on the receive data (RX) pin. A simple parallel interface is used to receive/transmit data and status information between the device and the local controller. These devices have integrated IEC 61000-4-4/5 EFT and surge protection. In addition, tolerance to ±70-V transients enables flexibility to choose from a wider range of TVS diodes if an application requires higher levels of protection. These integrated robustness features will simplify the system level design by reducing external protection circuitry. TIOL112 or TIOL112x transceivers implement protection features for overcurrent, overvoltage and over- temperature conditions. The devices also provide a current-limit setting of the driver output current using an external resistor. The devices derive the low-voltage supply from the IO-Link L+ voltage (24 V nominal) via an internal linear regulator to provide power to the local controller and sensor circuitry.
8.2 Functional Block Diagrams
& CONTROL CONTRO L LOGIC ILIM_ADJ CUR_OK EN TX PWR_OK CQ TMP_OK WAKE RX NFAULT Rev. Polarity Protection Rev. Polarity Protection ESD and Surge Protection ESD and Surge Protection VCC_IN Figure 8-1. Block Diagram TIOL112 TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 www.ti.com
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& CONTROL CONTRO L LOGIC ILIM_ADJ CUR_OK EN TX PWR_OK CQ TMP_OK WAKE RX NFAULT Rev. Polarity Protection Rev. Polarity Protection ESD and Surge Protection ESD and Surge Protection VCC_OUT VSEL (YAH package only) Figure 8-2. Block Diagram TIOL1123, TIOL1125
8.3 Feature Description
8.3.1 Wake-Up Detection
The TIOL112(x) may be operated in IO-Link mode or Standard Input / Output (SIO) mode. If the device is in SIO mode and the IO-link master node wants to initiate communication with the device node, the master drives the CQ line to the opposite of its present state, and will either sink or source the current ( ≥ 500 mA) for the wake-up duration (typically 80 μs) depending on the CQ logic level as per the IO-Link specification. The TIOL112(x) detects this as a wake-up condition and communicates to the local microcontroller via the WAKE pin. The IO-Link communication specification requires the device node to switch to receive mode within 500 μs after receiving the wake-up signal. For overcurrent conditions shorter or longer than a valid wake-up pulse, the WAKE pin remains in a high- impedance (inactive) state. This is illustrated in Figure 7-5. If the driver of TIOL112(x) is disabled (EN = L), any change in CQ logic level for duration t WU1 < t < t WU2 is detected as a wake-up event and WAKE asserts low for the duration of t WUL. This is illustrated in Figure 7-6. Please refer to Table 8-4 for the summary of the conditions for Wake-Up detection.
8.3.2 Current Limit Configuration
The output current can be configured with an external resistor on ILIM_ADJ pin. The highest current limit setting with an external resistor of 10 k Ω provides a minimum of 300 mA over the operating temperature and voltage range. Output disable due to current fault and current fault auto recovery features can be disabled by floating ILIM_ADJ pin. However, the current fault indication is still active in this configuration. This feature is useful when driving large capacitances. When ILIM_ADJ pin is shorted to ground, the TIOL112(x) is configured to be in the IO-link master mode. In this mode, the TIOL112(x) can source or sink minimum of 500 mA to generate a wake-up request. In addition, the TIOL112(x) enables a small current sink of 5 mA (minimum). The current fault indication, output disable, and auto recovery features are disabled in this mode. www.ti.com TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TIOL112 TIOL1123 TIOL1125
Table 8-1. Current Limit Configuration ILIM_ADJ Pin Condition CQ Current Limit (Min.) NFAULT Indication During Fault Output Disable and Auto Recovery RSET resistor to L- (10 kΩ to 110 kΩ) Variable (35 mA to 300 mA) Yes Yes Connected to L- (RSET 0 to 5 kΩ) 500 mA No No OPEN 260 mA Yes No
8.3.3 Current Fault Detection, Indication and Auto Recovery
If the output current at CQ exceeds the internally-set current limit I O(LIM) for a duration longer than t SC, the NFAULT pin is driven logic low to indicate a fault condition. The output is turned off, but the LDO continues to function. The output periodically retries to check if the output is still in the over current condition. In this mode, the output is switched on for t SC in tSCEN intervals. Current fault auto recovery mode can be disabled by setting ILIM_ADJ = OPEN. See Table 8-5. Toggling EN will clear NFAULT.
8.3.4 Thermal Warning, Thermal Shutdown
If the die temperature exceeds T (WRN), the NFAULT flag is held low indicating a potential over temperature problem. When the T J exceeds T(SDN), The output is disabled but the LDO remains operational. As soon as the temperature drops below the temperature threshold (and after T (HYS)), the internal circuit re-enables the driver, subject to the state of the EN and TX pins.
8.3.5 Fault Reporting (NFAULT)
NFAULT is driven low if either a current fault condition is detected, die temperature has exceeded T (WRN) or supply has dropped below the UVLO threshold. NFAULT returns to high-impedance as soon as all three fault conditions clear. NFAULT = [CUR_OK && PWR_OK && TMP_OK] T < T WRN & EN* T > TWRN CQ @ ILIM for tWU1 < t < tWU2 CQ @ ILIM for t > tSC CQ NOT @ ILIM Wake WAKE = L CUR_OK = Z Driver = ON LDO = ON Receive Only CUR_OK = Z WAKE = Z Driver = OFF LDO = ON Receive and Transmit CUR_OK = Z WAKE = Z Driver = ON LDO = ON Current Fault WAKE = Z CUR_OK = L Driver = OFF LDO=ON Thermal Warning CUR_OK = Z TMP_OK = L WAKE = Z Driver = EN/EN* LDO = ON t>tWUL EN* CQ @ I LIMfor t > t SC EN* T > T WRN EN T > T WRN T > TWRN Thermal Shutdown CUR_OK = Z TMP_OK = L WAKE = Z Driver = OFF LDO = ON T > TSD T < (TSD + THYS) T < T WRN & EN Current Fault Recovery WAKE = Z CUR_OK = L Driver = ON for tsc LDO=ON t = tSCEN CQ @ ILIM T < TWRN & Current Fault Receive Only-Wake CUR_OK = Z WAKE = L for tWUL Driver = OFF LDO = ONCQ pulse width tWU1 < t < t WU2 Figure 8-3. Device State Diagram TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 www.ti.com
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8.3.6 Transceiver Function Tables
Table 8-2. Driver Function EN TX CQ COMMENT L / Open X Hi-Z Device is in ready-to-receive state H L H CQ is sourcing current (high-side drive) H H / Open L CQ is sinking current (low-side drive) Table 8-3. Receiver Function CQ VOLTAGE RX COMMENT V(CQ) < V(THL) H Normal receive mode, input low V(THL) < V(CQ) < V(THH) ? Indeterminate output, may be either high or low V(THH) < V(CQ) L Normal receive mode, input high Open ? Indeterminate output, may be either high or low Table 8-4. Wake-Up Function (tWU1 < t < tWU2) EN TX CQ CURRENT WAKE COMMENT L / Open X X Asserts low for tWUL Device asserts low for tWUL if RX output changes high- to-low or low-to-high for tWU1 < t < tWU2 H H / Open | I(CQ) | ≥ 500 mA L Device receives high-level wake-up request over the IO-Link bus H L | I(CQ) | ≥ 500 mA L Device receives low-level wake-up request over the IO-Link bus Table 8-5. Current Limit Indicator Function (t > tSC) EN TX CQ CURRENT NFAULT COMMENT H H / Open | I(CQ) | > IO(LIM) L CQ current exceeds the set limit for over tSC | I(CQ) | < IO(LIM) Z Normal operation H L | I(CQ) | > IO(LIM) L CQ current exceeds the set limit for over tSC | I(CQ) | < IO(LIM) Z Normal operation L / Open X X Z Driver is disabled, Current limit indicator is inactive Note Current limit indicator function is disabled when ILIM_ADJ is connected to GND (or RSET < 5 kΩ
8.3.7 The Integrated Voltage Regulator (LDO)
The TIOL1123 and TIOL1125 each have an integrated linear voltage regulator (LDO) which can supply power to external components. The voltage regulator is specified for L+ voltages in the range of 7 V to 36 V with respect to L-. The LDO is capable of delivering up to 20 mA. In the DSBGA (YAH) package, TIOL1123 offers pin-configurable LDO output via VSEL pin. When VSEL is connected to GND, VCC_OUT is configured to provide a 5-V output. When VSEL is left floating, VCC_OUT provides a 3.3-V output. Table 8-6. LDO Output Configuration via VSEL pin (YAH Package) VSEL pin connection VCC_OUT Connected to L- 5 V Floating 3.3 V www.ti.com TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TIOL112 TIOL1123 TIOL1125
The LDO is designed to be stable with standard ceramic capacitors with values of 1 μF or larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR should be less than 1 Ω. With tolerance and dc bias effects, the minimum capacitance to ensure stability is 1 μF. The voltage regulator has an internal 35-mA current limit to protect against initial startup inrush current due to large decoupling capacitors and accidental short circuit conditions. TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 www.ti.com
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8.3.8 Reverse Polarity Protection
Reverse polarity protection circuitry protects the devices against accidental reverse polarity connections to the L+, CQ and L- pins. The maximum voltage between any of the pins may not exceed 65 V DC at any time. Figure 8-4 and Figure 8-5 shows all the possible connection combinations. TIOL112(x) CQ DC RL CQ DC RL TIOL112(x) CQ DC RL CQ DC RL TIOL112(x) CQ DC RL CQ DC RL Correct Con gura on TIOL112(x) TIOL112(x) TIOL112(x) Reverse Polarity Protected Fault Condi on Reverse Polarity Protected Fault Condi on Reverse Polarity Protected Fault Condi on Reverse Polarity Protected Fault Condi on Reverse Polarity Protected Fault Condi on Figure 8-4. High-Side Driver Configuration www.ti.com TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TIOL112 TIOL1123 TIOL1125
TIOL112(x) CQ DC RL CQ DC RL TIOL112(x) CQ DC RL CQ DC RL TIOL112(x) CQ DC RL CQ DC RL Correct Con gura on TIOL112(x) TIOL112(x) TIOL112(x) Reverse Polarity Protected Fault Condi on Reverse Polarity Protected Fault Condi on Reverse Polarity Protected Fault Condi on Overcurrent Fault Protec on Condi on Reverse Polarity Protected Fault Condi on Figure 8-5. Low-Side Driver Configuration TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 www.ti.com
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8.3.9 Integrated Surge Protection and Transient Waveform Tolerance
The L+ and CQ pins of the device are capable of withstanding up to 1.2 kV of 1.2/50 – 8/20 μs IEC 61000-4-5 surge with a source impedance of 500 Ω. The surge testing should be performed with a minimum 100 nF supply decoupling capacitor between L+ and L-, and 1 µF between VCC_IN/OUT and L-. External TVS diodes may be required for higher transient protection levels. The system designer should ensure that the maximum clamping voltage of the external diodes should be < 65 V at the desired current level. The device is capable of withstanding up to ±70-V transient pulses < 100 µs. Decoupling Network R EUT CQ > 100 nF Combination wave Generator Protection Equipment Auxiliary Equipment 1.2/50 – 8/20 µs CWG R = 500 Ω Figure 8-6. Surge Test Setup
8.3.10 Power Up Sequence (TIOL112)
VCC_IN and L+ domains can be powered up in any sequence. In the event of L+ is powered and VCC_IN is not, the CQ pin will remain in high impedance.
8.3.11 Undervoltage Lock-Out (UVLO)
The device enters UVLO if the L+ voltage falls below V (UVLO). (For the device without the integrated LDO, the device monitors VCC_IN in addition to L+. UVLO happens if either supply falls below the threshold.) As soon as the supply falls below V(UVLO), NFAULT is pulled low, and the driver (CQ) is disabled (Hi-Z). Receiver performance is not specified in this mode. When the supply rises above V (UVLO), NFAULT returns to Hi-Z (given no other fault conditions present). The CQ output is turned on after t(UVLO) delay. www.ti.com TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TIOL112 TIOL1123 TIOL1125
8.4 Device Functional Modes
These devices can operate in three different modes.
8.4.1 NPN Configuration (N-Switch SIO Mode)
Set TX pin high (or open) and use EN pin as control for realizing the function of an N-switch (low-side configuration) on CQ.
8.4.2 PNP Configuration (P-Switch SIO Mode)
Set TX pin low and use EN pin as control for realizing the function of a P-switch (high-side configuration) on CQ.
8.4.3 Push-Pull, Communication Mode
Set EN pin high and toggle TX as control for realizing the function of a push-pull output on CQ. Table 8-7, Table 8-8 and Table 8-9 summarize the pin configurations to accomplish the functional modes. Table 8-7. NPN Mode EN TX CQ L / Open H / Open Hi-Z H H / Open N-Switch Table 8-8. PNP Mode EN TX CQ L / Open L Hi-Z H L P-Switch Table 8-9. Push-Pull, Communication Mode EN TX CQ L / Open X Hi-Z H H N-Switch H L P-Switch TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 www.ti.com
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9 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
9.1 Application Information
When TIOL112(x) is connected to an IO-Link master through a three-wire interface ( Figure 9-1), the master can initiate communication and exchange data with a remote node with the TIOL112(x) IO-Link transceiver acting as a complete physical layer for the communication.
9.2 Typical Application
1 µF 10 V Microcontroller 0.1 µF 100 V 10 k 10 k Sensor Front-End IO-Link Master PHY VOLTAGE REGULATOR DIAGNOSTICS & CONTROL CONTRO L LOGIC ILIM_ADJ CUR_OK EN TX PWR_OK CQ TMP_OK WAKE RX NFAULT Rev. Polarity Protection Rev. Polarity Protection ESD and Surge Protection ESD and Surge Protection VCC_OUT Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements
TIOL112 and TIOL112x IO-Link transceivers can be used to communicate using the IO-Link protocol, or as standard digital outputs to either sense or drive a wide range of sensors and loads. Table 9-1 shows recommended components for a typical system design. Table 9-1. Design Parameters PARAMETERS Design Requirement TIOL112(x) Specification Input voltage range (L+) 24 V (typ), 30 V (max) 7 V to 36 V Output current (CQ) 200 mA Choose 250 mA limit with RSET = 27 kΩ LDO Output voltage 5 V Choose TIOL1125; VCC_OUT = 5 V LDO output current 5 mA I(VCC_OUT): Up to 20 mA Pull-up resistors for NFAULT and WAKE 10 kΩ 10 kΩ L+ decoupling capacitor 0.1 µF / 100 V 0.1 µF / 100 V LDO output capacitor 1 µF / 10 V 1 µF / 10 V Maximum Ambient Temperature, TA 105 °C TIOL112 can support up to TA of 125 °C if TJ < T(SDN) www.ti.com TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TIOL112 TIOL1123 TIOL1125
9.2.2 Detailed Design Procedure
9.2.2.1 Maximum Junction Temperature Check
For a 200 mA current limit:
- Choose driver output current limit, IO(LIM) = 250 mA (allowing for current limit tolerance); RSET = 27 kΩ
- The maximum voltage drop across the high-side switch at 250 mA current is VDS(ON) = 1.1 V. This causes a power consumption of: PD O P = V DS ON × I O L I M = 1.1 V × 250 m A = 275 m W (1) For a 5 mA LDO current output, PD L DO = V L + − V VC C OU T × I VC C _ OU T = 30 − 5 V × 5 m A = 125 m W (2) Total power dissipation, PD = PD LD O + PD OP = 275 m W + 125 m W = 400 m W (3) Multiply this value with the Junction-to-ambient thermal resistance of θJA = 45.9 °C/W (taken from the Thermal Information table) to receive the difference between junction temperature, TJ, and ambient temperature, TA: ∆ T = T J − T A = PD × θ J A = 400 m W × 45.9 ℃ W = 18.36 ℃ (4) Add this value to the maximum ambient temperature of TA = 105°C to receive the final junction temperature: T J = T A + ∆ T = T A + PD × θ J A = 105 ℃ + 400 mW × 45.9 ℃ W = 105 ℃ + 18.36 ℃ = 123.36 ℃ (5) As long as T J is below the recommended maximum value of 150°C, no thermal shutdown will occur. However, the junction temperature is closer to T WRN and thermal warning may be generated if the junction temperature rises above TWRN. Note that the modeling of the complete system may be necessary to predict junction temperature in smaller PCBs and/or enclosures without air flow.
9.2.2.2 Driving Capacitive Loads
These devices are capable of driving capacitive loads on the CQ output. Assuming a pure capacitive load without series/parallel resistance, the maximum capacitance that can be charged without triggering current fault can be calculated as: SCO LIM LOAD L I x [ ] t C V (6) To drive higher capacitive loads and avoid overcurrent condition disabling the driver, it is recommended leave ILIM_ADJ pin floating. With ILIM_ADJ floating, TIOL112(x) indicates overcurrent fault without blanking time delay (tSC) but does not disable the driver. Another approach is to drive high capacitive loads with a series resistor between the CQ output and the load to avoid overcurrent condition. Capacitive loads can be connected to L- or L+.
9.2.2.3 Driving Inductive Loads
The TIOL112(x) family is capable of magnetizing and demagnetizing large inductive loads. These devices contain internal circuitry that enables fast and safe demagnetization when configured as either P-switch or N-switch mode. TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 www.ti.com
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In P-switch configuration, the load inductor L is magnetized when the CQ output is driven high. When the PNP is turned off, there is a significant amount of negative inductive kick back at the CQ pin. This voltage is safely clamped internally at about -15 V. Similarly, in N-switch configuration, the load inductor L is magnetized when the CQ output is driven low. When the NPN is turned off, there is a significant amount of positive inductive kick back at the CQ pin. This voltage is safely clamped internally at about 15 V. The equivalent protection circuits are shown in Figure 9-2 and Figure 9-3. The minimum value of the resistive load R can be calculated as: L )O LIM ( V R I (7) L R CQ L+Rev. Polarity Protection Rev. Polarity Protection ESD and Surge Protection ESD and Surge Protection Figure 9-2. P-Switch Mode L R CQ L+Rev. Polarity Protection Rev. Polarity Protection ESD and Surge Protection ESD and Surge Protection L- Figure 9-3. N-Switch Mode www.ti.com TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TIOL112 TIOL1123 TIOL1125
9.2.3 Application Curves
6 V/div300 mA/div4 V/div
Figure 9-4. CQ in Current Fault Auto Recovery, Low Side Mode Figure 9-5. CQ in Current Fault Auto Recovery, High Side Mode NFAULT is indicated for the duration of charging and discharging of the capacitor but driver is not disabled when ILIM_ADJ is floating L+ = 24 V CL = 20 µF RL = 100 Ω RSET = 1 MΩ (ILIM_ADJ Floating) TA = 25 °C Figure 9-6. CQ Driving Capacitive Load, Push-Pull Mode
10 Power Supply Recommendations
The TIOL112 and TIOL112x transceivers are designed to operate from a 24-V nominal supply at L+, which can vary by +12 V and -17 V from the nominal value to remain within the device's recommended supply voltage range of 7 V to 36 V. This supply should be buffered with at least a 100-nF/100-V capacitor. TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 www.ti.com
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11 Layout
11.1 Layout Guidelines
- Use of a 4-layer board is recommended for good heat conduction. Use layer 1 (top layer) for control signals, layer 2 as power ground layer for L-, layer 3 for the 24-V supply plane (L+), and layer 4 for the regulated output supply (VCC_IN/OUT).
- Connect the thermal pad to L- with maximum amount of thermal vias for best thermal performance.
- Use entire planes for L+, VCC_IN/OUT and L- to assure minimum inductance.
- The L+ terminal must be decoupled to ground with a low-ESR ceramic decoupling capacitor. The recommended minimum capacitor value is 100 nF. The capacitor must have a voltage rating of 50 V minimum (100 V depending on max sensor supply fault rating) and an X5R or X7R dielectric.
- The optimum placement of the capacitor is closest to the transceiver’s L+ and L- terminals to reduce supply drops during large supply current loads. See Figure 11-1 for a PCB layout example.
- Connect all open-drain control outputs via 10 kΩ pull-up resistors to the VCC_IN/OUT plane to provide a defined voltage potential to the system controller inputs when the outputs are high-impedance.
- Connect the RSET resistor between ILIM_ADJ and L-.
- Decouple the regulated output voltage at VCC_IN/OUT to ground with a low-ESR, ≥ 1-μF, ceramic decoupling capacitor. The capacitor should have a voltage rating of 10 V minimum and an X5R or X7R dielectric.
11.2 Layout Example
VIA to Layer 2: Power Ground Plane (L-) VIA to Layer 3: 24V Supply Plane (L+) VIA to Layer 4: Regulated Supply Plane (VCC_IN/OUT) CQ CQ TX EN ILIM_ADJ VCC_IN/OUT Use Multiple Vias for L+ and L- Figure 11-1. Layout Example www.ti.com TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TIOL112 TIOL1123 TIOL1125
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TIOL112, TIOL1123, TIOL1125 SLLSFJ1 – FEBRUARY 2022 www.ti.com
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www.ti.com 27-Feb-2022 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTIOL1125DRCR ACTIVE VSON DRC 10 5000 TBD Call TI Call TI -40 to 125 PTIOL112DRCR ACTIVE VSON DRC 10 5000 TBD Call TI Call TI -40 to 125 TIOL1123DRCR ACTIVE VSON DRC 10 5000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1123 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
www.ti.com 27-Feb-2022 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 25-Feb-2022 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TIOL1123DRCR VSON DRC 10 5000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 25-Feb-2022 Pack Materials-Page 2
www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VSON - 1 mm max heightDRC 10 PLASTIC SMALL OUTLINE - NO LEAD3 x 3, 0.5 mm pitch 4226193/A
www.ti.com PACKAGE OUTLINE C 10X 0.3 0.2 2.4 2.2 1.75 1.55 8X 0.5 1.0 0.8 10X 0.5 0.3 0.05 0.00 A 3.1 2.9 B 3.1 2.9 (0.2) TYP 4X (0.25) 2X (0.5) VSON - 1 mm max heightDRC0010V PLASTIC SMALL OUTLINE - NO LEAD 4226575/A 02/2021 PIN 1 INDEX AREA SEATING PLANE 0.08 C 5 6 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED SYMM SYMM11 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND0.07 MAX ALL AROUND 10X (0.24) (2.3) (2.8) 8X (0.5) (1.65) (0.2) TYP VIA (0.575) (0.9) 10X (0.6) (R0.05) TYP (3.4) (0.25) (0.5) VSON - 1 mm max heightDRC0010V PLASTIC SMALL OUTLINE - NO LEAD 4226575/A 02/2021 SYMM 5 6 LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 11SYMM NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP (0.61) 10X (0.24) 10X (0.6) 2X (1.51) (1.02) (2.8) 8X (0.5) (0.5) 4X (0.34) 4X (0.25) (1.53) VSON - 1 mm max heightDRC0010V PLASTIC SMALL OUTLINE - NO LEAD 4226575/A 02/2021 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 5 6 EXPOSED METAL TYP SYMM
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