THVD2419 TI | Alldatasheet
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Technical content
THVD24x9 3V to 5.5V RS-485 Transceivers With Integrated Surge and High Bus-Fault Protection in Small Packages
1 Features
- Meets or exceeds the requirements of the TIA/ EIA-485A standard
- 3V to 5.5V Supply Voltage
- Industry's smallest surge-integrated RS-485 device in 9mm2 package
- VIO Support from 1.65V to VCC supply level
- Bus I/O protection – ± 2.5kV IEC 61000-4-5 1.2/50μs surge (SOIC) – ± 1.5kV IEC 61000-4-5 1.2/50μs surge (VSON) – ± 8kV IEC 61000-4-2 Contact discharge – ± 4kV IEC 61000-4-4 Electrical fast transient – ± 15kV HBM ESD – ± 42V DC bus fault
- Available in two speed grades – THVD2419: 250kbps – THVD2429: 20Mbps
- Extended ambient temperature range: -40°C to 125°C
- Extended operational common-mode range: ± 25V
- Large receiver hysteresis for noise rejection
- Low Power Consumption – Standby supply current: < 3µA – Current during operation: < 5.3mA
- Glitch-free power-up and down for hot plug-in capability
- Open, short, and idle bus failsafe
- 1/8 Unit load (up to 256 bus nodes)
- Industry standard 8-pin SOIC for drop-in compatibility
- Small surge-integrated RS-485 device in 3mm x 3mm leadless (VSON) package
2 Applications
- Wireless infrastructure
- Factory automation
- Motor drives
- Building automation
- HVAC
- Grid infrastructure
3 Description
THVD24x9 devices are half-duplex RS-485 transceivers with integrated surge protection. Surge protection is achieved by integrating transient voltage suppressor (TVS) diodes in the standard 8-pin SOIC (D) package as well as small 10-pin VSON package. This feature increases the reliability by providing better immunity to noise transients coupled to the data cable which eliminates the need for external protection components. THVD24x9 devices in the standard pin-out SOIC package operate from a single 3.3V or 5V supply. In addition, THVD24x9 devices in 10-pin VSON package and the V-versions of SOIC package support an additional V IO supply to operate the IOs from as low as 1.65V supply level. The devices in this family feature a wide common-mode voltage range making them suitable for multi-point applications over long cable runs.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) THVD2419, '2429 THVD2419V, '2429V SOIC (8) 4.9mm × 6mm THVD2419, '2429 VSON (10) 3mm × 3mm (1) For more information, see Section 12. (2) The package size (length × width) is a nominal value and includes pins, where applicable. RE DE D R GND A B VCC THVD24x9 Block Diagram (SOIC Package) DE D R GND A B VCC VIO RE THVD24x9 Block Diagram (VSON Package) ADVANCE INFORMATION THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.
10.2 Receiving Notification of Documentation Updates..24
12 Mechanical, Packaging, and Orderable
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4 Device Comparison Table
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5 Pin Configuration and Functions
R 7 B 3 6 A 4D 5 GND Not to scale RE DE Figure 5-1. THVD2419, THVD2429, 8-Pin (SOIC) (Top View) Not to scale VIO D DE RE
10 VCC
7 GND
6 GND Figure 5-2. THVD2419, THVD2429, 10-Pin (VSON) (Top View) VIO 8 VCC 2R 7 B 3DE/RE 6 A 4D 5 GND Not to scale Figure 5-3. THVD2419V, THVD2429V, 8-pin (SOIC) (Top View) PIN TYPE DESCRIPTION NAME SOIC-8 SOIC-8 (VIO) VSON-10 VIO - 1 1 P 1.8V to 5V supply for R, D, and RE/DE R 1 2 2 O Receiver data output RE 2 3 I Receiver enable, active low (2MΩ internal pull-up) DE 3 4 I Driver enable, active high DE/RE - 3 - I Driver enable (Active high), Receiver enable (Active Low). (2 MΩ internal pull-down) D 4 4 5 I Driver data input GND 5 5 6, 7 - Device ground A 6 6 8 I/O Bus I/O port, A (complementary to B) B 7 7 9 I/O Bus I/O port, B (complementary to A) VCC 8 8 10 P 3.3V to 5V supply for the device THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Logic supply voltage VIO (DRC package Only) –0.5 VCC + 0.2 V Bus supply voltage VCC –0.5 6.5 V Bus voltage Range at any bus pin (A or B) as differential or common-mode with respect to GND –42 42 V Input voltage Range at any logic pin (D, DE or RE) Versions with VIO pin –0.3 VIO + 0.2 V Input voltage Range at any logic pin (D, DE or RE) D Package –0.3 VCC + 0.2 V Receiver output current IO –24 24 mA Storage temperature Tstg –65 170 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/ JEDEC JS-001(1) Bus terminals and GND ±16,000 V All pins except bus terminals and GND ±4,000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1,500 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings [IEC]
V(ESD) Electrostatic discharge, bus terminals Contact discharge, per IEC 61000-4-2 Bus terminals and GND ±8,000 V Air-gap discharge, per IEC 61000-4-2 Bus terminals and GND ±8,000 V(SURGE) Surge Per IEC 61000-4-5, 1.2/50-8/20 μs CWG (DRC Package) Bus terminals and GND ±1,500 V V(SURGE) Surge Per IEC 61000-4-5, 1.2/50-8/20 μs CWG (D Package) Bus terminals and GND ±2,500 V www.ti.com THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: THVD2419 THVD2429
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Supply voltage 3 5.5 V VIO I/O supply voltage (DRC Package) 1.65 VCC V VIH High-level input voltage (driver, driver enable, receiver enable and slew rate select inputs) 0.7*VIO VIO V VIL Low-level input voltage (driver, driver enable, receiver enable and slew rate select inputs) 0 0.3*VIO V VIH High-level input voltage (driver, driver enable, receiver enable and slew rate select inputs) D Package without VIO option 0.7*VCC VCC V VIL Low-level input voltage (driver, driver enable, receiver enable and slew rate select inputs) 0 0.3*VCC V VI Input voltage at any bus terminal (separately or common mode)(1) –25 25 V VID Differential input voltage –25 25 V IO Output current, driver –60 60 mA IOR Output current, receiver VIO = 1.8V or 2.5V (Devices with VIO pin) –4 4 mA IOR Output current, receiver VIO = 3.3V or 5V (Devices with VIO pin) –8 8 mA RL Differential load resistance 54 60 Ω 1/tUI Signaling rate THVD2419 250 kbps THVD2429 20 Mbps TA Operating ambient temperature -40 125 °C TJ Junction temperature -40 150 °C (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
6.5 Thermal Information
THERMAL METRIC(1) THVD2419, THVD2429 UNITDRC (VSON) D (SOIC)
10 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 65.2 117.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 41.7 40.2 °C/W RθJB Junction-to-board thermal resistance 36.4 65.3 °C/W ψJT Junction-to-top characterization parameter 1.4 3.3 °C/W ψJB Junction-to-board characterization parameter 36.3 64.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 24.9 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.6 Power Dissipation
PARAMETER TEST CONDITIONS VALUE UNIT PD Driver and receiver enabled, VCC = 5.5 V, TA = 125 °C, square wave at 50% duty cycle Unterminated RL = 300Ω, CL = 50pF (driver) THVD2419 250 kbps 258 mW THVD2429 20Mbps 335 RS-422 load RL = 100Ω, CL = 50pF (driver) THVD2419 250 kbps 273 mW THVD2429 20Mbps 325 RS-485 load RL = 54Ω, CL = 50pF (driver) THVD2419 250 kbps 315 mW THVD2429 20Mbps 355 THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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6.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC = 5V, VIO = 3.3V , unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Driver |VOD| Driver differential output voltage magnitude RL = 60Ω, –25V ≤ Vtest ≤ 25V (See Figure 7-1) 1.5 2.8 V RL = 60Ω, –25V ≤ Vtest ≤ 25V, 4.5V ≤ VCC ≤ 5.5V (See Figure 7-1) 2.1 3.3 V RL = 100Ω (See Figure 7-2) 2 2.9 V RL = 54Ω (See Figure 7-2) 1.5 2.5 V Δ|VOD| Change in differential output voltage RL = 54Ω or 100Ω (See Figure 7-2) –50 50 mV VOC Common-mode output voltage RL = 54Ω or 100Ω (See Figure 7-2) 1 VCC/2 3 V ΔVOC(SS) Change in steady-state common-mode output voltage RL = 54Ω or 100Ω (See Figure 7-2) –50 50 mV IOS Short-circuit output current DE = VIO, -42V ≤ (VA or VB) ≤ 42V, or A shorted to B –250 250 mA Receiver II Bus input current DE = 0 V, VCC and VIO = 0 V or 5.5 V VI = 12 V 75 125 μA VI = 25 V 200 250 μA VI = –7 V –100 –60 μA VI = –25 V –350 –300 μA VTH+ Positive-going input threshold voltage(1) Over common-mode range of ± 25 V 40 125 200 mV VTH- Negative-going input threshold voltage(1) –200 –125 -40 mV VHYS Input hysteresis 250 mV VTH_FSH Input fail-safe threshold –40 40 mV CA,B Input differential capacitance Measured between A and B, f = 1 MHz 50 pF IOZ Output high-impedance current, R pin VO = 0 V or VIO, RE = VIO –1 1 µA Logic IIN Input current (DE , SLR) DRC: 1.65 V ≤ VIO ≤ 5.5 V, 0 V ≤ VIN ≤ VIO D: 3 V ≤ VCC ≤ 5.5 V, 0 V ≤ VIN ≤ 5.5 V 5 µA IIN Input current (D, RE) DRC: 1.65 V ≤ VIO ≤ 5.5 V, 0 V ≤ VIN ≤ VIO D: 3 V ≤ VCC ≤ 5.5 V, 0 V ≤ VIN ≤ 5.5 V –5 µA Thermal Protection TSHDN Thermal shutdown threshold Temperature rising 150 170 °C THYS Thermal shutdown hysteresis 10 °C Supply UVVCC (rising) Rising under-voltage threshold on VCC 2.3 2.6 V UVVCC (falling) Falling under-voltage threshold on VCC 1.95 2.2 V UVVCC(hys Hysteresis on under-voltage of VCC 170 mV UVVIO (rising) Rising under-voltage threshold on VIO 1.4 1.6 V UVVIO (falling) Falling under-voltage threshold on VIO 1.2 1.3 V www.ti.com THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: THVD2419 THVD2429
over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC = 5V, VIO = 3.3V , unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UVVIO(hys) Hysteresis on under-voltage of VIO 120 mV ICC Supply current (quiescent), VCC = 4.5 V to 5.5 V Driver and receiver enabled RE = 0 V, DE = VIO, No load 3.5 5.3 mA Driver enabled, receiver disabled RE = VIO, DE = VIO, No load 2.5 4.2 mA Driver disabled, receiver enabled RE = 0 V, DE = 0 V, No load 1.8 2.4 mA Driver and receiver disabled (D package, no VIO pin) RE = VCC, DE = 0 V, D = open, No load 0.1 5 µA Driver and receiver disabled (DRC paclkage, with VIO pin) RE = VIO, DE = 0 V, D = open, No load 0.1 3 µA ICC Supply current (quiescent), VCC = 3 V to 3.6 V Driver and receiver enabled RE = 0 V, DE = VIO, No load 3 4.1 mA Driver enabled, receiver disabled RE = VIO, DE = VIO, No load 2 3 mA Driver disabled, receiver enabled RE = 0 V, DE = 0 V, No load 1.6 2.2 mA Driver and receiver disabled (D Package, no VIO) RE = VCC, DE = 0 V, D = open, No load TBD 4 µA Driver and receiver disabled (DRC package, with VIO pin) RE = VIO, DE = 0 V, D = open, No load TBD 2 µA IIO Logic supply current (quiescent), VIO = 3 to 3.6 Driver disabled, Receiver enabled DE = 0 V, RE = 0 V, No load 3.3 8.4 µA Driver disabled, Receiver disabled DE = 0 V, RE = VIO, No load 0.1 2 µA (1) Under any specific conditions, VTH+ is specified to be at least VHYS higher than VTH–. THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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6.8 Switching Characteristics_250kbps
250-kbps (THVD2419) over recommended operating conditions. All typical values are at 25°C and supply voltage of VCC = 5 V , VIO = 3.3 V, unless otherwise noted. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Driver tr, tf Differential output rise/fall time RL = 54 Ω, CL = 50 pF See Figure 7-3 VCC = 3 to 3.6 V, Typical at 3.3V 400 650 1200 ns VCC = 4.5 to 5.5 V, Typical at 5 V 500 710 1200 ns tPHL, tPLH Propagation delay VCC = 3 to 3.6 V, Typical at 3.3V 525 750 ns VCC = 4.5 to 5.5 V, Typical at 5 V 560 770 ns tSK(P) Pulse skew, |tPHL – tPLH| VCC = 3 to 3.6 V, Typical at 3.3V 30 70 ns VCC = 4.5 to 5.5 V, Typical at 5 V 30 70 ns tPHZ, tPLZ Disable time RE = X See Figure 7-4 and Figure 7-5 33 75 ns tPZH, tPZL Enable time RE = 0 V TBD 280 ns RE = VIO 2 4.5 µs tSHDN Time to shutdown RE = VIO 50 500 ns Receiver tr, tf Output rise/fall time CL = 15 pF See Figure 7-6 13 20 ns tPHL, tPLH Propagation delay 850 1270 ns tSK(P) Pulse skew, |tPHL – tPLH| 5 45 ns tPHZ, tPLZ Disable time DE = X 30 40 ns tPZH(1) Enable time VIO = 3 V to 3.6 V; DE = VIO See Figure 7-7 90 120 ns VIO = 1.65 V to 1.95 V, DE = VIO TBD 130 ns tPZL(1) VIO = 3 V to 3.6 V; DE = VIO 900 1320 ns VIO = 1.65 V to 1.95 V; DE = VIO TBD 1320 ns tPZH(2), tPZL(2) Enable time DE = 0 V See Figure 7-8 3.3 5.4 μs tD(OFS) Delay to enter fail-safe operation CL = 15 pF See Figure 7-9 7 11 18 μs tD(FSO) Delay to exit fail-safe operation 540 850 1260 ns tSHDN Time to shutdown DE = 0 V See Figure 7-8 50 500 ns (1) A, B are driver output and receiver input terminals for Half duplex devices. A, B are RX input, Y/Z are driver output terminals for Full duplex device
6.9 Switching Characteristics_20Mbps
20-Mbps (THVD2429) over recommended operating conditions. All typical values are at 25°C and supply voltage of VCC = 5 V, VIO = 3.3 V, unless otherwise noted. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Driver tr, tf Differential output rise/fall time RL = 54 Ω, CL = 50 pF See Figure 7-3 VCC = 3 to 3.6 V, Typical at 3.3 V 4 8 15 ns VCC = 4.5 to 5.5 V, Typical at 5 V 4 TBD 15 ns tPHL, tPLH Propagation delay VCC = 3 to 3.6 V, Typical at 3.3 V 6 15 30 ns VCC = 4.5 to 5.5 V, Typical at 5 V 6 TBD 26 ns tSK(P) Pulse skew, |tPHL – tPLH| VCC = 3 to 3.6 V, Typical at 3.3 V TBD 3 ns VCC = 4.5 to 5.5 V, Typical at 5 V TBD 3 ns www.ti.com THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: THVD2419 THVD2429
20-Mbps (THVD2429) over recommended operating conditions. All typical values are at 25°C and supply voltage of VCC = 5 V, VIO = 3.3 V, unless otherwise noted. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPHZ, tPLZ Disable time RE = X See Figure 7-4 and Figure 7-5 15 35 ns tPZH, tPZL Enable time RE = 0 V 8 39 ns RE = VIO 2 4.5 μs tSHDN Time to shutdown RE = VIO 50 500 ns Receiver tr, tf Output rise/fall time CL = 15 pF See Figure 7-6 1.5 6 ns tPHL, tPLH Propagation delay VIO = 3 V to 3.6 V, TBD 40 57 ns VIO = 1.65 V to 1.95 V, TBD TBD 60 ns tSK(P) Pulse skew, |tPHL – tPLH| CL = 15 pF 5.5 ns tPHZ, tPLZ Disable time DE = X 11 22 ns tPZH(1), tPZL(1) Enable time DE = VIO See Figure 7-7 55 82 ns tPZH(2), tPZL(2) Enable time DE = 0 V See Figure 7-8 1.5 4.5 μs tD(OFS) Delay to enter fail-safe operation CL = 15 pF See Figure 7-9 7 11 18 μs tD(FSO) Delay to exit fail-safe operation 19 25 50 ns tSHDN Time to shutdown DE = 0 V See Figure 7-8 50 500 ns (1) A, B are driver output and receiver input terminals for Half duplex devices. A, B are RX input, Y/Z are driver output terminals for Full duplex device THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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7 Parameter Measurement Information
A B DE Vcc Vtest VOD D 375 RL 375 Figure 7-1. Measurement of Driver Differential Output Voltage With Common-Mode Load A B VOC VOC(PP) ûVOC(SS) VA VB0V or Vcc A B D RL/2 CL VOC VOD RL/2 Figure 7-2. Measurement of Driver Differential and Common-Mode Output With RS-485 Load VOD VI tPLH tPHL tr tf 90% 50% 10% 50% Vcc ± 2 V 0 V Input Generator A B Vcc VOD D RL= 54 VI 50 DE CL= 50 pF ~~2 V Figure 7-3. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays VO VI tPZH tPHZ 50% 50% Vcc ~ 0V 0 V VOH90%Input Generator A B VOD RL = 110 VI 50 DE CL = 50 pF Figure 7-4. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down Load VO VI tPZL tPLZ 50% 50 % Vcc Vcc 0 V VOL 10%Input Generator A B VOD RL= 110 VI 50 DE CL= 50 pF Vcc Figure 7-5. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load www.ti.com THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: THVD2419 THVD2429
90% 50 % 10 % 50% 3 V VOH VOL 0 V Input Generator VO VI 50 RE A B R 1.5V 0 V CL=15 pF Figure 7-6. Measurement of Receiver Output Rise and Fall Times and Propagation Delays VO VI tPHZ 50 % 50 % Vcc VOH90 % 50 % 10 % VOL VCC tPLZ tPZL(1) VO tPZH(1) D at Vcc S1 to GND Input Generator VO VI 50 A B R CL=15 pF RE 0V or Vcc DE Vcc D Vcc 1 k D at 0V S1 to Vcc Figure 7-7. Measurement of Receiver Enable/Disable Times With Driver Enabled VO VI 50% Vcc §0V VOH 50% VOL VCC tPZL(2) VO tPZH(2) 50% Input Generator VO VI 50 A B R CL=15 pF RE V or 1.5V Vcc 1 N
1.5 V or 0V
A at 1.5V B at 0V A at 0V B at 1.5V S1 to VCC Figure 7-8. Measurement of Receiver Enable Times With Driver Disabled VO A B R CL= 15 pFRE VA = 0 V or -750 mV VB = 0 V or +750 mV 0 V VA - VB -1.5 V 0 V VO 0 V VCC VCC / 2 tD(OFS) tD(FSO) Copyright © 2017, Texas Instruments Incorporated Figure 7-9. Fail-Safe Delay Measurements THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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8 Detailed Description
8.1 Overview
THVD24x9 devices are surge-protected, half duplex RS-485 transceivers available in two speed grades suitable for data transmission up to 250kbps and 12Mbps respectively. Surge protection is achieved by integrating transient voltage suppressor (TVS) diodes in the standard 8-pin SOIC (D) package and a small 10-pin leadless package. THVD2419 and THVD2429 devices have active-high driver enables and active-low receiver enables. A low standby current can be achieved by disabling both driver and receiver. THVD2419V and THVD2429V devices in the SOIC package have a single enable/disable pin (DE/ RE) that either enables the driver or the receiver at a time.
8.2 Functional Block Diagrams
D R GND A B VCC Figure 8-1. THVD2419 and THVD2429 Block Diagram (SOIC Package) REDE / D R GND A B VCC VIO Figure 8-2. THVD2419V and THVD2429V Block Diagram (SOIC Package with VIO pin) DE D R GND A B VCC VIO RE Figure 8-3. THVD2419 and THVD2429 Block Diagram (VSON Package) www.ti.com THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: THVD2419 THVD2429
8.3 Feature Description
8.3.1 Electrostatic Discharge (ESD) Protection
The bus pins of the THVD24x9 transceiver family include on-chip ESD protection against ±15kV HBM and ±8kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far more severe than the HBM ESD test. The 50% higher charge capacitance, C (S), and 78% lower discharge resistance, R(D), of the IEC model produce significantly higher discharge currents than the HBM model. As stated in the IEC 61000-4-2 standard, contact discharge is the preferred transient protection test method. R(C) R(D) C(S) High-Voltage Pulse Generator Device Under Test Current (A) Time (ns) 0 50 100 150 200 250 300 10-kV IEC 10-kV HBM 330 Ω (1.5 kΩ) 150 pF (100 pF) 50 M (1 M) Figure 8-4. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis) The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common discharge events occur because of human contact with connectors and cables.
8.3.2 Electrical Fast Transient (EFT) Protection
Inductive loads such as relays, switch contactors, or heavy-duty motors can create high-frequency bursts during transition. The IEC 61000-4-4 test is intended to simulate the transients created by such switching of inductive loads on AC power lines. Figure 8-5 shows the voltage waveforms in to 50 Ω termination as defined by the IEC standard. THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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200 µs at 5 kHz 10 µs at 100 kHz Normalized Voltage Time 15 ms at 5 kHz 0.75 ms at 100 kHz300 ms Normalized Voltage Time 0.5 5 ns 50ns Figure 8-5. EFT Voltage Waveforms Internal ESD protection circuits of the THVD24x9(V) protect the transceivers against ±4kV EFT. With careful system design, one could achieve EFT Criterion A (no data loss when transient noise is present).
8.3.3 Surge Protection
Surge transients often result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the switching of power systems, including load changes and short circuit switching. These transients are often encountered in industrial environments, such as factory automation and power-grid systems. Figure 8-6 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD transient. The diagram on the left shows the relative pulse-power for a 0.5kV surge transient and 4kV EFT transient, both of which dwarf the 10kV ESD transient visible in the lower-left corner. 500V surge transients are representative of events that may occur in factory environments in industrial and process automation. The diagram on the right shows the pulse-power of a 6kV surge transient, relative to the same 0.5kV surge transient. 6kV surge transients are most likely to occur in power generation and power-grid systems. www.ti.com THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: THVD2419 THVD2429
Pulse Power (kW) Time (µs) 0 5 10 15 20 25 30 35 40 0.5-kV Surge 10-kV ESD 4-kV EFT Pulse Power (MW) 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 Time (µs) 0 5 10 15 20 25 30 35 40 0.5-kV Surge 6-kV Surge 3.0 2.8 2.6 2.4 Figure 8-6. Power Comparison of ESD, EFT, and Surge Transients Figure 8-7 shows the test setup used to validate THVD24x9 surge performance according to the IEC 61000-4-5 1.2/50μs surge pulse. Surge Generator
2 OSource Impedance
A B GND Figure 8-7. THVD24x9 Surge Test Setup THVD24x9 product family is robust up to ±2.5kV surge transients without the need for any external components. The bus pin voltage is clamped by the integrated surge protection diodes such that the internal circuitry is not damaged during the surge event.
8.3.4 Enhanced Receiver Noise Immunity
The differential receivers of THVD24x9(V) family feature fully symmetric thresholds to maintain duty cycle of the signal even with small input amplitudes. In addition, 250mV (typical) hysteresis displays excellent noise immunity.
8.3.5 Failsafe Receiver
The differential receivers of the THVD24x9 family are failsafe to invalid bus states caused by the following:
- Open bus conditions, such as a disconnected connector
- Shorted bus conditions, such as cable damage shorting the twisted-pair together
- Idle bus conditions that occur when no driver on the bus is actively driving In any of these cases, the receiver outputs a fail-safe logic high state if the input amplitude stays for longer than tD(OFS) at less than |VTH_FSH|. THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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8.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. The differential output voltage defined as VOD = VA – VB is positive. When D is low, the output states reverse: B turns high, A becomes low, and VOD is negative. When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin has an internal pull-down resistor to ground. When left open the driver is disabled (high-impedance) by default. The D pin has an internal pull-up resistor to V CC; thus, when left open while the driver is enabled, output A turns high and B turns low. Table 8-1. Driver Function Table INPUT ENABLE OUTPUTS FUNCTION D DE A B H H H L Actively drive bus high L H L H Actively drive bus low X L Z Z Driver disabled X OPEN Z Z Driver disabled by default OPEN H H L Actively drive bus high by default When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as V ID = V A – V B is higher than the positive input threshold, V TH+, the receiver output, R, turns high. When VID is lower than the negative input threshold, V TH-, the receiver output, R, turns low. If V ID is between VTH+ and VTH- the output is indeterminate. When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of V ID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus). Table 8-2. Receiver Function Table DIFFERENTIAL INPUT ENABLE OUTPUT FUNCTION VID = VA – VB RE R VTH+ < VID L H Receive valid bus high VTH- < VID < VTH+ L Indeterminate Indeterminate bus state VID < VTH- L L Receive valid bus low X H Z Receiver disabled X OPEN Z Receiver disabled by default Open-circuit bus L H Fail-safe high output Short-circuit bus L H Fail-safe high output Idle (terminated) bus L H Fail-safe high output www.ti.com THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: THVD2419 THVD2429
9 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
9.1 Application Information
THVD24x9 are half-duplex RS-485 transceivers with integrated system-level surge protection. Standard 8-pin SOIC (D) package allows drop-in replacement into existing systems and eliminate system-level protection components.
9.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line reflections, each cable end is terminated with a termination resistor, R T, with a value that matches the characteristic impedance, Z 0, of the cable. This method, known as parallel termination, allows for higher data rates over longer cable length. RT RT R A B R RE DE D D R A B R RE DE D D R D R RE DE D A B R D R RE DE D A B Figure 9-1. Typical RS-485 Network With Half-Duplex Transceivers
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of applications with varying requirements, such as distance, data rate, and number of nodes.
9.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the short the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485 systems use data rates between 10kbps and 100kbps, some applications require data rates up to 250kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or 10%. THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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Cable Length (ft) Data Rate (bps) 10000 1000 100 100 1k 10 k 100 k 1M 10 M 100 M Conservative Characteristics 5%, 10%, and 20% Jitter Figure 9-2. Cable Length vs Data Rate Characteristic Even higher data rates are achievable (that is, 12Mbps for the THVD2429(V)) in cases where the interconnect is short enough (or has suitably low attenuation at signal frequencies) to not degrade the data.
9.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as shown in Equation 1. L(STUB) ≤ 0.1 × tr × v × c (1) where
- tr is the 10/90 rise time of the driver
- c is the speed of light (3 × 108 m/s)
- v is the signal velocity of the cable or trace as a factor of c
9.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit load represents a load impedance of approximately 12k Ω. Because the THVD24x9(V) devices consist of 1/8 UL transceivers, connecting up to 256 receivers to the bus is possible. www.ti.com THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: THVD2419 THVD2429
9.2.2 Detailed Design Procedure
RS-485 transceivers operate in noisy industrial environments typically require surge protection at the bus pins. Figure 9-3 compares 4kV surge protection implementation with a regular RS-485 transceiver (such as THVD14x0) against with the THVD24x9(V). The internal TVS protection of the THVD24x9(V) achieves ±2.5kV IEC 61000-4-5 surge protection (SOIC package) without any additional external components, reducing system level bill of materials. 3.3V ±5 V RxD TxD DIR MCU/ UART 10k 10k 100nF DIR 10k R D DE /RE B A GND VCC 3.3V ±5 V RxD TxD DIR MCU/ UART 10k 10k 100nF DIR 10k R D DE /RE B A GND VCC TVS RS-485 transceiver THVD24x9 System level surge protection implementation using a typical RS-485 transceiver System level surge protection implementation using THVD14x9 transceiver TBU TBU MOV MOV Figure 9-3. Implementation of System-Level Surge Protection Using THVD24x9(V) THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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9.2.3 Application Curves
Ch 2: D Input, Ch4: VOD VCC = 5V Data rate: 12Mbps Ch1: R Output Figure 9-4. THVD2429 Waveforms with 54Ω Termination and VCC = 5V Ch 2: D Input, Ch4: VAB VCC = 3.3V Data rate: 12Mbps Ch1: R Output Figure 9-5. THVD2429 Waveforms with 54Ω Termination and VCC = 3.3V
9.3 Power Supply Recommendations
For reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and inductance of the PCB power planes. www.ti.com THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: THVD2419 THVD2429
9.4 Layout
9.4.1 Layout Guidelines
Additional external protection components generally are not needed when using THVD24x9 transceivers. 1. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents tend to follow the path of least impedance and not the path of least resistance. Apply 100nF to 220nF decoupling capacitors as close as possible to the VCC pins of transceiver, UART and/or controller ICs on the board. 2. Use at least two vias for VCC and ground connections of decoupling capacitors to minimize effective via inductance. 3. Use 1kΩ to 10kΩ pull-up and pull-down resistors for enable lines to limit noise currents in these lines during transient events.
9.4.2 Layout Example
R R C Via to VCC RE DE D VCC B A GND R Figure 9-6. THVD2419, THVD2429 Layout Example (SOIC Package) THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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10 Device and Documentation Support
10.1 Device Support
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES January 2024 * Initial Release
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] .041 [1.04] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) SOIC - 1.75 mm max heightD0008B SMALL OUTLINE INTEGRATED CIRCUIT 4221445/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15], per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A TYPICAL DETAIL A SCALE 2.800 www.ti.com THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: THVD2419 THVD2429
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] (.217) [5.5] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] 8X (.055) [1.4] 8X (.024) [0.6] 6X (.050 ) [1.27] (R.002 ) [0.05] TYP SOIC - 1.75 mm max heightD0008B SMALL OUTLINE INTEGRATED CIRCUIT 4221445/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSDE METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE:6X SYMM 4 5 SEE DETAILS IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE SYMM HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE SYMM 4 5 SEE DETAILS SYMM THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] 8X (.055) [1.4] 8X (.024) [0.6] 6X (.050 ) [1.27] (.217) [5.5] (R.002 ) [0.05] TYP SOIC - 1.75 mm max heightD0008B SMALL OUTLINE INTEGRATED CIRCUIT 4221445/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE BASED ON .005 INCH [0.127 MM] THICK STENCIL SOLDER PASTE EXAMPLE SCALE:6X SYMM SYMM 4 5 IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE SYMM SYMM 4 5 www.ti.com THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: THVD2419 THVD2429
www.ti.com PACKAGE OUTLINE C A 3.1 2.9 B 3.1 2.9 10X 0.3 0.2 2.4 2.2 1.75 1.55 8X 0.5 1.0 0.8 10X 0.5 0.3 0.05 0.00 (0.2) TYP 4X (0.25) 2X (0.5) VSON - 1 mm max heightDRC0010V PLASTIC SMALL OUTLINE - NO LEAD 4226575/A 02/2021 PIN 1 INDEX AREA SEATING PLANE 0.08 C 5 6 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED SYMM SYMM11 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. SCALE 4.000 THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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www.ti.com EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND0.07 MAX ALL AROUND 10X (0.24) (2.3) (2.8) 8X (0.5) (1.65) (0.2) TYP VIA (0.575) (0.9) 10X (0.6) (R0.05) TYP (3.4) (0.25) (0.5) VSON - 1 mm max heightDRC0010V PLASTIC SMALL OUTLINE - NO LEAD 4226575/A 02/2021 SYMM 5 6 EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE:20X 11SYMM NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) EXPOSED METAL www.ti.com THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: THVD2419 THVD2429
www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP (0.61) 10X (0.24) 10X (0.6) 2X (1.51) (1.02) (2.8) 8X (0.5) (0.5) 4X (0.34) 4X (0.25) (1.53) VSON - 1 mm max heightDRC0010V PLASTIC SMALL OUTLINE - NO LEAD 4226575/A 02/2021 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 5 6 EXPOSED METAL TYP SYMM THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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12.1 Tape and Reel Information
Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PTHVD2419DR PTHVD2419VDR PTHVD2429DR PTHVD2429VDR PTHVD2419DRCR PTHVD2429DRCR www.ti.com THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 ADVANCE INFORMATION Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: THVD2419 THVD2429
TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PTHVD2419DR PTHVD2419VDR PTHVD2429DR PTHVD2429VDR SOIC D 8 2500 340.5 338.1 20.6 PTHVD2419DRCR PTHVD2429DRCR VSON DRC 10 5000 367.0 367.0 35.0 THVD2419, THVD2429 SLLSFP5 – JANUARY 2024 www.ti.com ADVANCE INFORMATION
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www.ti.com 10-Feb-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTHVD2419DRCR ACTIVE VSON DRC 10 5000 TBD Call TI Call TI -40 to 125 Samples PTHVD2429DRCR ACTIVE VSON DRC 10 5000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com 10-Feb-2024 Addendum-Page 2
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